Read amplifier of a memory cell

Abstract

A read amplifier of a memory cell, comprising: - a read voltage generation circuit configured to generate a read voltage that is dependent on a power supply which charges a bit line capacity of the memory cell during a pre-charge phase, and which is independent of the power supply during a read phase; and - a read circuit configured to compare a bit line voltage with the read voltage and output a digital output signal indicating the contents of the memory cell.

Description

[0001] From US 2008 / 0291763 A1, a memory is known for which a bit line is preloaded.

[0002] A read amplifier is a circuit that reads data from a memory cell in a memory matrix. The read amplifier reads low-voltage signals from a bit line representing a data bit ("1" or "0") stored in the memory cell and amplifies these low-voltage signals to full CMOS-level signals for digital post-processing.

[0003] A read operation using a read amplifier is triggered by a memory address change or a dedicated read start and has two phases: a pre-charge phase and a read phase. During the pre-charge phase, the bit line capacitance is charged to a pre-charge potential VDD_pre. In the subsequent read phase, the bit line is discharged by the memory cell current towards the voltage source VSS (e.g., ground). The read amplifier behaves like a voltage comparator, comparing a read voltage (i.e., reference voltage) with the voltage on the bit line. When a cell of low resistance is accessed (data bit "0"), the bit line discharges comparatively faster than a bit line discharge corresponding to a cell of high resistance (data bit "1"). The digital output signal of the read amplifier changes to a logic "0" when the bit line voltage is lower than the read voltage.

[0004] The energy consumption of a read amplifier should be as low as possible to achieve the goals of ultra-low energy consumption applications. However, some known read amplifiers have features that detract from this goal.

[0005] For example, a read amplifier is continuously biased by a global power supply, which consumes static and dynamic energy. Furthermore, the read amplifier can be biased by the VDD power supply during the read phase. The bit line is also typically pre-charged by a regulated VDD_pre supply, which necessitates additional circuitry and power.

[0006] Furthermore, good power supply rejection conditions typically require voltage regulation for the bitline voltage or the read amplifier itself, which further increases energy consumption. Additionally, the maximum bitline voltage is limited by the voltage level required by the voltage regulation.

[0007] One task, therefore, is to improve known approaches.

[0008] This problem is solved according to the features of the independent claims. Preferred embodiments can be found in particular in the dependent claims.

[0009] The described properties, characteristics, and advantages, as well as the manner in which they are achieved, are further explained in connection with the following schematic description of exemplary embodiments, which are further clarified in conjunction with the drawings. For clarity, identical or equivalent elements may be designated with the same reference numerals. Fig. Figure 1A shows a circuit diagram of a memory cell coupled to a read amplifier according to an exemplary embodiment. Fig. 1B represents a timing diagram of the circuit of Fig. 1 dar. Fig. 2A, Fig. 2C and Fig. Figure 2D represents circuit diagrams of a memory matrix coupled to a read amplifier according to another exemplary embodiment. Fig. 2B shows a timing diagram of the circuit. Fig. 2A, Fig. 2C and Fig. 2D representation. Fig. Figure 3 represents a flowchart of a process according to an exemplary embodiment.

[0010] The present disclosure relates to a read amplifier of a memory cell, which has a read voltage generation circuit configured to generate a read voltage; and a read signal circuit configured to compare a bit line voltage of the memory cell with the read voltage and output a digital output signal indicating a content of the memory cell, wherein the read circuit is decoupled during a read phase from a voltage supply that charges a bit line capacitance during a pre-charge phase, and is coupled to and supplied by the bit line capacitance. The read voltage generation circuit can further be configured to generate a read voltage that is dependent on the voltage supply during a pre-charge phase and independent of the voltage supply during a read phase.Such a reading amplifier is advantageous in that it has lower energy consumption and good voltage supply rejection compared to previous approaches.

[0011] Fig. Figure 1A represents a circuit diagram 100A of a memory matrix 110, which is coupled to the read amplifier 120A according to an exemplary embodiment. Fig. 1B represents a timing diagram 100B of the circuit of Fig. 1A.

[0012] Memory matrix 110 comprises a memory cell, represented by the bit line, and a switch S1, which is coupled between the voltage supply VDD and the bit line. The bit line has a capacitance, represented by C_BL, and a current, represented by I_CELL.

[0013] Amplifier 120A includes read circuit 122A along with other elements not shown for simplicity. Read circuit 122A is based on two transistors: a P-channel metal-oxide-semiconductor field-effect transistor (PMOS) P1 and an N-channel metal-oxide-semiconductor field-effect transistor (NMOS) N1. PMOS P1 is coupled between the bit line and digital output DO and functions as a voltage sensing transistor. NMOS N1 is coupled between digital output DO and a voltage source VSS (e.g., ground) and functions as a current source that generates the bias current I_BIAS.

[0014] A read operation by the read amplifier 120A is triggered by a memory address change and has two phases - a pre-charging phase and a subsequent read phase. Fig. 1B shows this memory address change in the top row of the timing diagram and the preload phase in the second row.

[0015] During the pre-charging phase, switch S1 conducts to charge the bit line directly to the supply potential VDD, as shown in the third line of Fig. Figure 1B shows that the pre-regulated bit line voltage VDDpre from previous approaches is omitted, thus saving energy and eliminating the need for additional circuitry or current for bit line regulation.

[0016] During the subsequent read phase, the read circuit 122A is decoupled from the power supply VDD due to the open switch S1 and remains coupled to the bit line to be powered directly by the bit line voltage V_BL instead of a global power supply as in previous approaches. In other words, the amplifier 120A reuses the bit line charge for its read operation. Read circuit 122A compares the bit line voltage V_BL of the memory cell with the read voltage V_SENSE and outputs a digital output signal at digital output DO, indicating the contents of the memory cell, as shown in the third and fourth lines of Fig. Figure 1B shows the read voltage V_SENSE as the sum of the gate voltage and the absolute value of the threshold voltage of transistor P1 (V_SENSE = V_PGATE + |V_THP1|).

[0017] More precisely, during the read phase, the pre-charged bit line capacitance C_BL is discharged by the cell current I_CELL. Furthermore, current discharges through PMOS P1 and NMOS N1, determining the digital output signal DO, which indicates the contents of the memory cell. PMOS P1 charges from the bit line capacitance C_BL to the digital output DO as long as the bit line voltage V_BL is greater than the read voltage V_SENSE, and NMOS N1 discharges the digital output DO to the voltage source VSS when the bit line voltage V_BL falls below the read voltage V_SENSE. In other words, when the bit line voltage V_BL reaches the read voltage V_SENSE, the difference between the gate voltage V_PGATE and the bit line voltage V_BL becomes less than the PMOS threshold voltage V_THP1, and PMOS P1 is turned off. When PMOS P1 is off, and current is still flowing through NMOS N1, the digital output DO is discharged to VSS (e.g., ground) with the precharge current I_BIAS.The discharge rate of the digital output DO is high compared to the discharge rate of the bit line capacitance C_BL because the digital output DO has only a small stray capacitance; this is reflected by the sudden drop in the digital output signal at the digital output DO when the bit line voltage V_BL crosses the read voltage V_SENSE. If the bit line voltage V_BL remains greater than the read voltage V_SENSE, the memory cell is assumed to be written to (logic "1"). Conversely, if the bit line voltage V_BL of the memory cell becomes less than the read voltage V_SENSE, the memory cell is assumed to be erased (logic "0").

[0018] Therefore, similar to previous approaches, the bitline capacitance C_BL is charged to the voltage supply VDD during the pre-charge phase (i.e., switch S1 is conducting) and discharged during the subsequent read phase (i.e., S1 is non-conducting). However, during a read phase, the read circuit 120A is decoupled from the voltage supply VDD, coupled to the bitline voltage V_BL, and powered by the bitline voltage V_BL. The current consumption of the read amplifier 120A after the pre-charge phase is complete becomes zero because there is no current path from the voltage supply VDD to the voltage source VSS.

[0019] For simplicity, memory matrix 110 represents a single memory cell. It is well known that memory matrix 110 can contain any number of memory cells suitable for the intended purpose. Furthermore, the voltage read amplifier 120A is shown coupled to read this single memory cell. Depending on the type of memory matrix, a voltage signal amplifier 120A can be coupled via a multiplexer circuit to read any number of memory cells suitable for the intended purpose.

[0020] Furthermore, the memory matrix can be any known volatile or non-volatile memory. Examples of memory matrix types include, but are not limited to, RO, PCRAM (phase-change RAM), CBRAM (bridging RAM), and MRAM (resistance magnetic memory), etc.

[0021] Fig. 2A, Fig. 2C and Fig. Figure 2D represents circuit diagrams of a memory cell 110 coupled to a read amplifier 220, which has a read voltage generation circuit 224 that generates a local read voltage V_SENSE according to an exemplary embodiment. More precisely, it represents Fig. 2A represents the reading voltage generation circuit 224A in general, Fig. 2C represents the reading voltage generation circuit 224C during the pre-charging phase, and Fig. Figure 2D represents the reading voltage generation circuit 224 during the reading phase. Fig. 2B represents a timing diagram 200B of the reading amplifier 220 of the Fig. 2A, Fig. 2C and Fig. 2D representation.

[0022] First, with reference to Fig. 2A, is a circuit diagram 200A of a storage matrix 110 shown, which is coupled to the read amplifier 220A.

[0023] Memory matrix 110 is the same memory matrix that was used in Fig. 1A is shown, and to make it brief, its description will not be repeated here.

[0024] The 220A read amplifier comprises the 222A read circuit and the 224A read voltage generation circuit. The 222A read circuit was described above with reference to Fig. It is described in section 1A, and to keep it brief, its description will not be repeated here.

[0025] Read voltage generation circuit 224A is a local circuit that replaces the previous approaches of a global read voltage generation circuit that generates the PMOS gate voltage V_PGATE for all of the read amplifiers of a memory matrix. The local read voltage generation circuit 224A of this disclosure is implemented by three additional switches S2-S4, sample capacitor C_SAMPLE, and read resistor R_SENSE. The switches allow the read voltage V_SENSE to depend on the supply voltage VDD during the pre-charge phase and to be independent of the supply voltage VDD during the read phase, as described below with reference to Fig. 2C and Fig. Each 2D dimension is described in more detail.

[0026] More precisely, switch S2 is coupled between the bit line and the source of PMOS P1. Switch S3 is coupled between the voltage supply VDD and the source of PMOS P1. Switch S4 is coupled between the gate and drain of PMOS P1. Read resistor R_SENSE is coupled between the voltage supply VDD and switch S3. Sample capacitor C_SAMPLE is coupled between the gate of PMOS P1 and a stable voltage source (for example, voltage source VSS) and is configured during the read phase to apply a voltage to V_PGATE to keep V_PGATE stable.

[0027] Fig. 2C is the circuit diagram of Fig. 2A, shown during its pre-charge phase. As will be described, the read voltage generation circuit 224C is configured such that the read voltage V_SENSE during the pre-charge phase depends on the voltage supply VDD.

[0028] Switch S2 is configured to be open during the pre-charging phase, and switches S3 and S4 are configured to be closed. Read circuit 222C is connected to the voltage supply VDD, and therefore the read voltage V_SENSE depends on the voltage supply VDD.

[0029] The local read voltage generation circuit 224C is advantageous over the global read voltage generation circuit of previous approaches in that no "shock" of the local voltage supply (i.e., a sudden rise or fall in the supply voltage VDD) interrupts the read operation during the read phase, because the read voltage V_SENSE depends on the supply voltage VDD. The advantages of the local read voltage generation circuit 224C are best illustrated by a description of the global read generation circuit of previous approaches.

[0030] The global signal generation circuits of the previous approaches do not have a read voltage V_SENSE that depends on VDD. For example, an interruption of the read operation can occur if a sudden change (such as a drop) in the supply voltage VDD occurs during the pre-charge phase. More precisely, the gate voltage V_PGATE is fixed, so the read voltage V_SENSE, which depends on the gate voltage V_GATE (V_SENSE = V_PGATE + |V_THP1|), is also fixed. On the other hand, the supply voltage V_DD can rise and fall due to noise and the overall behavior of the system. A sudden drop in the supply voltage V_DD, which charges the bit line capacitance C_BL during the pre-charge phase, leads to a drop in the pre-charge bit line voltage V_BL. But again, the read voltage V_SENSE is held constant. Therefore, at the beginning of the read phase, the dropped bit line voltage V_BL may already be below the read voltage V_SENSE.Therefore, if the bit line voltage V_BL continues to fall during the discharge of the bit line, there is never a point at which the bit line voltage V_BL can transition from being greater than the read voltage V_SENSE to being less than the read voltage V_SENSE, which would indicate a cleared cell (logical "0"). There is no actual read phase because it is not possible in this situation to read the memory cell to read between logical "0" and "1".

[0031] The read voltage generation circuit 224C of the present disclosure does not suffer from the disadvantages of the global approach because the read voltage V_SENSE responds to fluctuations in the supply voltage VDD by taking any VDD surges into account. If a supply voltage suddenly drops, the read voltage V_SENSE also drops by a similar amount because the switch S3 is closed to couple PMOS P1 to the supply voltage VDD, so that the supply voltage VDD is not less than the read voltage V_SENSE.

[0032] Furthermore, the local read voltage generation described in this disclosure compensates for a transistor mismatch of PMOS P1 due to manufacturing differences between the read amplifiers. More precisely, during the pre-charge phase, PMOS P1 is in diode contact and adjusts its gate voltage V_PGATE to be approximately the read voltage minus the threshold voltage (V_PGATE = V_SENSE - |V_THP1|) of PMOS P1. The read voltage V_SENSE is related to the local voltage supply VDD by V_SENSE = V_IN = VDD - R_SENSE * I_BIAS. Fluctuations in V_PGATE are avoided by PMOS P1 setting its own gate voltage V_PGATE and using this same gate voltage V_PGATE during the read phase.

[0033] Fig. 2D is the circuit diagram of Fig. 2A, shown during its read phase. As will be described, the read voltage generation circuit 224A is configured during the read phase such that the read voltage V_SENSE is independent of the voltage supply VDD, unlike the pre-charge phase, during which the read voltage V_SENSE depends on the voltage supply VDD.

[0034] During the read phase, switch S2 is configured to be closed, and switches S3 and S4 are configured to be open. Read circuit 222 C is not connected to the voltage supply VDD, and therefore the read voltage V_SENSE is independent of VDD.

[0035] During this read phase, the bit line, which has a capacitance C_BL, is discharged with the cell current I_CELL plus the current flowing through transistor N1 (for example, bias current I_BIAS). The sampled voltage in C_SAMPLE is applied to the gate of PMOS P1. There is no current flowing through R_SENSE.

[0036] The local read voltage generation circuit 224D is advantageous compared to the global read voltage generation circuit of previous approaches in that a surge in the local voltage supply VDD does not interrupt the read operation, since the read voltage V_SENSE is independent of the voltage supply VDD. If, during the read phase, the read voltage V_SENSE were to remain dependent on the voltage supply VDD, as it is during the pre-charge phase, then a sudden increase, for example in the voltage supply VDD, would necessarily lead to an increase in the read voltage V_SENSE. The bit line voltage V_BL would essentially remain at the same level because the bit line is no longer coupled to the voltage supply VDD, since switch S1 is open, and would already be below the read voltage V_SENSE.Then, when the bit line voltage V_BL drops during the read phase, it would be lower than the read voltage V_SENSE. There is never a point at which the bit line voltage V_BL can transition from being greater than the read voltage V_SENSE to being less than the read voltage V_SENSE, which would indicate a cleared cell (logical "0"). This does not occur with the read voltage generation circuit 224D of the present disclosure, where, during the read phase, the read voltage V_SENSE is independent of the supply voltage VDD.

[0037] Fig. Figure 3 shows a flowchart of a method for reading a memory cell by a read amplifier according to an exemplary embodiment.

[0038] In step 310, during a pre-charging phase, the bit line C_BL of the memory cell is charged by the voltage supply VDD.

[0039] Next, in step 320, the read voltage generation circuit generates the read voltage V_SENSE. The read voltage V_SENSE depends on the voltage supply VDD during the pre-charge phase and is independent of the voltage supply VDD during the read phase.

[0040] Step 330 begins during the read phase, during which the signal circuit 122A, 222A, 22B, 222C is decoupled from the voltage supply VDD, but remains coupled to the bit line and is supplied by the bit line voltage V_BL.

[0041] In step 340, the read circuit compares the bit line voltage V_BL with the read voltage V_SENSE, and in step 350 it outputs a digital output signal at the digital output DO, which indicates a content of the memory cell.

[0042] The read amplifiers disclosed herein are described as drain-side read amplifiers, but the disclosure is not limited in this respect. Alternatively, the read amplifiers can be source-side read amplifiers.

[0043] Furthermore, bipolar transistors (for example, PNP or NPN) can be used instead of MOS transistors. A PNP can be used instead of an NPN, and a PMOS can be used instead of an NMOS. Accordingly, it is intended that the disclosure is limited only by the appended claims. The systems described herein could be converted into equivalent digital logic functions and still remain within the scope of the disclosure.

Claims

[1] A read amplifier of a memory cell, comprising: - a read voltage generation circuit configured to generate a read voltage that is dependent on a power supply which charges a bit line capacity of the memory cell during a pre-charge phase, and which is independent of the power supply during a read phase; and - a read circuit configured to compare a bit line voltage with the read voltage and output a digital output signal indicating the contents of the memory cell. [2] The reading amplifier according to claim 1, wherein the reading circuit comprises: - a voltage sensing system coupled between the bit line of the memory cell and the output of the read circuit; and - a current source that is coupled between the output of the reading circuit and the voltage source. [3] The reading amplifier according to claim 2, wherein the voltage sensing is a P-channel metal oxide semiconductor field-effect transistor (PMOS) and the current source is an N-channel metal oxide semiconductor field-effect transistor (NMOS). [4] The reading amplifier according to one of claims 2 or 3, wherein during the reading phase: - the voltage sensing is configured to discharge the bit line capacitance of the memory cell to the output of the read circuit when the bit line voltage of the memory cell is greater than the read voltage, and - the power source is configured to discharge the output of the read circuit to the voltage source when the bit line voltage of the memory cell is less than the read voltage. [5] The reading amplifier according to claim 3, wherein the reading voltage generation circuit comprises: - a first switch that is coupled between the bit line of the memory cell and the source of the PMOS; - a second switch that is coupled between the power supply and the source of the PMOS; and - a third switch that is coupled between the gate of the PMOS and the drain of the PMOS. [6] The reading amplifier according to claim 5, wherein during the pre-charging phase the first switch is configured to be open and the second switch and third switch are configured to be closed, so that the reading voltage depends on the voltage supply. [7] The reading amplifier according to one of claims 5 or 6, wherein during the reading phase the first switch is configured to be closed and the second and third switches are configured to be open, so that the reading voltage is independent of the power supply. [8] The reading amplifier according to any one of claims 5 to 7, wherein the reading voltage generation circuit further comprises: - a reading resistor coupled between the power supply and the second switch; and - a sensing capacity coupled between the gate of the PMOS and a stable voltage source, and configured to apply a voltage to the gate of the PMOS during the read phase. [9] A memory matrix comprising the memory cell coupled to the read amplifier according to any one of claims 1 to 8. [10] The memory matrix according to claim 9, further comprising a switch coupled between the power supply and the bit line, wherein the switch is closed during the pre-charging phase and the switch is open during the read phase.

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