Method, wafer-level package component and electronic device

Abstract

Procedure (200), comprising: Receiving (202) a processed wafer of an integrated circuit; Forming a metal plate (108, 308) on the machined wafer of an integrated circuit; Forming (206) a first dielectric layer (110, 310) on at least a partial area of ​​the wafer of an integrated circuit and at least a partial area of ​​the metal plate (108, 308); Forming (208) a rewiring layer structure at least on a partial area of ​​the metal plate (108, 308) and the first dielectric layer (110, 310); Forming (210) a second dielectric layer (114, 314) on the first dielectric layer (110, 310) and a sub-region of the rewiring layer structure; Forming (212) a pillar structure on the rewiring layer structure; Forming (216) a cast layer on the second dielectric layer (114, 314) and a part of the pillar structure (116, 316); Forming (214) a pier layer (120, 320) on the pier structure (116, 316) and a portion of the cast layer, wherein the pier layer (120, 320) extends from a first pier structure (116, 316) to a further pier structure (116, 316); and Forming (218) a metallization layer on the pillar layer (120, 320) and further comprising singling (220) the processed wafer of an integrated circuit, which includes cutting along a saw path (124, 324) that crosses the metallization layer, wherein the singling of the processed integrated circuit results in a wafer-level package component (100, 300) with terminal surface contacts exposed on at least two sides of the wafer-level package component (100, 300).

Description

background

[0001] Over the years, there have been advances in packaging technology, with the development of smaller, cheaper, more reliable, and more environmentally friendly packages. For example, chip-scale packaging techniques have been developed that use directly surface-mountable packages. Flat no-lead packaging techniques, such as quad-flat no-lead packaging (QFN) techniques, physically and electrically connect integrated circuit chips to printed circuit boards. Flat no-lead packaging techniques typically use a conductor frame that contains an integrated circuit chip (a die) mounted on it. The chip can be electrically connected to the conductor frame via wire bonding or flip-chip technology.

[0002] US Patent 2011 / 0227219 A1 discloses a wafer-level package (WLP) bump structure comprising a copper column. This column extends perpendicularly over a first distance from a fabricated WLP silicon surface and includes column sides as well as a distal section with a copper surface. A first encapsulation is arranged around the column sides and covers the fabricated WLP silicon surface. The copper surface is recessed a distance below the first encapsulation surface, creating a recessed area above the copper surface. An under-ball metallic (UBM) material is metallurgically bonded to the copper surface. The UBM comprises a first section within the recessed area and a second section above the recessed area. The encapsulation surface overlaps the recessed area.

[0003] According to US 6,326,701 B1, a chip-sized package and a method for its fabrication provide a removal zone as the first parting line. Coating materials are applied to the flanks of the removal zone, forming a resin layer, and a parting blade narrower than the removal zone is used to completely cut a second parting line. This allows the interface exposed by the first parting to be coated and protected.

[0004] US Patent 2012 / 0056328 A1 describes a semiconductor device with chip edge contacts. An integrated circuit chip has a passivation layer with a groove filled with a conductive material, extending from a contact to the chip edge. This forms a chip edge contact. Optionally, a via in the substrate can be positioned along the chip edge. In this case, the conductive material in the groove is electrically coupled to the via in the substrate, resulting in a larger chip edge contact. Summary

[0005] A wafer-level package, an electronic component, and a manufacturing process are described that include forming an exposed terminal tip of the wafer-level package to provide a solder filler structure on the wafer-level package. The solder filler can be optimized to improve reliability at the printed circuit board level and to provide easy visual inspection. In embodiments, the wafer-level component employing exemplary techniques according to the present disclosure comprises a machined semiconductor wafer containing at least one integrated circuit chip, a metal plate arranged on the at least one integrated circuit chip, a first dielectric layer arranged on the at least one integrated circuit chip and at least a portion of the metal plate, a rewiring layer formed at least partially on the metal plate and the first dielectric layer, and a second dielectric layer.The electronic component comprises a first pillar formed on the first dielectric layer and a portion of the rewiring layer, a casting layer formed at least partially on the second dielectric layer, a second pillar formed on the first pillar, and a metallization layer formed on the second pillar. Furthermore, an electronic component may include a printed circuit board and a wafer-level component as described above. In embodiments, a method for fabricating the surface-mount component, employing exemplary techniques according to the present disclosure, includes receiving a machined wafer of an integrated circuit, forming a metal plate on the machined wafer of an integrated circuit, forming a first dielectric layer on at least a portion of the wafer of an integrated circuit and at least a portion of the metal plate.forming a rewiring layer structure at least on a portion of the metal plate and the first dielectric layer, forming a second dielectric layer on the first dielectric layer and a portion of the rewiring layer structure, forming a pillar on the rewiring layer structure, forming a cast layer on the second dielectric layer and a portion of the pillar, forming a pillar layer on the pillar and a portion of the cast layer, wherein the pillar layer extends from a first pillar to a further pillar, forming a metallization layer on the pillar layer, and singulating the processed wafer of an integrated circuit, comprising cutting along a saw path traversing the metallization layer, wherein the singulation of the processed integrated circuit results in a wafer-level package with terminal pads.which are exposed on at least two sides of the wafer-level package.

[0006] This summary is intended to introduce, in simplified form, a selection of concepts that are further described in detail below. This summary is not intended to indicate any principal or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. Drawings

[0007] The detailed description is provided with reference to the accompanying figures. The use of the same reference numbers in different places in the description and the figures may denote similar or identical elements. Fig. Figure 1A is a schematic sectional view representing an embodiment of a wafer-level package containing an exposed terminal tip, according to an exemplary embodiment of the present disclosure. Fig. Figure 1B is a partial bottom view representing an embodiment of a wafer-level package containing an exposed terminal tip, according to an exemplary embodiment of the present disclosure. Fig. Figure 1C is a partial sectional view representing an embodiment of a wafer-level package containing an exposed terminal tip, according to an exemplary embodiment of the present disclosure. Fig. Figure 1D is a partial sectional view representing an embodiment of a wafer-level package containing an exposed terminal tip, wherein the wafer-level package is coupled to a printed circuit board, according to an exemplary embodiment of the present disclosure. Fig. Figure 2 is a flowchart illustrating an exemplary procedure for manufacturing a wafer-level package containing an exposed terminal tip, such as the one shown in Fig. Surface mounting components shown in 1A to 1D. Fig. 3A is a schematic sectional side view illustrating the fabrication of a wafer-level package, such as the one described in Fig. The component shown in 1A to 1D represents, according to the Fig. 2 methods shown. Fig. Figure 3B is a schematic sectional side view illustrating the fabrication of a wafer-level package, such as the one described in Fig. The component shown in 1A to 1D represents, according to the Fig. 2 methods shown. Fig. 3C is a schematic sectional side view illustrating the manufacturing of a wafer-level package, such as the one in Fig. The component shown in 1A to 1D represents, according to the Fig. 2 methods shown. Fig. 3D is a schematic sectional side view showing the manufacturing of a wafer-level package, such as the one in Fig. The component shown in 1A to 1D represents, according to the Fig. 2 methods shown. Fig. 3E is a schematic sectional side view illustrating the fabrication of a wafer-level package, such as the one in Fig. The component shown in 1A to 1D represents, according to the Fig. 2 methods shown. Detailed description Overview

[0008] Wafer-level packaging is a chip-scale packaging technique encompassing a variety of methods for packaging integrated circuit chips into packages at the wafer level, prior to segmentation. Wafer-level packaging extends wafer fabrication processes to include component interconnection and component protection techniques. Consequently, wafer-level packaging streamlines the manufacturing process by enabling the integration of wafer fabrication, packaging, testing, and pre-aging processes at the wafer level.

[0009] Devices using low-profile, no-lead packaging techniques, such as QFN packaging, provide good mechanical protection for the dies contained within the package by fully encapsulating the integrated circuit chips. However, low-profile, no-lead package devices (e.g., QFN package devices) can be expensive to manufacture and typically have relatively low pin counts (e.g., the pins of a QFN package are typically located along the bottom edge). QFN packages can be coupled to other devices, such as by using a solder joint to couple the package to a printed circuit board (PCB). However, the solder joint of a wafer-level QFN device to other devices is often not inspectable and can lead to reduced reliability at the PCB level compared to a frame-mounted QFN device with a solder joint.

[0010] Accordingly, a wafer-level package, an electronic component, and a manufacturing process are described that include forming an exposed terminal tip of the wafer-level package to provide a solder filler structure on the wafer-level package. The solder filler can be optimized to improve reliability at the printed circuit board level and to provide easy visual inspection. In embodiments, the wafer-level component employing exemplary techniques according to the present disclosure comprises a machined semiconductor wafer containing at least one integrated circuit chip, a metal plate arranged on the at least one integrated circuit chip, a first dielectric layer arranged on the at least one integrated circuit chip and at least a portion of the metal plate, and a rewiring layer formed at least partially on the metal plate and the first dielectric layer.A second dielectric layer arranged on the first dielectric layer and a portion of the rewiring layer, a first pillar formed on the rewiring layer, a casting layer formed at least partially on the second dielectric layer, a second pillar formed on the first pillar, and a metallization layer formed on the second pillar. Furthermore, an electronic device may include a printed circuit board and a wafer-level device as described above. In embodiments, a method for fabricating the surface-mount device, employing exemplary techniques according to the present disclosure, includes receiving a machined wafer of an integrated circuit, forming a metal plate on the machined wafer of an integrated circuit,Forming a first dielectric layer on at least a sub-region of the wafer of an integrated circuit and at least a sub-region of the metal plate, forming a rewiring layer structure on at least a sub-region of the metal plate and the first dielectric layer, forming a second dielectric layer on the first dielectric layer and a sub-region of the rewiring layer structure, forming a pillar on the rewiring layer structure, forming a casting layer on the second dielectric layer and a sub-region of the pillar, forming a pillar layer on the pillar and a sub-region of the casting layer, wherein the pillar layer extends from a first pillar to a further pillar, forming a metallization layer on the pillar layer, and singulating the processed wafer of an integrated circuit, comprising cutting along a saw path.which traverses the metallization layer, whereby singulation of the processed integrated circuit results in a wafer-level package with terminal contacts that are exposed on at least two sides of the wafer-level package. Examples of implementation

[0011] Fig. 1A to 1D represent a wafer-level package component 100 according to an exemplary embodiment of the present disclosure. As in Fig. As shown in Figure 1A, the wafer-level package component 100 can contain an integrated circuit chip 106. In embodiments, the integrated circuit chip 106 can contain at least one integrated circuit chip 106 formed from and / or as a partial region of a machined semiconductor wafer. The integrated circuit chip 106 can contain digital integrated circuits, analog integrated circuits, mixed-signal circuits, and so on. In one or more embodiments, the integrated circuit chip 106 can contain digital logic devices, analog devices (e.g., amplifiers, etc.), and combinations thereof, etc. In the embodiment shown in Fig. In the embodiment shown in Figure 1A, a partial area of ​​a machined semiconductor wafer is shown, containing a first housing 102 of an integrated circuit chip and a second housing 104 of an integrated circuit chip.

[0012] As described above, the integrated circuit chip 106 can be manufactured using various fabrication techniques. For example, the integrated circuit chip 106 can be manufactured using complementary metal-oxide-semiconductor (CMOS) techniques, bipolar semiconductor techniques, and so on. The integrated circuit chip 106 can contain electrical interconnects formed within it (e.g., integrated circuits, rewiring layers, vias, contact pads, etc.). In embodiments, the integrated circuit chip 106 can contain an active chip (e.g., a processor) and / or a passive chip (e.g., a capacitor, a transistor, etc.). Furthermore, the integrated circuit chip 106 can contain and / or be configured to interact with electrical interconnects (e.g., contact pads, metal plates such as copper and / or aluminum, under-hump metallization (UBM), etc.).) to couple, set up to provide an electrical connection between the integrated circuit chip 106 (by means of a rewiring layer, vias and / or other electrical intermediate connections) and an external component (e.g. a printed circuit board 130).

[0013] As in Fig. As shown in Figure 1A, the wafer-level package component 100 includes a metal plate 108 formed on the integrated circuit chip 106. In embodiments, the metal plate 108 can be configured to provide an electrical contact between the integrated circuit chip 106 and other metallic conductor paths, such as a pillar and / or rewiring conductor path (e.g., a rewiring layer structure 112). In one particular embodiment, a metal plate 108 includes an aluminum plate formed on the integrated circuit chip 106. In other embodiments, the metal plate 108 can contain metals other than aluminum, such as copper. The metal plate 108 can be formed using methods such as deposition (e.g., physical, chemical, plating, etc.).

[0014] The wafer-level package component 100 contains a dielectric layer 109 and a dielectric layer 110. As shown in Fig. As shown in Figure 1A, the dielectric layer 109 is formed on the surface of a machined semiconductor wafer with at least one integrated circuit chip 106 formed therein. In one particular embodiment, the dielectric layer 109 can contain a combination of silicon dioxide (SiO2) and silicon nitride (Si3N4). It is considered that other dielectric materials, such as PBO, etc., can be used to form the dielectric layer 109. As shown in Fig. As shown in Figure 1A, the dielectric layer 110 can be formed on a surface of the processed semiconductor wafer and / or the dielectric layer 109. Furthermore, the dielectric layer 110 can be arranged against the metal plate 108 and / or the dielectric layer 109 and cover a portion thereof. In some embodiments, the dielectric layer 109 and the dielectric layer 110 can be formed using the same or a similar material and / or using the same process step. In one particular embodiment, the dielectric layer 110 can be formed over the processed semiconductor wafer and the metal plate 108 (e.g., by coating or deposition) and subsequently etched to expose at least a portion of the metal plate 108.The dielectric layer 109 and / or the dielectric layer 110 can function as electrical insulation between the integrated circuit chip 106, the metal plates 108, and other electrical components. In some embodiments, the dielectric layer 110 can contain a benzocyclobutene polymer material (BCB), a polyimide material (PI), a polybenzoxazole material (PBO), an oxide material (e.g., silicon dioxide (SiO2)), and / or combinations thereof, etc. In one particular embodiment, the dielectric layer 110 contains polybenzoxazole (PBO).

[0015] As in Fig. As shown in Figure 1A, the wafer-level package component 100 further comprises a rewiring layer structure 112 formed on the metal plate 108 and a portion of the dielectric layer 110. In embodiments, the rewiring layer structure 112 functions as a rerouting and interconnection system for rewiring electrical connections within the wafer-level package component 100. The rewiring layer structure 112 can electrically connect a conductive plate (e.g., the metal plate 108) to another component (e.g., a solder bump, not shown). Furthermore, the rewiring layer structure 112 can also include other associated interconnection components, such as under-bump metallization (UBM), contact pads, metal conductors, and / or conductive paths, etc.In a particular embodiment, the rewiring layer structure 112 can include a titanium separating layer (Ti) and a copper seed layer (Cu) that is electroplated to its full thickness to form metal conductors and / or a conductive connection surface adjacent to and abutting the metal plate 108. As shown in . Fig. As shown in Figure 1A, a further (a second) dielectric layer 114 can be formed on the first dielectric layer 110 and a portion of the rewiring layer structure 112 in a similar manner to the first dielectric layer 110 described above, wherein the dielectric layer 114 can be formed over at least a portion of the rewiring layer structure 112 and subsequently etched and / or removed to expose at least a portion of the rewiring layer structure 112. In embodiments, the dielectric layer 114 can comprise a benzocyclobutene polymer material (BCB), a polyimide material (PI), a polybenzoxazole material (PBO), an oxide material (e.g., silicon dioxide (SiO2)), or other electrically insulating materials and / or combinations thereof, etc. In one particular embodiment, the dielectric layer 114 comprises polybenzoxazole (PBO).

[0016] Next, the pillar structure 116 can be arranged on a sub-area of ​​the rewiring layer structure 112, as shown in Fig. Figure 1A shows that in some embodiments the pillar structure 116 can be arranged on a portion of the rewiring layer structure 112 where a portion of the dielectric layer 114 is removed, thus providing suitable electrical contact between the rewiring layer structure 112 and the pillar structure 116. A pillar structure 116 can include a structure extending from the rewiring layer structure 112, thereby creating a gap between it and the rewiring layer structure 112. In some embodiments, the pillar structure 116 can include a separating layer of titanium (or titanium / tungsten) and / or galvanized copper, aluminum, or other conductive metal.

[0017] In embodiments, a pillar layer 120 is arranged on the pillar structure 116. As in Fig. As shown in Figure 1A, the pillar layer 120 can overlap a first pillar structure 116 and extend across a saw path 124 (before sawing and singulation) to a further (e.g., second) pillar structure 116. In one embodiment, the pillar layer 120 can contain a separating material (e.g., titanium, titanium / tungsten, etc.), aluminum, and / or copper. The pillar layer 120 can overlap each pillar structure 116, for example, the one shown in Figure 1A. Fig. Figure 1A shows a partially cantilevered arrangement. In embodiments, the pillar layer 120 is sawn through during the singulation process, and the exposed side of the pillar layer 120 provides an exposed terminal tip, which can provide an enlarged surface area for the adhesion of solder 126 and form a solder fillet, further providing solder joint strength and improved reliability at the printed circuit board level.

[0018] As in Fig. As shown in Figure 1A, the wafer-level package component 100 contains a casting layer 118. In embodiments, the casting layer 118 can contain plastic casting compounds, which may further contain composite materials such as epoxy resins, phenolic hardeners, silica, catalysts, pigments, thermosets, and mold release agents. In one particular embodiment, the casting layer 118 contains an epoxy-based material. The casting layer 118 can be formed on top of and / or below the dielectric layer 114, as well as the pillar structure 116 and the pillar layer 120. In embodiments, the casting layer 118 can serve to electrically insulate and mechanically support the pillar structure 116 and the pillar layer 120.The casting compounds used for the casting layer 118 in the wafer-level package component 100 can be selected to exhibit a low moisture absorption rate, high flexural strength at assembly temperatures, or a combination of both. In various embodiments, the casting layer 118 can be formed using processes such as injection molding, filling and curing with a thermoset, compression molding, transfer molding, etc.

[0019] Following the formation of a casting layer 118, a metallization layer 122 can be formed on a surface of the pier layer 120. As in Fig. 1A and Fig. As shown in Figure 1B, the metallization layer 122 can be formed on the exposed surface of the pillar layer 120. Fig. Figure 1B shows a top view of the wafer-level package component 100, which represents the metallization layer 122 formed on the pillar layer 120 and the casting layer 118. A saw path 124 through multiple metallization layers 122 is shown here, which, after sawing and singulation, form a first package 102 and a second package 104 of an integrated circuit chip. Additional packages of integrated circuit chips can be formed using this technique, although only two packages of integrated circuit chips are shown.

[0020] In embodiments, the metallization layer 122 can contain materials suitable for soldering, for example, lead-free metals such as a tin-silver-copper alloy (Sn-Ag-Cu) (i.e., SAC), a tin-silver alloy (Sn-Ag), a tin-copper alloy (Sn-Cu), etc. In one particular embodiment, a tin-lead material (PbSn) can be used as the metallization layer 122. The metallization layer 122 can be configured to be flush with the surface of the casting layer 118, or to be set off from the casting layer 122, as shown in Fig. Shown in 1A.

[0021] Fig. Figure 1C shows a side view of a single wafer-level package component 100. As in Fig. Figure 1C, a side view of the wafer-level package component 100, shows that the wafer-level package component 100 contains an integrated circuit chip 106, a cast layer 118, and a sawn metallization layer 122, which forms an exposed lead tip. The exposed lead tip is designed to adhere to solder 126 such that the connection of the solder 126 forms a solder fillet, resulting in a reinforced solder joint and increased reliability at the printed circuit board level.

[0022] Fig. Figure 1D shows a partial view of an exemplary electronic component 132, which includes a wafer-level package component 100 coupled to a printed circuit board 130 using solder 126 and a solder pad 128. As shown in Fig. In 1D, the solder 126 adheres to a sawn pillar layer 120 (exposed terminal tip) at the base of the wafer-level package component 100 (e.g., the side distal to the integrated circuits) and to the exposed pillar layer 120 on the side of the wafer-level package component 100 (e.g., with the surface of the pillar layer 120 resulting from the singulation process). In this example, solder 126 is in contact with several sides of the sawn pillar layer 120 (e.g., the side exposed by sawing and the metallization layer 122). This configuration results in a solder fillet and a solder protrusion structure. Exemplary procedures

[0023] Fig. 2 presents an exemplary method 200 that uses semiconductor packaging techniques to fabricate a wafer-level package component with an exposed terminal tip, such as the one in Fig. Wafer-level package component shown in 1A to 1D: 100. Fig. Figures 3A to 3E show a section through a machined semiconductor wafer 334 during the fabrication of an exemplary wafer-level package component 300 (such as the one in Fig. 1A to 1D shown wafer-level package component 100).

[0024] In the described procedure 200, a machined wafer of an integrated circuit and an integrated circuit chip are received (block 202). As in Fig. As shown in Figure 3A, receiving a machined semiconductor wafer 334 can include receiving a machined semiconductor wafer that has been machined to form one or more integrated circuits (e.g., a first integrated circuit chip package 302, a second integrated circuit chip package 304, etc.). In some embodiments, the machined semiconductor wafer 334 can include a dielectric layer 109 formed on the surface of the machined semiconductor wafer 334 with at least one exposed metal plate 108. In other embodiments, the dielectric layer 109 and / or the at least one metal plate 108 are formed after receiving the machined semiconductor wafer 334. The metal plate 108 can be pre-formed and exposed on the machined semiconductor wafer and the integrated circuit chip(s) 306.The formation of a metal plate 308 may involve the use of at least one suitable deposition technique, such as physical vapor deposition, chemical vapor deposition, molecular beam epitaxy, etc. Other techniques, such as lithography and etching, may be used to form the metal plate 308. The metal plate 308 may contain conductive material, such as copper and / or aluminum.

[0025] As in Fig. As shown in Figure 3A, a first dielectric layer is formed on the surface of the processed semiconductor wafer (Block 206). In embodiments, the first dielectric layer 310 can be deposited and / or formed over the dielectric layer 109 on the surface of the processed semiconductor wafer 334 and the metal plate(s) 308. The first dielectric layer 310 can be formed and / or deposited over the dielectric layer 109, the processed semiconductor wafer 334, and the metal plate(s) 308 using, for example, one or more suitable deposition techniques, such as those described above. In one embodiment, forming the first dielectric layer 310 can include coating the first dielectric layer 310 onto the dielectric layer 109, the processed semiconductor wafer 334, and / or the metal plates 308 using a rotational coating process.In other embodiments, forming the first dielectric layer 310 may involve the use of deposition techniques such as physical vapor deposition and / or chemical vapor deposition. After deposition, the first dielectric layer 310 may be etched and / or exposed to at least partially expose the metal plate(s) 308 using lithography and / or etching techniques. In embodiments, the first dielectric layer 310 may contain a suitable dielectric material, such as benzocyclobutene polymer (BCB), polyimide (PI), polybenzoxazole (PBO), silicon dioxide (SiO2), etc. In one particular embodiment, forming the first dielectric layer 310 involves forming a layer of polybenzoxazole (PBO).

[0026] As in Fig. As shown in Figure 3B, a rewiring layer structure is formed on the metal plate and the first dielectric layer (block 208). In embodiments, forming a rewiring layer structure 312 involves depositing a conductive material (e.g., copper, aluminum, etc.) on the metal plate 308 and at least a portion of the first dielectric layer 310, followed by selective etching of the deposited conductive material to form the rewiring layer structure 312. Suitable deposition methods may include sputtering, physical vapor deposition, electroplating, etc. Following deposition, the rewiring layer structure 312 may be etched as required using lithography and / or etching techniques.In one particular embodiment, forming the rewiring layer structure 312 involves forming a thin titanium separator layer (Ti) and a copper seed layer (Cu) on the metal plate 308 and / or the first dielectric layer 310, and further electroplating the copper seed layer to a desired copper thickness. In some other embodiments, the separator layer may contain other materials, for example, a titanium / tungsten layer (Ti / W). As shown in . Fig. As further shown in Figure 3B, a second dielectric layer is formed on the rewiring layer structure and the first dielectric layer (block 210). In embodiments, the formation of the second dielectric layer 314 can be similar to the formation of the first dielectric layer 310, such as using a rotary coating process or another deposition technique, lithography, and etching.

[0027] The second dielectric layer 314 can be selectively etched to at least partially expose at least a sub-region of the rewiring layer structure 312. In one embodiment, the second dielectric layer 314 can be formed using a suitable dielectric material, such as benzocyclobutene polymer (BCB), polyimide (PI), polybenzoxazole (PBO), silicon dioxide (SiO2), and so on.

[0028] Next, a pillar structure is formed on the rewiring layer structure (block 212). In some embodiments, the pillar structure 316 can be formed using a suitable copper plating process. In one embodiment that employs a metallization step, the formation of the pillar structure 316 involves forming a thin separating layer of titanium (other materials, such as titanium / tungsten, may also be used) and a thin copper seed layer, and then electroplating the copper seed layer to a desired thickness. The size, shape, and dimensions of the pillar structure 316 can vary according to the different design / manufacturing considerations of the wafer-level package component 100. In one embodiment, the pillar structure can be formed using a metallization process and then selectively etched to form a conductive pillar structure.

[0029] A pillar layer is formed on the pillar structure (block 214). In embodiments, the pillar layer 320 can be formed on the pillar structure 316 such that the pillar layer 320 extends from the first pillar structure to a second pillar structure or between several pillar structures, as shown in Fig. The pillar layer 320 is shown in 3D. It can be deposited or formed in a similar manner to the formation of the pillar structure 316, using deposition and / or metallization techniques. In one embodiment, forming the pillar layer 320 involves forming a thin titanium separator layer and a copper seed layer, followed by electroplating the copper seed layer to a desired thickness. In another embodiment, forming the pillar layer 320 can involve using physical deposition, lithography, and / or etching techniques. Furthermore, the pillar layer 320 can be pre-formed and then placed onto and coupled to the pillar structure 316 and the wafer-level package component 300. The pillar layer 320 can be designed such that a saw track 324 can traverse the formed pillar layer 320, resulting in an exposed connection tip in a single wafer-level package component 100.

[0030] A cast layer is formed (block 216). In embodiments, a cast layer 318 is formed on or encompassing the second dielectric layer 314, the pillar structure 316, the pillar layer 320, and / or the integrated circuit chip 306. As shown in Fig. 3C and Fig. As depicted in 3D, the formation of the second dielectric layer 314 can include forming a casting material around the pillar layer 320 and covering it. In one embodiment, the casting layer 318 can be formed before the pillar layer 320 is formed. In another embodiment, the casting layer 318 can be formed after the pillar layer 320 has been formed. In some embodiments, the formation of the casting layer 318 can involve the use of processes such as compression molding, heat pressing, selective encapsulation, injection molding, and / or other encapsulation and / or casting processes. In some embodiments, the casting material can, for example, include epoxy-based materials, silicone, and / or polyurethane. Generally, the casting layer 318 can include an insulating material designed to provide mechanical protection and environmental protection for the wafer-level package component 100.In one particular embodiment, forming a cast layer 318 involves potting with epoxy. Encapsulating the pillar structure 316 and / or the pillar layer 320 can serve to protect the wafer-level package component 100 and to electrically insulate the integrated circuit component 302. In other embodiments, the cast layer 118 is formed such that at least a portion of the pillar layer 320 is exposed.

[0031] Then, a metallization layer is formed on an exposed surface of the pillar layer (block 218). In some embodiments, forming the metallization layer 322 on the pillar layer 320 involves using a process such as deposition (e.g., sputtering, physical vapor deposition, etc.). In other embodiments, forming the metallization layer 322 may involve printing and / or coating the metallization layer 322. In still other embodiments, forming the metallization layer 322 may involve using a metallization process. In some embodiments, forming the metallization layer 322 may involve forming a material suitable for adhesion to a solder material while remaining conductive. In some embodiments, the metallization layer 322 can be a tin-silver-copper alloy (Sn-Ag-Cu) (i.e., SAC), a tin-silver alloy (Sn-Ag), a tin-copper alloy (Sn-Cu), copper, aluminum, etc.contain.

[0032] After the metallization layer has formed, the processed semiconductor wafer and the integrated circuits can be separated (block 220). In embodiments, separating the processed semiconductor wafer and / or each integrated circuit chip 306 may involve the use of a cutting saw. In one embodiment, and as described in Fig.Figure 3E shows that singulating an integrated circuit chip 306 can involve using a saw to cut through at least the metallization layer 322, the pillar layer 320, the casting layer 318, and / or the machined semiconductor wafer 334. In embodiments, the wafer-level package component 100 can be singulated and cut along a saw path 324 that traverses the metallization layer 322 and / or the pillar layer 320. In embodiments, a saw, such as the one used to singulate the machined semiconductor wafer, can be equipped with a circular, diamond-coated cutting blade. In this step, the machined semiconductor wafer 334 can be mounted in a frame and placed under the saw, with the saw blades operating at approximately 30,000 to 60,000 rpm in some embodiments. -1Rotate to cut along the saw path 124 while using a mixture of cutting fluid and water. Cutting through the pillar layer 320 exposes connection points, providing an additional solder adhesion surface designed to allow a solder fillet and / or solder stem.

[0033] After the wafer-level package component 100 has been fabricated, it can be further processed and / or coupled to a printed circuit board 130 or another substrate to form an electronic device 132 that can be used in other systems, such as mobile phones and / or computer systems. In one embodiment, the wafer-level package component 100 can be attached to a printed circuit board 130 using solder. In this embodiment, the solder joint 126 can be applied / adhered to the metallization layer 322 and the exposed side of the pillar layer 320 following the singulation and cutting process, forming a solder fillet and a solder pedestal structure that can result in improved reliability at the printed circuit board level.

Claims

[1] Procedure (200), comprising: Receiving (202) a processed wafer of an integrated circuit; Forming a metal plate (108, 308) on the machined wafer of an integrated circuit; Forming (206) a first dielectric layer (110, 310) on at least a partial area of ​​the wafer of an integrated circuit and at least a partial area of ​​the metal plate (108, 308); Forming (208) a rewiring layer structure at least on a partial area of ​​the metal plate (108, 308) and the first dielectric layer (110, 310); Forming (210) a second dielectric layer (114, 314) on the first dielectric layer (110, 310) and a sub-region of the rewiring layer structure; Forming (212) a pillar structure on the rewiring layer structure; Forming (216) a cast layer on the second dielectric layer (114, 314) and a part of the pillar structure (116, 316); Forming (214) a pier layer (120, 320) on the pier structure (116, 316) and a portion of the cast layer, wherein the pier layer (120, 320) extends from a first pier structure (116, 316) to a further pier structure (116, 316); and Forming (218) a metallization layer on the pillar layer (120, 320) and further comprising singling (220) the processed wafer of an integrated circuit, which includes cutting along a saw path (124, 324) that crosses the metallization layer, wherein the singling of the processed integrated circuit results in a wafer-level package component (100, 300) with terminal surface contacts exposed on at least two sides of the wafer-level package component (100, 300). [2] Wafer-level package component (100, 300), comprising: a machined semiconductor wafer (334) containing at least one integrated circuit chip (106, 306); a metal plate (108, 308) arranged on the at least one integrated circuit chip (106, 306); a first dielectric layer (110, 310) arranged on the at least one integrated circuit chip (106, 306) and at least one part of the metal plate (108, 308); a rewiring layer (112, 312), formed at least partially on the metal plate (108, 308) and the first dielectric layer (110, 310); a second dielectric layer (114, 314) arranged on the first dielectric layer (110, 310) and a part of the rewiring layer (112, 312); a pillar structure (116, 316) formed on the rewiring layer (112, 312); a cast layer (118, 318), formed at least partially on the second dielectric layer (114, 314); a pillar layer (120, 320) formed on the pillar structure (116, 316); a metallization layer (122, 322) formed on the pillar layer (120, 320); and further the processed wafer (334) is cut along a saw path (124, 324) that crosses the metallization layer (122, 322), wherein the singulation of the processed integrated circuit results in a wafer-level package component (100, 300) with terminal contacts that are exposed on at least two sides of the wafer-level package component (100, 300). [3] Wafer-level package component according to claim 2, wherein the metal plate (108, 308) arranged on the at least one integrated circuit chip (106, 306) contains aluminium. [4] Wafer-level package component according to claim 2, wherein at least one of the first dielectric layer (110, 310) and the second dielectric layer (114, 314) contains a polybenzoxazole material. [5] Wafer-level package component according to claim 2, wherein at least one of the first dielectric layer (110, 310) and the second dielectric layer (114, 314) contains a polyimide material. [6] Wafer-level package component according to claim 2, wherein at least one of the pillar structure (116, 316) and the pillar layer (120, 320) contains copper. [7] Wafer-level package component according to claim 2, wherein the pillar structure (116, 316) contains a separating material. [8] Wafer-level package component according to claim 2, wherein the pier layer (120, 320) forms a cantilever on the pier structure (116, 316). [9] Wafer-level package component according to claim 2, wherein the cast layer (118, 318) contains an epoxy-based material. [10] Wafer-level package component according to claim 2, wherein the metallization layer (122, 322) formed on the pillar layer (120, 320) contains tin. [11] Electronic device comprising: a printed circuit board (130); and a wafer-level package component (100, 300) coupled to the printed circuit board (130), wherein the wafer-level package (100, 300) contains: a machined semiconductor wafer containing at least one integrated circuit chip (106, 306); a metal plate (108, 308) arranged on the at least one integrated circuit chip (106, 306); a first dielectric layer (110, 310) arranged on the at least one integrated circuit chip (106, 306) and at least one part of the metal plate (108, 308); a rewiring layer (112, 312), formed at least partially on the metal plate (108, 308) and the first dielectric layer (110, 310); a second dielectric layer (114, 314) arranged on the first dielectric layer (110, 310) and a part of the rewiring layer (112, 312); a pillar structure (116, 316) formed on the rewiring layer (112, 312); a cast layer (118, 318), formed at least partially on the second dielectric layer (114, 314); a pillar layer (120, 320) formed on the pillar structure (116, 316); a metallization layer (122, 322) formed on the pillar layer (120, 320); and further the processed wafer (334) is cut along a saw path (124, 324) that crosses the metallization layer (122, 322), wherein the singulation of the processed integrated circuit results in a wafer-level package component (100, 300) with terminal contacts that are exposed on at least two sides of the wafer-level package component (100, 300). [12] Electronic device according to claim 11, wherein the metal plate (108, 308) arranged on the at least one integrated circuit chip (106, 306) contains aluminium. [13] Electronic device according to claim 11, wherein at least one of the first dielectric layer (110, 310) and the second dielectric layer (114, 314) contains a polybenzoxazole material. [14] Electronic device according to claim 11, wherein at least one of the first dielectric layer (110, 310) and the second dielectric layer (114, 314) contains a polyimide material. [15] Electronic device according to claim 11, wherein at least one of the pillar structure (116, 316) and the pillar layer (120, 320) contains copper. [16] Electronic device according to claim 11, wherein the pillar structure (116, 316) contains a separating material. [17] Electronic device according to claim 11, wherein the casting layer (118, 318) contains an epoxy-based material. [18] Electronic device according to claim 11, wherein the metallization layer (122, 322) formed on the pillar layer (120, 320) contains tin. [19] Electronic device according to claim 11, further comprising a soldering pre-assembly structure coupled to a solder pad of the printed circuit board (130) and coupled to at least a part of an exposed terminal tip of the wafer-level package (100, 300).

Images