System and method for a switchable capacity

Abstract

Switchable capacitor circuit comprising the following: a multitude of capacitive switching cells, each capacitive switching cell comprising the following: a capacitor circuit with a capacitor between a first terminal and a second terminal of the capacitor circuit; and a semiconductor switching circuit comprising the following a first connection that is coupled to the first connection of the capacitor circuit, a plurality of series-connected high-frequency switching cells comprising a load path and a common node, wherein each of the plurality of series-connected high-frequency switching cells comprises a switching transistor and a gate resistor having a first end coupled to a gate of the switching transistor and a second end coupled to the common node and a resistor circuit with a first end coupled to the common node and a second end coupled to a control node, wherein the resistor circuit includes a resistor between the first end and the second end.

Description

Technical area

[0001] The present disclosure relates generally to an electronic device and, more particularly, to a system and method for a switchable capacitance. background

[0002] Tunable passive elements, such as capacitors and inductors, are used in a variety of radio frequency (RF) circuits to implement tunable matching networks for antennas and power amplifiers, and to provide tunable tuning for radio frequency filters. Due to the high demand and manufacturing of portable devices, such tunable passive elements can be found in products such as mobile phones, smartphones, and portable computers. Providing tuning for RF circuits in such products enables these products to provide high-performance RF transmission and reception under a variety of RF conditions. Programmable tuning is also useful in RF devices configured to operate across different RF bands and / or configured to operate using different standards.

[0003] Tunable capacitors can be implemented in a number of ways. For example, a voltage-controlled capacitor can be used to provide variable capacitance. Such variable capacitance can be implemented using a reverse-biased diode junction with a capacitance inversely proportional to the applied reverse bias voltage. Another way in which tunable capacitance can be implemented is by using an array of switchable capacitors whose various elements are either connected or disconnected via controllable switches. One challenge in designing a switchable capacitor is dealing with the effects of parasitic capacitance from transistors used to implement the switches.Such parasitic capacitances associated with the switching transistors may add additional capacitance to the switchable capacitance, which may reduce the accuracy of the circuit and / or increase the parasitic load.

[0004] A. Thomas et al., "A high-quality factor bulk-CMOS switch-based digitally programmable RF capacitor" in Microwave Conference (APMC), 2014 Asia-Pacific, pp. 58-60, 2014, discloses a tunable capacitor with series-connected high-frequency switching cells. A similar arrangement is also known from A. Thomas et al., "A MIM-cap free digitally tunable NMOS capacitor," in Microwave Integrated Circuits Conference (EuMIC), pp. 2-24, 2013.

[0005] DE 10 2014 106 633 A1 discloses another switchable capacitance circuit with a plurality of cells.

[0006] DE 10 2014 115 295 A1 discloses a circuit with several varactor transistors implemented as field-effect transistors.

[0007] DE 10 2014 210 199 A1 discloses a device for antenna tuning with a variable capacitance.

[0008] It is therefore a task to provide improved opportunities for tunable capacities. Short summary

[0009] A switchable capacitance circuit according to claim 1, a method according to claim 12, and a tunable high-frequency circuit according to claim 18 are provided. The subclaims define further embodiments.

[0010] In accordance with one embodiment, a switchable capacitance circuit comprises a plurality of capacitance switching cells, each of which comprises a capacitance circuit having a capacitance between a first terminal and a second terminal of the capacitance circuit, and a semiconductor switch circuit having a first terminal connected to the first terminal of the capacitance circuit, a plurality of series-connected radio frequency (RF) switching cells having a load path and a common node. Each of the plurality of series-connected RF switching cells comprises a switching transistor and a gate resistor having a first end connected to a gate of the switching transistor and a second end connected to the common node.The switchable capacitance circuit also includes a resistance circuit having a first end connected to the common node and a second end connected to a control node. Brief description of the drawings

[0011] For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which: Fig. 1a-c shows conventional switched capacitor circuits; Fig. Figure 2 shows an embodiment of a switched capacitor circuit; Fig. 3 shows another embodiment of a switched capacitor circuit; Fig. 4 shows a bare-chip photograph of an embodiment of a switched capacitor circuit; Fig. 5a-b are Smith charts showing the performance of one embodiment of a switched capacitor circuit; Fig. 6 shows a flowchart of a method of an embodiment; Fig. 7a-b show RF systems according to an embodiment; and Fig. 8 shows an embodiment of an RF circuit.

[0012] Corresponding numbers and symbols in different figures generally refer to corresponding components unless otherwise noted. The figures are provided to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily to scale. To further illustrate certain embodiments, a number in a figure may be followed by a letter indicating variations of the same structure, material, or processing step. Detailed description of exemplary embodiments

[0013] The making and using of the present preferred embodiments are discussed in detail below. However, it should be recognized that the present invention provides many applicable inventive concepts that may be practiced in a wide variety of specific contexts. The specific embodiments discussed are merely examples of specific ways to make and use the invention and do not limit the scope of the invention.

[0014] The present invention is described with reference to preferred embodiments in a specific context, a system and method for a switchable capacitance that can be used in RF circuits to provide tuning for antennas, matching networks, and filters. The invention can also be applied to other systems and applications, including other circuits that use a programmable capacitance such as digitally tunable oscillators to enable a wide output frequency range and that use charge pumps to enable variable frequency operation.

[0015] In embodiments of the present invention, a switchable capacitance circuit comprises a plurality of capacitors connected in series with associated switches implemented using the series-connected switching transistors. Each switching transistor is associated with a gate resistor connected in series with its gate and a common node, and another resistor is coupled between the common node and a driver circuit. This another resistor can be configured to reduce the effect of a load from a combination of parasitic capacitances of the series-connected switching transistors and parasitic capacitances of the gate resistors. Furthermore, the common resistors can be dimensioned to control the turn-on and turn-off time constants of each branch of the switchable capacitance circuit.

[0016] Fig. Figure 1a shows a conventional digitally tunable capacitor circuit 100 comprising binary weighted capacitors 104, 106, 108, 110 and 112, each of which is connected to series switches 120, 122, 124, 126 and 128, respectively.

[0017] The values ​​of capacitors 104, 106, 108, 110, and 112 are 8 pF, 4 pF, 2 pF, 1 pF, and 0.5 pF, respectively. Each of capacitors 104, 106, 108, 110, and 112 is connected to output pad 102 as well as to electrostatic discharge (ESD) protection transistor 113. The amount of capacitance seen at output pad 102 is controllable using digital signals D4, D3, D2, D1, and D0. For example, if signal D3 is at a logic high, turning on series switch 122 and signals D4, D2, D1, and D0, or at a low, turning off series switches 120, 124, 126, and 128, then the capacitance load seen at output pad 102 is about 4 pF. Similarly, if signals D3, D2, D1, and D0 are all at a logic high, the load seen at output pad 102 is about 15.5 pF.

[0018] Many systems that use digitally tunable capacitors can be subject to higher voltages across the digitally tunable capacitor. One example is the antenna interface of a mobile phone. For example, the mobile phone's transmit power amplifier can achieve approximately 35 dBm of power at the output into a nominal impedance of 50 ohms, corresponding to a voltage of approximately 18 V. However, impedances far exceeding 50 ohms can occur at the antenna interface, which can result in transient voltages in the range of 50 V to 60 V. Since devices in many semiconductor processes are only capable of withstanding voltages in the range of 10 V, device stacking is used to prevent device failure and destruction. As shown, each of the capacitors 104, 106, 108, 110, and 112 is implemented using a series combination of capacitors.Similarly, series switches 120, 122, 124, 126, and 128 are implemented using series-connected transistors 116, each of which has a resistor 118 connected in series with its gate. Resistors 118 maintain the gate impedance high enough not to affect the RF impedance of the capacitor-switch combination.

[0019] An important quality factor for a capacitor is the Q factor, which is defined as follows: Q=Im(z)Re(Z), where Z is the complex impedance of the capacitive element, Im(Z) is the imaginary part of the impedance, and Re(Z) is the real part of the impedance. If a capacitor is connected in series with a switch, the following approximation can be assumed: Im(Z)=Im(1jωC)=1ωC, Re(Z)=Ran, where C is the value of the capacitance, Ran is the on-resistance of the switch, and ω is the angular frequency. Therefore, the Q of the capacitor can be expressed as follows: Q=(1ωC)Ran

[0020] As shown above, the Q-factor improves as C or Ran decreases. Therefore, the more devices connected in series, the lower the Q-factor. Accordingly, the corresponding Ran decreases as the capacitance and frequency increase to maintain a given Q-factor. However, in some cases, the corresponding lower heterodyne capacitances can increase as a transistor width is increased to lower the Ran. The above equation further shows that Ran and the transistor width can be scaled with capacitance to achieve a capacitance-independent "smooth frequency response" of the Q-factor for all possible switching combinations.

[0021] Fig. Figure 1b shows a schematic diagram of an exemplary RF switch 130 that has been provided with various parasitic elements and is connected to the corresponding driver 127. As shown, switch 130 comprises series MSWs with parasitic gate-drain capacitances Cgs and gate-source capacitances Cgs. When switch 130 is off, the series combination of parasitic capacitances Cgs and Cgd spreads the RF signal present at the input node In1 or at the output node Out homogeneously across transistors MSW. To prevent distortion of the RD signal, the resistance of RGATE and RDS can be selected high enough to ensure that capacitances Cgs and Cgd appear as series-connected capacitances to prevent a parasitic load at input node In1 and output node Out. Example values ​​for RGATE and RDS are 400 kΩ and 400 kΩ, respectively; However, other values ​​can also be used.Under non-ideal conditions, the degree of isolation achieved by the resistors RGATE may be limited by the parasitic capacitance Cbp associated with the resistors RGATE and by and the shunt capacitance of resistor RDS represented by capacitance Cp.

[0022] Parasitic capacitances Cbp and Cp can result from non-idealities in the physical implementation of resistor RGATE. For example, when resistor RGATE and / or RDS are placed on the substrate using polysilicon, a small value of bypass capacitance results. For example, a 400 kΩ resistor may have a 2 fF bypass capacitance, depending on the particular resistor design. At 1 GHz, a 2 fF capacitance corresponds to a capacitive impedance of 80 kΩ, thereby reducing the total effective impedance of RGATE at 1 GHz. It should be recognized that this is only one specific example of a physical resistor. Other resistor embodiments may have different resistance values ​​and / or other parasitic capacitances associated with them.

[0023] When multiple transistors are stacked, the effect of the parasitic capacitance of resistor RGATE on device isolation is further exacerbated. For example, in one embodiment, 40 transistors are stacked in a series configuration using 1.5V technology to accommodate RF voltage fluctuations of approximately 60V. Each of these 40 transistors has an associated gate resistor. When the switch is off, the parallel combination of 40 gate resistors, along with their associated parasitic capacitance, reduces the effective impedance isolating the gate of the transistors when the transistors are off.With reference to the previous example, stacking 40 devices, each having an associated 400 kΩ resistor with 2 fF of parasitic capacitance, results in an effective impedance of a 20 kΩ resistive impedance connected in parallel with a 2 kΩ capacitive impedance, resulting in very little gate isolation when the switching transistors are turned off.

[0024] Inverter-type drivers such as driver 127, which use transistors 140 and 142, provide a very low impedance at the gates of transistors MSW of switch 130. In some implementations, this low impedance may appear as an RF ground. Furthermore, if the parasitic capacitances Cgs and Cgs are applied with a low impedance, the parasitic capacitance seen at input node In1 and output node Out is further increased due to the effect of the parasitic capacitance Cbp added in parallel. The parasitic capacitance seen at input node In1 and output node Out increases when multiple transistors are stacked and when the widths of transistors MSW are increased. Thus, the RON*-Cout figure of merit, which is often used for RF switches, is reduced because Cbp reduces the impedance of the gate resistor RGATE.

[0025] As the frequency increases, the impedance of gate resistors RGATE decreases due to parasitic capacitances Cbp, causing capacitive coupling between interface nodes In1 and Out of switch 130 and the control output of driver 127, which may be an RF ground. In such a case, a parasitic shunt capacitance is formed by Cgs / Cgs and Cbp, adding a parasitic shunt capacitance to the adjustable capacitance circuit. This additional parasitic capacitance may, in some cases, require a change in the topology of an RF matching circuit. Such a change may, for example, involve additional components.

[0026] Fig. Figure 1c shows switch 132 in which resistors RDS are connected in parallel with the source / drain connections of transistors MSW, instead of coupling a source / drain connection to ground. The value of RDS in this case can be in the range between approximately 20 kΩ and approximately 40 kΩ; however, other values ​​outside this range can also be used, depending on the particular application and its requirements. Again, the parasitic shunt capacitance of each gate resistor RGATE is represented by capacitance Cbp, and the parallel capacitance of resistor RDS is represented by capacitance Cp. In such a circuit, the source / drain connections are biased to ground via an additional resistor (not shown) coupled to ground or coupled to ground via a switch input.

[0027] Fig. Figure 2 shows one embodiment of a tunable capacitor circuit 200 including binary-weighted capacitors 104, 106, 108, 110, and 112, each connected in series with switches 220, 222, 224, 226, and 228, respectively. Based on the state of digital input bus DIG, control unit 204 generates control signals D4, D3, D2, D1, and D0 that control the value of the capacitance seen at output pad 102. Control unit 204 may include a series interface connected to digital bus DIG, which may be implemented, for example, using an SPI interface, an I2C interface, MIPI / RFFE, or other series interface known in the art. In alternative embodiments of the invention, control unit 204 may be implemented using a parallel interface.Control unit 204 may determine signals D4, D3, D2, D1, and D0 using digital circuitry known in the art, such as a decoder or a look-up table. In some embodiments, the performance of control unit 204 may be programmable using non-volatile memory, fuses, mask-programmable memory, or other programming circuitry and techniques known in the art.

[0028] As shown, series switches 220, 222, 224, 226, and 228 each include a common resistor 202 coupled between respective control signals (D4, D3, D2, D1, and D0) and gate resistors 118. Adding this resistor creates a higher impedance in series with the parasitic shunt capacitance associated with resistors 118, thereby reducing the parasitic capacitive load on tunable capacitor circuit 200. As shown, transistors 116 are implemented using NMOS devices; however, transistors 116 may be implemented using a PMOS device or other transistor type in a CMOS bulk, CMOS SOI using thin film or thick film silicon on an insulator (SOI), GaAs HEMTs, or other FET transistor type technology. In some cases PIN diodes can also be used.The capacitors within capacitances 104, 106, 108, 110, and 112 may be implemented using metal-insulator-metal (MIM) capacitors and may include a plurality of capacitors connected in series. In alternative embodiments, a single capacitor may be used, e.g., in embodiments where a single capacitor can withstand the maximum applied AC voltage swing.

[0029] In a specific embodiment, the value of resistors 118 is approximately 100 kΩ, and the value of common resistors 202 is 10 kΩ for series switch 220 connected to 8 pF capacitor 104, 20 kΩ for series switch 222 connected to 4 pF capacitor 106, 40 kΩ for series switch 224 connected to 2 pF capacitor 108, 80 kΩ for series switch 226 connected to 1 pF capacitor 110, and 160 kΩ for series switch 228 connected to 0.5 pF capacitor 112. By scaling the resistance of common resistors 202 as inversely proportional to each corresponding capacitor, the RC time constant of the switching time for each branch can be kept substantially constant. As further described in Fig. As shown in Figure 2, the width of the transistors used to switch transistors 116 is proportional to each corresponding capacitor. For example, a 20 mm transistor width is used in switch 220, a 10 mm width is used in series switch 222, a 5 mm width is used in series switch 224, a 2.5 mm width is used in series switch 226, and a 1.25 mm width is used in switch 228. Alternatively, other widths may be used.

[0030] It should be recognized that the topology of the tunable capacitor circuit 200 shown in Fig. 2, as well as its component values, number of branches, transistor widths, and control unit, are only one example of many implementations of tunable capacitor circuits. In alternative embodiments, the tunable capacitor circuit may have different capacitance and resistance values, a different number of branches, different capacitor implementations, and different topologies. For example, embodiments of tunable capacitor circuits may further incorporate circuits and methods described in U.S. Patent Application No. 13 / 894,096, entitled "System and Method for a Switchable Capacitance," filed May 14, 2013, the entire application of which is incorporated herein by reference.

[0031] Fig. Figure 2 shows a schematic representation of an embodiment of a switch circuit with N-series transistors, gate resistors R G1, which are coupled between the gates of the series transistors and a common node, and common resistance R G2 , which is coupled between the common node and a voltage source, the voltage U O As shown, current i generated by the voltage source is divided by N among the N-series transistors and is used to determine the gate-source capacitance C GS each series transistor. Voltage u C is generated between the gate and source of each series transistor. An expression for the time constant τ of the gate charge time of the series transistors can be derived as follows: iN=CGS⋅ducdt Uo=i.RG2+iN.RG1+uc Uo=(N.RG2+RG1).CGS.ducdt+uc τ=(N.RG2+RG1).CGS. Under Using the above equation for time constant τ and the relationship that the gate-source capacitance C GSof a transistor is proportional to the width of the transistor, a value for R G2 for a given N, R G1 , C GS and time constant τ can be determined as follows: RG2≤τ−RG1.CGSN.CGS

[0032] In some embodiments, R G2 as large as possible to obtain the same time constant τ. Alternatively, this calculated value for R G2 be treated as a maximum value. In some embodiments, the switching time for each capacitor switching branch is set to be the same according to the above expression.

[0033] Fig. Figure 4 shows a die photograph of an embodiment of an integrated circuit (IC) 400 with a 6-bit tunable capacitor. As shown, a tunable capacitor 410, represented by a capacitor symbol, has a first electrode connected to pins 402 and 404 and a second electrode connected to pins 406 and 408. In one embodiment, capacitor 410 may be programmed to achieve capacitance values ​​between about 0.5 pF and about 5 pF. It should be appreciated that in alternative embodiments of the present invention, capacitor 410 may be configured to achieve capacitance values ​​below 0.5 pF and higher than 5 pF. Furthermore, while the connections to IC 400 are shown as solder balls, other types of package and die connections known in the art may also be used.

[0034] Fig. 5a and Fig. 5b shows Smith charts showing the impedance of switchable capacitor circuits in different capacitor settings. Fig. Figure 5a shows a Smith chart of a circuit in which the common resistance R G2 was omitted. Line 504 represents a locus curve, and line 502 represents an ideal switchable capacitor circuit. Mark m4 represents a small capacitance setting, such as 0.5 pF, and mark m3 represents a large capacitance setting, such as 5 pF. As shown, line 504 deviates from the ideal capacitance represented by line 502. In particular, the real part of the impedance is less than a normalized resistance of 1. For example, the real part of the normalized impedance at the minimum capacitance setting is approximately 0.615, while the real part of the normalized impedance at the maximum capacitance setting is approximately 0.410.

[0035] Fig. Figure 5b shows a Smith chart of a circuit in which common resistance R G2 used in accordance with embodiments described herein. Line 506 represents a locus, and line 502 represents an ideal switchable capacitor circuit. As shown, line 506 has less deviation from the ideal capacitance indicated by line 502 than line 504 in Fig. 5a. In particular, the real part of the impedance in the example from Fig. 5a is closer to a normalized resistance of 1 than the example from Fig. 5a. For example, the real part of the normalized impedance is about 0.830 at the minimum capacitance setting, while the real part of the normalized impedance at the maximum capacitance setting is about 1.075, which is closer to a normalized true impedance of 1 than line 504 from Fig. 5a. It must be acknowledged that the example from Fig. Figure 5b illustrates the performance of a specific exemplary embodiment. Other embodiments may behave differently.

[0036] Fig. 6 shows a flowchart of an embodiment of a method 600 that operates a switchable capacitance circuit. In step 602, a load capacitance of an embodiment of a switchable capacitance circuit is increased by turning on at least one of a plurality of capacitance switching cells. Such an embodiment of a switchable capacitance circuit may include a semiconductor switch circuit having a common resistor connected to respective gate resistors of a plurality of series switching transistors. Turning on at least one of a plurality of capacitance switching cells may, for example, comprise activating the semiconductor switch circuit of at least one of the plurality of capacitance switching cells. Thereafter, in step 604, the load capacitance is reduced by turning off, which may, for example, comprise deactivating the semiconductor switch circuit of at least one of the plurality of capacitance switching cells.

[0037] Fig. 7a-b show examples of how an embodiment of switchable capacitance circuits can be connected to antennas. As in Fig. As shown in Figure 7a, system 700 circuit 702 includes one embodiment of a switchable capacitance circuit 704 connected to antenna 706. In one embodiment, switchable capacitance circuit 704 can be adjusted to provide matching to antenna 706.

[0038] Fig. Figure 7b shows system 720 including a flat inversion-F (PIFA) antenna 722 connected to circuit 724 including one embodiment of a switchable capacitance circuit 726. In one embodiment, the switchable capacitance circuit 726 can be adjusted to provide matching for tuning the PIFA antenna 720.

[0039] Fig.8 shows an embodiment of an integrated circuit 800 that includes an embodiment of a switchable capacitance circuit 814 coupled between pins C+ and C-. Drivers 812 provide control signals within the switchable capacitance circuit 814. The state of these control signals can be set using control unit 810, which can be implemented, for example, using a MIPI, an RFEE, or another type of series control unit. Capacitance settings can be input to the control unit 810 using interface pins S_DATA, S_CLOCK, and VIO, and electrostatic discharge (ESD) circuit 806 provides ESD protection for circuitry coupled to these interface pins. Another electrostatic discharge (ESD) circuit 816 is also included to provide ESD protection for the switchable capacitance 814.Voltage regulator 802 and charge pump 804 provide the required voltage levels to operate drivers 812. As illustrated, voltage regulator 802 provides a positive supply upon which driver 812 bases positive control signal levels, and charge pump 804 generates a negative supply upon which driver 812 bases negative control signal levels. Charge pump 804 may further generate a bias level for a substrate of integrated circuit 800. It should be appreciated that integrated circuit 800 is only one example of many possible circuit implementations of an embodiment of switchable capacitance circuits.

[0040] In accordance with one embodiment, a switchable capacitance circuit comprises a plurality of capacitance switching cells, each comprising a capacitance circuit having a capacitance between a first terminal and a second terminal of the capacitance circuit and a semiconductor switch circuit having a first terminal connected to the first terminal of the capacitance circuit; a plurality of series-connected radio frequency (RF) switching cells having a load path and a common node. Each of the plurality of series-connected RF switching cells has a switching transistor and a gate resistor with a first end connected to a gate of the switching transistor and a second end connected to the common node.The switchable capacitance circuit also includes a resistance circuit having a first end connected to the common node and a second end connected to a control node, wherein the resistance circuit includes a resistor between the first end and the second end. The second terminal of each capacitance circuit of the plurality of capacitance switching cells may be coupled to the same node, and a second terminal of the semiconductor switch circuit of each of the plurality of capacitance switching cells may be coupled to ground.

[0041] In one embodiment, a value of the resistance of the resistance circuit is inversely proportional to a value of the capacitance of the capacitance circuit in the plurality of switching capacitance cells. Furthermore, a value of the capacitance of the capacitance circuit of a first of the plurality of switching capacitance cells may differ from a value of the capacitance of a second of the plurality of switching capacitance cells. In some embodiments, a value of the resistance of the resistance circuit is inversely proportional to the value of the capacitance of the capacitance circuit in the plurality of switching capacitance cells.

[0042] In one embodiment, the resistance circuit comprises a resistor coupled between the first end and the second end of the resistance circuit, and the capacitance circuit comprises a capacitor coupled between the first terminal and the second terminal of the capacitance circuit. The capacitor may comprise a plurality of capacitors connected in series. In some embodiments, the resistor has a value substantially equal to a value of the resistance between the first end and the second end of the resistance circuit, and the capacitor has a value substantially equal to a value of the capacitance between the first terminal and the second terminal of the capacitance circuit. Values ​​of the capacitance of the capacitance circuit from the plurality of capacitance switching cells may be binary weighted.

[0043] In one embodiment, the switchable capacitance circuit may further comprise a control circuit having a plurality of outputs connected to the corresponding control nodes of the plurality of capacitance switching cells. In some embodiments, a resistance value of each resistance circuit of the plurality of capacitance switching cells is selected such that each of the plurality of capacitance switching cells has a substantially uniform switching time.

[0044] In accordance with another embodiment, a method for operating a switchable capacitance circuit comprises increasing the load capacitance of the switchable capacitance circuit by switching on at least one of the plurality of capacitance switching cells. Switching on comprises activating the semiconductor switch circuit of at least one of the plurality of capacitance switching cells. The method further comprises decreasing the load capacitance of the switchable capacitance circuit by switching off at least one of the plurality of capacitance switching cells, wherein switching off comprises deactivating the semiconductor switch circuit of at least one of the plurality of capacitance switching cells. Each of the plurality of capacitance switching cells comprises, for example, a capacitance circuit having a capacitance between a first terminal and a second terminal of the capacitance circuit and a semiconductor switch circuit.The semiconductor switch circuit includes a first terminal connected to the first terminal of the capacitance circuit, a plurality of series-connected radio frequency (RF) switching cells having a load path and a common node, and a resistance circuit. Each of the plurality of series-connected RF switching cells includes a switching transistor and a gate resistor having a first end connected to a gate of the switching transistor and a second end connected to the common node. The resistance circuit has a first end connected to the common node and a second end connected to a control node, wherein the resistance circuit includes a resistor between the first and second ends.

[0045] In one embodiment, activating the first semiconductor switch circuit of at least one of the plurality of capacitance switching cells comprises activating the plurality of series-connected RF switch cells of at least one of the plurality of capacitance switching cells via the control node. A value of the resistance of the resistance circuit may be inversely proportional to a value of the capacitance of the capacitance circuit of the plurality of switching capacitance cells.

[0046] In one embodiment, the method further comprises applying an RF signal to a switchable capacitance circuit. The method may further comprise coupling the switchable capacitance circuit to an antenna and tuning the antenna by increasing and decreasing the load capacitance of the switchable capacitance load. In some embodiments, the method further comprises receiving a command from a digital interface and decrypting the command. Increasing and decreasing the load capacitance may further comprise selectively activating the first semiconductor switch circuit from the plurality of capacitance switching cells according to the decrypted command.

[0047] In accordance with further embodiments, a tunable radio frequency (RF) circuit comprises a semiconductor substrate and a plurality of capacitance switching cells disposed on the semiconductor substrate. Each capacitance switching cell comprises a capacitor coupled between a first terminal and a second terminal, and a semiconductor switch circuit having a first terminal connected to the first terminal of the capacitance circuit, a plurality of series-connected radio frequency (RF) switching cells, and a common resistor. The plurality of series-connected radio frequency (RF) switching cells each comprises a switching transistor and a gate resistor having a first end connected to a gate of the switching transistor and a second end connected to the common node.The common resistor has a first end connected to the common node and a second end connected to a control node.

[0048] In one embodiment, a capacitance of the capacitor is inversely proportional to a resistance of the common resistor. In one example, values ​​of the capacitors of the capacitance circuit from the plurality of capacitance switching cells are binary weighted. The switching transistor can be implemented using a MOSFET transistor. In some cases, the gate width of the MOSFET is inversely proportional to a capacitance of the capacitor. This capacitor can, for example, comprise a metal-insulator-metal (MIM) capacitor.

[0049] In one embodiment, the tunable RF circuit further comprises a driver circuit connected to the control nodes of the plurality of capacitance switching cells and may further comprise at least one of a charge pump and a voltage regulator connected to the driver circuit. The driver circuit, the charge pump, and / or the voltage regulator may also be arranged on the semiconductor substrate.

[0050] Advantages of embodiments of the present invention include the ability to create a switchable capacitance circuit with more precise capacitance due to the reduction of parasitic loading of capacitances associated with resistors connected to gates of switching transistors. Another advantage includes the ability to switch multiple switching capacitance branches with the same time constant. Further advantages of embodiments include better decoupling from an RFIC versus a logic IC, as well as better leakage performance.

[0051] While this invention has been described with reference to exemplary embodiments, this description is not intended to be limiting. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to the description. For example, switch drivers of one embodiment may be used to tune oscillators by switching capacitors or other tuning components on and off. Switch driver circuits of one embodiment may also be applied to receiver / transmit switches, attenuators, power gain bypass circuits, RF matching, RF filter switching in general, and other types of circuits and systems.

Claims

[1] Switchable capacitance circuit comprising: a plurality of capacitance switching cells, each capacitance switching cell comprising: a capacitance circuit having a capacitance between a first terminal and a second terminal of the capacitance circuit; and a semiconductor switching circuit comprising a first terminal coupled to the first terminal of the capacitance circuit, a plurality of series-connected high-frequency switching cells comprising a load path and a common node, wherein each of the plurality of series-connected high-frequency switching cells comprises a switching transistor and a gate resistor having a first end coupled to a gate of the switching transistor and a second end coupled to the common node, and a resistive circuit having a first end coupled to the common node and a second end coupled to a control node, the resistive circuit comprising a resistor between the first end and the second end. [2] The switchable capacitance circuit of claim 1, wherein the second terminal of each capacitance circuit of the plurality of capacitance switching cells is coupled to the same node. [3] The switchable capacitance circuit according to claim 1 or 2, wherein a value of the resistance of the resistance circuit is inversely proportional to a value of the capacitance of the capacitance circuit of the plurality of switching capacitance cells. [4] The switchable capacitance circuit according to any one of claims 1-3, wherein a value of the capacitance of the capacitance circuit of a first of the plurality of capacitance switching cells differs from a value of the capacitance of a second of the plurality of capacitance switching cells. [5] Switchable capacitance circuit according to one of claims 1-4, wherein: the resistance circuit comprises a resistance component coupled between the first end and the second end of the resistance circuit; and / or the capacitance circuit comprises a capacitor coupled between the first terminal and the second terminal of the capacitance circuit. [6] A switchable capacitance circuit according to claim 5, wherein the capacitor comprises a plurality of capacitors connected in series. [7] Switchable capacitance circuit according to claim 5 or 6, wherein: the resistance component comprises a value substantially equal to a value of the resistance between the first end and the second end of the resistance circuit; and / or the capacitor has a value substantially equal to a value of the capacitance between the first terminal and the second terminal of the capacitance circuit. [8] Switchable capacitance circuit according to one of claims 1-7, wherein values of the capacitance of the capacitance circuit from the plurality of capacitance switching cells are binary weighted. [9] The switchable capacitance circuit of any of claims 1-8, further comprising a control circuit having a plurality of outputs coupled to the respective control nodes of the plurality of capacitance switching cells. [10] The switchable capacitance circuit of any of claims 1-9, wherein a second terminal of the semiconductor switching circuit of each of the plurality of capacitance switching cells is coupled to ground. [11] The switchable capacitance circuit of any of claims 1-10, wherein a value of the resistance of each resistance circuit of the plurality of capacitance switch cells is selected such that each of the plurality of capacitance switch cells has a substantially uniform switching time. [12] A method for operating a switchable capacitance circuit, the method comprising: Increasing a load capacitance of the switchable capacitance circuit comprising switching on at least one of a plurality of capacitance switching cells, each of the plurality of capacitance switching cells comprising: a capacitance circuit having a capacitance between a first terminal and a second terminal of the capacitance circuit and a semiconductor switching circuit comprising: a first terminal coupled to the first terminal of the capacitance circuit, a plurality of series-connected high-frequency switching cells comprising a load path and a common node, wherein each of the plurality of series-connected high-frequency switching cells comprises a switching transistor and a gate resistor having a first end coupled to a gate of the switching transistor and a second end coupled to the common node, and a resistance circuit having a first end coupled to the common node and a second end coupled to a control node, the resistance circuit comprising a resistor between the first and second ends, switching on comprises activating the semiconductor switching circuit of at least one of the plurality of capacitance switching cells; and Reducing the load capacitance of the switchable capacitance circuit, comprising switching off the at least one of the plurality of capacitance switching cells, wherein the switching off comprises deactivating the semiconductor switching circuit of the at least one of the plurality of capacitance switching cells. [13] The method of claim 12, wherein activating the semiconductor switching circuit of the at least one of the plurality of capacitance switching cells comprises activating the plurality of series-connected high-frequency switching cells of the at least one of the plurality of capacitance switching cells via the control node. [14] The method according to claim 12 or 13, wherein a value of the resistance of the resistance circuit is inversely proportional to a value of the capacitance of the capacitance circuit of the plurality of switching capacitance cells. [15] The method of any of claims 12-14, further comprising applying a high frequency signal to a switchable capacitance circuit. [16] A method according to any one of claims 12-15, further comprising: coupling the switchable capacitance circuit to an antenna; and Tuning the antenna by increasing and decreasing the load capacitance of the switchable capacitance circuit. [17] A method according to any one of claims 12-16, further comprising: Receiving a command from a digital interface; and Decrypting the command, wherein increasing and decreasing the load capacitance further comprises selectively activating the semiconductor switching circuit of the plurality of capacitance switching cells according to the decrypted command. [18] Tunable high-frequency circuit comprising: a semiconductor substrate; and a plurality of capacitance switching cells arranged on the semiconductor substrate, each capacitance switching cell comprising: a capacitor coupled between a first terminal and a second terminal and a semiconductor switching circuit comprising: a first terminal coupled to the first terminal of the capacitor, a plurality of series-connected high-frequency switching cells comprising a load path and a common node, wherein each of the plurality of series-connected high-frequency switching cells comprises a switching transistor and a gate resistor having a first end coupled to a gate of the switching transistor and a second end coupled to the common node, and a common resistor having a first end coupled to the common node and a second end coupled to a control node. [19] The tunable high-frequency circuit of claim 18, wherein a capacitance of the capacitor is inversely proportional to a resistance of the common resistor. [20] A tunable high-frequency circuit according to claim 18 or 19, wherein values of the capacitors from the plurality of capacitance switching cells are binary weighted. [21] A tunable high frequency circuit according to any one of claims 18-20, wherein the switching transistor comprises a MOSFET transistor. [22] The tunable high-frequency circuit of claim 21, wherein a gate width of the MOSFET is inversely proportional to a capacitance of the capacitor. [23] A tunable high frequency circuit according to any one of claims 18-22, wherein the capacitor comprises a metal-insulator-metal capacitor. [24] A tunable radio frequency circuit according to any one of claims 18-23, further comprising a driver circuit coupled to the control nodes of the plurality of capacitance switching cells. [25] The tunable radio frequency circuit of claim 24, further comprising a charge pump and / or a voltage regulator coupled to the driver circuit.

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