Optoelectronic semiconductor chip and method for manufacturing an optoelectronic semiconductor chip

Abstract

Optoelectronic semiconductor chip (1) comprising a carrier (5) and a semiconductor body (2) arranged on the carrier (5) with a sequence of semiconductor layers, as well as a chip front and a chip back, wherein - the semiconductor layer sequence includes an active region (20) located between a first semiconductor layer (21) and a second semiconductor layer (22) and designed to generate or receive electromagnetic radiation, - the first semiconductor layer (21) is electrically connected to a first contact (41), - the first contact (41) on the front of the chip, especially next to the active area (20), is formed, - the second semiconductor layer (22) is electrically connected to a second contact (42), - the second contact (42) is also formed on the front of the chip, in particular next to the active area (20) and - the optoelectronic semiconductor chip comprises an electrically insulating separating layer (6) which electrically isolates the back of the chip from the active area (2) of the semiconductor chip, wherein the electrically insulating separating layer (6) comprises at least a first separating layer (61) which has at least one atomic layer or at least one molecular layer, and - the electrically insulating separating layer (6) has a second separating layer (62) and a third separating layer (63), and - the first separating layer (61) seals or fills pinholes and cracks in the second separating layer (62).

Description

[0001] The present invention relates to an optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip.

[0002] Thin-film light-emitting diode chips typically consist of a semiconductor body for generating and / or receiving radiation, a carrier substrate (for example Si, Ge) which does not correspond to the growth substrate for the epitaxial production of the light-emitting layer sequence, and a first and a second electrical connection layer which are electrically insulated from each other by means of a separating layer. Fig. Figure 3 shows a schematic sectional view of a prior art thin-film light-emitting diode chip in the form of a surface emitter. The light-emitting diode chip (1) has a semiconductor body (2) comprising a semiconductor layer sequence. The semiconductor layer sequence has, in particular, an active region (20) designed to generate and / or receive radiation. Typically, the active region (20) is arranged between a first semiconductor layer (21) and a second semiconductor layer (22) with different conductivity types. For example, the first semiconductor layer (21) facing the front side is n-conducting, and the second semiconductor layer (22) facing away from the front side is p-conducting.

[0003] The semiconductor body (2) is arranged on the front side (51) of an electrically conductive carrier (5). Typically, a first (31) and a second (32) electrical connection layer are located between the semiconductor body (2) and the carrier (5), as well as an insulating separating layer (9) for electrically separating them. Contact is made between the first semiconductor layer (21) via recesses (25) in the semiconductor body (2) and via the first connection layer (31) to a first contact (41) located on the back side of the carrier (5). The second semiconductor layer (22) is electrically connected to a second contact (42) on the front side of the semiconductor chip via the second connection layer (32). The presented light-emitting diode chip (1) therefore has both a front-side contact (42) and a back-side contact (41).

[0004] For various applications, a thin-film light-emitting diode chip is advantageous whose contacts are located exclusively on the front side. For such a light-emitting diode chip, referred to below as a back-side-insulated chip, an electrical separation of the back and front sides of the chip is necessary. There must be no electrical connection between the back of the chip and the electrical connection layers (31, 32). An electrical separation of the front and back sides of a thin-film light-emitting diode chip can be achieved, for example, by using a ceramic carrier (e.g. made of AlN, SiN), a glass carrier, or a high-resistance, e.g. undoped or lightly doped silicon or germanium carrier. Such solutions are often expensive in practice and are difficult to integrate into the existing manufacturing process for standard thin-film light-emitting diode chips.

[0005] The document DE 10 2011 115 659 A1 relates to a photovoltaic semiconductor chip.

[0006] The document US 2013 / 0 285 067 A1 describes a method for forming a buried metal layer structure.

[0007] The document DE 10 2010 048 159 A1 discloses a light-emitting diode chip.

[0008] The document DE 10 2010 013 494 A1 discloses an optoelectronic semiconductor chip.

[0009] The document DE 10 2007 022 947 A1 relates to an optoelectronic semiconductor body and a method for its production.

[0010] The publication US 2010 / 0 140 636 A1 addresses a light-emitting diode with improved light extraction.

[0011] One object is to provide an optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip which allow improved backside insulation.

[0012] This problem is solved, among other things, by the subject matter of the independent claims. Further embodiments are the subject matter of the dependent claims.

[0013] According to at least one embodiment, an optoelectronic semiconductor chip comprises a carrier on which a semiconductor layer sequence is arranged. Furthermore, the semiconductor chip comprises a chip front side and a chip back side.

[0014] The semiconductor layer sequence comprises an active region arranged between a first semiconductor layer and a second semiconductor layer. The active region of the semiconductor layer sequence is intended for generating or receiving electromagnetic radiation. The active region is designed, for example, to receive or generate radiation in the ultraviolet, visible, or infrared spectrum. Furthermore, the active region is arranged, for example, between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are expediently made of a semiconductor material with different conductivity types. For example, the first semiconductor layer is n-conducting and the second semiconductor layer is p-conducting, or vice versa.

[0015] The first semiconductor layer is electrically connected to a first contact. The first contact is formed on the chip front side, in particular adjacent to the active region. The second semiconductor layer is electrically connected to a second contact. The second contact is also formed on the chip front side, in particular adjacent to the active region. For example, the first and second contacts are arranged on or near two opposite outer sides of the semiconductor chip and laterally from the semiconductor body on the chip front side.

[0016] Furthermore, an additional electrically insulating separating layer is provided. This is located, for example, between the electrical connection layer closest to the carrier substrate, such as the first connection layer, and the carrier, and completely covers both. Alternatively, the insulating separating layer can be arranged over the entire surface of the back of the carrier. For example, the insulating separating layer comprises one or more atomic or molecular monolayers.

[0017] A carrier in the form of a three-layer system is also conceivable, in which the insulating separating layer is enclosed on both sides by the carrier material (e.g., Si or Ge) in the manner of an interlayer. In a thin-film LED chip without an external carrier, the separating layer is located on the back of the chip, on the connection layer closest to the back.

[0018] Preferably, a first and a second electrical connection layer are arranged between the carrier and the semiconductor body. The first and second connection layers are electrically insulated from each other by means of a separating layer.

[0019] According to at least one embodiment, the insulating separating layer is arranged on a front side of the carrier, on a back side of the carrier, or within the carrier. For example, the insulating separating layer is arranged between the connection layer and the carrier that is closest to the carrier.

[0020] According to at least one embodiment, the electrically insulating separating layer comprises at least a first separating layer. This first separating layer comprises at least one atomic layer or at least one molecular layer. For example, the first separating layer is formed as a closed layer without recesses or pores. Such a layer can be achieved, for example, by atomic layer deposition or molecular layer deposition through two or more cyclically performed self-limiting surface reactions on a surface of the semiconductor body or the carrier.

[0021] According to at least one embodiment, the atomic layer and / or the molecular layer comprises one or more layers. For example, through atomic layer deposition or molecular layer deposition, the separation layer can grow by a determinable amount per process cycle through a self-limiting reaction. The separation layer thus grows proportionally to the number of reaction cycles, which enables precise control of the layer thickness.

[0022] According to at least one embodiment, the first separating layer comprises at least one or more insulating oxide or nitride compounds, for example Al x O y , SiO2, Ta x O y , TaN, TiO, SiN, AlN, TiN, ZrO2, HfO2, HfSiO4, ZrSiO4, HfSiON.

[0023] According to at least one embodiment, the electrically insulating separating layer comprises a layer sequence of electrically insulating materials. In particular, the electrically insulating materials can be different. According to at least one embodiment, the layer sequence comprises the first separating layer and at least one second separating layer. The second separating layer has one or more deposition layers. For example, the second separating layer can be applied using alternative methods with high deposition rates, such as vapor deposition or the sputtering method. The first and second separating layers can be coordinated with one another and achieve improved electrical insulation. The first separating layer is preferably applied directly onto the second separating layer in chronological succession.

[0024] According to at least one embodiment, the layer sequence comprises a third separating layer. The third separating layer comprises one or more layer layers deposited by means of vapor deposition or sputtering. The deposition of the first separating layer follows the deposition of the second and / or third separating layer. In a further embodiment, the first separating layer is at least partially enclosed by the second and third separating layers. The first separating layer is thus an intermediate layer whose surfaces are at least partially enclosed by the second and third separating layers.

[0025] According to at least one embodiment, the second and / or the third separating layer comprise at least one or more insulating oxide or nitride compounds, for example Al x O y , SiO2, Ta x O y , TaN, TiO, SiN, AlN, TiN, ZrO2, HfO2, HfSiO4, ZrSiO4, HfSiON.

[0026] According to at least one embodiment, the carrier comprises an electrically conductive material or a semiconductive material. Furthermore, the carrier can comprise a molding material, a ceramic material, and / or a high-resistance material. For example, the choice of carrier material affects its thermal expansion coefficient and can be adapted depending on the application. A ceramic material or a high-resistance material can be provided, for example, for additional electrical insulation.

[0027] According to at least one embodiment, the first semiconductor layer is arranged on the side of the active region facing away from the carrier. The first semiconductor layer is electrically conductively connected to the first contact via a first connection layer.

[0028] According to at least one embodiment, the semiconductor body has at least one recess that extends through the second semiconductor layer and the active region into the first semiconductor layer. The first connection layer is arranged at least partially in the recess and is electrically conductively connected to the first semiconductor layer.

[0029] According to at least one embodiment, the second semiconductor layer is electrically connected to the second contact via a second connection layer. The second connection layer is arranged on the side of the active region facing the carrier.

[0030] A method for producing an optoelectronic semiconductor chip having a chip front side and a chip back side comprises, according to at least one embodiment, the following steps.

[0031] First, a semiconductor layer sequence is provided, which has an active region arranged between a first semiconductor layer and a second semiconductor layer. A first contact is formed on a chip front side, in particular adjacent to the active region. Furthermore, an electrically conductive connection is established between the first semiconductor layer and the first contact. In addition, a second contact is formed on the chip front side, in particular adjacent to the active region. In addition, an electrically conductive connection is established between the second semiconductor layer and the second contact.

[0032] An electrically insulating separating layer is formed on a rear side of the semiconductor body facing away from the carrier, on the front side of the carrier, or within the carrier. Finally, a composite consisting of the semiconductor layer sequence and the carrier is formed and assembled to form the semiconductor chip.

[0033] According to at least one embodiment, the method for producing an optoelectronic semiconductor chip comprises the following steps: 1. A semiconductor layer sequence is provided on a growth substrate, which has the active region arranged between the first semiconductor layer and the second semiconductor layer. 2. A second electrical connection layer is applied on the second semiconductor layer. 3. A breakthrough is formed in the active region. 4. The separation layer is then applied to the back of the semiconductor layer sequence. 5. A first electrical connection layer is applied to the back side of the semiconductor layer sequence, wherein a partial region of the first electrical connection layer is formed in the opening. 6. The electrically insulating separating layer is applied over the entire surface of the first connection layer. 7. A composite of semiconductor layer sequence, carrier and connection layers is formed and assembled to form the semiconductor chip. 8. The growth substrate is thinned or completely removed. 9. The semiconductor layer sequence is removed in places and the first and second contacts are applied.

[0034] As an alternative to step 6), the insulating release layer is applied over the entire surface of the front or back of the carrier or carrier substrate. The latter is also possible after the composite has been formed. Alternatively, the carrier substrate contains the release layer partially enclosed on both sides.

[0035] According to at least one embodiment, the electrically insulating separating layer is applied to the side of the semiconductor body facing the carrier or to the carrier by means of atomic layer deposition or by means of molecular layer deposition.

[0036] According to at least one further embodiment, the electrically insulating separating layer is implemented as a combination of a first separating layer based on atomic layer deposition or molecular layer deposition with at least one further separating layer based on vapor deposition or based on a sputtering process. The layer based on atomic layer deposition / molecular layer deposition directly adjoins at least one vapor deposition layer, such as a CVD-based (chemical vapor deposition) or a sputtered layer, with the former being deposited chronologically after the latter.

[0037] Atomic layer deposition (ALD) or molecular layer deposition (MLD) are possible processes for producing the electrically insulating separating layer as an atomic layer or molecular layer. These processes lead to the deposition of thin films or layers through two or more cyclically performed, self-limiting surface reactions. The layers usually have a polycrystalline or amorphous structure. Within the framework of the presented principle, however, atomic layer deposition or molecular layer deposition should not be understood as a conventional gas phase deposition or the CVD process (chemical vapor deposition). In contrast to CVD processes, the starting materials are reacted cyclically and sequentially. The partial reactions can be separated from one another and limited to the surface. The partial reactions are self-limiting, i.e.a starting material of a partial reaction does not react with itself or ligands of itself, which limits the layer growth of a partial reaction per cycle to a maximum of one monolayer.

[0038] According to at least one embodiment, the electrically insulating separating layer is applied by means of at least one of the atomic layer coating and / or molecular layer coating processes known under the following names: - atomic layer deposition, - atomic layer epitaxy, - atomic layer evaporation, - atomic layer growth, - molecular layer deposition (molecular layer deposition), - molecular layer epitaxy.

[0039] In the proposed optoelectronic semiconductor chip, the electrical separation of the front and back sides is achieved by incorporating an additional electrically non-conductive layer into the chip. The electrically insulating separation layer makes it possible to achieve simple electrical isolation of the front and back sides of a thin-film light-emitting diode chip. Special, electrically insulating carrier materials are dispensed with, making the proposed design and method particularly cost-effective. Furthermore, the proposed method can be integrated into known standard processes for the production of optoelectronic semiconductor chips. In particular, in contrast to the use of other carrier materials, such as ceramic-based substrates, only marginal to no effects on the processability of the semiconductor components are observed.

[0040] In particular, the proposed method is compatible with existing separation processes used to separate a large number of optoelectronic semiconductor chips from a wafer. This is not possible with ceramic carriers due to the occurrence of chipping. The latter must be separated using a complex "scribe & break" process. Compared to ceramic carriers, there is also improved compatibility with existing bonding technologies. With ceramic carriers, high breakage rates of the carrier and / or sapphire occur due to CTE (coefficient of thermal expansion) mismatches. Finally, the proposed method is also compatible with existing backside metallization. Unlike with ceramic carriers, adhesion issues are not expected.A further advantage of the proposed method compared to a ceramic-based backside insulation is the good thermal connection of the chip produced in this way to its housing, since the majority of the LED chip can be made of materials with high thermal conductivity, such as GaN and silicon.

[0041] The presented method is not only suitable for various light-emitting diode chips. Accordingly, the method can also be advantageously used for a thin-film chip in which the contact layer for the first semiconductor layer is located on the semiconductor body on the chip front side. Thin-film semiconductor chips without recesses and thin-film semiconductor chips in which the connection for the first semiconductor layer sequence is arranged on the semiconductor body are also conceivable. Furthermore, carrierless thin-film semiconductor chips are possible as a variant. For example, their carrier comprises a molding material.

[0042] Separating layers based on vapor deposition, e.g. SiO2 and / or SiN x , are manufactured at relatively low temperatures due to the temperature sensitivity of the optoelectronic semiconductor chip. This leads, among other things, to the formation of pores and pinholes in the dielectric, which manifest themselves in a significant reduction in the breakdown voltage. In addition, cracks form in the layers at steps (in the topography) of the component during a CVD process. The requirements for the backside insulation of the optoelectronic semiconductor chip cannot usually be met in this way.

[0043] The first separation layer, either alone or in a layer sequence with at least a second separation layer based on vapor deposition or a sputtering process, can close pores or pinholes in an already deposited layer and further improve electrical insulation. An atomic or molecular layer layer typically represents a closed layer with very good overmolding properties. Thus, the first separation layer (e.g., ALD) can counteract the negative effects of pinholes and cracks on the breakdown strength. Pinholes on a surface of the vapor-phase layers are filled, which also applies to cracks in the layers that are more common at steps.

[0044] The breakdown strength of an ideal dielectric layer follows the relationship: Ubr=Ecrit⋅d, where U br the breakdown voltage, E critrepresents the critical field strength for layer failure and d the layer thickness. A high breakdown voltage can therefore be achieved by a high value of E crit or a large layer thickness d. The layer thickness d can be adjusted essentially freely, apart from cost and tension issues. E crit is a layer parameter that is determined by the material and the deposition process. Layers of a specific material based on atomic layer deposition or molecular layer deposition naturally have a higher value of E critthan layers of the same material based on CVD or sputtering. However, ALD layers are typically only realized with thin layers (approximately <200 nm) due to the low deposition rates of the respective coating methods. In contrast, vapor deposition or the sputtering process, due to their high deposition rates, enable relatively large layer thicknesses of several 100 nm within a sufficiently short process time. However, this is offset by relatively small values ​​of E due to the poorer layer quality caused by pores and cracks (especially at the low coating temperatures). crit With the help of a subsequent atomic layer deposition or molecular layer deposition, these pores and cracks can be closed, which leads to an increase in E crit and thus from U brThe total thickness d of the layer sequence changes only insignificantly due to the relatively low growth rates of the atomic layer deposition / molecular layer deposition. With the help of a suitable combination of layers based on vapor deposition or sputtering and atomic layer deposition / molecular layer deposition, both the layer thickness d and the critical field strength E crit be optimized for high breakdown voltage.

[0045] Overall, the first separation layer eliminates or reduces electrical breakdowns at low applied voltages, which are typically attributed to the presence of pinholes. The breakdown strength thus approaches the intrinsic value of a pinhole-free CVD bulk layer. In summary, the introduction of the first separation layer enables more reliable insulation of the front and back surfaces by means of an additional dielectric in the layer structure of the optoelectronic semiconductor chip.

[0046] Further advantages and advantageous embodiments as well as further developments emerge from the following embodiments shown in conjunction with figures.

[0047] They show: the Fig. 1 an embodiment of an optoelectronic semiconductor chip in a schematic sectional view, the Fig. 2 Measurement characteristics of optoelectronic semiconductor chips with different separation layers, and the Fig. 3 an embodiment of an optoelectronic semiconductor chip in a schematic sectional view from the prior art.

[0048] Identical, similar, or functionally identical elements are provided with identical reference numerals in the figures. The figures and the relative sizes of the elements depicted in the figures are not to be considered to scale. Rather, individual elements, and in particular layer thicknesses, may be exaggerated for clarity and / or clarity.

[0049] The following description is based on an example of a semiconductor chip intended for generating radiation, for example, a light-emitting diode semiconductor chip, such as an LED. Alternatively, the semiconductor chip can also be designed as a radiation receiver, in which an active region is provided for generating an electrical signal depending on the radiation power incident on the active region.

[0050] Fig. 1 shows an embodiment of an optoelectronic semiconductor chip in a schematic sectional view.

[0051] The optoelectronic semiconductor chip 1 comprises a semiconductor body 2. The semiconductor body 2 has a semiconductor layer sequence with an active region 20. The active region 20 is intended for generating radiation in the ultraviolet, visible, or infrared spectral range. In the vertical direction, i.e., perpendicular to a main extension plane of the semiconductor layer sequence of the semiconductor body, the semiconductor body 2 extends between a radiation passage area 26 and a main area 27. The active region 20 is arranged between a first semiconductor layer 21 of a first conductivity type and a second semiconductor layer 22 of a second conductivity type different from the first conductivity type. For example, the first semiconductor layer is n-conducting and the second semiconductor layer is p-conducting, or vice versa. The semiconductor body, in particular the active region, preferably contains a III-V or II-VI compound semiconductor material.

[0052] The optoelectronic semiconductor chip 1 is designed, for example, as a thin-film semiconductor chip in which a growth substrate for the semiconductor layer sequence of the semiconductor body 2 is removed after its epitaxial deposition. Such a semiconductor chip represents, to a good approximation, a Lambertian surface radiator. However, the growth substrate can also remain completely in the semiconductor chip or be removed or thinned only in certain areas.

[0053] III-V compound semiconductor materials are used to generate radiation in the ultraviolet (Al x In y Ga 1-x-y N) over the visible (Al x In y Ga 1-x-y N, especially for blue to green radiation, or Al x In y Ga 1-x-y P, especially for yellow to red radiation) to the infrared (Al x In y Ga 1-x-yAs) spectral range is particularly suitable. Here, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and x + y ≤ 1 apply, in particular with x ≠ 1, y ≠ 1, x ≠ 0, and / or y ≠ 0. High internal quantum efficiencies can also be achieved in radiation generation using III-V compound semiconductor materials, particularly those made from the aforementioned material systems.

[0054] The semiconductor body 2 has a plurality of recesses 25 that extend from the main surface 27 through the second semiconductor layer 22 and the active region 20 into the first semiconductor layer 21 and terminate there. For clarity, only two recesses 25 are shown in the drawing. The recesses 25 are each electrically conductively connected to a first connection layer 31 that extends between the semiconductor body 2 and the carrier substrate 5. The recesses 25 are electrically conductively connected to one another by means of the connection layer 31.

[0055] Charge carriers can be injected evenly into the first semiconductor layer 21 in a lateral direction via the plurality of recesses 25. Depending in particular on the transverse conductivity of the first semiconductor layer 21, the number of recesses 25 can be varied within wide limits. In extreme cases, a single recess 25 may be sufficient for electrically contacting the first semiconductor layer 21.

[0056] The semiconductor chip 1 comprises a carrier 5, which extends vertically between a front side 51 and a rear side 52. In this embodiment, the carrier 5 comprises, for example, a doped semiconductor material, such as silicon or germanium. The first and second electrical connection layers 31, 32 are arranged between the carrier 5 and the semiconductor body 2. The semiconductor body 2, together with the connection layers 31, 32, is mechanically stably connected to the carrier 5 by means of a connecting layer (not shown), for example by means of an electrically conductive adhesive layer or by means of a solder layer.

[0057] In addition, the first connection layer 31 covers the entire surface of the carrier 5 in the region of the recesses 25 and extends horizontally along the front side 51 of the carrier 5. In the region of a recess 25, the first connection layer 31 is delimited in the lateral direction by an insulation layer 9 of the recess, which extends vertically through the recess along the semiconductor layer sequence. The first semiconductor layer 21 is electrically conductively connected to a first contact 41 via the first connection layer 31. The first contact 41 is located on the front side of the semiconductor chip, laterally from the semiconductor body 2.

[0058] The optoelectronic semiconductor chip 1 further comprises a second connection layer 32, which is electrically conductively connected to the second semiconductor layer 22. The connection layer 32 extends at least partially in the horizontal direction along the main surface 27 of the semiconductor body 2. The connection layer 32 extends laterally far enough that a second contact 42 is formed at one end. The first connection layer 31 and the second connection layer 32 can overlap at least partially when viewed from above on the semiconductor chip 1.

[0059] The first and second contact 41, 42 may be formed as a layer provided in addition to the first or second connection layer 31, 32, as shown in Fig. 1. Alternatively, a region of the first or second connection layer 31, 32 that is freely accessible for external electrical contacting can itself form the contacts 41, 42.

[0060] An insulating layer 9 is formed between the first connection layer 31 and the second connection layer 32, and also partially along the carrier 5. The insulating layer 9 also covers side surfaces of the recesses 25 and thus insulates the first connection layer 31 from the second semiconductor layer 22 and from the active region 20. In other words, the first contact 41 and the second contact 42 are electrically connected to one another only via a diode. During operation of the optoelectronic semiconductor chip 1, an external electrical voltage can therefore be applied between the first contact 41 and the second contact 42, so that charge carriers are injected into the active region 20 and recombine there, emitting radiation.

[0061] An electrically insulating separating layer 6 is provided between the semiconductor body 2 and the carrier 5. The electrically insulating separating layer 6 extends horizontally parallel to the main surface 27 of the semiconductor body 2 or along the front side 51 of the carrier 5. In this exemplary embodiment, the electrically insulating separating layer 6 comprises a layer sequence consisting of a first separating layer 61, a second separating layer 62, and a third separating layer 63.

[0062] The first separation layer 61 is a closed layer formed using an atomic layer deposition process (here: ALD). Alternatively, the first separation layer 61 can also be formed using a molecular layer deposition process (here: MLD). The first separation layer 61 comprises at least one monolayer of an electrically insulating material, for example, Al2O3, SiO2, or Ta2O5, or a combination of these materials. The first separation layer has a thickness of approximately 40 nm, for example, and thus comprises multiple monolayers. Depending on the desired degree of insulation and field of application, the first separation layer 61 can have other thicknesses, which can amount to several hundred nm. The thickness of the first separation layer is limited to a smaller thickness, for example for cost reasons, because the atomic layer deposition process can only apply monolayers one after the other and is therefore time-consuming.

[0063] The first separating layer 61 represents a dielectric, which is enclosed by the second and third separating layers 62, 63 in the manner of an interlayer. Both the second and third separating layers 62, 63 represent layers applied by means of a vapor deposition process or a sputtering process. Electrically insulating materials, such as SiO2, SiN, are also suitable as materials. x or Si-ON.

[0064] As a result of the deposition from the gas phase at low temperatures, the second and third separation layers 62, 63 have pinholes and pores, which would be noticeable in a significant reduction in the breakdown voltage. In addition, cracks form in the two separation layers at the steps in the topography. The first separation layer 61 is a highly closed layer with very good overmolding properties, which already provides highly reliable electrical insulation as a single layer. By directly applying the first separation layer 61 to the CVD-based layer, the effects of the pinholes and cracks on the breakdown strength are counteracted and, to a certain extent, they are closed or filled. In this way, electrical breakdowns can be eliminated or reduced at low applied voltages, for example in the range of 100 V to 200 V. The application of the first separation layer to a CVD-based orsputtered layer or the introduction of the first separation layer 61 as an intermediate layer thus allows an even more reliable insulation of the front and back of the optoelectronic semiconductor chip than would be possible with a conventional CVD-based layer or layer sequence.

[0065] In further embodiments (not shown), thin-film semiconductor chips are conceivable that do not have recesses 25 and thin-film semiconductor chips in which the connection 32 for the first semiconductor layer sequence is arranged on the semiconductor body 2. Furthermore, carrierless thin-film semiconductor chips are possible as a variant. For example, their carrier comprises a molding material.

[0066] Fig. Figure 2 shows the measurement characteristics of optoelectronic semiconductor chips with different insulation layers 9.

[0067] The graph shows measurement curves that illustrate the improved electrical insulation achieved using the presented method. Different curves are shown that compare the results of various insulation measures. Different voltages were applied between the front and back of the chip, and the number of chips with breakdowns was determined. Curves G1 to G4 are taken from semiconductor chips with insulation layers that were completely applied using vapor deposition. The layers each have the same total thickness; they differ only in the arrangement and / or thickness of the individual layers of SiO2 and SiN. x . Finally, curve G5 shows the measurement data on a layer sequence consisting of the first, second and third separation layer 61, 62, 63 as they are related to Fig. 1 was discussed.

[0068] The x-axis shows the voltage U[V] applied to the respective semiconductor chip in a first, second, and third measurement cycle. The voltage was increased from zero to a value U max For each value U, the semiconductor chips that exhibited insulation failure due to the voltage were then sorted out. The number of these rejected semiconductor chips is indicated on the y-axis as a percentage.

[0069] The graphic shows a surprising effect that can be achieved with the layer sequence of the proposed principle. Curve G1 shows that a layer sequence consisting solely of layers from a chemical vapor deposition leads to a significant failure rate N[%] of almost 80% even in the first measurement cycle. Although the failure rate can be significantly reduced by appropriate variation of the CVD-based individual layers while maintaining the same total thickness, it remains high and can lead to additional costs and effort in the production and testing phase of semiconductor chips. Furthermore, it is noticeable that the failure rate N[%] increases, as expected, with the applied voltage U. The proposed layer sequence, on the other hand, shows a significantly different curve. According to measurement curve G5, the failure rate is not only significantly reduced, but within the test range it is also independent of the applied voltage.The negligible failures at the minimum value of U in the first measurement cycle are attributed to other problems of the semiconductor chip in question, such as processing errors.

Claims

[1] Optoelectronic semiconductor chip (1) comprising a carrier (5) and a semiconductor body (2) arranged on the carrier (5) with a semiconductor layer sequence, as well as a chip front side and a chip back side, wherein - the semiconductor layer sequence comprises an active region (20) which is arranged between a first semiconductor layer (21) and a second semiconductor layer (22) and is intended for generating or receiving electromagnetic radiation, - the first semiconductor layer (21) is electrically conductively connected to a first contact (41), - the first contact (41) is formed on the chip front side, in particular next to the active area (20), - the second semiconductor layer (22) is electrically conductively connected to a second contact (42), - the second contact (42) is also formed on the chip front side, in particular next to the active area (20), and - the optoelectronic semiconductor chip comprises an electrically insulating separating layer (6) which electrically insulates the chip rear side from the active region (2) of the semiconductor chip, wherein the electrically insulating separating layer (6) comprises at least one first separating layer (61) which has at least one atomic layer or at least one molecular layer, and - the electrically insulating separating layer (6) has a second separating layer (62) and a third separating layer (63), and - the first separating layer (61) closes or fills pinholes and cracks in the second separating layer (62). [2] Optoelectronic semiconductor chip according to claim 1, wherein the insulating separating layer (6) is arranged on a front side (51) of the carrier, on a back side of the carrier (52) or within the carrier (5). [3] Optoelectronic semiconductor chip according to one of the preceding claims, wherein the atomic layer and / or molecular layer has one or more layers. [4] Optoelectronic semiconductor chip according to one of the preceding claims, wherein the first separating layer (61) comprises at least one or more insulating oxide or nitride compounds or one or more of the following materials: Al x O y , SiO2, Ta x O y , TaN, TiO, SiN, AlN, TiN, ZrO2, HfO2, HfSiO4, ZrSiO4, HfSiON. [5] Optoelectronic semiconductor chip according to one of the preceding claims, wherein the electrically insulating separating layer (6) comprises a layer sequence of electrically insulating materials. [6] Optoelectronic semiconductor chip according to one of the preceding claims, wherein the second separation layer (62) comprises one or more layers deposited by vapor deposition or sputtering processes. [7] Optoelectronic semiconductor chip according to claim 6, wherein - the third separating layer (63) comprises one or more layers deposited by a gas phase deposition or by a sputtering process, and - the first separating layer (61) is at least partially enclosed by the second and third separating layers (62, 63). [8] Optoelectronic semiconductor chip according to claim 7, wherein the second and / or the third separating layer (62, 63) comprise at least one or more insulating oxide or nitride compounds or one or more of the following materials: SiN x , Si-ON, SiO2, Al x O y , Ta x O y , TaN, TiO, SiN, AlN, TiN, ZrO2, HfSiO4, HfO2, ZrSiO4, HfSiON. [9] Optoelectronic semiconductor chip according to one of the preceding claims, wherein the carrier (5) comprises an electrically conductive material, semiconductive material, a molding material, a ceramic material and / or a high-resistance material. [10] Optoelectronic semiconductor chip according to one of the preceding claims, wherein the first semiconductor layer (21) is arranged on the side of the active region (20) facing away from the carrier (5) and the first semiconductor layer (21) is connected to the first contact (41) via a first connection layer (31). [11] Optoelectronic semiconductor chip according to claim 10, wherein the semiconductor body (2) has at least one recess (25) which extends through the second semiconductor layer (22) and through the active region (20), and wherein the first connection layer (31) is at least partially arranged in the recess (25) and connected to the first semiconductor layer (21). [12] Optoelectronic semiconductor chip according to one of the preceding claims, - wherein the second semiconductor layer (22) is electrically conductively connected to the second contact (42) via a second connection layer (32), and - wherein the second connection layer (32) is arranged on the side of the active region (20) facing the carrier (5). [13] Method for producing an optoelectronic semiconductor chip (1) having a chip front side and a chip back side, comprising the steps: - Providing a semiconductor layer sequence (2) having an active region (20) arranged between a first semiconductor layer (21) and a second semiconductor layer (22); - forming a first contact (41) on the chip front side, in particular next to the active region (20), and forming an electrically conductive connection between the first semiconductor layer (21) and the first contact (41), - forming a second contact (42) on the chip front side, in particular next to the active region (20), and forming an electrically conductive connection between the second semiconductor layer (22) and the second contact (42), - forming an electrically insulating separating layer (6) which electrically insulates the chip backside from the active region (20) of the semiconductor chip, and - forming a composite of semiconductor layer sequence (2) and a carrier (5) wherein - the electrically insulating separating layer (6) comprises a first separating layer (61) which has at least one atomic layer or at least one molecular layer, and - wherein the electrically insulating separating layer (6) has a second separating layer (62) and a third separating layer (63), and - the first separating layer (61) closes or fills pinholes and cracks in the second separating layer (62). [14] Method according to claim 13, wherein the electrically insulating separating layer (6) is applied by means of atomic layer coating or molecular layer coating. [15] The method of claim 14, wherein - the first separation layer (61) is made on the basis of atomic layer deposition or molecular layer deposition, - the second separating layer (62) is formed on the basis of a vapor deposition or on the basis of a sputtering process, - the depositions of the first and second separating layers (61,62) occur directly one after the other. [16] Method according to one of claims 13 to 15, wherein the electrically insulating separating layer (6) is applied by means of at least one of the following atomic layer coating and / or molecular layer coating methods: - atomic layer deposition, - atomic layer epitaxy, - atomic layer evaporation, - atomic layer growth, - molecular layer deposition, - molecular layer epitaxy.

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