Structure and method for devices for suppressing transient stresses with a base with two areas
The two-layer base structure in TVS devices addresses the challenge of achieving high breakdown voltage and low electric field strength by simplifying fabrication and reducing thickness, enhancing circuit protection while lowering costs.
Patent Information
- Application Number
- DE102015116651
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2014-10-03
- Filing Date
- 2015-10-01
- Publication Date
- 2025-12-18
- Estimated Expiration
- 2035-10-01
AI Technical Summary
Existing TVS devices face challenges in achieving high breakdown voltage and low electric field strength while maintaining a thin base thickness, requiring complex fabrication processes and increased resistance, which complicates manufacturing and increases costs.
A TVS device design with a base comprising two layers of different dopant concentrations and thicknesses, allowing independent control of breakdown voltage and electric field strength, enabling a thinner base without compromising performance and simplifying the manufacturing process.
The two-layer base structure reduces base thickness, simplifies fabrication, and maintains high breakdown voltage and low electric field strength, thereby reducing manufacturing costs and improving circuit protection capabilities.
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Abstract
Description
BACKGROUND
[0001] This description relates to semiconductor devices and in particular to transient voltage suppression (TVS) diodes having a base with two regions, and methods for manufacturing them using wide bandgap materials.
[0002] At least some known punch-through transient suppression (TVS) semiconductor devices incorporate a uniformly doped base layer. The TVS device achieves breakdown when a depletion region of one reverse-biased pn junction reaches a depletion region of another pn junction (or when open-base breakdown conditions are met). The blocking capability of the TVS device is defined by its base thickness and doping (the amount of dopant that must be cleared to achieve punch-through conditions). A punch-through limited breakdown design simplifies the structure to such an extent that no special edge termination is required, and the TVS device can be fabricated using a mesa process.Although silicon carbide (SiC) can withstand up to about 3 megavolts / centimeter (MV / cm), the breakdown strength of the mesa surface is usually 2-3 times lower, so it is consequently necessary to design the TVS device in such a way that an electric field in the TVS device is confined in the bulk region or is maintained at all voltages up to breakdown at less than a surface breakdown strength.
[0003] The breakdown voltage and maximum electric field strength in a base of a TVS device at breakdown depend at least in part on the base thickness and / or doping. Generally, for a higher reverse voltage rating of the TVS device, the base is thicker and its doping is less concentrated than for devices with a lower reverse voltage rating. A TVS device design with a specific breakdown voltage (BV) and low electric field strength (E) max ) requires an even thicker base and lower doping.
[0004] For example, the SiC-TVS device for an NPN or PNP-TVS device with a breakdown voltage (BV) of approximately 600 volts (V) can have a base that is approximately 6 micrometers (µm) thick and a dopant concentration of approximately 2×10 16 per cubic centimeter (cm³) -3). At the breakdown voltage, the electric field strength reaches approximately 2.2 megavolts per centimeter (MV / cm). If a lower electric field strength is observed for the same BV = 600V, e.g., a maximum electric field strength (E) max )<1, 1MV / cm, is required, the base area thickness would have to be increased to approximately 11 µm, and its doping would have to be reduced, for example, to less than 5.5x10 16 cm -3 The disadvantage of a TVS design for "low electric field strength" is the requirement for a thick base region (especially at high BV). Fabricating such a mesa structure with high TVS requires a deep etching process and a special mask to protect the active area of the device during etching.
[0005] Increasing the thickness of the base layer to achieve a higher breakdown voltage encounters practical limitations. When using a typical three-layer NPN or PNP structure for any voltage beyond a certain point, beyond a certain breakdown voltage, increasing the thickness of the base layer increases the resistance of the device itself, increases the voltage clamping factor of the TVS, and thus worsens the clamping capability of the device.
[0006] US 8 270 131 B2 describes an element for protection against electrostatic discharges comprising a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area.
[0007] US 2013 / 0240903A1 describes a method for forming a silicon carbide device for suppressing transient stresses.
[0008] US 5 880 511 A describes a device for suppressing transients based on a punch-through diode.
[0009] The document Yu B. et al., “Punchthrough Transient Voltage Suppressor for EOS / ESD Protection of Low-Voltage ICs”, in: IEEE Proceedings, Electrical Overstress / Electrostatic Discharge Symposium, 1995, pp. 27-33, describes a silicon-based device for suppressing transient voltages that operates in punch-through mode. SUMMARY
[0010] In one embodiment, a transient voltage suppression (TVS) device comprises a first layer of a wide-bandgap semiconductor material formed from a material of a first conductivity type, a second layer of a wide-bandgap semiconductor material formed from a material of a second conductivity type over at least a section of the first layer, wherein the second layer has a first dopant concentration, and a third layer of a wide-bandgap semiconductor material formed from the material of the second semiconductor type over at least a section of the second layer, wherein the third layer has a second dopant concentration, the second dopant concentration being different from the first dopant concentration.The TVS device further includes a fourth layer of a large bandgap semiconductor material, which is formed from the material of the first conductivity type over at least one section of the third layer.
[0011] The aforementioned device may further comprise a first electrical contact surface on a side of the first layer opposite the second layer.
[0012] Additionally, the device may also have a second electrical contact surface on one side of the fourth layer opposite the third layer.
[0013] In any of the aforementioned devices, the dopant concentration in the second and third layers can be determined using: N_third_layer*t_third_layer < 10*N_second_layer*t_second_layer, where N_third_layer indicates a dopant concentration in layer 108, t_dritte_Schicht denotes a thickness of layer 108, N_second_layer indicates a dopant concentration in layer 106 and t_second layer denotes a thickness of layer 106.
[0014] In the device of the last-mentioned type, a dopant concentration of 1×10 can be found in the third layer. 14 cm -3 < N_third_layer < 2×10 17 cm -3 be.
[0015] Additionally or alternatively, a dopant concentration in the second layer N_second_layer < 1×10 18 cm -3 be.
[0016] Furthermore, the thickness of the third layer in the device of the type mentioned last can be t_third layer > 0.5µm.
[0017] Additionally or alternatively, the thickness of the second layer can be 0.1µm < t_second layer < 5µm.
[0018] In one configuration, the thickness of the second layer can be determined using 0.1µm < t_second_layer < 0.2*t_third_layer.
[0019] In any device of the type mentioned above, the TVS device can operate using punch-through physics.
[0020] In one configuration, the TVS device can be set up to exhibit a punch-through characteristic between approximately 5.0 volts and approximately 75.0 volts.
[0021] In another configuration, the TVS device can be set up to exhibit a punch-through characteristic between approximately 75.0 volts and approximately 200.0 volts.
[0022] In a further configuration, the TVS device can be set up to exhibit a punch-through characteristic at voltages greater than approximately 200 volts.
[0023] In one configuration, the TVS device can be set up to discharge a current of more than 10 kA / cm² during a transient overvoltage event. 2 to lead.
[0024] In another configuration, the TVS device can be set up to discharge a current between 5 kA / cm² during a transient overvoltage event. 2 and 10 kA / cm 2 to lead.
[0025] In a further configuration, the TVS device can be set up to discharge a current between 1 kA / cm² during a transient overvoltage event. 2 and 5 kA / cm 2 to lead.
[0026] In a further embodiment, a method for manufacturing a transient voltage suppression (TVS) arrangement comprises providing a silicon carbide semiconductor substrate having a first surface and an opposing second surface, forming a first silicon carbide semiconductor layer having a conductivity of a first polarity over at least one section of the first surface, forming a second silicon carbide semiconductor layer having a conductivity of a second polarity over at least one section of the first layer, and forming a third silicon carbide semiconductor layer having a conductivity of the second polarity over at least one section of the second layer.The method further includes forming a fourth silicon carbide semiconductor layer, which has a conductivity with the first polarity, over at least a section of the third layer and forming electrical contacts on the device on the second surface and on the third surface.
[0027] In a further embodiment, a transient voltage suppression (TVS) arrangement for protecting electronic equipment against transient electrical energy comprises several TVS devices connected at least electrically in parallel, wherein each of the several TVS devices comprises a first layer formed from a wide-bandgap semiconductor material of a first conductivity type, a second layer formed from the wide-bandgap semiconductor material of a second conductivity type, a third layer formed from the wide-bandgap semiconductor material of the second conductivity type, and a fourth layer formed from the wide-bandgap semiconductor material of the first conductivity type.
[0028] In the previously mentioned arrangement, the multiple TVS devices can be formed on a first chip and packed together into a single integrated circuit package.
[0029] Alternatively, the multiple TVS devices can be monolithically formed on a single chip. DRAWINGS
[0030] These and other features, aspects and advantages of the present disclosure will be better understood if the following detailed description is read with reference to the accompanying drawings, in which the same reference numerals represent the same parts throughout the drawings, wherein: Fig. Figure 1 shows a cross-sectional view of a semiconductor device for transient voltage suppression (TVS). Fig. Figure 2 shows a graphical representation of a doping profile (acceptors and donors) in a structure of a TVS device with a uniformly doped base region. Fig. Figure 3 shows a graphical representation of a doping profile (acceptors and donors) in the TVS device structure, which is in Fig. Figure 1 shows a base region containing two differently doped areas. Fig. Figure 4 shows a graphical representation of an electric field in the base region of a TVS device structure having a base with a single homogeneous region, and of an electric field in the base region of a TVS device structure having a base region containing two differently doped regions, as in Fig. 1 illustrates. Fig. Figure 5 shows a planar view of a transient voltage suppression (TVS) arrangement for the protection of electrical equipment against transient electrical energy, which is set up to divert electrical energy away from the electrical equipment.
[0031] Unless otherwise stated, the drawings provided herein are intended to illustrate features of embodiments of the disclosure. It is assumed that these features are applicable in a wide variety of systems, including one or more embodiments of the disclosure. In themselves, the drawings are not intended to include all conventional features that a person skilled in the art would know to be necessary for putting the embodiments disclosed herein into practice. DETAILED DESCRIPTION
[0032] In the following description and claims, reference is made to various expressions which shall be defined in such a way that they shall have the following meaning.
[0033] The singular forms “ein”, “eine” and “der”, “die”, and “das” encompass multiple references, unless the context clearly indicates otherwise.
[0034] “Optional” or “choice” means that the event or circumstance described below may or may not occur, and that the description includes cases in which the event occurs as well as cases in which it does not.
[0035] An approximation language, such as is used throughout this description and the claims, can be used to modify a quantitative representation, which may permissibly vary without altering the basic function with which it is associated. Accordingly, a value modified by an expression or expressions such as "approximately" and "essentially" is not restricted to the exact specified value. In at least some cases, the approximation language may correspond to the precision of an instrument for measuring the value.
[0036] As used herein, references to materials of conductivity of the n+ or p+ type signify a relatively high concentration of dopant defects (e.g. 1×10⁻⁶). 18 cm -3 up to 1×10 21 cm -3References to n- or p-type conductivity materials indicate a relatively low concentration of dopants (e.g., 1 × 10⁻⁶). 14 cm -3 up to 1×10 17 cm -3 ).
[0037] Embodiments of the present disclosure describe the design and process for fabricating a unidirectional transient punch-through voltage suppression (TVS) device or circuit protection device using wide-bandgap semiconductors having a blocking or base region containing two layers with specific dopant concentrations and thicknesses of each layer. This design allows independent control of the breakdown voltage (BV) and the electric field strength (E) in the TVS device and enables a reduction in the blocking region thickness. The independent control of the electric field allows for edge-termination-free designs, thus enabling the use of a simplified etching process to create a vertical mesa and surface passivation to minimize leakage currents along mesa sidewalls.Simplifying the fixture structure (without a cap) and reducing the mesa height (thus simplifying the manufacturing process) results in a reduction of the overall fixture costs.
[0038] The disclosed design allows for a reduced base thickness without compromising BV or E max -Requirements. The base of the TVS structure contains two regions: a relatively thicker, weakly doped region (base region 1) and a relatively thinner, relatively heavily doped region (base region 2). In this structure, depletion propagates first through the weakly doped region and then through the heavily doped region until it reaches the opposite pn junction.
[0039] The following description refers to the attached drawings, in which, unless otherwise stated, the same reference symbols in different drawings represent similar elements.
[0040] Fig. Figure 1 shows a cross-sectional view of an embodiment of a semiconductor device 100 for transient voltage suppression (TVS). In the exemplary embodiment, the TVS device 100 comprises a structure consisting of a substrate 102 made of, for example, silicon carbide with n-type conductivity, an epitaxially grown layer 104 with n+-type conductivity, a first epitaxially grown p--layer 106 coupled in electrical contact with layer 104, a second epitaxially grown p--layer 108 connected in electrical contact with layer 106, and an epitaxially grown n+-layer 110 connected in electrical contact with the second epitaxially grown p--layer 108. Substrate 102 is usually doped with a dopant of a first conductivity type during substrate growth or diffusion processes.In some embodiments, the TVS structure includes a mesa structure with negatively chamfered edges 116 and 118, respectively. The angle α can range from 90° to 135°. Although the mesa structure is described and illustrated as having a negatively chamfered edge, it can also have vertical or nearly vertical edges. Because the TVS device 100 is designed to keep the electric field within the TVS device 100 below a critical electric field strength level by shaping the electric field such that no avalanche breakthrough occurs within the TVS device and through the edges 116 and 118, the angle of the chamfered edge is not critical for the operation of the TVS device 100.
[0041] In various other embodiments, the n+ layers 104 and 110 and / or the p- layers 106 and 108 are produced by ion implantation. For example, in one embodiment, the substrate 102 is an n+ layer, wherein a first n+ layer 104 is formed on the substrate 102, a very lightly doped n-epitaxial layer is formed on the first n+ layer 104, a first section of the n-epitaxial layer up to a predetermined depth is subsequently converted into a p- layer 106 with a first dopant concentration by ion implantation, a second section of the n-epitaxial layer up to a predetermined depth is subsequently converted into a p- layer 108 with a first dopant concentration by ion implantation, and the n+ layer 110 can also be formed on the p- layer 108 by n+ implantation.
[0042] For applications with relatively low voltage, the generation of the p--layers 106 and 108 and / or n+-layers 104 and 110 by ion implantation can enable tighter control of the integrated charge of these layers, which in turn allows for more precise control of the electrical properties of the TVS device 100.
[0043] A first electrical contact, or cathode 112, is electrically connected to the substrate 102. A second electrical contact, or anode 114, is electrically connected to the epitaxially grown or implanted n+ layer 110. The TVS device 100 operates using punch-through physics, also known as pass-through physics, such that when the voltage across the TVS device 100 is increased, a depletion region extends through all p- layers 106 and 108 and reaches the n+ layer 104 and the n+ layer 110. This results in a state known as punch-through, and large amounts of current can flow through the TVS device 100. The TVS device 100 is able to maintain this state with minimal changes in the voltage across it. In the exemplary embodiment, a punch-through operation is achieved when N a *t p- / εε0 is smaller than E c , where Na The acceptor doping concentration in layers 106 and 108 is; t p- is the thickness of layers 106 and 108; ε is the dielectric constant of a material; E c is the critical electric field strength. In embodiments where the TVS device 100 is configured with a PNP junction, punch-through operation is achieved when N d *t n- / εε0 is smaller than E c , where N d The donor doping concentration in layer 108 is; t n- The thickness of the layer is 108.
[0044] In various embodiments, the SiC TVS device 100 is dimensioned and configured to ensure that a maximum electric field strength inside the semiconductor material of the TVS device 100 is maintained at less than approximately two megavolts per centimeter. In other embodiments using different semiconductors, the maximum electric field strength inside the semiconductor material of the TVS device 100 is maintained at a value corresponding to the semiconductor material used. Furthermore, the TVS device 100 is configured to maintain the difference between the Zener and reverse voltages of less than 5%. As used herein, the reverse voltage is the highest voltage at which the TVS device 100 does not conduct or remains in an "off" state. Additionally, the TVS device 100 is configured to maintain an electrical leakage current of less than approximately 1.0 microampere / cm². 2up to approximately the punch-through voltage of the TVS device 100 at room temperature and less than 100.0 microamperes / cm² 2 to maintain up to approximately the punch-through voltage at operating temperatures of up to 225° Celsius.
[0045] In various embodiments, the TVS device 100 is configured to exhibit a punch-through characteristic between approximately 5.0 volts and approximately 75.0 volts. In various further embodiments, the TVS device 100 is configured to exhibit a punch-through characteristic between approximately 75.0 volts and approximately 200.0 volts. In still further embodiments, the TVS device 100 is configured to exhibit a punch-through characteristic at voltages above approximately 200 volts.
[0046] The first epitaxially grown p-layer 106 and the second epitaxially grown p-layer 108 are produced such that layer 106 is relatively thinner than layer 108 and has a relatively higher dopant concentration than layer 108. Varying the relative thickness and doping concentration of layers 106 and 108 allows for the control of an electric field within the TVS device 100 upon breakdown. Constructing the base of the TVS device 100 from two separate layers with different thicknesses and dopant concentrations makes it possible to reduce the overall thickness of layers 106 and 108 compared to an equivalent homogeneously doped layer.
[0047] Furthermore, the disclosed design allows for a reduction in base thickness without loss of BV or E max-Requirements. The base of the TVS structure 100 contains two regions: a relatively thicker, relatively less doped layer 108 and a relatively thinner, relatively more doped layer 106. In this structure, depletion propagates first through the less doped region and second through the more highly doped region until it reaches the opposite pn junction.
[0048] If the doping of layer 108 is very low, the electric field distribution in this layer becomes nearly constant and drops rapidly once it reaches layer 106. Thus, the maximum electric field strength (E) approaches max ) in the two-layer base structure of the TVS device 100 of the dependence V / t_basis, where V is the applied stress and t_basis is the total base thickness. As in Fig. As illustrated in Figure 4, the electric field strength curve of a TVS device with a uniformly doped base has a triangular shape, and thus E max ≈ 2V / t_Basis. This means that the structure of the TVS device with a two-layer base achieves a higher BV for the same base thickness and with the same E max This enables. Alternatively, the TVS fixture structure with a two-layer base allows for a reduction in base thickness while maintaining the same BV and E. max offered. Because the thickness of layer 106 has only a minor influence on E max From a practical point of view, layer 106 is produced as thin as possible to reduce, for example, the mesa height and the etching time during manufacturing.
[0049] Fig. Figure 2 shows a graphical representation 200 of a doping profile (acceptors and donors) in a TVS device structure, which has a uniformly doped base region and provides a BV = 620 V with E < 1.1 MV / cm². The graphical representation 200 includes an x-axis 202, which is divided into units of a base region thickness, e.g., in micrometers, and a y-axis 204, which is divided into units of the dopant concentration, e.g., in electrically activated dopant ions per cm². 3The diagram is divided into sections. A track 206 illustrates a level of acceptor concentration along a depth of the uniformly doped basal region, which is also an indication of the charge contained in the uniformly doped basal region. Tracks 208 and 210 illustrate a concentration of donor concentration along the depth of the uniformly doped n+ regions, which is an indication of the thickness of the uniformly doped basal region. A distance 212 between the vertical sections of tracks 208 and 210 indicates the physical distance between the pn junctions at the interface between the basal region and the adjacent layers in the TVS device. In the exemplary embodiment, the thickness can be determined as the difference between 12 micrometers from track 210 and 0.5 micrometers from track 208, or approximately 11.5 micrometers.
[0050] Fig. Figure 3 shows a graphical representation of a doping profile (acceptors and donors) in a TVS structure with a base region containing two differently doped regions, as in Fig. Figure 1 illustrates this, and the same parameters as the TVS device with the one in Fig. 2 shows a uniformly doped base region, BV = 620V with E < 1.1MV / cm.
[0051] Graph 300 contains an x-axis 302, which is divided into units of the base area thickness, e.g. in micrometers, and a y-axis 304, which is divided into units of the dopant concentration, e.g. in dopant ions per cm. 3The area is divided into sections. A track 306 illustrates a level of acceptor concentration along a depth of the uniformly doped basal region, which also indicates the charge contained in the uniformly doped basal region. Tracks 308 and 310 illustrate a concentration of donors along the depth of the uniformly doped n+ regions, which indicates the thickness of the non-uniformly doped basal region. A distance 312 between the vertical sections of tracks 308 and 310 indicates the physical distance between the pn junctions at the interface between the basal region and the adjacent layers in the TVS device. In the exemplary embodiment, the thickness can be determined as the difference between 6.75 micrometers from track 310 and 0.5 micrometers from track 308, or approximately 6.25 micrometers.
[0052] As in the Fig. 2 and Fig. 3 illustrates, reaches the (in Fig. 1) Illustrated construction with a two-layer base due to the different electric field distribution (see Fig. 4) the same BV and E max in a smaller thickness of the entire base area.
[0053] Fig. Figure 4 shows a graphical representation of an electric field strength in the TVS device having a base with a single homogeneous region and an electric field strength in the TVS device having a base region containing two differently doped regions, as in Fig. Figure 1 illustrates this. Due to the low doping of the base, the electric field is mostly confined to the base region of the TVS device structures. Each of the illustrated TVS device structures provides the same parameters: BV = 620 V with E < 1.1 MV / cm.
[0054] Graph 400 contains an x-axis 402, which is divided into units of the base region thickness, e.g., micrometers, and a y-axis 404, which is divided into units of the electric field, e.g., volts / cm. A track 406 illustrates the electric field strength in the TVS device structure, which has a base with a single homogeneous region. A track 408 illustrates the electric field in the TVS device structure with a base region that has two differently doped regions, such as the (in Fig. (1 illustrated) layers 106 and 108, contains.
[0055] The relationship between the electric field, the breakdown voltage, and the base doping / thickness is defined by a Poisson equation: ∂2ψ∂X2=ρε where ψ denotes a potential, ρ denotes a charge density, ε represents a dielectric constant and x represents a positional coordinate.
[0056] The applicable areas for a SiC punch-through TVS with a two-layer base structure are defined:
[0057] Electric field in the base region under breakthrough conditions: E(x)=∫ot_basisq×N−basis(x)ε×dx, where N_Basis(x) is the dopant concentration in the base region; t_Basis = t_Basis1+t_Basis2 is the total base thickness; q is the electron charge. BV≈∫oEmaxE(x)×dx
[0058] The equations above allow for an estimation of the base doping / thickness to achieve the required BV, E max to obtain. It should be noted that several solutions are possible.
[0059] To minimize the thickness of the base area, the following design rules (equations 4 and 5) are used: N_Basis1*t_Basis1≤10*N_Basis2*t_Basis2 where N_Basis1 represents a dopant concentration in layer 108, e.g. 1×10 14 cm -3 ≤ NBasis1 ≤ 2×10 17 cm -3 , t_Basis1 represents a thickness of layer 108, e.g. t_Basis1 ≥ 0.5µm, N_Basis2 represents a dopant concentration in layer 106, e.g. N_Basis2 ≤ 1×10 18 cm -3 , and t_Basis2 represents a thickness of layer 106, e.g. 0.1µm ≤ t_basis2 ≤ 5µm. 0.1μm≤t_Base2≤0.2* t_Base1
[0060] Trace 406 shows an essentially linear electric field through the thickness of the single homogeneous base region. Trace 408 shows a first linear section 410, a second linear section 412, and a kink 414 at a junction between layer 106 and layer 108.
[0061] Fig.Figure 5 shows a planar view of a transient voltage suppression (TVS) arrangement 500 for protecting electrical equipment against transient electrical energy, configured to dissipate electrical energy from the electrical equipment. In the exemplary embodiment, the TVS arrangement 500 comprises several TVS devices 502, which are connected together at least electrically in parallel. The several TVS devices 502 are formed on a first chip 504 and packed into a single integrated circuit package 506. In various embodiments, several chips of the TVS devices 502 are packed together in a single integrated circuit package 506, or several TVS devices 506 are formed monolithically on a single chip.
[0062] The punch-through TVS design, as described herein, allows for a reduction in the thickness of the blocking area (the base) without compromising fixture performance. Independent electric field control enables edge-closing designs, thus reducing fixture manufacturing costs and overall fixture costs.
[0063] The embodiments of a structure and a method for fabricating a transient voltage suppression (TVS) device described above, which has a base with two regions, each region being independently controlled with respect to thickness and doping concentration, provide a cost-effective and reliable means of improving circuit protection using TVS devices. In particular, the structure and method described herein enable a reduction in the thickness of a TVS device while maintaining circuit protection capabilities compared to a TVS device having a conventional single-layer base region. Consequently, the structure and method described herein enable an improvement in the circuit protection capability of TVS devices in a cost-effective and reliable manner.
[0064] Exemplary embodiments of transient voltage suppression (TVS) devices with multiple domains and methods for manufacturing such devices are not limited to the specific embodiments described herein. Rather, components of devices and / or steps of methods may be used independently and separately from other components and / or steps described herein. For example, the methods may also be used in combination with other devices, and they are not limited to being implemented only in the TVS devices and methods described herein. Rather, the exemplary embodiment may be implemented and used without restriction in conjunction with many other TVS devices.
[0065] Although specific features of different embodiments of the disclosure are illustrated in some drawings and not in others, this is merely for convenience. In accordance with the principles of the disclosure, any feature from one drawing may be referenced and / or claimed in combination with any feature from any other drawing.
[0066] This written description uses examples to disclose the subject matter of the disclosure, including the best way of carrying it out, and also to enable any person skilled in the art to carry out the subject matter of the disclosure, including the creation and use of any devices or systems and the performance of any methods contained therein.
[0067] A device 100 for suppressing transient voltages (TVS device) and a method for manufacturing the device 100 are provided. The TVS device 100 comprises a first layer 104 of a wide-bandgap semiconductor material formed from a material of a first conductivity type, and a second layer 106 of a wide-bandgap semiconductor material formed from a material of a second conductivity type over at least a section of the first layer 104, wherein the second layer has a first dopant concentration.The TVS device further comprises a third layer 108 of a wide-bandgap semiconductor material, formed from the material of the second conductivity type over at least a section of the second layer 106, wherein the third layer contains a second dopant concentration, the second dopant concentration being different from the first dopant concentration. The TVS device further comprises a fourth layer 110 of a wide-bandgap semiconductor material, formed from the material of the first conductivity type over at least a section of the third layer 108. Parts list 100 TVS device 102 Substrat 104 first n+ layer 106 shifts 108 shifts 110 shifts 112 Cathode 114 Anode 116 margins 118 margins 200 graphics 202 x-axis 204 y-axis 206 lane 208 lane 210 track 212 distance 300 graphics 302 x-axis 304 y-axis 306 track 308 lane 310 track 312 distance 400 graphics 402 x-axis 404 y-axis 406 track 408 track 410 first linear section 412 second linear section 414 Folding point 500 TVS arrangement 502 TVS device 504 first chip 506 pack
Claims
[1] Device (100) for suppressing transient voltages (TVS) comprising: a first layer (104) of a large bandgap semiconductor material formed from a material of a first conductivity type; a second layer (106) of a large bandgap semiconductor material formed from a material of a second conductivity type over at least one section of the first layer (104), wherein the second layer has a first thickness and a first dopant concentration; a third layer (108) of a large bandgap semiconductor material formed from the material of the second conductivity type over at least a section of the second layer (106), wherein the third layer (108) has a second thickness and a second dopant concentration, wherein the second thickness is greater than the first thickness, and wherein the second dopant concentration is lower than the first dopant concentration; and a fourth layer (110) of a large bandgap semiconductor material formed from the material of the first conductivity type over at least a section of the third layer (108), wherein the first dopant concentration and the second dopant concentration are determined according to: Nthird_layer*tthird_layer < 10*Nsecond_layer*tsecond_layer, where N_third_layer represents the second dopant concentration, where the second dopant concentration is 1x1015 cm -3 < N third layer < 2×10 17 cm -3 fulfilled where t_third_layer represents the second thickness of the third layer (108), where N_second_layer represents the first dopant concentration, and where t_second layer represents the first thickness, where the first thickness satisfies 2 µm < t_second layer < 5 µm. [2] Device according to claim 1, further comprising at least one of the following: a first electrical contact surface (112) on a side of the first layer (104) opposite the second layer (106); or a second electrical contact surface (114) on a side of the fourth layer (110) opposite the third layer (108). [3] Device according to claim 1, wherein the first dopant concentration in the second layer (106) N_second layer < 1×10 18 cm -3 fulfilled. [4] Device according to claim 1, wherein the second thickness of the third layer (108) t_third layer > 0.5 µm. [5] Device according to claim 1, wherein the first thickness of the second layer (106) is determined according to 2 µm < t_second_layer < 0.2*t_third_layer. [6] Device according to any one of the preceding claims, wherein the TVS device operates using punch-through physics. [7] Device according to claim 6, wherein the TVS device is configured to exhibit a punch-through characteristic between approximately 75.0 volts and approximately 200.0 volts. [8] Device according to claim 6, wherein the TVS device is configured to exhibit a punch-through characteristic between approximately 5.0 volts and approximately 75.0 volts; or wherein the TVS device is configured to exhibit a punch-through characteristic at voltages above approximately 200 volts. [9] Device according to any one of the preceding claims, wherein the TVS device is configured to deliver a current of more than 10 kA / cm² during a transient overvoltage event 2 leads; or the TVS device is configured to deliver a current between 5 kA / cm² during a transient overvoltage event 2 and 10 kA / cm 2 leads; or the TVS device is configured to deliver a current between 1 kA / cm² during a transient overvoltage event 2 and 5 kA / cm 2 leads.
Citation Information
Patent Citations
Method and system for ultra miniaturized packages for transient voltage suppressors
US20130240903A1
Low-voltage punch-through transient suppressor employing a dual-base structure
US5880511A
Electrostatic discharge protection element and electrostatic discharge protection chip and method of producing the same
US8270131B2