Load control reset signal generation circuit

Abstract

A load control reset signal generating circuit (20) for supplying a reset control signal (SGbk) to a switch (32) of a load (31) in the event that an abnormality occurs in a control processor (10), the switch (32) of the load (31) being connected to an output (11) of the control processor (10) operating according to a program, the load control reset signal generating circuit (20) comprising: a first input terminal (21) receiving a constant period signal (SGw / d) periodically output from the control processor (10) when the control processor (10) is normal; a constant-period signal observation section (26, 52) which observes a state of the constant-period signal (SGw / d) to identify whether a length of time during which a high or low level state of the constant-period signal (SGw / d) lasts longer than a predetermined time (Tth2), and which outputs a signal (SGT2) corresponding to a result of the identification; a reset control signal output section (27) which outputs the reset control signal (SGbk) to control on and off switching of the switch (32) of the load (31) when the output of the constant period signal observation section (26, 52) corresponds to a predetermined condition; a second input terminal (23) receiving a control signal (SGout) output from the control processor (10) when the control processor (10) is normal; a control signal observation section (25, 51) which observes a state of the control signal (SGout) to identify whether a length of time during which the abnormal level state of the control signal (SGout) lasts longer than a predetermined time (Tth1), and which outputs a signal (SGT1) corresponding to a result of the identification, wherein the reset control signal output section (27) outputs a reset control signal (SGbk) when an output of the control signal observation section (25,51) corresponds to a predetermined condition.

Description

[0001] The present invention relates to a load control reset signal generating circuit for supplying a reset control signal to the switch of a load connected to the output of a control processor operating according to a predetermined program in the event that an abnormality occurs in the control processor.

[0002] For example, a control microprocessor, that is, a microcomputer (CPU: central processing unit) that operates according to a predetermined program, is used in various electrical control units (ECUs) mounted on vehicles.

[0003] Such a microcomputer typically executes various controls as intended according to the scope of a previously created program. However, for example, in the case of external electromagnetic noise, in the case of a malfunction, or in the case of defects (bugs) contained in the program itself, the microcomputer may temporarily perform unexpected operations and enter an uncontrolled state.

[0004] When the microcomputer is brought into such an uncontrolled state, the entire electrical control unit falls into an uncontrollable state. Therefore, in the systems of various electrical control units, it is necessary to monitor whether an abnormality has occurred in the microcomputer, and if an abnormality is detected, it is necessary to return the microcomputer to its normal state.

[0005] Therefore, in such various electrical control units, the microcomputers perform controls to periodically output pulse signals related to monitoring signals to the outside. Furthermore, a monitoring circuit is connected to the outside of the microcomputer, and this monitoring circuit constantly monitors the monitoring signal output from the microcomputer. When an abnormality occurs in the microcomputer, the monitoring signal does not appear. By detecting the state where the monitoring signal does not appear for a constant period of time, the monitoring circuit initializes the operation of the microcomputer.

[0006] In the electronic control unit in the vehicle according to JP 2010-13988 A, when the main CPU 10 shown in Fig. 1, is brought into an uncontrolled state and the pulse signal width of the monitoring signal WDS becomes extremely large, a power control circuit 113 detects this state and generates a reset pulse signal RST.

[0007] Also, in the electronic control system used in a vehicle according to JP 2011-98593 A, a monitor signal timer 24 incorporated in a power source control IC 23 monitors the operation state of a CPU 1 based on the monitor signal transmitted from the CPU 1 and transmits a reset signal RST when abnormality occurs.

[0008] As described in JP 2010-13988 A and JP 2011-98593 A, abnormalities in the operation of the microcomputer can be detected by observing the monitor signal output from the microcomputer. In addition, upon detection of the abnormality, the monitor signal monitoring circuit applies a reset signal to the microcomputer. When the reset signal is applied, the microcomputer initializes the hardware state and restarts program execution from its initial position at the time of power supply.

[0009] Therefore, in the case where the microcomputer has been brought into an uncontrolled state due to a temporary factor such as the occurrence of electromagnetic noise, the operation of the microcomputer can be returned to its normal state by applying the reset signal.

[0010] However, if a continuous error occurs in the microcomputer, the microcomputer's operation cannot be restored to its normal state even if the reset signal is applied. Furthermore, if a failure occurs in the microcomputer provided in an electronic control unit for controlling the power supply to a load, the power supply to the load cannot be turned on or off even if a monitoring signal monitoring circuit is installed.

[0011] Therefore, it is advantageous that a reset circuit be mounted on an electronic control unit in a vehicle or the like in preparation for the occurrence of a fault in the microcomputer. In other words, instead of the microcomputer, a circuit for generating a reset control signal for controlling a load is necessary so that the power supply to the load can be turned on / off even if the microcomputer is faulty.

[0012] Furthermore, even in a situation where the microcomputer is not in an uncontrolled state and the program is executed correctly, the function of only a specific output terminal of the microcomputer may be faulty. Therefore, for example, if the control signal for controlling the load on / off is generated using the faulty output terminal of the microcomputer, a faulty state occurs in which the load cannot be controlled, and this state persists even if the monitoring signal is normal.

[0013] Here's a case where the on / off request of the load power supply is set by using a PWM (Pulse Width Modulation) signal as the control signal to control the load. Furthermore, here's a case where the power supply is turned on and off using a simple binary signal (high / low). Therefore, it's not easy to identify whether the output function of the control signal is normal or not.

[0014] Furthermore, errors that can occur in the microcomputer are classified into errors that occur continuously and errors that occur temporarily. It is advantageous that the reset control signal can be used even when a temporary error occurs in the microcomputer. However, if the reset control signal occurs continuously at the time of error recovery, the operating state of the microcomputer cannot be restored to its normal operating state.

[0015] Further prior art is given in DE 10 2011 076 166 A1 and DE 10 2004 033 095 A1. SUMMARY

[0016] The present invention is made in view of the above circumstances, and the object of the invention is to provide a load control reset signal generating circuit capable of surely outputting a reset control signal for controlling a load in the event that a failure occurs in a microcomputer.

[0017] To achieve the above object, a load control reset signal generating circuit according to claim 1 is provided. The present disclosure includes the following items (1) to (8). (1) A load control reset signal generating circuit for supplying a reset control signal to a switch of a load connected to an output of a control processor operating according to a program in a case that abnormality occurs in the control processor, the reset signal generating circuit includes: a first input terminal receiving a constant period signal periodically outputted by the control processor when the control processor is normal; a constant-period signal observation section that observes a state of the constant-period signal to identify whether a length of time during which a high or low level state of the constant-period signal lasts longer than a predetermined time, and that outputs the signal corresponding to a result of the identification; and a reset signal output section that outputs the reset control signal when the output of the constant period signal observation section meets a predetermined condition. (2) The load control reset signal generating circuit described in the above-mentioned item (1), which further includes according to the invention: a second input terminal that receives a control signal output from the control processor when the control processor is normal; a control signal observation section that observes a state of the control signal to identify whether a length of time during which the abnormal level state of the control signal lasts longer than a predetermined time, and that outputs the signal according to a result of the identification, wherein the reset control signal output section outputs a reset control signal when an output of the control signal observation section corresponds to a predetermined condition. (3) The load control reset signal generating circuit described in the above-mentioned item (2), wherein the reset control signal output section generates a reset control signal according to a logical OR of a state in which the output of the constant period signal observing section satisfies the predetermined condition and a state in which the output of the control signal observing section satisfies the predetermined condition. (4) The load control reset signal generating circuit described in the above item (1), which includes: a timing clock generating section that outputs timing clock pulses when a status signal applied to an input in the control processor is active; a first counter that counts the timing clock pulses output from the timing clock generating section when a level of the control signal output from the control processor is a predetermined level; a second counter that counts the timing pulses output from the timing clock generating section during the time in which the high or low level state of the constant period signal periodically output from the control processor progresses; and a cancellation circuit that returns the state of the reset signal output section to an initial state of the reset control signal output section after detecting that both the control signal and the constant period signal are normal. (5) The load control reset signal generating circuit described in the above item (2), which includes: a signal gate circuit connected between the first input terminal and the input of the constant-period signal observation section, wherein the output of the control signal observation section is connected to a control input of the signal gate circuit. (6) The load control reset signal generating circuit described in the above item (5), which includes: a cancellation circuit that observes an output signal of the signal gate circuit and that returns the state of the reset signal output section to an initial state of the reset signal output section when it is detected that the output signal of the signal gate circuit is normal. (7) The load control reset signal generating circuit described in the above item (6), which further includes: a timing clock generation section that outputs timing clock pulses when the status signal applied to the input of the control processor is active; and a counter that counts the timing clock pulses output from the timing clock generating section during the time in which a high or low level state of the constant period signal reaching the output of the timing clock generating section progresses. (8) The load control reset signal generating circuit described in the above-mentioned item (7), wherein a DC cutoff capacitor is connected between the output of the signal gate circuit and the input of the counter; and wherein the input of the counter is connected to a predetermined potential line via a potential control resistor provided therebetween.

[0018] With the load control reset signal generation circuit configured as described in the above item (1), the constant-period signal observation section observes the constant-period signal as a monitoring signal, thereby being able to reliably identify the presence or absence of abnormality. In addition, when the constant-period signal observation section detects the occurrence of an abnormality, the reset signal output section generates a reset control signal. Therefore, even when an abnormality occurs in the control processor, the power supply to the load can be controlled using the reset control signal.

[0019] With the load control reset signal generation circuit configured as described in item (2) above, the control signal monitoring section monitors the state of a control signal, such as a PWM signal or a simple binary signal, thereby reliably identifying the presence or absence of an abnormality. Additionally, when the control signal monitoring section detects the occurrence of an abnormality, the reset signal output section generates a reset control signal. Therefore, even when an abnormality occurs in the control processor, the power supply to the load can be controlled using the reset control signal.

[0020] With the load control reset signal generation circuit configured as described in the above-mentioned item (3), the reset control signal can be generated when either the constant-period signal monitoring section or the control signal monitoring section detects the occurrence of an abnormality. Therefore, the reset control signal can be output in both the case where an abnormality has occurred in the control processor caused by program uncontrollability and the case where the abnormality is caused by a fault at the output terminal.

[0021] With the load control reset signal generation circuit configured as described in the above item (4), the first counter can identify the presence or absence of abnormality related to the control signal, and the second counter can identify the presence or absence of abnormality related to the constant period signal. Furthermore, when the normal state is restored from a state where an abnormality occurs, the reset control signal can be automatically released using the function of the cancellation circuit.

[0022] Furthermore, since the output of the timing pulses is suppressed when the status signal is not active, the reset control signal can be prevented from being erroneously output, for example, in a situation where observation is not necessary or in a situation where fault identification is impossible.

[0023] With the load control reset signal generation circuit configured as described in the above item (5), the output state of the control signal observation section can be reflected to the input state of the constant-period signal observation section. Therefore, the constant-period signal observation section can simultaneously observe both the constant-period signal and the control signal.

[0024] With the load control reset signal generation circuit configured as described in the above item (6), when the normal state is restored from a state where an abnormality occurs, the reset control signal can be automatically released using the function of the cancellation circuit. Furthermore, the configuration of the cancellation circuit can be simplified by using the output signal from the signal gate circuit as the target to be monitored.

[0025] With the load control reset signal generation circuit configured as described in the above item (7), the counter can identify the presence or absence of an abnormality related to the control signal and the presence or absence of an abnormality related to the constant period signal. Furthermore, since the output of the timing clock pulses is suppressed when the status signal is not active, the reset control signal is prevented from being erroneously output, for example, in a situation where observation is not necessary or in a situation where fault identification is impossible.

[0026] With the load control reset signal generating circuit configured as described in the above item (8), for example, when a fault occurs and the high / low level change in the constant period signal as the monitor signal stops, the input to the counter is fixed to a specific level regardless of whether the level of the constant period signal is "high" or "low", whereby reliable operation can be expected.

[0027] With the load control reset signal generating circuit according to the present invention, in the event that a failure occurs in a microcomputer, the reset control signal for controlling a load can be surely output.

[0028] The present invention has been described above in a preliminary manner. The details of the present invention will be further clarified by reading the description of the mode (hereinafter referred to as "embodiment") for carrying out the invention described below while referring to the accompanying drawings. DESCRIPTION OF THE DRAWINGS Fig. 1 is an electrical circuit diagram showing a basic configuration example of an electronic control unit including a reset signal generating circuit according to an embodiment. Fig. Figure 2 is a timing diagram showing the main electrical signals in the electronic control unit shown in Fig. 1, shows. Fig. 3 is a timing chart showing an operation in the case that abnormality occurs in a monitor signal. Fig. 4 is a timing chart showing an operation in the case that abnormality occurs in a control signal. Fig. 5 is a time chart showing an operation in a case where an abnormal condition is resolved. Fig. 6 is an electrical circuit diagram showing another specific configuration example of the electronic control unit shown in Fig. 1, shows. Fig. 7 is an electrical circuit diagram showing a configuration of a modified example of the reset signal generating circuit. Fig. Fig. 8 is an electrical circuit diagram showing a more specific configuration example of the reset signal generating circuit shown in Fig. 7, shows. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0029] A specific embodiment relating to a load control reset signal generating circuit according to the present invention will be described below with reference to the drawings. <Beschreibung eines Konfigurationsbeispiels><Grundsätzliche Beschreibung der gesamten Steuereinheit>

[0030] A configuration example of a main portion of an electronic control unit 100 including a reset signal generating circuit 20 according to this embodiment is shown in Fig. 1 shown.

[0031] The electronic control unit 100 shown in Fig. 1, includes a microcomputer 10 serving as a main control section. The microcomputer 10 can, for example, perform controls for implementing functions required by the electronic control unit by executing programs previously incorporated into an internal memory (ROM).

[0032] In the configuration example shown in Fig. 1, the microcomputer 10 has a function for controlling the power supply to a load 31 based on the on / off of a status signal SGin output from an instruction switch SW. Furthermore, when the power supply to the load 31 is turned on, the current for the load can be adjusted by performing operation control using a PWM signal.

[0033] A switch operable by a user or a sensor, or the like, can be assumed as a specific example of the instruction switch SW. The microcomputer 10 starts outputting a control signal SGout so that the load 31 is energized when the instruction switch SW is turned on, and stops outputting the control signal SGout so that the load 31 is not energized when the instruction switch SW is turned off. The control signal SGout is a PWM signal or a binary signal.

[0034] Any of various electronic components in a vehicle can be considered a specific example of the load 31. Further, a switching device 32 consisting of a power FET controls the on / off state of the power supply of the load 31 according to the on / off (high / low) level of the power supply control signal SG2, such as a PWM signal or a binary signal.

[0035] During operation of the microcomputer 10, the power supply control signal SG2 for controlling the load 31 usually changes depending on the control signal SGout output from the microcomputer's output terminal 11. However, in some cases, a continuous or temporary failure may occur in the microcomputer 10. If the microcomputer 10 is faulty, the control signal SGout does not change, causing the microcomputer to be unable to perform the on / off control of the load 31.

[0036] The reset signal generating circuit 20 is mounted as a reset in the event that the microcomputer 10 becomes faulty. In other words, when an abnormality occurs in the control signal SGout, which is normally output, a reset control signal SGbk output from the reset signal generating circuit 20 controls the load 31 instead of the microcomputer 10. <Beschreibung des Rückstell-Signal-Erzeugungs-Kreises 20>

[0037] The reset signal generating circuit 20 shown in Fig. 1, includes a monitor input terminal 21, a reset control signal output terminal 22, a control signal input terminal 23, and a status signal input terminal 24 for inputting and outputting various signals. Additionally, two timing circuits 25 and 26, a latch circuit 27, a cancel circuit 28, and diodes D1 to D4 are provided in the reset signal generating circuit 20.

[0038] One input terminal of the timer circuit 25 is connected to the output terminal 11 of the microcomputer 10 via the control signal input terminal 23. Therefore, the timer circuit 25 can observe the high (Hi) / low (Lo) level (potential) of the control signal SGout. Furthermore, the other input terminal of the timer circuit 25 is connected to the instruction switch SW via the status signal input terminal 24. Consequently, the timer circuit 25 can perform an operation depending on the high (Hi) / low (Lo) level of the status signal SGin, which represents the on / off state of the instruction switch SW.

[0039] When the level of the status signal SGin is active (Hi), the timer circuit 25 detects whether the time during which the "Lo" level state of the control signal SGout continues for longer than a predetermined threshold time (Tth1) indicates the presence or absence of an abnormality, and outputs a binary signal representing the detection result as a timer output signal SGT1. When the level of the status signal SGin is inactive (Lo), the detection operation is inhibited.

[0040] One input terminal of the timer circuit 26 is connected to the monitor signal output terminal 12 of the microcomputer 10 via the monitor input terminal 21. Therefore, the timer circuit 26 can monitor the high (Hi) / low (Lo) level of a monitor signal SGw / d. Furthermore, the other input terminal of the timer circuit 26 is connected to the instruction switch SW via the status signal input terminal 24. Consequently, the timer circuit 26 can perform an operation depending on the high (Hi) / low (Lo) level of the status signal SGin, which represents the on / off state of the instruction switch SW.

[0041] When the level of the status signal SGin is active (Hi), the timer circuit 26 detects whether the time during which the "Lo" or "Hi" level state of the monitor signal SGw / d continues for longer than a predetermined threshold time (Tth2) indicates the presence or absence of an abnormality, and outputs a binary signal representing the detection result as the timer output signal SGT2. When the level of the status signal SGin is inactive (Lo), the detection operation is inhibited.

[0042] The output terminal of the timing circuit 25 is connected to the input terminal of the latch circuit 27 via a backflow prevention diode D1. Additionally, the output terminal of the timing circuit 26 is connected to the input terminal of the latch circuit 27 via the backflow prevention diode D2.

[0043] Upon detection of either (logical OR) the presence of abnormality in the timer output signal SGT1 output from the timer circuit 25 or the presence of abnormality in the timer output signal SGT2 output from the timer circuit 26, the latch circuit 27 closes (latches) the level (Hi) of the state and outputs the level as the reset control signal SGbk.

[0044] The reset control signal SGbk output from the latch circuit 27 is applied to the control input (gate terminal) of the switching device 32 via the backflow prevention diode D4. Furthermore, the control signal SGout output from the output terminal 11 of the microcomputer 10 is applied to the control input (gate terminal) of the switching device 32 via the backflow prevention diode D3. Therefore, the on / off of the switching device 32 is determined by either (logical OR) the control signal SGout or the reset control signal SGbk.

[0045] The cancel circuit 28 is provided to return the latch circuit 27 to its initial state and stop the output of the reset control signal SGbk at the time the normal state is detected. One input terminal of the cancel circuit 28 is connected to the output connector 11 via the control signal input terminal 23. Furthermore, the other input terminal of the cancel circuit 28 is connected to the monitor signal output connector 12 via the monitor input terminal 21. Furthermore, a signal SG3, which serves as the logical OR of the two timer output signals SGT1 and SGT2, is applied to the reset input (RST) of the cancel circuit 28.

[0046] The cancellation circuit 28 identifies whether a normal signal is present as the control signal SGout after the "Hi" level of the signal SG3 is closed by the latch circuit 27, and whether a normal signal also appears as the monitor signal SGw / d, and then outputs a binary signal representing the result of the identification as a reset signal SGrst. This reset signal SGrst is applied to the reset input (RST) of the latch circuit 27. <Beschreibung des Betriebs><Beschreibung des Basisbetriebs>

[0047] Examples of the waveforms of the timing generators of the main electrical signals in the electronic control unit 100 shown in Fig. 1, are in Fig. 2 shown.

[0048] In the electronic control unit 100, shown in Fig. 1, when the instruction switch SW is turned on, the microcomputer 10 detects the active level of the state signal SGin, and the microcomputer 10 outputs the control signal SGout to the output terminal 11 according to the state signal. The control signal SGout is usually a PWM signal, the high (Hi) / low (Lo) level of which is periodically switched, or a binary signal, the level of which is fixed at "Hi," as shown in Fig. 2. Furthermore, in the case of the PWM signal, operation control can be performed by adjusting the ratio between the "Hi" zone (ToH) and the "Lo" zone (ToL) of the signal.

[0049] On the other hand, the microcomputer 10 inverts the signal levels of the monitor signal output terminal (W / D) 12 in synchronization with the execution of the process of each routine in a program to be executed. Therefore, in the state where the microcomputer 10 executes the program normally, a pulse signal in which Hi / Lo switching occurs switches continuously in relatively short periods as the monitor signal SGw / d output from the monitor signal output terminal 12, as shown in Fig. 2 shown. <In dem Fall, dass das Überwachungs-Signal SGw / d abnormal ist>

[0050] An operation example in the case that abnormality occurs in the monitoring signal SGw / d is shown in Fig. 3. The operation shown in Fig. 3, is described below.

[0051] Sometimes, a case occurs where the microcomputer 10 cannot continuously execute the program normally (the microcomputer is placed in an unstable state), for example, due to the influence of external electromagnetic noise or defects (bugs) in the program. In such a case, the microcomputer 10 cannot switch the level of the monitor signal output terminal 12 in every routine, causing the pulse of the monitor signal SGw / d to stop and its level to be fixed at "Hi" or "Lo."

[0052] In the operating example shown in Fig. 3, it is assumed that the abnormality in the operation of the microcomputer 10 occurs around the time t01, the pulse of the monitor signal SGw / d stops at the time t01, and the level of the pulse remains “Hi” and is unchanged.

[0053] On the other hand, in the reset signal generating circuit 20 shown in Fig. 1, the timing circuit 26 monitors the pulse of the monitoring signal SGw / d. Specifically, the timing circuit identifies whether the length of time during which the "Hi" or "Lo" level state of the monitoring signal SGw / d remains longer than a predetermined threshold time (Tth2).

[0054] In the operating example shown in Fig. 3, after the level of the monitor signal SGw / d changes from "Lo" to "Hi" at time t01, the "Hi" state remains for a long time. Therefore, the level of the timer output signal SGT2 changes from "Lo" to "Hi" at time t02 when the elapsed time from time t01 is more than the threshold value (Tth2). In other words, the level change of the timer output signal SGT2 to "Hi" indicates the occurrence of an abnormality in the monitor signal SGw / d.

[0055] Furthermore, when the level of the timer output signal SGT2 output from the timer circuit 26 changes to "Hi", the latch circuit 27 in the later state closes this level "Hi" and outputs the level as the reset control signal SGbk.

[0056] In other words, as in Fig. As shown in Figure 3, when the time elapsed after the monitor signal SGW / D remains unchanged for more than the predetermined time (Tth2), "Hi" is output as the reset control signal SGbk. Therefore, in the event that the microcomputer 10 is brought into an unstable state and the monitor signal SGw / d stops, the on / off operation of the switching device 32 can be controlled using the reset control signal SGbk. <In dem Fall von Abnormalität in dem Steuer-Signal SGout>

[0057] An operation example in the case that abnormality occurs in the control signal SGout is shown in Fig. 4. The operation shown in Fig. 4, is described below.

[0058] Even if the microcomputer 10 continues to execute the program normally, sometimes a case occurs where some of the functions of the microcomputer 10 become faulty. For example, if a physical failure occurs in the circuit of the output terminal 11, the current level of the output terminal 11 may sometimes remain unchanged at "Low" even if "Hi" is output to the output terminal 11 by the execution of the program using the microcomputer 10.

[0059] The timer circuit 25, shown in Fig. 1, monitors the control signal SGout to detect the occurrence of such an error. Currently, the state in which pulses periodically occur in the control signal SGout is normal, and the state in which the level of the control signal SGout is fixed at "Hi" is also normal. On the other hand, the state in which the level of the control signal SGout remains unchanged at "Low" even though the level of the state signal SGin is active is considered abnormal. Therefore, the timer circuit 25 compares the length of time during which the "Low" level state of the control signal SGout progresses with the threshold value (Tth1) and detects the occurrence of abnormality if the length is longer than the threshold value.

[0060] In the operating example shown in Fig. 4. After the level of the control signal SGout changes to "Lo" at time t11, the state in which the level remains unchanged continues for a long time. Therefore, when the threshold time (Tth1) from time t11 has elapsed, the timer circuit 25 detects an abnormality, and the level of the timer output signal SGT1 becomes "Hi."

[0061] Furthermore, when the level of the timing output signal SGT1 output from the timing circuit 25 changes to "Hi," the latch circuit 27 latches this "Hi" level and outputs the "Hi" level as the reset control signal SGbk. Therefore, even if a fault occurs in the output terminal 11, the switching device 32 can be controlled using the reset control signal SGbk. <Fall, in dem Abnormalität gelöst ist>

[0062] An operation example in which the abnormality condition is resolved after the occurrence of the abnormality in the microcomputer 10 is shown in Fig. 5. The operation shown in Fig. 5, is described below.

[0063] As in the case shown in Fig. 4, is shown in the operation in Fig. 5, in the case that the level of the control signal SGout is fixed at "Lo" for a long time from the time t11, the level of the timer output signal SGT1 becomes "Hi" at the time t12 and the level of the reset control signal SGbk also becomes "Hi".

[0064] However, in the operating example shown in Fig. 5, the state of the output terminal 11 is spontaneously returned after time t12, and a normal signal (Hi or pulse) reappears as the control signal SGout. In this case, the cancel circuit 28 detects that the monitor signal SGw / d is normal and detects that the state of the control signal SGout is "Hi" at time t13, and then outputs a "Hi" pulse as the reset signal SGrst.

[0065] The latch circuit 27 is reset to its initial state by the "Hi" pulse of the reset signal SGrst output from the cancel circuit 28. Therefore, the reset control signal SGbk output from the latch circuit 27 is reset from "Hi" to "Lo" after time t13.

[0066] In the operating example shown in Fig. 5, it is assumed that after the abnormality occurs in the control signal SGout, the abnormal state returns to normal. However, even in the case where the monitor signal SGw / d is abnormal, the cancellation circuit 28 can output the reset signal SGrst in the same way. <Beschreibung einer weiteren spezifischen Konfiguration>

[0067] A more specific configuration example of the electronic control unit 100 shown in Fig. 1, is in Fig. 6. The configuration of the electronic control unit 100A shown in Fig. 6, is the same as the one in Fig. 1, except for a reset signal generating circuit 20A. Therefore, the reset signal generating circuit 20A is described below.

[0068] The reset signal generating circuit 20A shown in Fig. 6, includes two counters 41 and 42, an edge detector 43, a timer generator 44, an AND gate 45, a D-type flip-flop (DFF) 46 and a cancellation circuit 47. Furthermore, as in the reset signal generating circuit 20 shown in Fig. 1, a diode is connected to each output of the counter 41 and 42 and to the output of the D flip-flop 46.

[0069] The circuit composed of the counter 41, the timer generator 44 and the AND gate 45 in the reset signal generating circuit 20A shown in Fig. 6, realizes the same functions as the timer circuit 25, shown in Fig. 1. In the same way, the circuit consisting of the counter 42, the edge detector 43, the timer generator 44 and the AND gate 45 realizes the same function as that of the timer circuit 26 shown in Fig. 1. Furthermore, the D-type flip-flop 46 realizes the same function as that of the latch circuit 27, and the cancel circuit 47 realizes the same function as that of the cancel circuit 28.

[0070] The timing generator (time source) 44 is formed from, for example, a CR oscillation circuit or a crystal oscillation circuit and constantly generates timing pulses with a constant period. The period of the timing pulses to be generated is determined to be sufficiently shorter than the period of the PWM pulses of the control signal SGout and the period of the pulses of the monitoring signal SGw / d.

[0071] The AND gate 45 generates a timing pulse signal CLK2 based on the timing pulse signal CLK1 output from the timing generator 44 and the state signal SGin. In other words, the AND gate 45 directly outputs the timing pulse signal CLK1 as the timing pulse signal CLK2 when the level of the state signal SGin is active (Hi) and prevents the pulse from being output as the timing pulse signal CLK2 when the level of the state signal SGin is inactive (Lo).

[0072] During the time the "Lo" level state of the control signal SGout persists, the counter 41 counts the number of pulses of the time pulse signal CLK2. Therefore, the counter 41 can measure the length of time while the "Lo" level state of the control signal SGout progresses. When the level of the control signal SGout becomes "Hi," the count value of the counter 41 is canceled. If the "Lo" level state of the control signal SGout persists for the predetermined time (Tth1), the output of the counter 41 becomes "Hi," and this "Hi" is applied to the input of the D-type flip-flop 46 via the diode provided at the output. However, in the case that the level of the status signal SGin is inactive (Lo), the pulses of the timing pulse signal CLK2 are stopped, thereby preventing the continued operation of the counter 41.

[0073] The edge detector 43 detects the rising edge from "Lo" to "Hi" and the falling edge from "Hi" to "Lo" in the pulse of the monitor signal SGw / d and outputs signals at these edge timings. Based on the signal output from the edge detector 43, the counter 42 counts the number of pulses of the timing pulse signal CLK2 output from the AND gate 45 during the time from the occurrence of one edge to the occurrence of the next edge. When the edge occurs, the count is canceled. Therefore, the counter 42 can measure the time interval between the edges of the pulses in the monitor signal SGw / d. Furthermore, in the case that the state in which the "Lo" or "Hi" level of the monitor signal SGw / d remains unchanged proceeds for the predetermined time (Tth2), the output of the counter 42 becomes "Hi", and this "Hi" is applied to the input of the D-type flip-flop 46 via the diode provided at the output.However, in the case that the level of the status signal SGin is inactive (Lo), the pulses of the time pulse signal CLK2 are stopped, thereby preventing the continuation of the operation of the counter 42.

[0074] When "Hi" is applied to the input of the D-type flip-flop 46, the flip-flop 46 can close the level and output the level as the reset control signal SGbk. Further, by applying the reset signal SGrst to the reset terminal of the D-type flip-flop 46 after outputting "Hi" as the reset control signal SGbk, the D-type flip-flop 46 can be reset, and the reset control signal SGbk can be released (Lo is output).

[0075] The cancellation circuit 47 for generating the reset signal SGrst is composed of two D-type flip-flops 47a and 47b and an AND gate 47c in the example shown in Fig. 6. The D-type flip-flop 47a is reset by the signal SG3, and when the state of the control signal SGout becomes "Hi," the D-type flip-flop 47a (latching) closes this "Hi" and outputs the close signal. Furthermore, the D-type flip-flop 47b is reset by the signal SG3, and when the edge detector 43 outputs an edge detection signal, the D-type flip-flop 47b closes "Hi" and outputs the close signal. When the output of the D-type flip-flop 47a is "Hi" and the output of the D-type flip-flop 47b is "Hi," the AND gate 47c outputs the effective level "Hi" as the reset signal SGrst.

[0076] Consequently, the reset signal generating circuit 20A shown in Fig. 6, functions equal to those of the components of the reset signal generating circuit 20 shown in Fig. 1. In other words, the reset signal generating circuit 20A can realize such operations as those shown in Fig. 2 to 5, execute. <Beschreibung eines Modifikationsbeispiels des Rückstell-Signal-Erzeugungs-Kreises 20><Beschreibung einer funktionalen Konfiguration>

[0077] A configuration of a modification example of the reset signal generating circuit 20 shown in Fig. 1, is in Fig. 7. The configuration of the electronic control unit, shown in Fig. 7, is equal to that of the electronic control unit 100 shown in Fig. 1, except for the configuration of the reset signal generating circuit 20B shown in Fig. 7. Therefore, the reset signal generating circuit 20B is described below.

[0078] The reset signal generating circuit 20B, shown in Fig. 7, includes first and second circuits 51 and 52, an analog gate circuit 53, a latch circuit 54 and a cancellation circuit 55. The first and second timing circuits 51 and 52, the latch circuit 54 and the cancellation circuit 55 shown in Fig. 7, have functions comparable to those of the timing circuits 25 and 26, the signal storage circuit 27 and the cancellation circuit 28, shown in Fig. 1.

[0079] The configuration shown in Fig. 7, is significantly different from that shown in Fig. 1, in that the analog gate circuit 53 is newly inserted between the monitoring signal output terminal 12 of the microcomputer 10 and the second timer circuit 52, and that the output of the first timer circuit 51 is connected to the control input of the analog gate circuit 53. In addition, since only the output of the second timer circuit 52 is connected to the input of the latch circuit 54, the diodes D1 and D2 shown in Fig. 1, not required to be connected to it.

[0080] The analog gate circuit 53, shown in Fig. 7, is configured to use a transistor. The collector terminal, emitter terminal, and base terminal of this transistor are connected to the monitoring signal output terminal 12, the input of the second timing circuit 52, and the output of the first timing circuit 51, respectively.

[0081] As in the above-mentioned timer circuit 25, the first timer circuit 51 identifies the presence or absence of abnormality in the control signal SGout and outputs the signal corresponding to the identification result. Specifically, if the "Lo" state of the control signal SGout persists for a predetermined time (Tth1) or longer, the first timer circuit 51 outputs a signal to turn off the analog gate circuit 53. If the control signal SGout is normal, the first timer circuit 51 outputs a signal to turn on the analog gate circuit 53.

[0082] Therefore, even in the case that the pulses of the monitor signal SGw / d are normally output, when the first timer circuit 51 detects the abnormality of the control signal SGout, the analog gate circuit 53 is turned off and the pulses of the monitor signal SGw / d do not act on the input of the second timer circuit 52. Therefore, the second timer circuit 52 can observe the abnormality of the monitor signal SGw / d and the abnormality of the control signal SGout at the same time by using one input.

[0083] In other words, if the first timer circuit 51 detects an abnormality in the control signal SGout or the specified time has elapsed while the pulses of the monitor signal SGw / d are stopped, the second timer circuit 52 detects an abnormality, and the output of the second timer circuit 52 becomes "Hi." After that, the latch circuit 54 closes this "Hi" and outputs the reset control signal SGbk.

[0084] Furthermore, if the pulse of the monitor signal SGw / d is applied to the output (the emitter terminal) of the analog gate circuit 53 after the output of the second timer circuit 52 changes to "Hi," the cancel circuit 55 outputs "Hi" as the reset signal SGrst. The latch circuit 54 is set by the "Hi" of the reset signal SGrst, and the reset control signal SGbk is released. <Beschreibung einer weiteren spezifischen Konfiguration>

[0085] In the case of the reset signal generating circuit 20B shown in Fig. 7, the circuit configuration thereof can be simplified and the number of components can be reduced compared to the reset signal generating circuit 20 shown in Fig. 1. In other words, the diodes D1 and D2 shown in Fig. 1, are not necessary and the internal configuration of the cancellation circuit 55 can be simplified. A more specific configuration example of the reset signal generating circuit 20B shown in Fig. 7, is in Fig. 8 shown.

[0086] In the reset signal generating circuit 20C shown in Fig. 8, the first timer circuit 51 is formed from a timer constant circuit formed from a capacitor C2 and a resistor R2 and a transistor (FET) 51a. Additionally, the timer circuit 52 is formed from a capacitor C1, a resistor R1, and a counter 52a. Furthermore, a timer generator 56 and an AND gate 57 are provided so that the counter 52a can perform a time count. The timer generator 56 and the AND gate 57 perform functions comparable to those of the timer generator 44 and the AND gate 45 shown in Fig. 6, out.

[0087] In Fig. 8, the latch circuit 54 is formed by a D-type flip-flop (DFF). In addition, the cancellation circuit 55, shown in Fig. 8, also formed of a D-type flip-flop (DFF). Since the cancellation circuit 55 only observes the signal output from the analog gate circuit 53, its configuration is simplified and the number of components is lower compared to the configuration of the cancellation circuit 47 shown in Fig. 6, reduced.

[0088] Instead of the edge detector 43 shown in Fig. 6, the circuit consisting of the capacitor C1 and the resistor R1 in the circuit shown in Fig. 8. Capacitor C1 is provided to switch off the DC components of the input signal. Furthermore, resistor R1 serves to quickly bring the potential of the input (cancellation control terminal) of counter 52a close to the desired potential when no pulses occur in the monitor signal SGw / d.

[0089] For example, if the microcomputer 10 malfunctions and the pulses of the monitor signal SGw / d are stopped, the state at the cancel control terminal of the counter 52a becomes "Low," and the counter 52a starts counting the time pulses. If the state at the cancel control terminal does not change to "High" before the specified time elapses, the counter 52a detects an abnormality, and the latch circuit 54 outputs the reset control signal SGbk. <Möglichkeit von Modifikationen anders als die oben beschriebenen>

[0090] In the reset signal generating circuit 20 shown in Fig. 1, the time measurement operations of the timer circuits 25 and 26 are inhibited when the status signal SGin output from the instruction switch SW is inactive (when the microcomputer 10 is not controlling the load 31). Various signals can be adopted as the status signal SGin. When a normal operation cannot be performed, for example, when the microcomputer 10 is performing an initialization process, the operation of the reset signal generation circuit 20 can be inhibited by setting the status signal SGin to inactive.

[0091] The switching device 32 for controlling the energization of the load 31 is not limited to power FETs, but various switching devices such as an IPD (intelligent power device) can be used.

[0092] The relationship between the high / low level of each signal and the on / off operation of each circuit in the electronic control unit 100 and the reset signal generating circuit 20 can be changed according to the unit's specifications. Furthermore, the time limit (Tth1) in the timer circuit 25 and the time limit (Tth2) in the timer circuit 26 can also be appropriately determined according to the unit's specifications.

[0093] Instead of the edge detector 43 shown in Fig. 6, the circuit consisting of the capacitor C1 and the resistor R1, shown in Fig. 8. In reverse, the circuit consisting of the capacitor C1 and the resistor R1, shown in Fig. 8, by the edge detector 43, shown in Fig. 6, be replaced.

[0094] Although the analog gate circuit 53 shown in Fig. 7, is formed of a transistor, in the case that the first timing circuit 51 outputs a digital signal, a logic circuit having an equivalent function may be used instead of the analog gate circuit 53.

[0095] Although the reset signal generating circuit 20 shown in Fig. 1, two signals are observed, that is, the monitor signal SGw / d and the control signal SGout, output from the microcomputer 10, and the reset control signal SGbk is generated, the reset signal generation circuit can be modified to observe other signals. For example, instead of observing the monitor signal SGw / d, the reset signal generation circuit can observe a constant-period signal similar to this. Furthermore, although the case where either a PWM signal or a simple binary signal is used as the signal output from the output terminal 11, assuming the configuration shown in Fig.1, in the case of a unit in which a PWM signal always occurs, the control signal SGout can be observed using the timing circuit 26. Furthermore, in the case of controlling a plurality of loads, each of which uses a plurality of control signals SGout, the number of timing circuits 25 can be increased.

[0096] The characteristics of the above-mentioned embodiment of the load control reset signal generating circuit according to the present invention are summarized and listed in the following items [1] to [8]. [1] A load control reset signal generating circuit (reset signal generating circuit 20) for supplying a reset control signal (SGbk) to a switch (switching device 32) of a load (31) connected to an output of a control processor (microcomputer 10) operating according to a program in case of abnormality occurring in the control processor, the reset signal generating circuit includes: a first input terminal (monitor input terminal 21) receiving a constant period signal (monitor signal SGw / d) periodically output from the control processor when the control processor is normal; a constant-period signal observation section (timer circuit 26) that observes a state of the constant-period signal to identify whether a length of time during which a high or low level state of the constant-period signal lasts longer than a predetermined time, and that outputs the signal corresponding to a result of the identification; and a reset signal output section (latch circuit 27) that outputs the reset control signal when the output of the constant period signal observation section meets a predetermined condition. [2] The load control reset signal generation circuit configured as described in the above item [1], which further includes: a second input terminal (control signal input terminal 23) receiving a control signal (SGout) output from the control processor when the control processor is normal; a control signal observation section (timer circuit 25) that observes a state of the control signal to identify whether a length of time during which the abnormal level state of the control signal lasts longer than a predetermined time, and that outputs the signal according to a result of the identification, wherein the reset control signal output section outputs a reset control signal when an output of the control signal observation section corresponds to a predetermined condition. [3] The load control reset signal generating circuit is configured as described in the above-mentioned item [2], wherein the reset control signal output section generates a reset control signal according to a logical OR of a state in which the output of the constant period signal observing section satisfies the predetermined condition and a state in which the output of the control signal observing section satisfies the predetermined condition. [4] The load control reset signal generating circuit (reset signal generating circuit 20A) configured as described in the above item [1], which further includes: a timing clock generating section (timing generator 44) that outputs timing clock pulses when a status signal (SGin) applied to an input in the control processor is active; a first counter (counter 41) that counts the timing pulses output from the timing clock generating section when a level of the control signal output from the control processor is a predetermined level; a second counter (counter 42) which counts the timing pulses output from the timing clock generating section during the time in which the high or low level state of the constant period signal periodically output from the control processor progresses; and a cancellation circuit (cancellation circuit 47) that returns the state of the reset signal output section to an initial state of the reset control signal output section after detecting that both the control signal and the constant period signal are normal. [5] The load control reset signal generating circuit (reset signal generating circuit 20B) configured as described in the above-mentioned item [2], which further includes: a signal gate circuit (analog gate circuit 53) connected between the first input terminal and the input of the constant-period signal observation section, wherein the output of the control signal observation section is connected to a control input of the signal gate circuit. [6] The load control reset signal generation circuit configured as described in the above item [5], which further includes: a cancellation circuit (55) which observes an output signal of the signal gate circuit and which returns the state of the reset signal output section to an initial state of the reset signal output section when it is detected that the output signal of the signal gate circuit is normal. [7] The load control reset signal generating circuit (reset signal generating circuit 20C) configured as described in the above-mentioned item [6], which further includes: a timing clock generation section (timing clock generator 56) that outputs timing clock pulses when the status signal applied to the input of the control processor is active; and a counter (52a) which counts the timing clock pulses output from the timing clock generating section during the time in which a high or low level state of the constant period signal reaching the output of the timing clock generating section progresses. [8] The load control reset signal generation circuit is configured as described in the above-mentioned item [7], wherein a DC cut-off capacitor (capacitor C1) is connected between the output of the signal gate circuit and the input of the counter; and wherein the input of the counter is connected to a predetermined potential line via a potential control resistor (resistor R1) provided therebetween.

Claims

[1] A load control reset signal generating circuit (20) for supplying a reset control signal (SGbk) to a switch (32) of a load (31) in the event that abnormality occurs in a control processor (10), the switch (32) of the load (31) being connected to an output (11) of the control processor (10) operating according to a program, the load control reset signal generating circuit (20) comprising: a first input terminal (21) receiving a constant period signal (SGw / d) periodically output from the control processor (10) when the control processor (10) is normal; a constant-period signal observation section (26, 52) which observes a state of the constant-period signal (SGw / d) to identify whether a length of time during which a high or low level state of the constant-period signal (SGw / d) lasts longer than a predetermined time (Tth2), and which outputs a signal (SGT2) corresponding to a result of the identification; a reset control signal output section (27) which outputs the reset control signal (SGbk) to control on and off switching of the switch (32) of the load (31) when the output of the constant period signal observation section (26, 52) corresponds to a predetermined condition; a second input terminal (23) receiving a control signal (SGout) output from the control processor (10) when the control processor (10) is normal; a control signal observation section (25, 51) which observes a state of the control signal (SGout) to identify whether a length of time during which the abnormal level state of the control signal (SGout) lasts longer than a predetermined time (Tth1), and which outputs a signal (SGT1) corresponding to a result of the identification, wherein the reset control signal output section (27) outputs a reset control signal (SGbk) when an output of the control signal observation section (25,51) corresponds to a predetermined condition. [2] The load control reset signal generating circuit (20) according to claim 1, wherein the reset control signal output section (27) generates a reset control signal (SGbk) according to a logical OR of a state in which the output of the constant period signal observing section (26) corresponds to the predetermined condition and a state in which the output of the control signal observing section (25) corresponds to the predetermined condition. [3] The load control reset signal generating circuit (20) according to claim 1, further comprising: a timing clock generating section that outputs timing clock pulses when a status signal (SGin) applied to an input in the control processor (10) is active; a first counter that counts the timing clock pulses output from the timing clock generating section when a level of the control signal (SGout) output from the control processor (10) is a predetermined level; a second counter that counts the timing pulses output from the timing clock generating section during the time in which the high or low level state of the constant period signal (SGw / d) periodically output from the control processor (10) progresses; and a cancellation circuit that returns the state of the reset control signal output section to an initial state of the reset control signal output section after detecting that both the control signal (SGout) and the constant period signal (SGw / d) are normal. [4] The load control reset signal generating circuit (20) according to claim 1, further comprising: a signal gate circuit (53) connected between the first input terminal (21) and the input of the constant period signal observation section (52), wherein the output of the control signal observation section (51) is connected to a control input of the signal gate circuit (53). [5] The load control reset signal generating circuit (20) according to claim 4, further comprising: a cancellation circuit (55) which observes an output signal of the signal gate circuit (53) and which returns the state of the reset control signal output section to an initial state of the reset control signal output section when it is detected that the output signal of the signal gate circuit (53) is normal. [6] The load control reset signal generating circuit (20) according to claim 5, further comprising: a timing clock generating section (56) which outputs timing clock pulses when the status signal (SGin) applied to the input of the control processor (10) is active; and a counter (52a) which counts the timing clock pulses output from the timing clock generating section (56) during the time in which a high or low level state of the constant period signal (SGw / d) reaching the output of the timing clock generating section (56) progresses. [7] The load control reset signal generating circuit (20) according to claim 6, wherein a DC cutoff capacitor (C1) is connected between the output of the signal gate circuit (53) and the input of the counter (52a); and wherein the input of the counter (52a) is connected to a predetermined potential line via a potential control resistor (R1) provided therebetween.

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