Semiconductor device

Abstract

Semiconductor device comprising: a first ceramic base plate (14); a second ceramic base plate (18); an inter-ceramic metal (16) comprising an intermediate part (16a) arranged between an upper surface of the first ceramic base plate (14) and a lower surface of the second ceramic base plate (18), a first projecting part (16b) formed on an upper surface of the second ceramic base plate (18), a second projecting part (16c) formed on an upper surface of the second ceramic base plate (18), a first connecting part (16d) adjacent to an outer edge of the second ceramic base plate (18) and connecting the intermediate part (16a) and the first projecting part (16b), and a second connecting part (16e) adjacent to an outer edge of the second ceramic base plate (18) and connecting the intermediate part (16a) and the second projecting part (16c);a circuit pattern (20a, 20c) formed from a metal on the second ceramic base plate (18), wherein the circuit pattern (20a, 20c) is separated from the inter-ceramic metal (16); and a semiconductor element (22, 24, 26, 28) provided on the circuit pattern (20a, 20c), wherein a current flowing through the semiconductor element (22, 24, 26, 28) flows through the inter-ceramic metal (16).

Description

Field of invention

[0001] The present invention relates to a semiconductor device which is used, for example, for motor control or electrical railway equipment or motor vehicle equipment. State of the art

[0002] Japanese patent no. 2006-66595 discloses a multi-layer base plate in which a plurality of metal plates are joined with ceramic base plates arranged between them. In this multi-layer base plate, a through-hole in each ceramic base plate is filled with a metal to connect the metal plates on the upper and lower surfaces of the ceramic base plate.

[0003] Filling the through-hole in each ceramic baseplate allows the metal plate (hereafter referred to as the inter-ceramic metal) positioned between each adjacent pair of ceramic baseplates to be used as an electrode. However, a problem arises in that stress (such as mechanical strain) caused by thermal expansion or similar forces in the metal plates becomes concentrated at the periphery of the through-hole in each ceramic baseplate, thereby causing a crack in the ceramic baseplate. Fracture of the ceramic baseplate can also occur as a result of the crack propagating. Summary of the invention

[0004] In view of the problem described above, an object of the present invention is to provide a semiconductor device that is able to use an inter-ceramic metal as an electrode while preventing the occurrence of cracks in the ceramic base plates.

[0005] The features and advantages of the present invention can be summarized as follows.

[0006] According to one aspect of the present invention, a semiconductor device comprises a first ceramic base plate, a second ceramic base plate, an inter-ceramic metal comprising an intermediate section arranged between an upper surface of the first ceramic base plate and a lower surface of the second ceramic base plate, a first projecting section formed on an upper surface of the second ceramic base plate, a second projecting section formed on an upper surface of the second ceramic base plate, a first connecting section adjacent to an outer edge of the second ceramic base plate and connecting the intermediate section and the first projecting section, and a second connecting section adjacent to an outer edge of the second ceramic base plate and connecting the intermediate section and the second projecting section, and a circuit pattern formed from a metal on the second ceramic base plate.and a semiconductor element provided on the circuit pattern, wherein a current flowing through the semiconductor element flows through the inter-ceramic metal.

[0007] According to another aspect of the present invention, a semiconductor device comprises a first ceramic base plate, a second ceramic base plate, an inter-ceramic metal having an intermediate section arranged between an upper surface of the first ceramic base plate and a lower surface of the second ceramic base plate, a first outer edge section extending outwards in a top view beyond an outer edge of the second ceramic base plate, the first outer edge section being connected to the intermediate section, and a second outer edge section extending outwards in a top view beyond an outer edge of the second ceramic base plate, the second outer edge section being connected to the intermediate section, a circuit pattern formed from a metal on the second ceramic base plate, a semiconductor element provided on the circuit pattern, a first conductor,which electrically connects the semiconductor element and the first outer edge part, and a second conductor that is connected to the second outer edge part.

[0008] According to another aspect of the present invention, a semiconductor device comprises a first ceramic base plate, a second ceramic base plate, an inter-ceramic metal comprising an intermediate section arranged between an upper surface of the first ceramic base plate and a lower surface of the second ceramic base plate, a projecting section formed on an upper surface of the second ceramic base plate, a connecting section adjacent to an outer edge of the second ceramic base plate and connecting the intermediate section and the projecting section, an outer edge section extending outwards beyond an outer edge of the second ceramic base plate in a top view, the outer edge section being connected to the intermediate section, a circuit pattern formed from a metal on the second ceramic base plate, a semiconductor element provided on the circuit pattern, a first conductor,which electrically connects the semiconductor element and the projecting part or the outer edge part, and a second conductor which is connected to the other by the projecting part and the outer edge part.

[0009] Other and further tasks, features and advantages of the invention will become more fully apparent from the following description. Brief description of the drawings

[0010] Fig. 1 is a sectional view of a semiconductor device according to a first embodiment;

[0011] Fig. 2 is a top view of the semiconductor device;

[0012] Fig. 3 is a circuit diagram of the semiconductor device;

[0013] Fig. Figure 4 is a sectional view of a semiconductor device according to a modified example;

[0014] Fig. 5 is a sectional view of the semiconductor device according to the second embodiment;

[0015] Fig. Figure 6 is a sectional view of a semiconductor device according to a modified example;

[0016] Fig. 7 is a sectional view of the semiconductor device according to the third embodiment;

[0017] Fig. 8 is a sectional view of the semiconductor device according to the fourth embodiment;

[0018] Fig. 9 is a sectional view of the semiconductor device according to the fifth embodiment;

[0019] Fig. 10 is a top view of the semiconductor device according to the fifth embodiment;

[0020] Fig. 11 is a circuit diagram of the semiconductor device according to the fifth embodiment;

[0021] Fig. Figure 12 is a sectional view of the semiconductor device according to the sixth embodiment; and

[0022] Fig. Figure 13 is a sectional view of the semiconductor device according to the seventh embodiment. Detailed description of preferred embodiments

[0023] Semiconductor devices according to embodiments of the present invention are described with reference to the accompanying drawings. Components that are identical or correspond to each other are identified by the same reference numerals, and repeated descriptions thereof are avoided in some cases. First embodiment

[0024] Fig. 1 is a sectional view of a semiconductor device 10 according to a first embodiment of the present invention. The semiconductor device 10 is equipped with a base plate 12 equipped with a metal such as Al or Cu to minimize the effect of heat dissipation from the semiconductor device 10 to improve. A first ceramic base plate 14 is above the base plate 12planned. A second ceramic base plate. 18 is above the first ceramic base plate 14 planned. Both the first ceramic base plate 14 as well as the second ceramic base plate 18 It is made, for example, from AlN, SiN or Al2O3.

[0025] An inter-ceramic metal 16 is between the first ceramic base plate 14 and the second ceramic base plate 18 trained. The Inter-Ceramic Metal 16 It is made from a metal such as aluminum or copper. The inter-ceramic metal 16 is applied to an upper surface side of the first ceramic base plate 14 trained and the base plate 12 is applied to a lower surface side of the first ceramic base plate 14 formed, whereby a balance is achieved between thermal expansions in the upper and lower surfaces of the first ceramic base plate 14 is found.

[0026] The Inter-Ceramic Metal 16 has an intermediate part 16a , a first outstanding part 16b , a second outstanding part 16c , a first connecting part 16d and a second connecting part 16e up. The intermediate part 16a is between the upper surface of the first ceramic base plate 14 and a lower surface of the second ceramic base plate 18 arranged. The first outstanding part 16b and the second outstanding part 16c are on an upper surface of the second ceramic base plate 18 trained.

[0027] The first connecting part 16d borders an outer edge of the second ceramic base plate 18 and is between the intermediate part 16a and the first outstanding part 16b connected. The second connecting part 16e borders another outer edge of the second ceramic base plate 18and is between the intermediate part 16a and the second outstanding part 16c tied together.

[0028] On the second ceramic base plate 18 are circuit patterns 20a , 20b , 20c and 20d Semiconductor elements are formed from a metal such as aluminum or copper. 22 and 24 are on the circuit diagram 20a planned. Semiconductor elements 26 and 28 are on the circuit diagram 20c provided for each of the semiconductor elements 22 and 26 is an insulated gate bipolar transistor (IGBT). Each of the semiconductor elements 24 and 28 is a diode that has an anode on its upper surface and a cathode on its lower surface.

[0029] The base plate 12 has a flat area 12a, which is attached to the lower surface of the first ceramic base plate 14 adjacent, and a thick film area 12b , which is located in the flat area 12a adjacent to, on. The thick film area 12b is an area located on an outer edge and the upper surface of the first ceramic base plate 14 adjacent to, and which borders the flat area 12a in a top view. An AC connection 42 is in the thick film area 12b with an insulating film placed in between 40 Provided. An emitter connection. 52 (N-terminal) is also connected with an insulating foil in between. 50 in the thick film area 12b A collector connection is planned. 56 (P-terminal) is on the emitter terminal 52 with an insulating film placed in between 54 provided. The AC connection 42 , the emitter connection 52and the collector connection 56 are connections that result from the semiconductor device 10 extend outwards.

[0030] A line W1 connects the gate of the semiconductor element. 22 and the circuit pattern 20b A line W2 connects the emitter of the semiconductor element. 22 and the anode of the semiconductor element 24 A line W3 connects the circuit pattern. 20a and the collector connection 56 A line W4 connects the first towering part. 16b and the emitter connection 52 .

[0031] A line W5 connects the anode of the semiconductor element. 24 and the circuit pattern 20c A line W6 connects the circuit pattern. 20d and the gate of the semiconductor element 26 A line W7 connects the emitter of the semiconductor element. 26 and the anode of the semiconductor element 28A conductor W8 connects the anode of the semiconductor element. 28 and the second outstanding part 16e A line W9 connects the circuit pattern. 20c and the AC connection 42 .

[0032] The connection between the semiconductor element 28 and the second outstanding part 16c through the W8 line and the connection between the first towering part 16b and the emitter connection 52 The conductor W4 allows a current flowing through the semiconductor element to pass through the inter-ceramic metal. 16 to flow. More precisely, the emitter current of the semiconductor element flows. 26 through the inter-ceramic metal 16 .

[0033] Fig. 2 is a top view of the semiconductor device 10 The emitter connection 52 is adjacent to the collector connection 56These connections are provided for, and they are arranged parallel to each other in such a way as to reduce the wiring inductance. The collector connection 56 and the emitter connection 52 extend in the negative x-direction from the left outer edge of the base plate 12 The AC connection 42 extends in the positive x-direction from the right outer edge of the base plate 12 .

[0034] A gate connector 60 to provide a gate driver signal to the gate of the semiconductor element 22 is on the base plate 12 attached. 62 and 64 are also on the base plate 12 attached. A gate connector 66 to provide a gate driver signal to the gate of the semiconductor element 26 is on the base plate 12 attached. 68 and 70are also on the base plate 12 attached.

[0035] Through holes 72 are located in four corner areas of the base plate 12 provided for. If the semiconductor device 10 The semiconductor device is used 10 with screws that pass through the through holes 72 The base plate is mounted on a heat sink or similar device. Preferably, thermal paste is applied between the lower surface of the base plate and the heat sink at this time. 12 and the heat sink or similar. Fig. Figure 1 is a sectional view along the line indicated by the arrows in Fig. 2 is displayed.

[0036] Fig. 3 is a circuit diagram of the semiconductor device 10 The semiconductor device 10 forms a branch of a three-phase AC inverter. Parts that are in Fig. The parts labelled C1, G1, E1, C2, G2 and E2 correspond to parts that are in Fig. 2 are designated by C1, G1, E1, C2, G2 and E2.

[0037] A method for manufacturing the semiconductor device 10 The multilayer base plate of the semiconductor device is described below. 10 It is formed through a bonding process with molten metal, which is a process for directly joining a metal to a ceramic base plate. In this bonding process, ceramic base plates are placed in a mold, and molten metal is poured into the mold. More precisely, molten metal is poured into a mold into which the first ceramic base plate is placed. 14 and the second ceramic base plate 18 were set, thereby the base plate 12 , the inter-ceramic metal 16 and the circuit patterns 20a , 20b , 20c and20d They are formed at the same time. The semiconductor elements are then attached to the circuit patterns and wire bonding is carried out, thus completing the semiconductor device. 10 is completed. This process allows the first, prominent part to be completed. 16b , the second outstanding part 16c , the first connecting part 16d and the second connecting part 16e can be formed simply by adjusting the shape of the mold.

[0038] The multilayer base plate of the semiconductor device 10It can be manufactured using an active metal bonding process, which involves joining a metal and a ceramic base plate with an indirect material such as solder. If the multilayer base plate is formed using either the molten metal bonding process or the active metal bonding process, the heat dissipation effect from the semiconductor device can be improved because no solder is used to bond the ceramic base plates to the metal. Furthermore, the manufacturing process can be simplified compared to joining components with solder.

[0039] To reduce wiring inductance, it is preferred to arrange the collector terminal (P terminal) and the emitter terminal (N terminal) adjacent and parallel to each other. However, this arrangement, which causes current to flow only on the second ceramic base plate, presents a problem: the terminal shapes become complex, and the semiconductor device becomes larger. Specifically, a large terminal is needed to connect the emitter of the semiconductor element. 26 and the anode of the semiconductor element 28 with the emitter connection 52 to provide and the size of the emitter connector 52 to increase.

[0040] However, in the semiconductor device according to the first embodiment of the present invention, the emitter of the semiconductor element 26 and the anode of the semiconductor element 28 with the emitter connection 52through the inter-ceramic metal 16 connected. Therefore, a remarkably simple connection form can be implemented, as in Fig. 2 shown. By using the inter-ceramic metal 16 As an electrode, a new current path can be provided below the second ceramic base plate.

[0041] Since the inter-ceramic metal 16 has parts (a first connecting part 16d and a second connecting part 16e ), which are attached to the outer edge of the second ceramic base plate 18 Adjacent to, the inter-ceramic metal can further 16 can be used as an electrode without drilling a hole in the second ceramic base plate. 18 to provide for. Thus, the use of the inter-ceramic metal will be implemented. 16 as an electrode, while preventing the occurrence of a crack from a bore in the ceramic base plate.

[0042] The semiconductor device according to the first embodiment of the present invention can be modified in various ways within a range of validity without losing its features. For example, while the emitter current of the IGBT (semiconductor element) 26 ) in the first embodiment for flowing through the inter-ceramic metal 16 Alternatively, the collector current can be caused to flow through the inter-ceramic metal, or an alternating current (output current) can be caused to flow through the inter-ceramic metal. Using the inter-ceramic metal as a current path simplifies the electrical connection of the semiconductor device. Likewise, multiple inter-ceramic metals can be provided beneath a ceramic base plate to offer multiple current paths. The semiconductor elements 22 , 24 , 26 and 28are not limited to IGBTs or diodes. For example, a MOSFET can be used as a semiconductor device. The necessary electrical connections can be made using electrically conductive parts such as electrodes instead of wires.

[0043] Fig. Figure 4 is a sectional view of a semiconductor device according to a modified example. Second ceramic base plates 18a and 18b are based on the Inter-Ceramic-Metal 16 planned. That is, a plurality of second ceramic base plates is planned.

[0044] Increasing the size of the ceramic base plate can make it more prone to breakage due to increased thermal stress from the adjacent metal. However, the size of the second ceramic base plate can be reduced by dividing it into multiple pieces, thus preventing breakage.

[0045] These modifications can be applied to the semiconductor devices according to the embodiments described below, as desired. Each of the semiconductor devices according to the embodiments described below shares a number of similarities with the semiconductor device according to the first embodiment and is therefore described with respect to its differences from the first embodiment. Second embodiment

[0046] Fig. Figure 5 is a sectional view of the semiconductor device according to the second embodiment. This semiconductor device has two second ceramic base plates. 18a and 18b and two inter-ceramic metals 100 and 102 on. The inter-ceramic metal 100 has an intermediate part 100a , a first outstanding part 100b , a second outstanding part 100c , a first connecting part 100d and a second connecting part 100e on. The inter-ceramic metal 102 has an intermediate part 102a , a first outstanding part 102b a second outstanding part 102c , a first connecting part 102d and a second connecting part 102e on.

[0047] A semiconductor element 101 is based on a circuit diagram 20e on the second ceramic base plate 18a attached. The semiconductor element 101is an element necessary to form a converter circuit. A semiconductor element. 103 is on the circuit diagram 20f on the second ceramic base plate 18b attached. The semiconductor element 103 This element is necessary to form an inverter circuit. That is, the semiconductor elements in the second embodiment form a converter circuit and an inverter circuit. Lines and connections are omitted from the illustration.

[0048] In the semiconductor device according to the second embodiment of the present invention, the inter-ceramic metal 100 can be used as an electrode for a converter circuit and the inter-ceramic metal 102 It can be used as an electrode for an inverter circuit. Thus, while a converter circuit and an inverter circuit are mixed, current paths for these circuits can be re-established.

[0049] In the second embodiment of the present invention, a converter circuit and an inverter circuit are provided on separate second ceramic base plates. However, two or more circuits, differing in functionality and not limited to a converter circuit and an inverter circuit, can be provided. The number of inter-ceramic metals is not limited to two. A plurality of current paths can be provided by forming a plurality of inter-ceramic metals.

[0050] Fig. Figure 6 is a sectional view of a semiconductor device according to a modified example. The semiconductor device has two first ceramic base plates. 14a and 14b up. Each of the first ceramic base plates 14a and 14bIt can therefore be reduced in size and cannot be made easily breakable. The effect described above can be achieved by using multiple initial ceramic base plates. Therefore, three or more initial ceramic base plates can be used. Third embodiment

[0051] Fig. Figure 7 is a sectional view of the semiconductor device according to the third embodiment. Heat sink fins 12c are on the base plate 12 formed from a metal on the lower surface of the first ceramic base plate 14 is manufactured. The heat sink fins 12c can be easily achieved by modifying the shape of the mold to form the base plate. 12 , of the inter-ceramic metal 16 and the circuit pattern 20a , 20b , 20c and 20d to be trained. The provision of the heat sink fins. 12con the base plate 12 eliminates the need to mount the semiconductor device on a heat sink or similar. Fourth embodiment

[0052] Fig. Figure 8 is a sectional view of the semiconductor device according to the fourth embodiment. A metal layer 150 is on the lower surface of the first ceramic base plate 14 trained. A third ceramic base plate 152 is on a lower surface of the metal layer 150 trained. The base plate 12 is made of a metal on a lower surface of the third ceramic base plate 152 trained.

[0053] The semiconductor device according to the fourth embodiment has three ceramic base plates and can therefore exhibit higher dielectric strength than those having only two ceramic base plates. The provision of the metal layer 150As a potential-free electrode, it enables the prevention of electrical discharge between the inter-ceramic-metal 16 and the base plate 12 can occur. Fifth embodiment

[0054] Fig. Figure 9 is a sectional view of the semiconductor device according to the fifth embodiment. This semiconductor device forms a branch of an inverter circuit (a switching element and a diode connected in inverse parallel to the switching element).

[0055] Three circuit patterns 20g , 20h and 20i are on the upper surface of the second ceramic base plate 18 trained. Semiconductor elements 22a and 24a are on the circuit diagram 20g attached. 22b and 24b are on the circuit diagram 20i attached.

[0056] A W10 line connects the first outstanding part16b and the anode of the semiconductor element 24a A line W11 connects the anode of the semiconductor element. 24a and the emitter of the semiconductor element 22a A line W12 connects the gate of the semiconductor element. 22a and the circuit pattern 20h A line W13 connects the circuit pattern. 20h and the gate of the semiconductor element 22b A line W14 connects the emitter of the semiconductor element. 22b and the anode of the semiconductor element 24b A conductor W15 connects the anode of the semiconductor element. 24b and the second outstanding part 16c .

[0057] Fig. Figure 10 is a top view of the semiconductor device according to the fifth embodiment. An emitter terminal 160 is with the first outstanding part 16b connected and extends in the positive z-direction from the upper outer edge of the base plate 12The circuit pattern 20g and the circuit pattern 20i are connected to form a circuit pattern. A collector connection 162 is with the circuit patterns 20g and 20i connected and extends in the positive z-direction from the upper outer edge of the base plate 12 The emitter connection 160 is adjacent to the collector connection 162 provided and these connections are arranged parallel to each other.

[0058] A gate connector 164 is with the circuit pattern 20h connected. 166 and 168 are each with the first outstanding part 16b and the anode of the semiconductor element 24a tied together.

[0059] Fig. 11 is a circuit diagram of the semiconductor device according to the fifth embodiment. Parts that are in Fig. Items 11, labeled C1, G1 and E1, correspond to parts that are in Fig. 10 are labelled C1, G1 and E1. In Fig. 11 are the three semiconductor elements 22a and the three semiconductor elements 22b in Fig. 10 represented by a switching element (IGBT), and the three semiconductor elements 24a and the three semiconductor elements 24b in Fig. 10 are represented by a semiconductor element (diode).

[0060] In the semiconductor device according to the fifth embodiment, the emitter current of the semiconductor element flows. 22b of the second outstanding part 16c about the intermediate part 16a to the first outstanding part 16b , as in Fig. Figure 9 shows the connection of the emitter of the semiconductor element. 22b to the first outstanding part 16b This allows the entire emitter current to pass through the first towering part. 16bflows. The shape of the emitter connection 160 This can therefore be simplified. Completing the wiring only on the second ceramic base plate, without using the inter-ceramic metal as an electrode, requires, if possible, connecting the emitter terminal to the emitter terminal of the semiconductor element. 22a and with the emitter of the semiconductor element 22b to connect them separately, thus forming the emitter connection into a complicated shape.

[0061] The semiconductor device according to the fifth embodiment, which is arranged to form a branch, can alternatively be arranged to form a different circuit. The degree of freedom of wiring can be increased if the inter-ceramic metal is used as an electrode, causing a current to flow beneath the second ceramic base plate, thereby enabling optimization of the terminal shape and layout. Sixth embodiment

[0062] Fig. Figure 12 is a sectional view of the semiconductor device according to the sixth embodiment. The inter-ceramic metal 16 has a first outer edge part 16f and a second outer edge piece 16g up. The first outer edge section 16f and the second outer edge part 16g in a top view extend outwards over the outer edge of the second ceramic base plate 18 outwards. The first outer edge section 16f and the second outer edge part 16g are with the intermediate part 16a connected. The second ceramic base plate 18 is in a top view between the first outer edge part 16f and the second outer edge part 16g arranged.

[0063] A first conductor W81 connects the anode of the semiconductor element. 28 and the first outer edge part 16felectrically. One end of a second conductor W41 is connected to the second outer edge section. 16g connected, while the other end of the second conductor W41 is connected to the emitter terminal. 52 is connected. Each of the first conductor W81 and the second conductor W41 is a conductor.

[0064] Connecting the first conductor W81 and the second conductor W41 to the inter-ceramic metal 16 This makes it possible to use inter-ceramic metal 16 to be used as an electrode. Compared to the semiconductor device in the first embodiment, the protruding parts and the connecting parts of the inter-ceramic metal can be removed, and the structure can therefore be simplified. On the other hand, it is necessary that the first outer edge part 16f and the second outer edge part 16gSufficient space must be available for bonding conductors. Therefore, the semiconductor device according to the sixth embodiment may be somewhat larger than the semiconductor device according to the first embodiment. The first conductor W81 and the second conductor W41 can alternatively be electrodes or similar components other than conductors. Seventh embodiment

[0065] Fig. Figure 13 is a sectional view of the semiconductor device according to the seventh embodiment. The inter-ceramic metal 16 the first outer edge part 16 , the first outstanding part 16b and the first connecting part 16d up. The first conductor W81 connects the first outer edge section. 16f and the semiconductor element 28 A second conductor, W42, connects the first, towering section. 16b and the emitter connection 52 The emitter current of the semiconductor element 26flows from the first outer edge part 16f about the intermediate part 16a and the first connecting part 16d to the first outstanding part 16b .

[0066] The seventh embodiment of the present invention presupposes a situation in which a bonding location for conductors can be easily provided in a right-hand region, while a similar location in a left-hand region cannot be easily provided. In such a case, the first outer edge portion is formed in a right-hand region and the first projecting portion is formed in a left-hand region, thereby enabling reliable conductor bonding.

[0067] The inter-ceramic metal can be modified in various ways, as long as it includes the projecting part on the upper surface of the second ceramic base plate, the connecting part adjacent to the outer edge of the second ceramic base plate and joining the intermediate part and the projecting part, and the outer edge part extending outwards beyond the outer edge of the second ceramic base plate in a top view and connected to the intermediate part. For example, the inter-ceramic metal can 16 in Fig.13 Alternatively, the semiconductor element may have a projecting part formed on the right side and an outer edge part formed on the left side. The first conductor W81 electrically connects the semiconductor element and the projecting part or the outer edge part. The second conductor W42 is connected to the other by the projecting part and the outer edge part. The first conductor W81 and the second conductor W42 may alternatively be electrodes or similar components other than conductors. A combination of some of the embodiments described above may be made and used as desired.

[0068] According to the present invention, no through-holes are formed in the ceramic base plates and an electrical connection is made at an outer edge of the inter-ceramic metal, making it possible to use the inter-ceramic metal as an electrode while preventing the occurrence of cracks in the ceramic base plates.

[0069] In light of the preceding teachings, it is evident that many modifications and variations of the present invention are possible. It should therefore be understood that, within the scope of the appended claims, the invention can be practiced differently than expressly described.

[0070] In summary, a semiconductor device comprises a first ceramic base plate, a second ceramic base plate, an inter-ceramic metal having an intermediate part arranged between an upper surface of the first ceramic base plate and a lower surface of the second ceramic base plate, a first projecting part formed on an upper surface of the second ceramic base plate, a second projecting part formed on an upper surface of the second ceramic base plate, a first connecting part adjacent to an outer edge of the second ceramic base plate and connecting the intermediate part and the first projecting part, and a second connecting part adjacent to an outer edge of the second ceramic base plate and connecting the connecting part and the second projecting part, a circuit pattern formed on the second ceramic base plate, and a semiconductor element.which is provided for in the circuit diagram. Reference symbol list 10 Semiconductor device 12 Base plate 12a flat area of ​​the base plate 12b Thick film area of ​​the base plate 14, 14a, 14b first ceramic base plate 16 Inter-Ceramic-Metal 16a Intermediate part 16b first outstanding part 16c second outstanding part 16d first connecting part 16e second connecting part 16f first outer edge part 16g second outer edge part 18, 18a, 18b second ceramic base plate 20a–20i Circuit diagram 22, 22a, 22b Semiconductor element 24, 24a, 24b Semiconductor element 26, 28 Semiconductor element 40 insulating foil 42 AC connection 50 insulating foil 52 Emitter connection 54 insulating foil 56 Collector connection 60 Gate connector 62, 64 measuring connections 66 Gate connector 68, 70 measuring connections 72 through holes 100a Intermediate part 100b first outstanding part 100c second outstanding part 100d first connecting part 100 second connecting part 101 Semiconductor element 102a Intermediate part 102b first outstanding part 102c second outstanding part 102d first connecting part 102e second connecting part 103 Semiconductor element 150 metal layer 152 third ceramic base plate 160 Emitter connection 162 Collector connection 164 Gate connector 166, 168 measuring connections W1–W15, W42, W81 lines QUOTES INCLUDED IN THE DESCRIPTION

[0071] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0072] JP 2006-66595

[0002]

Claims

[1] comprising a semiconductor device: a first ceramic base plate ( 14 ); a second ceramic base plate ( 18 ); an inter-ceramic metal ( 16 ), which is an intermediate part ( 16a ), which is between an upper surface of the first ceramic base plate ( 14 ) and a lower surface of the second ceramic base plate ( 18 ) is arranged, a first projecting part ( 16b ), which is located on an upper surface of the second ceramic base plate ( 18 ) is trained, a second outstanding part ( 16c ), which is located on an upper surface of the second ceramic base plate ( 18 ) is formed, a first connecting part ( 16d ), which is attached to an outer edge of the second ceramic base plate ( 18 ) borders and the intermediate part ( 16a ) and the first outstanding part ( 16b ) connects, and a second connecting part ( 16e), which is attached to an outer edge of the second ceramic base plate ( 18 ) borders and the intermediate part ( 16a ) and the second outstanding part ( 16c ) connects, exhibits; a circuit pattern ( 20a , 20c ), which consists of a metal on the second ceramic base plate ( 18 ) is trained; and a semiconductor element ( 22 , 24 , 26 , 28 ), which is based on the circuit pattern ( 20a , 20c ) is planned, where a current flows through the semiconductor element ( 22 , 24 , 26 , 28 ) flows through the inter-ceramic metal ( 16 ) flows. [2] comprising a semiconductor device: a first ceramic base plate ( 14 ); a second ceramic base plate ( 18 ); an inter-ceramic metal ( 16 ), which is an intermediate part ( 16a), which is between an upper surface of the first ceramic base plate ( 14 ) and a lower surface of the second ceramic base plate ( 18 ) is arranged, a first outer edge part ( 16f ), which extends outwards in a top view over an outer edge of the second ceramic base plate ( 18 ) extends beyond, with the first outer edge part ( 16f ) with the intermediate part ( 16a ) is connected, and a second outer edge part ( 16g ), which extends outwards in a top view over an outer edge of the second ceramic base plate ( 18 ) extends beyond, with the second outer edge part ( 16g ) with the intermediate part ( 16a ) is connected; a circuit pattern ( 20a , 20c ), which consists of a metal on the second ceramic base plate ( 18 ) is trained; a semiconductor element ( 22 , 24 , 26 , 28), which is based on the circuit pattern ( 20a , 20c ) is planned; a first conductor (W81) which connects the semiconductor element ( 28 ) and the first outer edge part ( 16f ) electrically connects; and a second conductor (W41), which is connected to the second outer edge part ( 16g ) is connected. [3] comprising a semiconductor device: a first ceramic base plate ( 14 ); a second ceramic base plate ( 18 ); an inter-ceramic metal ( 16 ), which is an intermediate part ( 16a ), which is between an upper surface of the first ceramic base plate ( 14 ) and a lower surface of the second ceramic base plate ( 18 ) is arranged, a superimposed part ( 16b ), which is located on an upper surface of the second ceramic base plate ( 18 ) is designed to be a connecting part ( 16d), which is attached to an outer edge of the second ceramic base plate ( 18 ) borders and the intermediate part ( 16a ) and the outstanding part ( 16b ) connects, and an outer edge part ( 16f ), which extends outwards in a top view over an outer edge of the second ceramic base plate ( 18 ) extends beyond, with the first outer edge part ( 16f ) with the intermediate part ( 16a ) is connected, exhibits; a circuit pattern ( 20a , 20c ), which consists of a metal on the second ceramic base plate ( 18 ) is trained; a semiconductor element ( 22 , 24 , 26 , 28 ), which is based on the circuit pattern ( 20a , 20c ) is planned; a first conductor (W81) which connects the semiconductor element ( 28 ) with one of the outstanding parts ( 16b ) and the outer edge part ( 16f ) electrically connects; and a second conductor (W42), which is connected to the other by the overhanging part ( 16b ) and the outer edge part ( 16f ) is connected. [4] Semiconductor device according to any one of claims 1 to 3, further comprising: a collector connection ( 56 ); and an emitter connection ( 52 ), adjacent to the collector connection ( 56 ) is planned; wherein a collector current or an emitter current of the semiconductor element ( 22 , 26 ) through the inter-ceramic metal ( 16 ) flows, and where the collector connection ( 56 ) and the emitter connection ( 52 ) are arranged parallel to each other. [5] Semiconductor device according to any one of claims 1 to 4, comprising a plurality of the second ceramic base plates ( 18a , 18b ) exhibits. [6] Semiconductor device according to any one of claims 1 to 5, comprising a plurality of inter-ceramic metals ( 100 , 102 ) exhibits. [7] Semiconductor device according to any one of claims 1 to 6, comprising a plurality of the first ceramic base plates ( 14a , 14b ) exhibits. [8] Semiconductor device according to any one of claims 5 to 7, wherein the semiconductor elements form a converter circuit and an inverter circuit, and wherein the converter circuit and the inverter circuit are mounted on separate second ceramic base plates ( 18a , 18b are planned. [9] Semiconductor device according to any one of claims 1 to 8, further comprising a base plate ( 12 ), which consist of a metal on a lower surface of the first ceramic base plate ( 14 ) is formed, wherein heat sink fins ( 12c ) on the base plate ( 12 are trained. [10] Semiconductor device according to any one of claims 1 to 8, further comprising: a metal layer ( 150 ), which are located on a lower surface of the first ceramic base plate ( 14 ) is trained; a third ceramic base plate ( 152 ), which are located on a lower surface of the metal layer ( 150 ) is trained; and a base plate ( 12 ), which consist of a metal on a lower surface of the third ceramic base plate ( 152 ) is trained.

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