Digital-type short-circuit protection for a DC-DC converter

Abstract

Switching converter with short-circuit protection, wherein the switching converter comprises: a) an overcurrent comparator configured to detect an inductor current exceeding a current limit; b) a masking interval generator configured to mask information provided by the overcurrent comparator for a period of time; c) Short-circuit detection controllers configured to detect whether the overcurrent comparator indicates an overcurrent condition after a certain time period, and when an overcurrent condition is no longer detected, the switching current converter regulates itself below an acceptable maximum peak current, in a hysteresis mode, with a pattern of N to N + 2 omitted pulses, using a counter, where N is a number dependent on the states SHORTCIRCUIT_EVENT and SHORTCIRCUIT_STATE; and d) a pulse skipper for skipping one or more pulses during the overcurrent condition; wherein the overcurrent condition is no longer detected if a switching frequency is less than its peak limit for more than a predetermined number of clock cycles.

Description

AREA

[0001] The present disclosure relates generally to DC-DC converters and in particular to a current loop operating mode control and to the detection of and protection against short-circuit conditions at the converter output.

[0002] In power conversion solutions that use, for example, DC-to-DC buck converters, there are overcurrent detection and overcurrent limiting schemes of varying usefulness and effectiveness.

[0003] Fig. Figure 1 is a circuit diagram of a typical buck converter with a current-mode control loop. The buck converter includes an input voltage VIN, an output voltage VOUT, an inductor L40, a capacitor C50, a high-side switch SH, and a low-side switch SL. The control loop includes a divider DIV, an operational amplifier OA1 with inputs VOUT / K and VREF, a current sensor RS, a summing function SUM with SLOPE_COMP, a comparator CP1 with a positive input RS*IL+SLOPE_COMP and a negative input VEA, and a flip-flop RS1, which provides an output signal MAG for the high side of switch SH. When operating in pulse-width modulation (PWM) at a constant frequency, a periodically output clock CLK sets the magnetization signal MAG to '1'. The inductor current IL across inductor L40 is detected and converted into a voltage RS*IL by multiplication with RS.Occasionally, a slope compensation SLOPE_COMP is added to the voltage RS*IL. If the total voltage (RS*IL + SLOPE_COMP) exceeds the fault voltage VEA, the comparator CP1 sends the STOP signal, forcing the magnetization signal MAG to '0'. VEA sets the target for the maximum inductor current, also called the peak current. The voltage VEA is regulated by the fault operational amplifier OA1 to set the required inductor peak current at VOUT to a value proportional to VREF. VREF could be generated using a digital control unit with a VDAC digital-to-analog converter. The output voltage of such a buck converter could, for example, supply power to other subsystems.

[0004] Fig. Figure 2 illustrates a timeline of a short-circuit event description and its effect on VEA, IL, and VOUT of the buck converter in Fig. 1. The first cycle shows that the buck converter regulates at a given VOUT by means of a magnetization phase triggered by a rising edge of the clock CLK, followed by a demagnetization phase. The inductor current IL varies with an upward slope rate of (VIN-VOUT) / L and a downward slope rate of (-VOUT) / L, assuming VSL = 0 V. At the end of the second clock cycle, the short circuit occurs and VOUT is pulled down to 0 V. The short circuit occurs during a demagnetization phase and when the inductor current downward slope is (-VOUT) / L. If VOUT is shorted to ground, the demagnetization downward slope becomes (-VSL) / L, and the downward slope becomes (-RSL*IL) / L if SL is in Fig. 1 is a diode switch. As VOUT drops, the fault voltage VEA jumps to its maximum. This forces the regulating loop to its maximum duty cycle and full magnetization. Furthermore, most buck converters have peak current limit protection. If the inductor current exceeds its peak current limit, demagnetization is initiated, even if loop compensation still requires magnetization. The third cycle shows that the magnetization increases at a rate of (VIN) / L until it reaches the peak current limit ILIM_PEAK, which causes demagnetization to begin. Due to the internal delay in limit detection and the instruction to switch off the magnetization phase, the inductor current always exceeds the peak current limit slightly.When VOUT drops to nearly 0 V, there is almost no reduction in inductor current during the demagnetization phase, and the downward slope is (-VSL) / L. Consequently, the inductor current IL increases cycle by cycle. This causes the inductor to overheat until it eventually damages itself and / or the buck converter. The theoretical final settling value for IL is DMIN*VIN / L = (1-DMIN)*RSL*IL / L, which yields IL = DMIN*VIN / (RSL*(1-DMIN))), where DMIN is the minimum achievable duty cycle for proper ILIMmax detection, for example, when DMIN = 0.1, RSL = 0.02, VIN = 5, and IL = 27.7 A. It is then necessary to prevent this inductor current from running out of control in the event of a short circuit at the buck converter output.

[0005] In the prior art, a second peak current limit, higher than the first, is often found. If the first current limit is triggered for a given clock cycle, the second peak current limit circuit is ON in the next cycle and ready to detect an anomalous peak current caused by the short circuit. Triggering the second peak current limit would set a flag for the digital control unit, which would then switch off the buck converter. After a certain time, the buck converter would be released again, and the same sequence would repeat until the short circuit persists. In the presence of a short circuit at the output, this sequence is necessary to prevent damage to the inductor and / or the buck converter. In this way, the buck converter would be unable to provide a constant supply voltage to other systems in the presence of a short circuit.

[0006] Furthermore, the current state of the art involves the use of analog components, which have high power requirements. A peak current limit detector typically requires a fast comparator with an associated current reference. Unfortunately, these components are large in terms of silicon area. The peak current limit detector requires a current sensor that is typically 1 / 100th the size of the high-side pass-through device.

[0007] US 2011 / 0291634A1 describes an overcurrent protection circuit with a determiner configured to determine whether the switching current exceeds a predetermined threshold.

[0008] The switching current is an overcurrent condition when the switching element is turned on. The circuit includes an OFF-period setting counter configured to increment or decrement a counter output depending on a determination result of the determiner. The circuit includes a control signal generator configured to generate a control signal for the switching element such that the length of an ON-time interval of the switching element corresponds to the counter output of the OFF-period setting counter.

[0009] US 2007 / 0008748A1 describes an overcurrent protection circuit for DC / DC converters. A controller adaptively provides overcurrent protection by detecting a current in the converter that exceeds a current limit during the minimum on-time of a circuit breaker. A count N is calculated for the number of consecutive active switching cycles in which a current exceeds a current limit during the minimum on-time of the circuit breaker.

[0010] US 2016 / 0049859A1 describes a pulse step modulation (PSM) control loop device with automatic transition to pulse frequency modulation (PFM), comprising a peak current loop configured to provide a method for generating a constant minimum inductor peak current. SUMMARY

[0011] Accordingly, one object of one or more embodiments of the present invention is to provide a circuit and a method for protecting a buck converter from destruction in the event of a short circuit to ground at the output.

[0012] Another task of one or more embodiments of the disclosure is to implement a low current limit that is not much higher than the intended maximum safe operating current.

[0013] Another task of one or more embodiments of the disclosure is to implement rapid detection of an overcurrent due to a short circuit and to achieve a rapid frequency drop.

[0014] Another objective of one or more embodiments of the disclosure is to implement trouble-free loop recovery upon removal of a short circuit and to prevent the converter from reverting to maximum frequency operating mode if it experiences a high overcurrent, thus providing a natural soft restart from the overcurrent caused by a short circuit. Further objectives will appear below.

[0015] The above and other problems of the present disclosure can be solved in the following manner. In the current-mode loop circuit arrangement, the inductor current is detected, and an overcurrent comparator is used. A masking interval generator is required to mask overcurrent false trips caused by disturbances generated by switching the converter. Simple logic is used to detect whether the current limit comparator indicates an overcurrent at the end of the masking interval and to implement overcurrent pulse omission upon detection of a true overcurrent. This method reuses existing analog circuitry to achieve overcurrent protection. Only a small amount of additional digital logic is required to handle overcurrent pulse omission and overcurrent pulse recovery. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present disclosure will be more clearly understood from the following description in conjunction with the accompanying drawings, in which the same reference numerals denote similar or corresponding elements, regions and sections, and in which: Fig. 1 is a circuit diagram of a typical buck converter with a current mode control loop. Fig. 2 is a time schedule of a short-circuit event description and the effect on VEA, IL and VOUT of the buck converter. Fig. 3 is a circuit diagram of a buck converter which illustrates the principle of short-circuit protection in a first preferred embodiment of the present disclosure. Fig. 4 is a time schedule that represents the detection of the short-circuit protection in a first preferred embodiment of the present disclosure. Fig. 5 a circuit diagram for generating signals based on the short-circuit protection event and the short-circuit protection state in a first preferred embodiment of the present disclosure. Fig. 6 is a timing schedule that represents overcurrent limiting and pulse skipping during short-circuit protection in a first preferred embodiment of the present disclosure. Fig. Figure 7 shows a flowchart of a disclosed method for short-circuit protection. DESCRIPTION

[0017] Fig. Figure 3 is a circuit diagram of a buck converter, illustrating the short-circuit protection principle in a first preferred embodiment of the present disclosure. The buck converter comprises an input voltage VIN, an output voltage VOUT, an inductor L340, and a capacitor C350. The buck converter also includes switches SH and LS, which are controlled by DRVHS and DRVLS, respectively. The control loop includes a loop control with input signals VREF and SHORTCIRCUIT_STATE and a comparator CP2 with a positive input KL*IL and a negative input IREF1. The control loop also includes a flip-flop RS2, which provides an output signal MAG to control the high side of switch SH and which is inverted in inverter 371 to control switch LS.

[0018] The main part of the short-circuit detection scheme uses comparator CP2, which compares an image of the inductor current KL*IL, where KL*IL is proportional to the current flowing through switch SH, with a predefined reference IREF1. Comparator CP2 could be a current or voltage comparator. During normal operation of the buck converter, the transition from demagnetization (SH OFF and LS NO) to magnetization (SH ON and LS OFF) causes the LX voltage to oscillate (ring) due to parasitic effects at node LX. Consequently, all detected currents and voltages around these transitions must be properly handled to avoid false triggering of the current limit ILIM_EVENT. A masker is used to ensure proper detection of the peak current limit ILIM_COMP_OUT by comparator CP2.As is known in the field, the MASKIERER masks the information provided by comparator CP2 for the first few nanoseconds of the magnetization phase. This delay allows the input signals ILIM_COMP_OUT and MASKER_ON to regulate before they are compared. Under normal operation, the triggering event that comparator CP2 goes deep immediately after MASK_ON never occurs.

[0019] In the event of a short circuit at VOUT, the current in inductor L, KL*IL, builds up rapidly, and comparator CP2 is triggered as soon as MASK_ON goes low. The ILIM_COMP_OUT signal sets the ILIM_EVENT signal high, and OR1 sends a STOP signal, forcing the magnetization signal MAG to '0'. Additionally, the MASK_ON and ILIM_COMP_OUT signals are used to set the SHORTCIRCUIT_STATE and LOOP_CONTROL_EVENT signals in the control loop when a short-circuit event is detected. In this way, MASK_ON and ILIM_COMP_OUT are used to detect a short-circuit event in the buck converter.

[0020] When a short circuit is detected, many systems switch off the DC-DC buck converter for a specified period before switching it back on and checking if the short circuit is still present. Often, the buck converter incorporates a pulse-skip or frequency-fold-back scheme. This consists of a system that skips pulses to emulate a lower switching frequency. It is particularly useful when the output current load is very low and when switching losses are significant in terms of efficiency. The pulse skipper from Fig. 3 is described, for example, in related patent application No. 14 / 468,588, filed on August 26, 2014, which is incorporated herein in its entirety by reference. The pulse skipper function helps to generate a constant minimum inductor peak current and is configured to provide a method for skipping pulses using pulse outlet modulation (PSM) mode. The pulse skipper includes a peak current loop configured to provide a method for automatic transition from pulse outlet modulation to pulse frequency modulation (PFM).

[0021] In the event of a short circuit to ground being detected, the buck converter enters pulse-out mode, triggering PULSE_SKIPPED to limit the inductor peak current. The clock switching frequency is set to ensure that the peak current limit is not reached too early in the cycle. The duty cycle D of the active signal cannot be lower than DMIN, the minimum achievable duty cycle.

[0022] Since DMIN*VIN / L = (1-DMIN)*RSL*IL / L, this means IL = D*VIN / (RSL*(1-D)). To decrease IL and avoid an out-of-control current, DMIN would need to be decreased so that D can also decrease. DMIN is given by a fixed duration for a fixed masking time, and if it is divided by N, the frequency feedback ratio, D is limited by DMIN / N. To then bring IL back to ILIM_PEAK, ILIM_PEAK = D*VIN / (RSL*(1-D)), where D = DMIN / N = RSL*ILIM_PEAK / (VIN + ILIM_PEAK*RSL). KL*IL, as in Fig. 3 is shown, and RS*IL, as in Fig. The values ​​shown in Figure 1 are similar, as they both represent a mapping of the inductor current IL. However, RS*IL is a voltage and KL*IL is a current. KL can have a range of values. For example, KL = 1 and IREF1 = 10 A for a current limit of 10 A. However, a preferred value for KL would be in the range of 1 / 10000 to reduce the value of IREF1 and improve efficiency.

[0023] The idea behind the PULSE-SKIPPER is to detect when the duty cycle should be shorter than DMIN / N or when it detects that it is longer than DMIN / N. N is then adjusted to remain at the edge of these two conditions so that the duty cycle is at DMIN / N. For this purpose, both signals MASK_ON and ILIM_COMP_OUT are used. If ILIM_COMP_OUT is high when MASK_ON becomes low, the switching frequency is decreased, a pulse is skipped, and PULSE_SKIPPED = 1. Conversely, if ILIM_COMP_OUT is low when MASK_ON becomes low, the switching frequency is increased, no pulse is skipped, and PULSE_SKIPPED = 0. To prevent any false triggering events due to the voltage transient of node LX and the reference regulation, the comparator output is masked. Exiting the short-circuit state would, of course, occur.In fact, the short circuit is considered to be terminated if the switching frequency returns to normal for more than a predetermined number of clock cycles.

[0024] Fig. Figure 4 is a timing diagram illustrating the short-circuit protection detection in a first preferred embodiment of the present disclosure. During cycle 0, VOUT is regulated close to its target voltage defined by VREF, and VEA is also regulated. IL decreases at a rate of (-VOUT / L) for the demagnetization phase. There is no short-circuit event, SHORTCIRCUIT_EVENT = 0, and no skipped pulse, PULSE_SKIPPED = 0.

[0025] During cycle 1, CLK (= CLK_PWM, since no pulse is skipped) rises, triggering MAG. VOUT remains around its expected target, and VEA remains constant. IL increases for the magnetization phase at a rate of (VIN - VOUT) / L. MASK_ON rises and then falls, and IL_COMP_OUT remains low because IL < ILIM_PEAK. At approximately 75% of the clock period set by CLK_PWM, MAG falls, forcing the buck converter into the demagnetization phase. For the demagnetization phase, IL decreases at a rate of (-VOUT / L). There is no short-circuit event (SHORTCIRCUIT_EVENT = 0), and no pulse is skipped (PULSE_SKIPPED = 0).

[0026] During cycle 2, CLK (= CLK_PWM, since no pulse is skipped) increases, triggering MAG. VOUT remains around its expected target, so VEA remains constant. During the magnetization phase, IL increases at a rate of (VIN - VOUT) / L. MASK_ON increases and then decreases, and IL_COMP_OUT remains low because IL < ILIM_PEAK. At approximately 75% of the period set by CLK_PWM, MAG decreases, forcing the buck converter into the demagnetization phase. During the demagnetization phase, IL decreases at a rate of (-VOUT / L). Suddenly, for example, towards the end of cycle 2, a short circuit occurs at VOUT, and VOUT drops to a value of VSHORT = 0 V. This directly affects VEA, which begins to increase slowly at a rate determined by the loop bandwidth. The buck converter remains in the demagnetization phase at a rate of (-VOUT) / L = (-VSL) / L with VSHORT ~ = 0 V.There is only a continuous demagnetization and the level of the current IL decreases very slowly.

[0027] During cycle 3, CLK (= CLK_PWM, since no pulse is skipped) rises, triggering MAG. VOUT remains short-circuited, and VEA has increased drastically. IL has remained quite high because there was virtually no demagnetization of the inductor during the preceding demagnetization phase. IL increases at a rate of (VIN - VOUT) / L and approaches VIN / L. MASK_ON rises and then falls, and IL_COMP_OUT remains low because IL < ILIM_PEAK. Due to the high rate at which the inductor is magnetized, IL very quickly equals ILIM_PEAK. Consequently, ILIM_COMP_OUT rises and, due to internal delays within the circuit controls, holds the magnetization slightly above ILIM_PEAK. Demagnetization begins, and as in cycle 2, IL decreases very slowly.

[0028] During cycle 4, CLK (= CLK_PWM, since no pulse is skipped) rises, triggering MAG. VOUT remains short-circuited, and VEA has reached its maximum, VEA_MAX. IL has remained quite high because there was virtually no demagnetization of the inductor during the preceding demagnetization phase. IL increases at a rate of (VIN-VOUT) / L and approaches VIN / L. IL becomes greater than ILIM_PEAK within a few nanoseconds. MASK_ON rises with CLK_PWM and then drops. While MASK_ON drops, IL_COMP_OUT has already triggered high because IL > ILIM_PEAK. IL_COMP_OUT halts the magnetization, and shortly thereafter, demagnetization begins. ILIM_COMP_OUT, which is high when MASK_ON drops, triggers SHORTCIRCUIT_EVENT and SHORTCIRCUIT_STATE to high. Since both SHORTCIRCUIT_EVENT and SHORTCIRCUIT_STATE are high, the pulse skipper is enabled.CLK_PWM goes low, causing PULSE_SKIPPED to be programmed to skip 1 pulse the next time CLK comes up.

[0029] Fig. Figure 5 is a circuit diagram for generating signals based on a short-circuit protection event and short-circuit protection state in a first preferred embodiment of the present disclosure. If the inductor current IL is greater than its peak limit ILIM_PEAK, IL_COMP_OUT is triggered high. If the input IL_COMP_OUT is high and the input MASK_ON is low and inverted by inverter 520, the flip-flop DFFA sets SHORTCIRCUIT_EVENT high. SHORTCIRCUIT_EVENT high, in turn, sets SHORTCIRCUIT_STATE high, which stops the magnetization, in the short-circuit detection controls of the buck converter via the counter COUNTERA and the flip-flop RSA. If both SHORTCIRCUIT_EVENT and SHORTCIRCUIT_STATE are high, the pulse skipper in the overcurrent limiting controls of the buck converter is enabled.

[0030] Fig. Figure 6 is a timing diagram illustrating overcurrent limiting and pulse skipping during short-circuit protection. During cycle 5, CLK rises, while CLK_PWM remains low as a result of PULSE_SKIPPED = 1. The buck converter remains low during demagnetization with MAG until CLK rises again in the next cycle. IL decreases slightly further, below ILIM_PEAK, hopefully preventing ILIM_COMP_OUT from rising when MASK_ON is low. If ILIM_COMP_OUT does not remain low, PULSE_SKIPPED is incremented, and two pulses are skipped instead of one.

[0031] During cycle 6, CLK (= CLK_PWM, since no pulse is skipped) rises, triggering MAG. VOUT remains short-circuited, and VEA remains at its maximum, VEA_MAX. IL has remained quite high because there was virtually no demagnetization of the inductor during the preceding demagnetization phase. IL has increased at a rate of (VIN - VOUT) / L, approaching VIN / L*IL and exceeding ILIM_PEAK within a few nanoseconds. MASK_ON rises with CLK_PWM and then drops. While MASK_ON drops, IL_COMP_OUT has already triggered because IL > ILIM_PEAK. IL_COMP_OUT halts the magnetization, and shortly afterward, demagnetization begins, causing MAG to drop. The fact that ILIM_COMP_OUT is high when MASK_ON drops triggers SHORTCIRCUIT_EVENT and SHORTCIRCUIT_STATE to rise. The fact that CLK_PWM goes low causes PULSE_SKIPPED to be programmed to skip 2 pulses the next time CLK comes up.

[0032] During cycles 7 and 8, CLK rises while CLK_PWM remains low. The buck converter remains low in demagnetization with MAG until CLK (and CLK_PWM) rise again. The pulse skipper plays its role, and PULSE_SKIPPED allows IL to decrease slightly further, hopefully preventing ILIM_COMP_OUT from rising when MASK_ON goes low. If this doesn't happen, PULSE_SKIPPED is incremented, and the next time CLK rises, 3 pulses are skipped.

[0033] During cycle 9, CLK (= CLK_PWM, since no pulse is skipped) rises, triggering MAG. VOUT remains short-circuited, and VEA remains at its maximum, VEA_MAX. IL has remained quite high, as there was virtually no demagnetization of the inductor. IL increases at a rate of (VIN - VOUT) / L and approaches VIN / L. IL becomes greater than ILIM_PEAK within a few nanoseconds. MASK_ON rises with CLK_PWM and then falls. While MASK_ON falls, IL_COMP_OUT has not triggered high because IL < ILIM_PEAK and becomes low. While this is happening, the counter is decremented by 1, and SHORTCIRCUIT_STATE remains high until the counter reaches 0. When IL becomes greater than ILIM_PEAK, IL_COMP_OUT rises. IL_COMP_OUT halts magnetization, and shortly after, demagnetization begins, causing MAG to become low. The fact that CLK_PWM becomes low causes PULSE_SKIPPED to be programmed to skip one pulse the next time CLK rises.

[0034] During cycle 10, CLK rises while CLK_PWM remains low. The buck converter remains in demagnetization mode, with MAG low, until CLK rises again. The pulse skipper then does its job, and PULSE_SKIPPED causes IL to drop slightly further, hopefully preventing ILIM_COMP_OUT from rising when MASK_ON goes low. If this doesn't happen, PULSE_SKIPPED is incremented, and the next time CLK rises, two pulses will be skipped.

[0035] During cycle 11, CLK (= CLK_PWM, since no pulse is skipped) rises, triggering MAG. VOUT remains short-circuited, and VEA remains at its maximum, VEA_MAX. Since there was virtually no demagnetization of the inductor, IL remained quite high. IL increases at a rate of (VIN-VOUT) / L and approaches VIN / L. IL becomes greater than ILIM_PEAK within a few nanoseconds. MASK_ON rises with CLK_PWM and then drops. While MASK_ON drops, IL_COMP_OUT did not trigger because IL < ILIM_PEAK. When IL becomes greater than ILIM_PEAK, IL_COMP_OUT rises. IL_COMP_OUT halts the magnetization, and shortly thereafter, demagnetization begins, causing MAG to drop. The fact that CLK_PWM goes low causes PULSE_SKIPPED to be programmed to skip 0 pulses the next time CLK comes up.

[0036] During cycle 12, CLK (= CLK_PWM, since no pulse is skipped) rises, triggering MAG. VOUT remains short-circuited, and VEA remains at its maximum, VEA_MAX. Since there was virtually no demagnetization of the inductor, IL remained quite high. IL increases at a rate of (VIN - VOUT) / L and approaches VIN / L. IL becomes greater than ILIM_PEAK within a few nanoseconds. MASK_ON rises with CLK_PWM and then falls. While MASK_ON falls, IL_COMP_OUT has already triggered because IL > ILIM_PEAK. IL_COMP_OUT halts the magnetization, and shortly afterward, demagnetization begins, causing MAG to fall. The fact that ILIM_COMP_OUT is high when MASK_ON falls low triggers SHORTCIRCUIT_EVENT and SHORTCIRCUIT_STATE to rise. The fact that CLK_PWM goes low causes PULSE_SKIPPED to be programmed to skip 1 pulse the next time CLK comes up.

[0037] During cycle 13, CLK rises while CLK_PWM remains low. The buck converter remains in demagnetization mode, with MAG low, until CLK rises again. The pulse skipper then performs its function, and PULSE_SKIPPED causes IL to drop slightly further, hopefully preventing ILIM_COMP_OUT from rising when MASK_ON goes low. If this doesn't happen, PULSE_SKIPPED is incremented, and the next time CLK rises, two pulses are skipped. If the short circuit is resolved or stopped during the demagnetization phase, VOUT remains low because there is no current from the buck converter to charge it.

[0038] The general impression from Fig. Figure 6 states that the buck converter in the disclosure is self-regulating, such that IL < ILIM_PEAK. A type of hysteresis mode regulates with a pattern of N to N + 2 skipped pulses, set by PULSE_SKIPPED depending on the states of SHORTCIRCUIT_EVENT, SHORTCIRCUIT_STATE, and CLK_PWM. This method reuses existing analog circuitry to create overcurrent protection. Only a small amount of additional digital logic is required to handle overcurrent pulse skipping and recovery.

[0039] Fig.Figure 7 shows a flowchart of a disclosed method for short-circuit protection. The method for short-circuit protection includes, in 701, a provision for comparing an inductor current with a current limit value, and in 702, a provision for masking the output of an overcurrent comparator for a certain period of time. Furthermore, the method for short-circuit protection includes, in 703, a provision for detecting a short-circuit event if the output of the overcurrent comparator indicates a short-circuit condition after the specified period of time, and in 704, a provision for omitting one or more pulses during the overcurrent condition.

[0040] The above disclosure could be applicable to other types of switching converters such as boost converters, buck-boost converters, ground-referenced primary inductor converters (SEPIC) or Cuk converters if the converter is operated using a current loop operating mode control. Advantages

[0041] The advantages of one or more embodiments of the present disclosure include the fact that a buck converter uses existing circuitry to implement effective short-circuit / overcurrent protection. In the case of current-mode loop control, no additional protective circuitry is required. Compared to previously known techniques, the present disclosure provides a lower current limit, faster response, and a natural soft restart from an overcurrent due to a short circuit. There is no need to switch off the buck converter in the event of a short circuit, as it regulates itself below an acceptable maximum peak current.

[0042] Although certain embodiments of the present disclosure have been presented and described, the person skilled in the art understands that various changes can be made to the form and details without deviating from the inventive concept and the scope of protection of this disclosure.

Claims

[1] Switching converter with short-circuit protection, wherein the switching converter comprises: a) an overcurrent comparator configured to detect an inductor current exceeding a current limit; b) a masking interval generator configured to mask information provided by the overcurrent comparator for a period of time; c) Short-circuit detection controllers configured to detect whether the overcurrent comparator indicates an overcurrent condition after a certain time period, and when an overcurrent condition is no longer detected, the switching current converter regulates itself below an acceptable maximum peak current, in a hysteresis mode, with a pattern of N to N + 2 omitted pulses, using a counter where N is a number dependent on the states SHORTCIRCUIT_EVENT and SHORTCIRCUIT_STATE; and d) a pulse skipper for skipping one or more pulses during the overcurrent condition; wherein the overcurrent condition is no longer detected if a switching frequency is less than its peak limit for more than a predetermined number of clock cycles. [2] Switching converter with short-circuit protection according to claim 1, wherein the comparator is configured to be a current or a voltage comparator. [3] Switching converter with short-circuit protection according to claim 1 or 2, wherein the masking interval generator is configured to mask overcurrent false trips caused by disturbances generated by switching and to detect true overcurrent events at the end of the masking interval. [4] Switching converter with short-circuit protection according to a previous claim, wherein the outputs of the overcurrent comparator and the masking interval generator are configured to detect a short-circuit event in the switching converter. [5] Switching converter with short-circuit protection according to a previous claim, wherein the outputs of the overcurrent comparator and the masking interval generator are configured to regulate the switching frequency such that in the pulse skipper the switching frequency is reduced and a pulse is skipped and a counter is incremented by 1 when the output of the overcurrent comparator is high and the output of the masking interval generator is low. [6] Switching converter with short-circuit protection according to a previous claim, wherein the outputs of the overcurrent comparator and the masking interval generator are configured to regulate the switching frequency such that the switching frequency is increased in the pulse skipper and a counter is decremented by 1 when the output of the overcurrent comparator is low and the output of the masking interval generator is low. [7] Switching converters with short-circuit protection according to a previous claim, wherein the short-circuit detection controls are configured to control the magnetization and regulate the inductor current below an acceptable maximum peak current. [8] Switching transducer with short-circuit protection according to a previous claim, wherein the short-circuit detection controls are configured to transition from demagnetization to magnetization by closing a first switch and opening a second switch, and are configured to transition from magnetization to demagnetization by opening the first switch and closing the second switch. [9] Switching converters with short-circuit protection according to a previous claim, wherein existing circuits are configured to implement effective short-circuit and overcurrent protection which does not require additional protective circuits in the case of current mode control. [10] Switching converter with short-circuit protection according to a previous claim, wherein the switching converter is configured to remain enabled at all times. [11] A procedure for short-circuit protection comprising the following steps: a) Comparing an inductor current with a current limit value; b) Masking the output of an overcurrent comparator for a period of time; c) Detecting a short circuit if the output of the overcurrent comparator indicates an overcurrent condition after a certain time period; and d) Omission of one or more pulses during the overcurrent condition; wherein the short circuit is no longer detected if a switching frequency is lower than its peak limit for more than a predetermined number of clock cycles. [12] Method for short-circuit protection according to claim 11, wherein the overcurrent comparator comprises a current or a voltage comparator. [13] Method for short-circuit protection according to claim 11 or 12, wherein the short-circuit protection detects a short-circuit event when the output of the overcurrent comparator is greater than its peak limit. [14] Method for short-circuit protection according to any one of claims 11 to 13, wherein the short-circuit protection stops the magnetization in the switching transformer when a short-circuit event is detected. [15] Method for short-circuit protection according to any one of claims 11 to 14, wherein the short-circuit protection in the switching transformer changes from demagnetization to magnetization when a short-circuit event is no longer detected. [16] Method for short-circuit protection according to any one of claims 11 to 15, wherein the frequency of the switching converter is regulated by omitting one or more pulses, incrementing a counter when a short-circuit event is detected. [17] Method for short-circuit protection according to any one of claims 11 to 16, wherein the frequency of the switching converter is regulated by decrementing a counter to omit pulses when a short-circuit event is no longer detected. [18] Method for short-circuit protection according to any one of claims 11 to 17, wherein a current operating mode control uses the existing current sensing circuit to implement overcurrent protection. [19] Method for short-circuit protection according to any one of claims 11 to 18, wherein a safe and steady state is maintained for the switching transformer, which ensures trouble-free recovery during a short-circuit event.

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