Initialization of memory in a computer system

Abstract

Computer system (200), comprising: a processor (204); an external non-volatile memory (202) external to the processor (204); a memory controller (206) for the external non-volatile memory (202); and a power management unit (208) arranged to perform the following steps in sequence: the power management unit (208) receives a wake-up signal; the power management unit (208) wakes up the memory controller (206); the memory controller (206) initializes the external non-volatile memory (202); the power management unit (208) wakes up the processor (204).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an apparatus and method for initializing non-volatile memory in a computer system having a processor along with the memory. BACKGROUND

[0002] A processor in a computer system is arranged to perform various operations, which may include one or more basic arithmetic, logic, control, and input / output (I / O) operations. A processor that can perform all these types of operations is commonly referred to as a central processing unit (CPU) and includes an arithmetic logic unit (ALU), registers, a control unit, and, in some cases, cache memory. The processor (via the control unit in the case of a CPU) fetches instructions from memory for execution for various purposes, such as initializing the system or running a program.

[0003] One area of increasing attention is that of embedded systems. An embedded system is a computer system with a dedicated function that can function as part of a larger mechanical or electrical system.

[0004] Embedded systems are a key component in enabling the so-called "Internet of Things" (IoT), which refers to a concept in which objects not traditionally considered computers or computing devices are equipped with embedded systems that allow the objects to collect and exchange data. In addition to the incorporation of embedded systems into existing, everyday objects, the term "Internet of Things" also encompasses new and emerging technologies, such as microelectromechanical (MEMS) and nanotechnology devices, smartdust, and similar sensor nodes.

[0005] The Internet of Things has created a need for small and low-power devices that can ultimately connect everything on a protocol backbone or a portable computing device (such as a smartphone or tablet). Protocols used for Internet of Things applications take advantage of the ability of such devices to remain idle for long periods of time, while being active for only a short time interval, just enough to send the typically small amounts of data to the backbone or portable computing device.

[0006] To achieve extremely low power during active times, deeply embedded systems feature embedded or serial non-volatile memory (NVM), typically FLASH, to store code and critical data. However, FLASH processes, which are well into the submicrometer range, are quite expensive, while FLASH cells significantly increase chip size, thereby increasing silicon costs.

[0007] An alternative approach is to use a processor and memory external to the processor, typically as a discrete component. This architecture provides the same performance as embedded NVM (non-volatile memory) while allowing for scalable memory size because it is an external, discrete component.

[0008] However, with this type of arrangement, the memory must be initialized before code can be executed by the processor. This initialization requirement causes a delay and increases the risk of system crashes.

[0009] Such a system will typically include a memory controller that manages the storage of data in the memory array and exchanges data between the processor and the memory. Just like the memory itself, the controller must also be initialized before the processor can execute code.

[0010] Fig.Figure 1 shows an example of a prior art embedded system in which a system-on-chip (SoC) 100 is provided with an external FLASH memory 102. A FLASH controller 106 manages communication between a CPU 104 and the memory 102. The system-on-chip 100 is also provided with a power management unit (PMU) 108, which can receive a wake-up signal when the system is asleep or powered off.

[0011] During system sleep, memory 102 may be completely disconnected from power or placed in a deep low-power, low-leakage mode. When the system wakes up, memory 102 must be ready for code fetching by processor 104. Controller 106 must also be configured to perform memory initialization. A specific command or command sequence may be required to place the system into a particular data transfer mode or to release the device from a low-power mode to a normal operating mode.

[0012] Furthermore, since many memory vendors use their own command codes for various commands, a connection-programmed or hard-wired implementation would lack flexibility.

[0013] The controller 106 itself must maintain vital configurations in case it is turned off or disconnected from power during sleep. This requires retention registers that retain their programming values so that the controller knows what to do when it wakes up.

[0014] US 6,230,274 B1 describes a method and apparatus for restoring a memory device channel upon exiting a power-saving mode. One method includes storing a set of memory initialization values from memory locations in a memory controller in a memory that retains values during a power-down state. These values may be required to access system memory. Upon exiting the power-down state, the values are restored to the memory locations in the memory controller. SUMMARY OF REVELATION

[0015] The present invention is defined by the appended claims. In the following, portions of the description and drawings that refer to prior embodiments and do not necessarily include all features for implementing embodiments of the claimed invention are to be understood as not representing embodiments of the invention, but rather as examples that facilitate understanding of embodiments of the invention.

[0016] According to a first example of the disclosure, which is not covered by the claims but is useful for understanding the invention, a computer system is provided, comprising: a processor; an external memory external to the processor; a memory controller for the external memory; and a power management unit arranged to receive a wake-up signal, then first wake up the memory controller; and second, at a later time, wake up the processor.

[0017] Optionally, the controller is arranged to initialize the external memory before the processor is woken up by the power management unit.

[0018] Optionally, the computer system further comprises an instruction memory storing memory initialization instructions for the external memory; and wherein the memory controller is arranged to retrieve the memory initialization instructions from the instruction memory when awakened by the wake-up signal received from the power management unit.

[0019] Optionally, the memory controller has a memory for storing the memory initialization instructions.

[0020] Optionally, the controller has a hardware state machine for initializing the external memory.

[0021] Optionally, the processor, instruction memory, power management unit and memory controller are provided as components of the same integrated circuit.

[0022] Optionally, the external memory is a FLASH memory or other EEPROM.

[0023] According to a second example of the disclosure, not covered by the claims but useful for understanding the invention, a method is provided for transitioning a computer system from a sleep or powered-off state to a powered-on state, the computer system comprising a processor, external memory external to the processor, a power management unit, and a memory controller, the method comprising: receiving, at the power management unit, a wake-up request; waking the memory controller; then, at a later time, waking the processor.

[0024] Optionally, the method includes initializing the external memory after waking the memory controller and before waking the processor.

[0025] Optionally, initializing external memory involves fetching memory initialization instructions from an instruction store and loading those instructions into the memory controller.

[0026] Optionally, initializing the external memory involves sending commands to the external memory using a hardware state machine.

[0027] Optionally, after the processor is woken up, it takes over and exchanges data with the external memory. SUMMARY OF DRAWINGS

[0028] The disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which: Fig. 1 shows an example of an embedded system according to the prior art in which a system-on-chip (SoC) with an external FLASH memory is provided; Fig.2 illustrates an embodiment of an embedded system according to the present disclosure; Fig. 3 illustrates an embodiment of a controller used in the system of Fig. 2 can be used; Fig. 4 shows an embedded system according to another embodiment of the present disclosure; and Fig. 5 illustrates a method for system initialization according to the disclosure. DETAILED DESCRIPTION

[0029] Fig.Figure 2 illustrates a system 200 according to one embodiment of the disclosure. A processor 204 retrieves instructions from a memory 202, which in a preferred embodiment is non-volatile memory (NVM). A memory controller 206 configures the memory 202 and interfaces with the processor 204. The components are connected by data buses 210, 212, 214, and a power management unit (PMU) 208 is provided, which sends wake-up signals 216, 218 to the processor 204 and the controller 206, respectively.

[0030] The disclosure is not limited to a specific architecture, however, in one example implementation, the processor 204, the controller 206, the power management unit (PMU) 208, and the optional instruction memory 210 are all provided as part of the same system-on-chip (SoC), and the memory 202 is provided as a separate, discrete component, external to the system-on-chip.

[0031] The processor 204 and the power management unit (PMU) 208 are shown as separate components, but they may alternatively be provided as part of a combined component; i.e., the power management unit PMU could be integrated into the processor 204, or vice versa. Similarly, the controller 206 could be provided as part of the system-on-chip (SoC), or it could be integrated together with the memory 202, in which case the memory 202 and the controller 206 are provided together as a discrete component, external to the system-on-chip (SoC).

[0032] The power management unit (PMU) is arranged to receive a wake-up signal from an external source or system. It may also include more complex components that provide one or more power management functions, such as battery management, voltage regulation, and charging functions.

[0033] An instruction memory 210 is provided that can store instructions for use by the controller 206, including code for initializing the controller 206. The instruction memory 210 is shown as an optional component because it is also possible for the required instructions to be stored in the main memory 202.

[0034] Fig. 3 shows an exemplary embodiment of a controller 206 for use with the system of Fig. 2. As in Fig.2, the controller 206 exchanges data with the processor 204, the power management unit 208, and the instruction memory 210 via the data bus 212, and exchanges data with the memory 202 via the data bus 214. The controller 206 includes a bus interface 300, a memory 302, and a finite state machine (FSM) 304. The memory 302 preferably includes an appropriate random access memory (RAM). The finite state machine (FSM) 304 changes state depending on the inputs it receives from the bus interface 300 and the random access memory (RAM) 302 and, in preferred embodiments, is implemented in hardware. The finite state machine (FSM) includes any suitable circuitry that can change state depending on the inputs.

[0035] It is possible that memory 202 may be either completely turned off or disconnected from power or in a deep low-power mode when the system enters a sleep mode (of any kind), particularly if controller 206 is used as part of an ultra-low-power system-on-chip (SoC). However, upon power-up or wake-up, memory 202 requires a series of instructions to reach a state where processor 204 can actually execute code. This initialization should occur before processor 204 is woken up.

[0036] When the power management unit 207 receives an interrupt 201 or other wake-up signal, it restores power and sends a wake-up command 218 to the controller 206. The controller 206 then receives initialization commands from the memory 210 and loads them into its operational memory 302, which may suitably be in the form of a FIFO (First In First Out) buffer or other suitable memory. The instruction memory 210 may be a suitable type of non-volatile memory, such as one-time programmable read-only memory (OTP ROM), and it may be preprogrammed, for example, during product testing.

[0037] Then, the controller 206 decodes the instructions in the random access memory 302 into memory instructions of an appropriate format and then initializes the memory 202. As in Fig.3, the controller 206 may include a hardware state machine 304 that may perform the decoding and initialization functions.

[0038] After initializing memory 202, power management unit 208 sends a wake-up command 216 to processor 204, indicating that memory 202 is now ready for code execution by processor 204. Processor 204 then takes over and begins fetching code from memory 202.

[0039] As mentioned above, in an alternative embodiment, the initialization instructions may be stored directly in memory 202 rather than in a dedicated instruction memory 210. Instructions for retrieving the instructions may be hard-coded in the controller.

[0040] The power management unit informs both the controller 206 and the processor 204 that the system should be woken up, but not at the same time. By ensuring that memory is initialized before the processor 204 wakes up, it appears to the processor 204 as if the memory 202 never went to sleep at all, and instructions can be fetched by the processor 204 as soon as it is started. Secondary loaders are not required to handle the initialization procedure.

[0041] Likewise, the processor 204 does not need to intervene in the initialization of the memory 202. Instead, a very small (compared to the processor) dedicated hardware state machine 304 or equivalent is provided to perform the initialization, resulting in power savings compared to the intervention of a processor.

[0042] The disclosure also provides great flexibility because all instructions, including cleanup wait states, can be programmed in the random access memory 302 of the controller 206.

[0043] Furthermore, retained registers or random access memory (RAM) are provided to store the memory initialization microcode in the controller even when a power island supplying the controller is completely turned off.

[0044] There are many types of systems, storage, and communication technologies to which the present disclosure can be applied. However, to further enhance the understanding of the disclosure, Fig. 4, by way of example only, a specific embodiment of the disclosure wherein the memory is a QSPI (quad serial peripheral interface) FLASH memory.

[0045] As in Fig.4, a system-on-chip 400 includes a CPU 404 that fetches instructions from a QSPI FLASH memory 402 provided external to the system-on-chip 400. A QSPI interface includes four bidirectional input and output data signals between master and slave, typically labeled IO0 through IO3. The QSPI controller 406 includes a bus interface 420, microcode RAM 426, and a hardware state machine (control FSM) 424. The system-on-chip (SoC) also includes read-only memory (ROM) configured to operate with the CPU 404 to perform a particular function for which the system-on-chip (SoC) is intended.

[0046] The operating principles of the system Fig. 4 are similar to those described above with reference to the Fig. 2 and Fig. 3, except that Fig.4 provides more details of a specific optional implementation. The initialization microcodes are stored on the system-on-chip 400 in a one-time programmable memory (OTP) 410. When the power management unit 408 receives an interrupt or is otherwise instructed to initiate a wake-up call, it sends a wake-up signal 418 to the QSPI controller 406. The controller 406 then retrieves the microcodes stored in the OTP 410 and stores them in its microcode random access memory (RAM) 426, which in this example is a FIFO memory buffer. The hardware state machine 424 then decodes the instructions located in the FIFO 426 and automatically initializes the QSPI FLASH 402.

[0047] Once the QSPI FLASH 402 is initialized, the power management unit 408 sends a wake-up signal 416 to the CPU 404, indicating that the QSPI FLASH 402 is available for code execution. The CPU 404 then takes over and begins fetching code from the QSPI FLASH memory 402.

[0048] An embodiment of the microcode could look like the following table: Table 1: Microcode implementation bit name Description Byte 0 7:3 CMD_BYTES The number of payload bytes to be sent 2:1 CMD_TX_MD QSPI bus mode when transmitting the command 0x0: single SPI 0x1: dual SPI 0x2: quad SPI 0x3: reserved 0 CMD_VALID 1: Instruction set valid 0: Instruction set not valid Byte 1 7:0 CMD_WT_CNT_LS Number of clock cycles to wait after the instruction is applied (least important byte) 7:0 CMD_WT_CNT_MS Number of clock cycles to wait after the instruction is applied (most important byte) Byte 3 to (CMD_NBYTES+2) The actual data bytes to be sent within a QSPI chip select envelope signal.

[0049] The first byte (LSByte) in the FIFO word contains the flag of the command, either valid or not valid, the bus operating mode and the number of bytes contained in the payload to be sent.

[0050] The second and third bytes define the number of clock cycles the QSPI controller must wait after applying the command. Depending on the clock period, if more time is needed for the FLASH to settle, multiple identical commands could be issued. Example:

[0051] If 0xAB is the command code to enable FLASH from deep low-current mode, the FIFO would be initialized with the following sequence: Table 2: Microcode example byte Value Description 0 0x11 Valid instruction set, single SPI mode, 2 bytes payload 1 0×01 Wait for 1 clock cycle after the command is sent 2 0x00 3 0xAB Actual QSPI FLASH command code. This command code means "release from deep low-power mode."

[0052] It should be noted that the embodiment of Fig. 4 is used for illustration purposes and many variations can be considered. For example, the interface can be a normal SPI or an I 2 C interface and the memory can be another type.

[0053] The present disclosure also relates to a method for initializing a computer system that corresponds to the capabilities of the above-described embodiments. The method is also a method for transitioning a computer system from a sleep or off state to a powered-on state. The method is illustrated in the flowchart in Fig.5. Here, it can be seen that at step 500, the power management unit (PMU) receives an interrupt, or equivalent instruction, to initiate a system wake-up. The power management unit (PMU) then restores power and sends a wake-up signal to a controller (step 502), whereupon the memory initialization microcode is loaded into the controller's random access memory (RAM) (504) and the memory is initialized (step 506). The power management unit (PMU) then wakes up the processor (step 508), which then takes over and fetches code from memory (step 510).

Claims

[1] Computer system (200), comprising: a processor (204); an external non-volatile memory (202) external to the processor (204); a memory controller (206) for the external non-volatile memory (202); and a power management unit (208) arranged to perform the following steps in sequence: the power management unit (208) receives a wake-up signal; the power management unit (208) wakes up the memory controller (206); the memory controller (206) initializes the external non-volatile memory (202); the power management unit (208) wakes up the processor (204). [2] The computer system (200) of claim 1, further comprising an instruction memory (210) storing memory initialization instructions for the external non-volatile memory (202); and wherein the memory controller (206) is arranged to retrieve the memory initialization instructions from the instruction memory (210) when awakened by the wake-up signal received from the power management unit (208). [3] The computer system (200) of claim 2, wherein the memory controller (206) includes a memory for storing the memory initialization instructions. [4] The computer system (200) of any preceding claim, wherein the controller comprises a hardware state machine for initializing the external non-volatile memory (202). [5] The computer system (200) of any of claims 2 to 4, wherein the processor (204), instruction memory (210), power management unit (208) and memory controller (206) are provided as components of the same integrated circuit. [6] A computer system (200) according to any preceding claim, wherein the external non-volatile memory is a FLASH memory or other EEPROM. [7] A method for transitioning a computer system from a sleep or off state to a powered-on state, the computer system (200) comprising a processor (204), an external non-volatile memory (202) external to the processor (204), a power management unit (208), and a memory controller (206), the method comprising the following steps, which are carried out in sequence: the power management unit (208) receives a wake-up signal; the power management unit (208) wakes up the memory controller (206); the memory controller (206) initializes the external non-volatile memory (202); the power management unit (208) wakes up the processor (204). [8] The method of claim 7, comprising initializing the external non-volatile memory (202) after waking the memory controller (206) and before waking the processor (204). [9] The method of claim 7 or claim 8, wherein initializing the external non-volatile memory (202) comprises retrieving memory initialization instructions from an instruction memory (210) and loading those instructions into the memory controller (206). [10] The method of any of claims 7 to 9, wherein initializing the external non-volatile memory (202) comprises sending commands to the external non-volatile memory (202) using a hardware state machine. [11] The method of any of claims 7 to 10, wherein, after the processor (204) is woken up, it takes over and exchanges data with the external non-volatile memory (202).

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