Dual rail storage, storage macro and associated hybrid power supply method

Abstract

Dual-rail storage device capable of operating at a first voltage (VDDM) and a second voltage (VDD), wherein the dual-rail storage device comprises the following: a memory array (150) that operates at the first voltage (VDDM); a word line driver circuit (140) configured to drive a word line of the memory array (150) to the first voltage (VDDM); a data path (110) configured to carry an input data signal or an output data signal; and a control circuit (120) configured to generate control signals for the memory array (150), the word line driver circuit (140) and the data path (110), wherein the data path (110) and the control circuit (120) are configured to operate at both the first voltage (VDDM) and the second voltage (VDD), wherein part of the data path (110) and part of the control circuit (120) are configured to operate at the first voltage (VDDM), and the remaining part of the data path (110) and the remaining part of the control circuit (120) are configured to operate at the second voltage (VDD).

Description

Background of the invention

[0001] Memory devices are subject to a phenomenon known as leakage current. Leakage current is typically drawn or consumed by the logic in the peripheral and core memory arrays whenever the memory is powered on. As device structures continue to shrink below subnanometer geometries, the leakage current absorption in a memory device increases. This leakage current becomes a significant factor in the total current consumption of the memory.

[0002] One method for reducing leakage current is to lower the supply voltage to a memory device. However, the voltage level of a bit cell in the memory must be maintained at a specified minimum voltage for storage, while peripheral parts of the memory device may operate below this specified voltage. Therefore, power supplies for dual-rail memory, where the peripheral and core of a memory operate with separate power supplies at different voltages, have been developed in an effort to reduce leakage current. Memory with dual-rail power supplies uses level shifters to separate a high-voltage domain (e.g., VDDM) for one group of circuits from a low-voltage domain (e.g., VDD) for another group of circuits, and to convert signal voltages to the appropriate domain using the level shifters.The prior art relevant to the present invention is given by US 2015 / 0 098 267 A1, US 2014 / 0 025 981 A1 and US 2012 / 0 033 517 A1. Brief description of the drawings

[0003] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 is a block diagram that conceptually represents a hybrid double-rail storage power supply scheme for a storage macro according to an exemplary embodiment of the present invention. Fig. 2 is a more detailed block diagram that shows the memory macro of Fig. 1 shows an exemplary embodiment of the present invention. Fig. Figure 3 is a block diagram showing part of a control circuit according to an exemplary embodiment of the present invention. Fig. Figure 4 is a block diagram showing a write driver according to an embodiment of the present invention. Fig. Figure 5 is a time history diagram showing waveforms of the hybrid dual-rail storage power supply scheme and existing dual-rail storage power supply schemes during a read operation. Fig. Figure 6 is a block diagram that conceptually represents a hybrid double-rail storage power supply scheme with a suppressed word line voltage for a storage macro according to an exemplary embodiment of the present invention. Fig. Figure 7 is a block diagram showing a word line suppression circuit according to an embodiment of the present invention. Fig. Figure 8 is a time-history diagram showing waveforms of the hybrid double-rail storage power supply scheme with a suppressed word line voltage during a read operation. Fig. Figure 9 is a diagram showing measurement curves of the hybrid power supply scheme and existing power supply schemes with respect to speed and power consumption behavior under different configurations of the second voltage. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and it may also include embodiments in which additional elements can be formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Embodiments of the present invention are described here in connection with an exemplary hybrid dual-rail storage power supply scheme for a storage device. However, it should be understood that the invention is not limited to the specific circuits and systems shown and described here by way of example. Rather, embodiments of the invention are largely directed to methods for advantageously integrating elements of a hybrid dual-rail storage power supply scheme into a high-density storage device, regardless of whether the storage device is an embedded or a standalone device.In this way, embodiments of the invention provide a hybrid dual-rail memory power supply scheme that can be advantageously used in many different memory applications and types, such as direct-access memory (RAM), static direct-access memory (SRAM), ROM, content-addressable memory (CAM), flash memory, register files, and the like. Those skilled in the art will recognize, in light of the principles of the present invention, that numerous modifications within the scope of protection of the present invention can be made to the described embodiments. That is to say, no restrictions are intended with respect to the specific embodiments described herein, nor may any such restrictions be inferred.

[0006] Fig. Figure 1 is a block diagram that conceptually represents a hybrid dual-rail memory power supply scheme for a memory macro 100 according to an exemplary embodiment of the present invention. The memory macro 100 can be a static direct access memory (SRAM) and can be located in a computer or other electronic systems. Fig. In Figure 1, the memory macro 100 has a plurality of memory arrays 150, which are usually two-dimensional and consist of memory bit cells configured to store corresponding logical states, i.e., either a logical H state (logical "1") or a logical L state (logical "0"). The memory bit cells are often arranged in one or more parallel columns 130 (each a one-dimensional subarray 130).

[0007] In the exemplary embodiment, the memory macro 100 has a symmetrical structure. For example, the left side of the memory macro 100 has similar elements to the right side of the memory macro 100. The multiple memory subarrays 130, which are arranged on the left and right sides of the memory macro 100, are in Fig. Figure 1 shows two data paths 110, which are also arranged symmetrically, i.e., one on the left and one on the right.

[0008] The data paths 110 comprise circuits for transferring data between corresponding memory subarrays 130 and circuits outside the memory macro 100. For example, in some embodiments, the data paths 100 comprise circuits for performing write mask operations, circuits for controlling column redundancy, circuits for encoding and decoding the error correction code (ECC), read amplifier circuits for global bit lines, write driver circuits for global bit lines, etc. However, this is not a limitation of the present invention.

[0009] Word line driver circuits 140, arranged between the two symmetrical memory arrays 150, serve to bring a word line of the memory arrays 150 to a word line control voltage with a defined voltage level. A control circuit 120 provides control signals for the plurality of subarrays 130 and the data paths 110 of the left and right memory arrays 150. In some embodiments, the control circuit 120 generates control and timing signals for read amplifiers used in read bit cells in the memory array 150. The control circuit 120 also includes circuits for selecting banks of memory cells, circuits for decoding the word line, word line drivers, etc.

[0010] In this embodiment, a first power supply with a first voltage VDDM and a second power supply with a second voltage VDD, which is lower than the first voltage VDDM, are used. The current domain assignment of the first voltage VDDM and the second voltage VDD is in Fig. Figure 1 shows that the memory macro 150 is structured such that the memory arrays 150 and the word line driver circuits 140 essentially operate at the first voltage VDDM, while the data paths 110 and the control circuit 120 are configured to operate at both the first voltage VDDM and the second voltage VDD. Specifically, a portion of the data paths 110 and a portion of the control circuit 120 are configured to operate at the first voltage VDDM, and the remaining portion of the data paths 110 and the remaining portion of the control circuit 120 are configured to operate at the lower second voltage VDD.

[0011] The hybrid double-rail storage power supply scheme of Fig. Method 1 has the advantage of achieving a balanced performance in terms of speed and power consumption, especially compared to existing dual-rail memory power supply schemes with interface level shifters and true dual-rail memory power supply schemes. A dual-rail memory macro is referred to as dual-rail memory with interface level shifters when the entire memory macro operates in a first voltage domain of a higher power supply than a second voltage domain outside the memory macro, with level shifters located at a pin boundary of the memory macro. In a true dual-rail memory power supply scheme, only the memory arrays and part of the word line driver of the memory macro operate at a first voltage, and the remaining circuitry of the memory macro operates in a different domain at a second voltage that is lower than the first voltage.

[0012] For the sake of simplicity, various circuits in the data paths 110, the control circuit 120, the memory array 150, and the word line driver circuits 140 are not shown in the block diagram. Details of the various circuits are given in the drawings below, and descriptions are provided in the sections below. It should be clear to those skilled in the art, in view of the principles of the present invention, that numerous modifications, which are within the scope of protection of the present invention, can be made to the described embodiments.

[0013] Fig. 2 is a more detailed block diagram, which uses the memory macro 100 from Fig. Figure 1 shows an exemplary embodiment of the present invention. For better understanding, elements in Fig. 2, which are those of Fig. 1. Similar items are designated with the same reference numbers. Top right in Fig. 2. The memory array 150 comprises a plurality of bit cells 1502–1508, which are shown for illustrative purposes only. As explained above, the entire memory array 150 operates at the first voltage VDDM, which is higher than the second voltage VDD, in order to reduce the occurrence of errors during read / write operations. Furthermore, reducing the supply voltage of the memory array 150 can make it more susceptible to soft error rate effects. The soft error rate is a measure of each bit cell's ability to maintain a data state in the presence of ambient noise, such as alpha (α) particles. Alpha particles are a form of radiation energy commonly found in the environment. They are very energetic particles with a strong ability to penetrate many objects in the environment.

[0014] bottom left in Fig. 2. The control circuit 120 comprises an address memory 1202, a word line column decoder 1204, a pulse generator 1206, a read / write control element 1208, and a trace path 1210. The control inputs for the control circuit 120 can include, for example, addresses, read / write enable, and chip select enable. The address memory 1202, the word line column decoder 1204, the pulse generator 1206, and the read / write control element 1208 operate at the first voltage VDDM. The trace path 1210 operates at both the first voltage VDDM and the second voltage VDD. Input level shifter (in Fig. (2 not shown) are arranged upstream of the address memory 1202, which stores the control inputs, and convert the control inputs from a peripheral voltage (e.g., the second voltage VDD) outside the memory macro 100 to the first voltage VDDM. The access time of the memory array 150 is not affected. In contrast, in the existing dual-rail memory power supply scheme with interface level converters, word line level converters are arranged downstream of the address memories, and the memory access time is affected by the level converter delay.

[0015] The word line column decoder 1204 serves as an interface for a specific column of the memory array 150. The pulse generator 1206 produces a pulse with a pulse duration. The pulse duration is chosen such that the voltage level of a specified bit cell in the memory array 150 is reduced for a period sufficient to write the data value to that bit cell, while remaining short enough to prevent other bit cells in the column from becoming unstable.

[0016] Fig. Figure 3 is a block diagram showing part of a control circuit 120 according to an exemplary embodiment of the present invention. As in Fig. As shown in Figure 3, the tracking path 1210 comprises a tracking array 1212, a p-channel metal-oxide-semiconductor field-effect transistor (hereinafter referred to as the "PMOS device") 1214, and an NMOS device 1216. By using an inverter 1218 operating at the first voltage VDD, an inverted output of the tracking path 1210 is connected to the bit cells of the memory array 150 so that the voltage level of the fixed bit cell can be reduced in response to the duration output by the pulse generator 120. The pulse generator 1210, the tracking array 1212, and the PMOS device 1214, like the memory array 150, are configured to operate at the first voltage VDDM. The NMOS 1216 is used as a transfer gate connected between the tracking array 1212 and the bit cells in the memory array 150. One gate of the NMOS 1216 is connected to the second voltage VDD.Although the second voltage VDD is lower than the first voltage VDDM, the NMOS can still be switched on to allow signals to pass through.

[0017] Let us now return to… Fig. 2. In the upper left, the word line driver circuits 140 comprise two word line drivers 1402 and 1404. In the lower right, in Fig. 2. Data paths 110 comprise a pair of data paths. The left data path includes a bit line preloader 1102, which is connected to a write data path and a read data path. The write data path of the left data path includes a write column multiplexer 1106, a write driver 1108, and latched data 1110. The read data path of the left data path includes a read column multiplexer 1112, a read amplifier 1114, and an output driver 1116. Similarly, the right data path includes a bit line preloader 1104, which is connected to a write data path and a read data path. The write data path of the right data path includes a write column multiplexer 1118, a write driver 1120, and latched data 1122. The read data path of the right data path includes a read column multiplexer 1114, a read amplifier 1126, and an output driver 1128.

[0018] The write driver 1108 is used to control input data latched by the latched data 1110 and received by a CPU or other processor during a write operation, where the input data can be complementary data. The input data must be written to a specified bit cell of the memory array 150, which is identified by the control circuit 120. In response to the decoding result of the word line column decoder 1204 of the control circuit 120, output signals from the write driver 1108 selectively pass through the corresponding write column multiplexer 1106. The output signals of the write driver 1108 are preloaded via the bit line preloader 1102.

[0019] The bit line preloader 1102 and the latched data 1110 are configured to operate at the second voltage VDD, while the write driver 1108 is configured to operate at both the first voltage VDDM and the second voltage VDD. Now let's move on to... Fig. 4. Fig. Figure 4 is a block diagram showing the write driver 1108 according to an embodiment of the present invention. The write driver 1108 comprises a write driver pre-stage 1130 and a write driver post-stage 1132. The write driver pre-stage 1130 comprises inverters 1134 and 1136, both configured to operate at the first voltage VDDM. The write driver pre-stage 1130 receives write data from the latched data 1110 via a level shifter (in Fig. 4 not shown). Since the latched data 1110 and the write driver pre-stage 1130 operate in different voltage domains, the level shifter transfers the write data from the domain of the second voltage VDD to the domain of the first voltage VDDM.

[0020] The write driver stage 1132 comprises cross-connected PMOS devices 1138 - 1144 and NMOS devices 1146 and 1148. In the hybrid dual-rail memory power supply scheme, the write driver stage 1132 is configured to operate at the second voltage VDD in order to eliminate any introduced DC current.

[0021] Let's return to... Fig. Back to 2. Here, the read data path of the left data path comprises a read column multiplexer 1112, a read amplifier 1114, and an output driver 1116. During a read operation, a voltage difference is generated across the corresponding bit lines, which is routed via the corresponding read column multiplexer 1112 to the read amplifier 1114. When a sufficient voltage difference is reached, the read amplifier 1114 is switched on. The read column multiplexer 1112, the read amplifier 1114, and the output driver 1116 are configured to operate at the second voltage VDD, thus eliminating the need for level shifters at one interface of the read data path. The right data path of data path 110 is essentially the same as the left data path, and for brevity, the details are omitted here.

[0022] Fig. Figure 5 is a time-series diagram showing waveforms of the hybrid dual-rail storage power supply scheme and existing dual-rail storage power supply schemes during a read operation. As shown in Fig. Figure 5 shows signals during a read operation for three different schemes: the hybrid dual-rail memory power supply scheme of the present invention, the dual-rail memory power supply scheme with interface level shifters, and the true dual-rail memory power supply scheme, to allow for comparison of timing. A top-level clock signal CK is used as a reference timing index for the three different power supply schemes. Each power supply scheme has a word line signal WL, a bit line signal BL and its complementary signal BLB, and a signal Q, which is detected by a read amplifier.

[0023] As explained above, the memory macro that uses the dual-rail memory power supply scheme with interface level shifters has only a control circuit and read data paths that operate in a voltage domain (i.e., at the first voltage VDDM) that is the same as the voltage domain of the memory arrays, whereas the memory macro that uses the true dual-rail memory power supply scheme has a control circuit and a read data path that operate in a lower voltage domain (i.e., at the second voltage VDD) than the voltage domain (i.e., at the first voltage VDDM) in which the memory array operates. Regarding the hybrid dual-rail memory power supply scheme of the present invention, the control circuit 120 operates at both the first voltage VDDM and the second voltage VDD, and the read data path operates at the second voltage VDD.

[0024] As from Fig. As can be seen in Figure 5, in the dual-rail storage power supply scheme with interface level converters, the word line signal WL has the fastest rise time at time T2 after the clock signal CK is applied at time T1. Due to the fact that the control circuit partially operates at the second voltage VDD, which more or less affects the rise rate of the word line signal WL, the rise time of the word line signal WL in the hybrid dual-rail storage power supply scheme at time T3 is slightly later than the rise time in the dual-rail storage power supply scheme with interface level converters.The word line signals WL of the dual-rail storage power supply scheme with interface level shifters and the hybrid dual-rail storage power supply scheme are both brought to the first voltage VDDM by the word line driver operating at the first voltage VDDM, whereas the word line signal WL in the true dual-rail storage power supply scheme rises until it reaches the second voltage VDD, because the word line driver is configured to operate at the second voltage VDD. Thus, the rise time of the word line signal WL of the true dual-rail storage power supply scheme at time T4 is significantly later than that of the dual-rail storage power supply scheme with interface level shifters and the hybrid dual-rail storage power supply scheme, as shown in the time history diagram.The width of the word line signal WL is also much larger than that of the other two power supply schemes in order to reserve a longer time for discharging the bit line BL or its complementary signal BLB.

[0025] In the dual-rail memory power supply scheme with interface level shifters, the bit line BL and its complementary signal BLB are pre-charged to the first voltage VDDM, while in the hybrid dual-rail memory power supply scheme and the true dual-rail memory power supply scheme, the bit line BL and its complementary signal BLB are pre-charged to the second voltage VDD. When the rise of the word line WL begins after the read operation, the bit line BL or its complementary signal BLB is slightly discharged, and as can be seen in the time-history diagram, the voltages on the bit line BL and its complementary signal BLB begin to dissipate.A bit line differential voltage is generated between the bit line BL and its complementary signal BLB, and this bit line differential voltage can then be read and amplified by a read amplifier connected to the pair of bit lines, as explained in the preceding sections, and the data read by the read amplifier is then output from the memory array.

[0026] In the dual-rail memory power supply scheme with interface level shifters, the bit line differential voltage is successfully read at time T5 using the read amplifier. The read operation in the hybrid dual-rail memory power supply scheme terminates at time T6, and slightly later in the dual-rail memory power supply scheme with interface level shifters. In contrast, the read operation in the true dual-rail memory power supply scheme terminates at time T7, which is much slower than the read speed of both the dual-rail memory power supply scheme with interface level shifters and the hybrid dual-rail memory power supply scheme.As can be seen from the time-series graph, the read speed of the hybrid dual-rail storage power supply scheme lies approximately between the read speed of the dual-rail storage power supply scheme with interface level shifters and the true dual-rail storage power supply scheme. In particular, the read speed performance of the hybrid dual-rail storage power supply scheme is relatively closer to that of the dual-rail storage power supply scheme with interface level shifters.

[0027] As the peripheral voltage (i.e., the second voltage VDD) continues to drop, the gap between the memory array voltage (i.e., the first voltage VDDM) and the peripheral voltage increases. Such a gap can lead to malfunctions during read operations, such as read / write errors. To address this problem, various auxiliary mechanisms have been developed to assist individual memory cells in functioning correctly when read and write operations are performed on those cells. In some embodiments, methods for implementing a suppressed word line voltage can be integrated into memory macro 100. Fig. Figure 6 is a block diagram that conceptually illustrates a hybrid dual-rail storage power supply scheme with a suppressed word line voltage for a storage macro 600 according to an exemplary embodiment of the present invention. The storage macro 600 is the same as the storage macro 100, except for a word line driver circuit 640. In the word line driver circuit 640, a word line suppression control circuit 6406, a word line suppression circuit 6408, and a word line suppression circuit 6410 are used to adjust a word line voltage, controlled by the word line drivers 1402 and 1404, from the first voltage VDDM to a suppressed voltage level that is lower than the first voltage VDDM. In some embodiments, the suppressed voltage is lower than the first voltage VDDM and higher than the second voltage VDD.

[0028] Fig. Figure 7 is a block diagram showing the word line suppression circuit according to one embodiment of the present invention. As shown in Fig. As shown in Figure 7, the word line suppression circuit 6408 is a PMOS device having a gate terminal connected to the word line suppression control circuit 6406 and a source terminal connected to the word line. In some embodiments, the word line suppression circuit 6408 can be implemented with an NMOS device. Fig. Figure 8 is a time-history diagram showing waveforms of the hybrid double-rail storage power supply scheme with a suppressed word line voltage during a read operation.

[0029] Fig. Figure 9 is a diagram showing measurement curves of the hybrid power supply scheme and existing power supply schemes with respect to speed and power consumption behavior under different configurations of the second voltage VDD. Fig. Figure 9 shows the X-axis as a quantized comparison result for the dual-rail storage power supply scheme with interface level shifters, and the Y-axis as the second voltage VDD. The upper curve D of Fig. Figure 9 refers to the read latency of the true dual-rail storage power supply scheme. As shown in the diagram, the read latency of the true dual-rail storage power supply scheme is essentially the same as that of the dual-rail storage power supply scheme with interface level shifters when the second voltage, VDD, is equal to the first voltage, VDDM. However, when the second voltage, VDD, reaches 0.8 VDDM, the read latency of the true dual-rail storage power supply scheme increases to approximately 180% of the read latency of the dual-rail storage power supply scheme with interface level shifters.

[0030] Experts will be aware that fluctuations in the first voltage VDDM and / or the second voltage VDD can occur due to several non-ideal factors, such as ohmic voltage drop, the thermal effect, or process variations. In practice, the first voltage VDDM and the second voltage VDD can each have a substantial voltage value with a range of variation of, for example, ±10%. However, this is not a limitation of the present invention.

[0031] Below the upper curve D, viewed from top to bottom, curve A refers to Fig.Curve 9 relates to the read latency of the hybrid dual-rail storage power supply scheme, curve B relates to the standby current of the hybrid dual-rail storage power supply scheme, curve C relates to the active current of the hybrid dual-rail storage power supply scheme, curve F relates to the active current of the true dual-rail storage power supply scheme, and curve E relates to the standby current of the true dual-rail storage power supply scheme. As can be seen from the measurement curves, the hybrid dual-rail storage power supply scheme has better performance in terms of speed and power consumption than the true dual-rail storage power supply scheme.

[0032] In some embodiments, the hybrid dual-rail memory power supply scheme can be advantageously used for many different memory arrangements and types, such as a single-port SRAM, a two-port SRAM, a dual-port SRAM, and a multi-port SRAM. The bit cells in the memory array of the memory macro can be 8-T bit cells (8 T: 8 transistors). However, those skilled in the art will recognize, in light of the principles of the present invention, that numerous modifications, within the scope of protection of the present invention, can be made to the described embodiments.

[0033] Some embodiments of the present invention provide a dual-rail memory capable of operating at a first voltage and a second voltage, and the dual-rail memory comprises: a memory array operating at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to carry an input data signal or an output data signal; and a control circuit configured to generate control signals for the memory array, the word line driver circuit, and the data path, wherein the data path and the control circuit are configured to operate at both the first and second voltages.

[0034] In some embodiments of the present invention, the first voltage is higher than the second voltage.

[0035] In some embodiments of the present invention, the data path comprises a write circuit for transmitting the input data signal, a read circuit for transmitting the output data signal, and a bit line preloader.

[0036] In some embodiments of the present invention, the write circuit comprises latched data, a write driver and a write column multiplexer.

[0037] In some embodiments of the present invention, the latched data are configured to latch the input data signal that is referenced for the second voltage.

[0038] In some embodiments of the present invention, the write driver is configured to control the latched input data, wherein a pre-stage of the write driver is configured to operate at the second voltage, and a post-stage of the write driver is configured to operate at the first voltage.

[0039] In some embodiments of the present invention, the bit line preloader preloads a bit line and a complementary bit line corresponding to a bit cell of the memory array to the second voltage.

[0040] In some embodiments of the present invention, the reading circuit comprises a read column multiplexer, a read amplifier and an output driver.

[0041] In some embodiments of the present invention, the reading amplifier is configured to operate at the second voltage.

[0042] In some embodiments of the present invention, the output driver is configured to operate at the second voltage.

[0043] Some embodiments of the present invention provide a memory macro comprising: a plurality of memory arrays configured to operate at a first voltage; a read path configured to operate at a second voltage; a write path configured to operate at both the first and second voltages; a word line driver circuit configured to drive a plurality of word lines corresponding to the plurality of memory arrays to a third voltage; and a control circuit configured to generate control signals for the memory arrays, the read path, the write path, and the word line drivers, wherein the read path is configured to operate at the second voltage, and the write path and the control circuit are configured to operate at both the first and second voltages.

[0044] In some embodiments of the present invention, the word line driver circuit comprises a plurality of word lines and a word line suppression circuit.

[0045] In some embodiments of the present invention, the word line suppression circuit is configured to push a control voltage level of the plurality of word line drivers to the third voltage, wherein the third voltage is lower than the first voltage.

[0046] In some embodiments of the present invention, the third voltage is higher than the second voltage.

[0047] In some embodiments of the present invention, the control circuit comprises an address memory, a word line column decoder, a pulse generator, a read / write control element, and a trace path.

[0048] In some embodiments of the present invention, the address memory, the word line column decoder, the pulse generator and the read / write control element are configured to operate at the first voltage.

[0049] In some embodiments of the present invention, the tracking path comprises a tracking array and a transmission gate, wherein the tracking array is configured to operate at the first voltage and the transmission gate is configured to operate at the second voltage.

[0050] Some embodiments of the present invention provide a hybrid power supply method in which a dual-rail storage device is configured to operate at a first voltage and a second voltage, wherein a storage array of the dual-rail storage device can operate at the first voltage, the method comprising the following steps: controlling a word line of the storage array to the first voltage and reading output data stored in the storage array via a read circuit that can operate at the second voltage.

[0051] In some embodiments of the present invention, the first voltage is higher than the second voltage.

[0052] In some embodiments of the present invention, the method further comprises writing input data into the storage array via a write circuit that can operate at both the first and the second voltage.

Claims

[1] A double-rail storage device that can operate at a first voltage (VDDM) and a second voltage (VDD), wherein the double-rail storage device has the following features: a memory array (150) that operates at the first voltage (VDDM); a word line driver circuit (140) configured to drive a word line of the memory array (150) to the first voltage (VDDM); a data path (110) configured to carry an input data signal or an output data signal; and a control circuit (120) configured to generate control signals for the memory array (150), the word line driver circuit (140) and the data path (110), wherein the data path (110) and the control circuit (120) are configured to operate at both the first voltage (VDDM) and the second voltage (VDD), wherein part of the data path (110) and part of the control circuit (120) are configured to operate at the first voltage (VDDM), and the remaining part of the data path (110) and the remaining part of the control circuit (120) are configured to operate at the second voltage (VDD). [2] Double rail storage according to claim 1, wherein the first voltage (VDDM) is higher than the second voltage (VDD). [3] Dual-rail memory according to claim 1 or 2, wherein the data path (110) comprises a write circuit for transferring the input data signal, a read circuit for transferring the output data signal and a bit line preloader (1102, 1104). [4] Dual-rail memory according to claim 3, wherein the write circuit comprises latched data, a write driver (1108, 1120) and a write column multiplexer (1106, 1118). [5] Dual rail memory according to claim 4, wherein the latched data are configured to latch the input data signal which is referenced for the second voltage (VDD). [6] Dual-rail memory according to claim 4 or 5, wherein the write driver (1108, 1120) is configured to control the latched input data, wherein a pre-stage of the write driver (1108, 1120) is configured to operate at the second voltage (VDD), and a post-stage of the write driver (1108, 1120) is configured to operate at the first voltage (VDDM). [7] Dual-rail memory according to any one of claims 3 to 6, wherein the bit line preloader (1102, 1104) preloads a bit line and a complementary bit line corresponding to a bit cell (1502-1508) of the memory array (150) to the second voltage (VDD). [8] Dual-rail memory according to any one of claims 3 to 7, wherein the read circuit comprises a read column multiplexer (1112, 1124), a read amplifier (1114, 1126) and an output driver (1116, 1128). [9] Dual-rail storage according to claim 8, wherein the read amplifier (1114, 1126) is configured to operate at the second voltage (VDD). [10] Dual-rail storage according to claim 8 or 9, wherein the output driver (1116, 1128) is configured to operate at the second voltage (VDD). [11] Storage macro with: a large number of memory arrays (150) configured to operate at a first voltage (VDDM); a read path configured to operate at a second voltage (VDD); a write path configured to operate at a second voltage (VDD); a word line driver circuit (140) configured to drive a plurality of word lines corresponding to the plurality of memory arrays (150) to a third voltage; and a control circuit (120) configured to generate control signals for the memory arrays (150), the read path, the write path and the word line drivers (1404), wherein the read path is configured to operate at the second voltage (VDD), and the write path and control circuit (120) are configured to operate at both the first and second voltages (VDD), wherein part of the write path (110) and part of the control circuit (120) are configured to operate at the first voltage (VDDM), and the remaining part of the write path (110) and the remaining part of the control circuit (120) are configured to operate at the second voltage (VDD). [12] Memory macro according to claim 11, wherein the word line driver circuit (1404) comprises a plurality of word lines and a word line suppression circuit (6410). [13] Memory macro according to claim 12, wherein the word line suppression circuit (6410) is configured to push a control voltage level of the plurality of word line drivers (1404) to the third voltage, and the third voltage is lower than the first voltage (VDDM). [14] Memory macro according to claim 13, wherein the third voltage is higher than the second voltage (VDD). [15] Memory macro according to any one of claims 11 to 14, wherein the control circuit (120) comprises an address memory (1202), a word line column decoder (1204), a pulse generator (1206), a read / write control element (1208) and a trace path (1210). [16] Memory macro according to claim 15, wherein the address memory (1202), the word line column decoder (1204), the pulse generator (1206) and the read / write control element (1208) are configured to operate at the first voltage (VDDM). [17] Memory macro according to claim 16, wherein the tracking path comprises a tracking array and a transfer gate, and the tracking array is configured to operate at the first voltage (VDDM), and the transfer gate is configured to operate at the second voltage (VDD). [18] Hybrid power supply method for configuring a double-rail storage system according to any one of claims 1 to 10 to operate at a first voltage (VDDM) and a second voltage (VDD), wherein a storage array (150) of the double-rail storage system can operate at the first voltage (VDDM), the method comprising the following steps: Controlling a word line of the memory array (150) to the first voltage (VDDM) and Reading output data stored in the memory array (150) via a read circuit that can operate at the second voltage (VDD). [19] Method according to claim 18, wherein the first voltage (VDDM) is higher than the second voltage (VDD). [20] Method according to claim 18 or 19, further comprising writing input data to the storage array (150) via a write circuit which can operate at both the first and the second voltage (VDD).

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