Power converter with dead-time variation for diffusing distortion

Abstract

Power converter, which includes the following: a DC connection (16) configured to receive a DC supply voltage; a phase branch (20) comprising an upper switching device (26) and a lower switching device (27) coupled via the DC connection, wherein a node (28) between the upper and lower switching devices is configured to be coupled to a load; a gate driver coupled to the phase branch, which activates the upper switching device according to an upper gate signal and activates the lower switching device according to a lower gate signal; and a controller (65) which 1) compares a PWM carrier signal with a commanded duty cycle to generate an initial upper and lower gate drive signal, 2) generates a first paired set of dead-time inserted signals as modifications of the original upper and lower gate signal; 3) generates a second paired set of dead-time inserted signals as a modification of the original upper and lower gate signal, wherein the first and second paired sets of dead-time inserted signals correspond to a different distortion of a current flowing in the load; and 4) switches among the paired sets to activate the switching devices.

Description

GENERAL STATE OF THE ART

[0001] The present invention relates generally to power converters including inverters for an electric drive system of an electrified vehicle, and more particularly to selectively inserting a dead time for controlling switching devices to avoid shoot-through without introducing any significant distortion into the output of the converter.

[0002] Electric vehicles, such as hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), and battery electric vehicles (BEVs), use inverter-driven electric machines to provide traction torque and regenerative braking torque. A typical electric drive system includes a DC power source (such as a battery pack or fuel cell) coupled through contactor switches to a variable voltage converter (VVC) to regulate a main bus voltage across a main DC link capacitor. An inverter is connected between the main DC link buses and a traction motor to convert the DC power to AC power, which is coupled to the motor windings to propel the vehicle.A second inverter may also be connected between the main bus and (if present) a generator to provide an additional power flow path from a prime mover, typically an internal combustion engine, to the DC link.

[0003] The inverters contain transistor switching devices (such as IGBTs (Insulated Gate Bypolar Transistors)) connected in a bridge configuration with multiple phase legs. A typical configuration includes a three-phase motor driven by a three-phase inverter. An electronic controller turns the switches on and off to invert a DC voltage from the bus to an AC voltage applied to the motor or to rectify an AC voltage from the generator to a DC voltage on the bus. In either case, the inverters are controlled in response to various sensed conditions, including the rotational position of the electric machine and the current flow in each of the phases.

[0004] The motor inverter can preferably pulse-width modulate the DC link voltage to provide an approximate sinusoidal current output to drive the motor at the desired speed and torque. Pulse-width modulation (PWM) control signals are applied to the gates of the IGBTs to turn them on and off as needed, so that the resulting current corresponds to the desired current.

[0005] Because each phase leg of the inverter has a pair of upper and lower switching devices connected across the DC link, it is important that both devices are not conducting (i.e., turned on) at the same time. Otherwise, the resulting phase leg "shoot-through" could damage the switching devices. A short time interval during which both the upper and lower switching devices of a phase leg are turned off, known as dead time, is typically used in conjunction with PWM control of inverters to prevent shoot-through. In typical PWM control, a comparison of a PWM duty cycle with a PWM carrier signal identifies a transition time at which the output node of a phase leg switches from connection to one side of the DC link (i.e., positive or negative) to the other.Without dead-time insertion, one gate signal for the phase leg would change from on to off at the same time that the other gate signal would change from off to on. The most common form of dead-time insertion adds dead time on either side of the transition time, for example, causing the "on" gate signal to go "off" before the transition time and briefly delaying the "off" gate signal's transition to the "on" state. However, inserting dead time has the effect of distorting the output waveform delivered to the load and introducing control delays.

[0006] Efforts to avoid or reduce distortion by modifying dead-time insertion have involved other drawbacks. For example, compensation circuits have been added to the switching devices in the phase legs, resulting in higher costs and increased manufacturing complexity. Other efforts have aimed at modifying the inserted dead times according to the direction of current flow within a particular phase leg, which has also resulted in additional costs and increased complexity.

[0007] In ZHAO, A. et al.: One-step digital dead-time correction for DC-DC converters. In: 2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010, pp. 132-137, a power converter is described which has a DC connection configured to receive a DC supply voltage and a phase leg comprising an upper switching device and a lower switching device coupled across the DC connection. A node is configured to be coupled to a load between the upper and lower switching devices. In addition, a gate driver is provided which is coupled to the phase leg and activates the upper switching device according to an upper gate signal and activates the lower switching device according to a lower gate signal.

[0008] US 6 477 067 B1 relates to a motor control system and a method and device for compensating switchgear drops and switchgear dynamics in converter systems BRIEF DESCRIPTION OF THE INVENTION

[0009] In one aspect of the invention, a power converter includes a DC connection configured to receive a DC supply voltage. A phase leg including an upper switching device and a lower switching device is coupled across the DC connection. A junction between the upper and lower switching devices is configured to be coupled to a load. A gate driver is coupled to the phase leg, which activates the upper switching device according to an upper gate signal and activates the lower switching device according to a lower gate signal in response to a pulse width modulation (PWM) control signal having a PWM frequency. The gate driver switches among a plurality of alternating paired sets of dead-time-inserted signals for the upper and lower gate signals. Each paired set of dead-time-inserted signals corresponds to a different distortion of a current flowing in the load. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram showing a powertrain of an electrified vehicle according to an embodiment of the present invention. Fig. Figure 2 is a waveform diagram showing the generation of original gate signals and gate signals with an inserted dead time. Fig. Figure 3 is a waveform diagram showing an alternative technique for inserting dead time. Fig. Figure 4 is a block diagram showing the generation of multiple alternating pairs of sets of dead-time inserted gate signals that are switched by a multiplexer to select a gate drive signal for application to the gate drivers of a phase branch. Fig. Figure 5 is a flow diagram showing a preferred method of the invention. Fig. Figure 6 is a schematic block diagram showing a circuit for selecting alternating pairs of gate signals in greater detail. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0010] Fig. 1 shows a hybrid electric vehicle 10 as one type of vehicle for implementing the reconfigured dead time insertion of the present invention.

[0011] Vehicle wheels 11 may be driven by an internal combustion engine 12 and / or by a traction motor 13 via a transmission 14. To provide electric propulsion, the motor 13 may be driven via an inverter 15, which receives a DC link voltage at a DC link capacitor 16. The DC link voltage may result from a conversion of DC power from a battery pack 17 by a converter 18, as known in the art.

[0012] The inverter 15 includes phase legs 20, 21, and 22 coupled to motor phase windings 23, 24, and 25. The phase leg 20 has an upper switching device 26 and a lower switching device 27 connected in series across the DC connection 16, providing a junction 28 between devices 26 and 27 that is connected to the winding 23 of the motor 13. Similarly, the phase leg 21 has an upper switching device 30 and a lower switching device 31, while the phase leg 22 has an upper switching device 32 and a lower switching device 33. Nodes 34 and 35 are coupled to the motor windings 24 and 25, respectively.

[0013] The switching devices may consist of IGBTs, anti-parallel diodes, wide bandgap FETs, or other devices. Each of the upper and lower switching devices has a respective gate terminal coupled to drivers 37 in a controller 38. Current sensors 40 measure the current flow through each phase winding. Measured current quantities are provided from sensors 40 to logic circuits 41 in the controller 38 for use in determining PWM switching signals to be applied by the drivers 37 to the switching devices. As is known in the art, the measured current may be compared to a desired motor current, as determined according to a torque demand 42, which may be derived from an operator input such as an accelerator pedal, so that the operator can control the vehicle speed.Thus, current feedback determines a PWM duty cycle within the logic circuits 41, which is then used to generate the timing of PWM switching signals for the phase leg switching devices.

[0014] Fig. Figure 2 shows a PWM carrier signal 45 generated as a triangular waveform with a high frequency (e.g., approximately 5 kHz) compared to the motor's rotational frequency. Using a known PWM method for generating gate drive switching signals based on current control, a PWM duty cycle signal 46 is generated in response to any error between the detected current and a target current. The duty cycle 46 is compared with the PWM carrier signal 45 to determine the Fig. 2. A signal 47 is an original gate signal Guo of an upper device, which has a low logic level when the PWM carrier signal 45 is greater than the duty cycle signal 46, and which has a high logic level when the duty cycle signal 46 is greater than the PWM carrier signal 45. A signal 48 shows an original gate signal G LO a lower device, which is the logical inverse of the Guo signal 47.

[0015] To avoid shoot-through, which could occur when using the original gate signals 47 and 48, dead-time insertion can be performed as follows. A waveform 50 is obtained by inserting a fixed time delay into the signal 47. The fixed time delay represents a sufficiently long dead-time insertion that avoids simultaneous activation of both upper and lower switching devices, which could occur as a result of noise or propagation delay differences between the upper and lower gate signals (typically with a duration of a few microseconds). A dead-time-inserted gate signal (G UDI) 51 of an upper switching device is obtained by forming a logical AND from the original gate signal 47 and the delayed gate signal 50, as shown. A signal 52 shows a time-delayed version of a lower gate signal 48 using the same fixed delay. A dead-time-inserted gate signal (G LDI ) 53 of a lower switching device is generated as a logical AND from the original gate signal 48 of a lower device and the delayed signal 52. In the prior art, dead-time-inserted upper and lower gate signals 51 and 53 (G UDI and G LDI ) were used to control the phase branch switching devices under all conditions, ie with a dead time 54 inserted at each switching event.

[0016] Fig. Figure 3 illustrates an alternative method for generating the dead-time inserted signals that does not require signal delay blocks as described for the Fig. 2 would be required. Instead of using explicit signal delays, offset duty cycles 56 and 57 are obtained by adding and subtracting a fixed offset (denoted by Δ) to and from the duty cycle signal 46, and the offset values ​​are used when generating the gate drive signals for comparison with the PWM carrier. Thus, the original drive signals Guo and G LOfor the upper and lower gates in the usual way based on comparing the duty cycle 46 with the PWM carrier 45, which provides transitions 58 and 59 for the original signals. To generate the dead-time-inserted signals, the PWM carrier signal 45 is compared with the offset duty cycles as follows. To generate the dead-time-inserted drive signal for the lower gate, the PWM carrier 45 is compared with the positive offset duty cycle 56 (i.e., commanded duty cycle + Δ) and the result of the comparison is inverted. Thus, the drive signal for the lower gate with the dead-time insertion G LDI equal to an inverted drive signal obtained by using the positive offset duty cycle 56 GUO+¯ for the upper gate. The signal GUO+¯ for the lower gate has transitions 60 and 61 corresponding to the crossings of the PWM carrier 45 with the positive offset duty cycle 56. To generate a dead-time inserted drive signal G UDI For the upper gate, the negative offset duty cycle 57 is used. Transitions 62 and 63 are shown for this signal, which is also referred to as Guo- because it is generated using the negative offset. Applying offsets to the duty cycle thus results in changes in transition times for the gate drive signals, which provide the deadtime intervals.

[0017] Concurrently filed, co-pending U.S. application Ser. No. 14 / 601,282, filed January 21, 2015, which is incorporated herein by reference in its entirety, discloses the selective insertion of dead-time signals, which depends on the direction and magnitude of current flow in a phase leg. For sufficiently positive phase current, an original unmodified gate signal is used for the upper switching device, while a dead-time-inserted gate signal is used for the lower switching device. For sufficiently negative phase current, an original unmodified gate signal is used for the lower switching device, while a dead-time-inserted gate signal is used for the upper switching device. For an intermediate current, both switches use a dead-time-inserted gate signal.An object of the present invention is to avoid the need to compare the measured current with the necessary threshold values ​​to indicate whether the current is sufficiently positive or negative.

[0018] The current distortion caused by dead-time insertion depends on the specific extent to which the final duty cycle used to drive the switching device deviates from the original duty cycle. Different processes for defining the dead time can produce different deviations in the final duty cycle from the original duty cycle. If G UO and GUO+¯ in Fig. 3 are used for the upper device and the lower device, respectively, there is no current distortion for the current flowing out of the node between the upper and lower devices because this current direction is controlled by the upper device and the upper device receives the original gate signal Guo. This combination of gate signals leads to current distortion for the current flowing into the node between the upper and lower devices because this current direction is controlled by the lower device and the lower device does not receive the original gate signal G. LO receives. If analogous Guo and G LO in Fig. 3 are used for the upper device and the lower device, respectively, there is no current distortion for the current flowing into the node between the upper and lower devices, but leads to current distortion for the current flowing out of this node. Instead of selecting the signal combinations for the upper and lower gates based on the current direction, the invention selects a specific pattern of gate signal combinations (i.e., reverses it) so that the distortion caused by an incorrect selection of the gate signal combinations with respect to the current direction can be dispersed. As a result, compared to the case where the conventional dead-time insertion and gate signal combination of Fig. 2 is used, lower current distortion is achieved.

[0019] As in Fig. As shown in Figure 4, a PWM controller provides 65 original gate drive signals Guo and G LOto dead-time insertion blocks 66-68, which provide respective paired sets of dead-time inserted signals for the upper and lower gate signals to respective inputs of a multiplexer 69. Each paired set of dead-time inserted signals corresponds to a different distortion of the current flowing in the load. For example, a first paired set of gate signals from the first insertion block 66 may consist of changing the duty cycle of the upper switching device without any deviation in the duty cycle of the lower switching device. A second paired set of gate signals from the second insertion block 67 may consist of changing the duty cycle of the lower switching device without any deviation in the duty cycle of the upper switching device.In this case, a third paired set of gate signals from the third insertion block 68 may consist of changing the duty cycles of both the upper and lower switching devices. Paired sets of dead-time inserted gate signals may alternatively be implemented using different delay times. Fig. 2, different duty cycle offsets in Fig. 3 or using other variations in the dead time insertion timing using different PWM carrier frequencies, different carrier signals (e.g. sawtooth instead of triangular wave) or different sizes for the duty cycle offset Δ in Fig. 3 are generated. The multiplexer 69 switches among the paired sets of dead-time inserted signals for the upper and lower gate signals according to a pattern that spreads the distortion.

[0020] A preferred method is in Fig. 6, where a pulse width modulation signal is sampled in step 75. By comparing the PWM carrier signal with the duty cycle command, with the duty cycle command with a positive offset (+Δ), and with the duty cycle command with a negative offset (-Δ), two or more alternating paired sets of dead-time-inserted gate signals are generated for the upper and lower switching devices. The switching of the paired sets is performed by obtaining the instantaneous value of a gate signal selection pattern in step 77. The selection pattern can be any pattern that provides sufficient distortion spread. Preferred patterns include a repeating pattern or a random pattern. Repeating patterns include alternating (e.g., "01010101...") or repeating blocks (e.g., "110100110100110100..."). A random pattern includes a quasi-random pattern based on a random number generator, for example.The selection pattern preferentially switches between the available paired sets of dead-time-inserted signals at the PWM carrier frequency. The selected paired set is designated as gate signals Gu and G in step 78. L to the gate drivers. In step 79, a check is performed to determine whether motor operation has ended. If not, a return is made to step 75 to continue sampling the modulation signal; otherwise, the process stops.

[0021] Fig. Figure 6 shows a logic circuit 80 for switching the insertion of alternating pairs of dead times according to a preferred embodiment of the invention. The logic circuit 80 may include dedicated electronic circuit components, as shown, or may be implemented using a programmable controller such as a microcontroller. A comparator 81 has a non-inverting input that receives the duty cycle command signal (e.g., duty cycle signal 46 in Fig.2). The comparator 81 has an inverting input that receives the PWM carrier signal. In response to the comparison, the comparator 81 outputs an original drive signal Guo for the upper gate to a first input of a multiplexer 82. The first input is a select-one input that passes through the multiplexer 82 when a signal with a high logic level (binary "1") is present at a select input (SEL) of the multiplexer 82. In addition, the output of the comparator 81 is inverted by an inverter 83 to produce an original drive signal G LO of the lower gate to a first (one-selected) input of a multiplexer 84.

[0022] Another pair of comparators 85 and 86 is provided for generating dead-time inserted signals as follows. Comparator 85 receives a duty cycle with negative offset (duty cycle -Δ) at its non-inverting input and receives the PWM carrier signal at its inverting input. The output of comparator 85 provides an upper dead-time inserted gate signal Guo- to a zero-selected input of multiplexer 82. Comparator 86 receives a duty cycle with positive offset (duty cycle +Δ) at its non-inverting input and receives the PWM carrier signal at its inverting input. The output of comparator 86 is inverted by an inverter 87 to produce a lower dead-time inserted gate signal GUO+¯ to a zero-selected input of the multiplexer 84.

[0023] A D-type flip-flop 88 receives a switching pattern at its D input. A clock input receives a clock signal (for example, at a frequency equal to the PWM carrier signal) to alternate the Q and non-Q outputs of flip-flop 88 such that the switching pattern and its inverse are coupled to the SEL inputs of multiplexers 82 and 84, respectively. When the switching pattern has a high logic level signal, multiplexer 82 selects the original upper gate drive signal Guo at the first input of multiplexer 82 for coupling to the input of an amplifier 91 in a carrier circuit 90. Simultaneously, the inverted output (non-Q) from flip-flop 88 supplied to multiplexer 84 selects the dead-time-inserted drive signal GUO+¯ of the lower gate at the zero input of the multiplexer 84 for coupling to the input of an amplifier 93 in the driver circuit 90. When the switching pattern has a signal with a low logic level, the alternating pair of dead-time signals (e.g., G LO and G UO -) and coupled to the switching devices 92 and 94.

[0024] In the present invention, the paired sets of dead-time-inserted signals correspond to a different distortion of the current flowing in the load (motor phase windings). In addition to the variation in distortion resulting from alternating the selected mode for forming the dead-time-inserted gate signals, the invention further reduces distortion whenever the selected set of gate signals happens to use the original (i.e., unmodified) gate signal for a switching device that then carries a large current (as further explained in co-pending U.S. application Ser. No. 83482739).

Claims

[1] Power converter comprising: a DC connection (16) configured to receive a DC supply voltage; a phase branch (20) comprising an upper switching device (26) and a lower switching device (27) coupled via the DC connection, wherein a node (28) between the upper and lower switching devices is configured to be coupled to a load; a gate driver coupled to the phase branch, which activates the upper switching device according to an upper gate signal and activates the lower switching device according to a lower gate signal; and a controller (65) that 1) compares a PWM carrier signal with a commanded duty cycle to generate an original upper and lower gate drive signal, 2) generates a first paired set of dead-time inserted signals as modifications of the original upper and lower gate signals; 3) generates a second paired set of dead-time inserted signals as modifications of the original upper and lower gate signals, the first and second paired sets of dead-time inserted signals corresponding to a different distortion of a current flowing in the load; and 4) switches among the paired sets to activate the switching devices. [2] The power converter of claim 1, wherein the first paired set of deadtime-inserted signals consists of 1) a modification of the original one of the upper and lower gate signals to add deadtime, and 2) an unmodified original of the other of the upper and lower gate signals. [3] The power converter of claim 2, wherein a second paired set of deadtime-inserted signals consists of 1) an unmodified original of one of the upper and lower gate signals and 2) a modification of the original of the other of the upper and lower gate signals to add deadtime. [4] The power converter of claim 1, wherein switching comprises selecting the paired sets according to a predetermined repeating pattern.

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