System and procedure for a fault protection circuit

Abstract

Fault protection system (108, 109a-e, 164), which includes the following: a first power supply connection; a second power supply connection; a fault circuit (116, 118) configured to receive a power supply signal; and a power supply circuit connected to the fault circuit (116, 118), the first power supply connection and the second power supply connection, wherein the power supply circuit is set up, to supply the power supply signal from the first power supply connection during a first operating mode, and during a second operating mode, the power supply signal is to be supplied from the second power supply terminal, wherein the first power supply terminal is configured to be connected to a regulated system supply signal (VDD) generated by a first power source, and the second power supply terminal is configured to be connected to an operating mode control signal (F) generated by the first power source. MC ) to be connected.

Description

TECHNICAL AREA

[0001] The present invention relates generally to an electronic circuit and, in specific embodiments, to a system and a method for a protective circuit. BACKGROUND

[0002] A semiconductor power device is a semiconductor component that can be used as a switch or rectifier in power electronics. For example, a switched-mode power supply (SMPS) often contains one or more semiconductor power switches as key elements for switching operations. Semiconductor power devices, which can be referred to as power components, are often designed as integrated circuits (ICs) to form power ICs. The applications of power devices are numerous, and advances in technology have further increased the number of possible applications, particularly in the field of power ICs.

[0003] Power devices are most often implemented as power switches to operate in either a conduction mode (ON) or a non-conduction mode (OFF). In such applications, power switches are often optimized for either the conduction or the non-conduction mode, while operation as a power transistor in linear mode is limited. Power devices are frequently used to conduct or block a high voltage intended to supply a load.

[0004] Some common power devices are power diodes, thyristors, power metal-oxide-semiconductor field-effect transistors (MOSFETs), and insulated-gate bipolar transistors (IGBTs). Power diodes and power MOSFETs operate on similar mechanisms to, for example, CMOS diodes and low-power MOSFETs, but are capable of conducting large currents and are typically able to carry or block a high reverse bias in the off (non-conducting) state.

[0005] Because of the increased current or voltage generally associated with power devices, a power device is often structurally designed to handle the higher current density, power dissipation, or breakdown voltage. For example, power devices are often built using a vertical structure and have a current-carrying capacity proportional to the device area and a voltage-blocking capacity proportional to the height or thickness of the device in the substrate. In vertical power devices, compared to lateral non-power devices, one of the device leads is located at the bottom of the semiconductor die.

[0006] US Patent 4,617,473 A discloses a fault protection system in which a power supply circuit delivers a power supply signal to a first terminal in a first operating mode and to a second terminal in a second operating mode.

[0007] DE 10 2013 001 109 A1 discloses a method for monitoring the functionality of a power switch, in which a gate signal of the switch is evaluated.

[0008] DE 10 2012 212 890 A1 discloses a further switch with a monitoring circuit.

[0009] Power components often incorporate protective mechanisms to prevent overcurrents or excessive temperatures. In certain applications, these protective mechanisms include intelligent elements, such as control and protection circuits, for monitoring and controlling the operation of one or more power components, such as circuit breakers. These intelligent elements deactivate the power components when an overcurrent or excessive temperature occurs. In some situations, existing protective mechanisms may fail to protect switching devices. Improved protection mechanisms for switching devices are desirable in various applications. One objective of this application is to provide such possibilities. SUMMARY

[0010] A fault protection system according to claim 1, a method according to claim 16, and a power supply system according to claim 21 are provided. The dependent claims define further embodiments.

[0011] According to one embodiment, a fault protection system comprises a first power supply terminal, a second power supply terminal, a fault circuit configured to receive a power supply signal, and a power supply circuit connected to the fault circuit, the first power supply terminal, and the second power supply terminal. The power supply circuit is configured to supply the power supply signal from the first power supply terminal during a first operating mode (hereinafter referred to as the first operating mode or first mode) and to supply the power supply signal from the second power supply terminal during a second operating mode (hereinafter referred to as the second operating mode or second mode).The first power supply connection is set up to be connected to a regulated system supply signal generated by a first power source, and the second power supply connection is set up to be connected to an operating mode control signal generated by the first power source. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions in conjunction with the accompanying drawings. These show: Fig. 1 a system block diagram of an embodiment of a power switching system; Fig. 2a and Fig. 2b a system block diagram of an embodiment of a protection system or a waveform diagram of an embodiment of a method for operating the protection system; Fig. 3a, Fig. 3b, Fig. 3c, Fig. 3D, and Fig. 3e. Schematic diagrams of embodiments of subsystems; Fig. 4a, Fig. 4b, and Fig. 4c Schematic diagrams of exemplary components of embodiments of power switching systems; Fig. 5a and Fig. 5b Schematic diagrams of another embodiment of a power switching system; Fig. 6 a schematic diagram of another embodiment of a power switching system; Fig. 7 a system diagram of an embodiment of a power switching system; and Fig. 8 a block diagram of an embodiment of a method for operating a fault protection system.

[0013] The corresponding reference numerals and symbols in the various figures generally refer to corresponding parts, unless otherwise indicated. The figures are shown to clarify the relevant aspects of the embodiments and are not necessarily to scale. DETAILED DESCRIPTION OF ILLUSTRATIVE EXECUTION FORMS

[0014] The manufacture and application of various embodiments are discussed in more detail below. It should be understood, however, that the various embodiments described herein are applicable in a wide variety of specific contexts. The specific embodiments discussed merely represent specific ways of manufacturing and applying various embodiments and are not to be considered restrictive.

[0015] The description refers to various embodiments in a specific context, namely fault protection systems, and in particular fault protection and fault systems for circuit breakers. Some of the various embodiments described herein include fault protection and fault systems for parallel circuit breakers, fault counter and repeater circuits for circuit breakers, automotive systems with circuit breakers, and power supply fault operating circuits for circuit breakers. In further embodiments, aspects can also be used in other applications, including any type of fault protection or fault system implemented in any known manner.

[0016] In various applications, such as automotive systems, circuit breakers can be used to connect a power supply to outputs, for example, to power various loads with different power requirements. During operation, damage to a circuit breaker can be prevented by a fault circuit configured to trip the breaker when a fault condition is detected. A fault signal can be generated based on a detected fault condition, such as an overcurrent or excessive temperature within the circuit breaker. This fault signal is fed to a fault and retry counter connected to the circuit breaker. The fault and retry counter is configured to deactivate the circuit breaker for an extended period if fault conditions recur.In some applications, the system may have a fault in a main power supply.

[0017] According to various embodiments, a low-power or fault mode is activated when a fault occurs in a regulated main power supply, such as a regulated main power supply (VDD). During a low-power or fault mode, the low-power mode control line or an unregulated supply voltage can be used to power a fault protection system to maintain protection and prevent damage to the circuit breaker(s). In various embodiments, the fault protection system includes a fault and retry counter and maintains the operation of the fault and retry counter by powering it through the low-power mode control line when a fault occurs in the regulated main power supply (VDD).Various embodiments are described herein with reference to the figures.

[0018] The Fig. Figure 1 shows a system block diagram of an embodiment of a power switching system 100 comprising a microcontroller (µC) 102, power switches 104, and a serial peripheral interface (SPI) controller 106. According to various embodiments, the power switches 104 supply loads connected to the output bus OUT with power from the supply voltage VS based on control signals from the microcontroller 102 and the SPI controller 106. The SPI controller 106 includes a fault protection system 108 for protecting each of the power switches 104. The fault protection system 108 can include fault and retry counters connected to each power switch.

[0019] In one embodiment, the microcontroller 102 communicates with the SPI controller 106 via an SPI bus, which includes a control signal CS, a serial clock signal SCLK, a serial output signal SO, and a serial input signal SI. Based on signals received via the SPI bus, the SPI controller 106 provides normal-mode switch control signals SWNCTL to the power switches 104. Each power switch of the power switches 104 has an input connected to the supply voltage VS and an output connected such that a load is supplied via the output bus OUT, which can have any number of outputs corresponding to any number of power switches and loads. In one embodiment, the supply voltage VS is provided by a battery.In a more specific embodiment, the supply voltage VS is provided by a battery in an automotive system, and the loads connected to the output bus OUT are (but are not limited to) automotive components, such as components of an air conditioning system, components of emergency safety systems, vehicle lights, electric windows, and electric locks.

[0020] In various embodiments, the SPI controller 106 receives a fault mode control signal (FMC) that indicates when a fault has occurred in the regulated main voltage (VDD). In various embodiments, the fault mode control signal (FMC) can be supplied by a power system monitoring circuit. In one such embodiment, the fault mode control signal (FMC) is implemented as an emergency driving input (LHI) from a system base chip (SBC) in an automotive power system to activate an emergency driving mode.

[0021] In various embodiments, the SPI controller 106 uses the fault-mode control signal FMC to receive power and maintain the operation of the fault protection system when a fault occurs in the regulated main voltage VDD, a process known as fault-mode operation. In some such embodiments, when a fault occurs in the regulated main voltage VDD, the SPI controller can be disabled and is unable to control the switching of the power switches 104 based on the SPI bus. During such fault-mode operation, the microcontroller 102 can directly control the power switches 104 via the fault-mode switch control signals SWFCTL. Thus, the power switches 104, or a subset thereof, can continue switching during a fault mode to maintain system loads that are critical for operation.

[0022] According to one embodiment, the power switching system 100 is implemented in an automotive system, and the fault mode operation can be referred to as emergency driving mode. In such an embodiment, vehicle lights can be powered by the power switches 104 during emergency driving mode operation, while other, less critical output loads can be disabled. In such an embodiment, the fault mode switch control signals SWFCTL control some of the power switches 104 to maintain a power supply for the vehicle lights, while the SPI controller 106 does not operate due to the fault in the regulated main voltage VDD. Although the SPI controller 106 is unable to control the switching, the fault protection system 108 is directly powered by the fault mode control signal FMC and continues to protect the power switches 104.In some specific embodiments, the fault mode control signal (FMC) supplies power to the fault and retry counters to prevent damage from continuous overcurrent or excessively high temperatures. In various embodiments, the fault protection system can include any type of protective circuitry, and the power switching system can be implemented in any type of system, such as automotive, industrial, or medical.

[0023] In various embodiments, during normal operation, when no fault occurs in the regulated main voltage VDD, the microcontroller 102 communicates with the SPI controller 106 via the SPI bus to generate normal-mode switch control signals SWNCTL for the power switches 104. Thus, the fault-mode switch control signals SWFCTL can remain unused during normal operation. In some embodiments, the microcontroller 102 can also receive feedback signals (not shown) from the power switches 104 at an analog input pin (not shown) and can modify the switching information transmitted via the SPI bus to the SPI controller 106 based on the feedback received from the power switches 104. In some embodiments, the fault-mode switch control signals SWFCTL can be supplied via general-purpose input / output (GPIO) pins on the microcontroller 102.

[0024] Further details and embodiments are described below with reference to the other figures.

[0025] The Fig. Figure 2a shows a block diagram of an embodiment of a protection system 110, which is an embodiment of the implementation of part of the power switching system 100. According to various embodiments, the protection system 110 comprises the circuit breakers 104, the SPI controller 106, and the fault protection system 108. The SPI controller 106 supplies normal-mode switch control signals SWNCTL to the circuit breakers 104 during operation in a non-fault mode, e.g., a normal mode, and to another control circuit, such as the microcontroller 102 as described with reference to Fig. 1, supplies the fault mode switch control signals SWFCTL to the circuit breakers 104 during a fault mode. As similarly described above, the circuit breakers 104 connect the supply voltage VS to output loads connected to outputs OUT, which can be represented as a multi-terminal output bus.

[0026] In various embodiments, the circuit breakers 104 can have overcurrent or overtemperature detection circuits that generate fault signals ERR. In specific embodiments, each circuit breaker of the circuit breakers 104 has a fault detection circuit that generates a fault signal. All such fault signals can be represented by the fault signals ERR, which can also be represented as a fault bus with multiple lines for transporting all the fault signals ERR. In such embodiments, the fault protection system 108 is configured to receive the fault signals ERR and to generate deactivation signals DIS based on the fault signals ERR. The deactivation signals DIS can also be represented as a deactivation bus with a deactivation line for each circuit breaker of the circuit breakers 104.For example, if the error signals ERR indicate that a fault condition occurs multiple times in a specific circuit breaker, that specific circuit breaker can be deactivated until a reset signal RS is received from the SPI controller 106. In various embodiments, any number of circuit breakers 104 can be implemented together with the corresponding number of deactivation signals DIS, error signals ERR, and outputs OUT.

[0027] In some embodiments, the fault protection system 108 has fault and retry counters for the circuit breakers 104. Fig. Figure 2b shows a waveform diagram of such an embodiment of a method for operating the protection system 110. In such embodiments, the Fig. 2b the operation of a single fault and retry counter for a single circuit breaker of circuit breakers 104. The counter value CNT is incremented each time a fault signal is received from the fault signals ERR and a fault is indicated in the single circuit breaker. As shown, the counter value CNT is incremented each time an overload condition occurs in an output of the outputs OUT for the single circuit breaker. In some embodiments, the overload condition is detected by an overcurrent or an excessively high temperature.

[0028] When an overload condition is detected at the value of any of the outputs OUT, the individual circuit breaker is deactivated, and the counter value is incremented. After a short delay, the individual circuit breaker is reactivated, which can be described as a retry. After each retry, if another overload condition is detected, the individual circuit breaker is deactivated, and the counter value CNT is incremented again. If overload conditions continue to be detected on each retry, the counter value CNT is incremented up to a limit n for retry attempts. During the time that further overload conditions occur at the individual circuit breaker, the reset signal RS and the deactivation signal DIS are held in a deactivated state. When the counter value CNT reaches n, the deactivation signal DIS is set to an activated state (i.e.,The deactivation signal is activated to deactivate the individual circuit breaker for an extended period. As shown, the output value is deactivated as long as the deactivation of the individual DIS is activated. The individual circuit breakers can be reactivated as soon as the reset signal RS is activated to reset the counter value and resume operation of the individual circuit breaker. In such embodiments, the reset value RS resets the counter value to the initial value and resets the deactivation signal DIS to the deactivated state. In various embodiments, the description of the individual circuit breaker and associated fault and retry counters can be applied to each circuit breaker of the circuit breakers 104. In further embodiments, the fault protection system 108 can include other types of fault or protection circuits.

[0029] In various embodiments, the fault protection system 108 is configured to receive signals or power from the regulated main voltage VDD and the fault mode control signal FMC. In such embodiments, when no fault occurs in the regulated main voltage VDD, the fault protection system 108 receives power from the regulated main voltage VDD to protect the circuit breakers 104 from damage, such as with regard to Fig. 2b described. If a fault occurs in the regulated main voltage VDD, the fault protection system 108 can receive power from the fault mode control signal FMC. In such embodiments, the fault mode control signal FMC is generated as a control signal in the system monitor 112 attached to the fault protection system 108. The system monitor 112 may have a separate voltage limiter connected to the supply voltage VS, which is used to generate the fault mode control signal FMC as a voltage-limited, stable control signal. In another embodiment, the system monitor 112 may have an active voltage regulator. In some special embodiments, a voltage limiter uses passive components, including, for example, resistors and diodes, to provide voltage-limiting functionality, while a voltage regulator has active components to provide active voltage regulation, such as a switching regulator.In various embodiments, the fault mode control signal (FMC) is used as a control signal to activate a fault mode and as a voltage-limited, stable power supply for the fault protection system 108. During fault mode operation, the fault protection system 108 continues to operate internal fault systems, such as fault and retry counters, to protect the circuit breakers 104 based on the power received from the fault mode control signal (FMC).

[0030] In specific embodiments, the protection system 110 is part of an automotive system, and the fault mode control signal (FMC) is an implementation of an emergency drive input (LHI) from the system base chip (SBC), which is an implementation of the system monitor 112 configured to detect a fault in the regulated main voltage (VDD) and to monitor aspects of the automotive system. In such embodiments, the LHI is used to enable the operation of the circuit breakers 104 and the fault protection system 108 during a fault or in emergency drive mode, while the operation of the SPI controller 106 is disabled. Thus, the LHI supplies power to the fault protection system 108 and maintains the operation of fault systems within the fault protection system 108, such as fault and retry counters, during emergency drive mode to maintain the protection of the circuit breakers 104.

[0031] In further embodiments, the fault protection system 108 can be configured to receive power from the supply voltage VS. The supply voltage VS can be provided by a battery, such as an automotive battery. In some embodiments, the battery can provide a supply voltage VS in the range of 10 V to 42 V. In one specific embodiment, the battery provides a supply voltage VS of 12 V. In various embodiments, the fault protection system 108 can include an additional voltage limiter or regulator for receiving the supply voltage VS and generating a voltage-limited supply for operation during a fault mode. In such embodiments, if a fault occurs in the regulated main voltage VDD, the supply voltage VS can be used to provide power and continue the operation of the fault protection system 108.

[0032] In various embodiments, a fault in the regulated main voltage VDD can be any event that affects the power supply by the regulated main voltage VDD. In some embodiments, a fault can occur when the regulated main voltage VDD is removed and drops to zero power. In another embodiment, a fault can occur when there is a fluctuation from the specified regulated target value in the regulated main voltage VDD. For example, the regulated main voltage VDD may be specified as 5 V. In such embodiments, faults can occur when the regulated main voltage VDD changes, for example, to above 5.5 V or below 4.5 V. In other embodiments, faults can be low voltage thresholds only. For example, faults can occur when the regulated main voltage VDD falls below 4.5 V.In further embodiments, the threshold or thresholds for a fault in the regulated main voltage VDD can be set to other values.

[0033] In some embodiments, the fault protection system 108 can be separate from the SPI controller 106 and connected between the circuit breakers 104 and the SPI controller 106. In other embodiments, the fault protection system 108 can be contained within the SPI controller 106. In certain embodiments, the SPI controller 106 and the fault protection system 108 can be integrated into the same semiconductor as a single integrated circuit (IC). In further embodiments, the SPI controller 106 is implemented on a separate IC from the fault protection system 108. In still other embodiments, the fault protection system 108 is formed from discrete components and mounted on a common printed circuit board like the SPI controller 106.

[0034] According to various embodiments, the normal-mode switch control signal SWNCTL can be combined with the disabling signal DIS in the fault protection system 108. In such embodiments, only a single control signal is used to control the switching, and the single control signal can be disabled in the fault protection system 108, as described herein. For example, the disabling signal DIS can be combined with the normal-mode switch control signal SWNCTL by combinational logic, which in some embodiments is included in or separate from the fault protection system 108.

[0035] In general, embodiments relating to multiple circuit breakers and multiple corresponding circuits connected to the multiple circuit breakers are described herein. In one embodiment, a single circuit breaker with a single fault protection system and an operating mode is also conceivable, as described herein, for example, with reference to fault protection system 108.

[0036] The Fig. 3a, Fig. 3b, Fig. 3c, Fig. 3D, and Fig. 3e present schematic diagrams of embodiments of subsystems. Fig. Figure 3a presents a schematic diagram of a first embodiment of a subsystem 111a comprising a fault protection system 109a, a system monitor 112, and a voltage regulator 114. According to various embodiments, the fault protection system 109a is an implementation of the fault protection system 108, as described above with reference to Fig. 2a described. The fault protection system 109a can include a fault counter 116, a reset logic 118 and diodes 120 and 122.

[0037] In various embodiments, the fault counter 116 receives the voltage supply VEC through diode 120 or diode 122 from the regulated main voltage VDD or the fault mode control signal FMC, respectively. During normal operation, the voltage regulator 114 generates the regulated main voltage VDD from the supply voltage VS, which can be supplied, for example, by a battery. The capacitor 124 at the output of the voltage regulator 114 can also provide stabilization for the regulated main voltage VDD. In some embodiments, the voltage regulator 114 supplies the regulated main voltage VDD to the fault counter 116 as the voltage supply VEC through diode 120, which is operated in forward bias, during normal operation. In such embodiments, normal operation can be defined as operation in which no fault occurs or no fault occurs in the regulated main voltage VDD that affects the power supply.The regulated main voltage VDD can be used to power multiple ICs or components (not shown). For example, in one embodiment of an automotive system, the regulated main voltage VDD can power other chips, including a microcontroller.

[0038] In various embodiments, the system monitor 112 generates the fault mode control signal FMC during a fault operating mode. In such embodiments, the system monitor supplies the fault mode control signal FMC to the fault counter 116 as a voltage supply VEC during a fault operating mode via diode 122, which is operated in forward bias. During a fault operating mode, diode 122 can be operated in reverse because the regulated main voltage VDD can fall below a voltage threshold for the forward-biased diode 120. Simultaneously, the fault mode control signal FMC is activated to indicate a fault in the regulated main voltage VDD. As described above with reference to Fig. As described in section 2a, the system monitor 112 can have a voltage limiter connected to the supply voltage VS, which generates a voltage-limited stable control signal as a fault mode control signal FMC to activate a fault operating mode. In such embodiments, the fault mode control signal FMC can operate the diode 122 in forward bias and supply power to the fault counter 116 as a voltage supply VEC.

[0039] According to various embodiments, the error counter 116 operates as described above with reference to Fig. 2b described, and the fault protection system 109a implements a protection system for circuit breakers, such as the circuit breakers 104, which is independent of a regulated main voltage supply, such as the regulated main voltage VDD. In various embodiments, the fault protection system 109a can be an implementation of part of the fault protection system 108 to implement fault protection for each circuit breaker of the circuit breakers 104, as described above with reference to Fig. 1 and Fig. 2a described.

[0040] In various embodiments, the regulated main voltage VDD and the fault mode control signal FMC can have a range of voltages. For example, in one embodiment, the regulated main voltage VDD is 5 V. In another embodiment, the regulated main voltage VDD is 3.3 V. In further embodiments, the regulated main voltage VDD can have a range of 2.5 V to 7.5 V. In alternative embodiments, the regulated main voltage VDD can be outside this range. Similarly, in one embodiment, the fault mode control signal FMC can be 5 V when activated and 0 V when deactivated. In further embodiments, the fault mode control signal FMC is in the range of 1.5 to 7.5 V when activated and less than 1.5 V when deactivated. In alternative embodiments, the fault mode control signal FMC can be outside this range when activated or deactivated.

[0041] In some embodiments, the supply voltage VS can be provided by a battery. In one specific embodiment, the supply voltage VS is provided by a battery with a voltage range of 10 V to 14 V. In some embodiments, the supply voltage VS can be in the range of 10 V to 42 V. In alternative embodiments, the supply voltage VS can be outside this range.

[0042] In some embodiments, as further described above with reference to the Fig. 2a and Fig. As described in 2b, the system monitor 112 can be implemented as an SBC for an automotive system, and the fault mode control signal FMC can be implemented as an LHI to activate the emergency driving mode for some fault situations.

[0043] According to various embodiments, the fault counter 116 generates the deactivation signal DIS when its internal counter value reaches a fault threshold. The deactivation signal DIS deactivates, for example, the circuit breakers (not shown) to which the fault counter 116 is connected. In other embodiments, the deactivation signal DIS and the fault signal ERR can be connected to any type of fault-protected component. In various embodiments, the deactivation signal DIS, for example, continues to deactivate the circuit breakers until the fault counter 116 is reset. In some embodiments, the fault counter 116 can be reset by the reset signal RS from, for example, the microcontroller 102 or the SPI controller 106, or by the reset logic 118.In one embodiment, the reset logic 118 can identify falling or rising edges of the fault mode control signal FMC, indicating the end or deactivation of the fault mode, and generate a reset for the fault counter 116 based on the falling or rising edge. In other embodiments, the reset logic 118 can identify falling or rising edges of an input control signal (not shown) and generate a reset for the fault counter 116 based on the input control signal. In a further embodiment, the fault counter 116 can have a single reset terminal connected to the reset logic 118. In such embodiments, the reset logic 118 receives the reset signal RS and generates a reset for the fault counter 116 based on the reset signal RS and the fault mode control signal FMC.In further embodiments, the reset logic 118 can also be connected to the regulated main voltage VDD or the supply voltage VS (not shown) and generate a reset for the error counter 116 based on any available signal or voltage.

[0044] The Fig. Figure 3b presents a schematic diagram of a second embodiment of a subsystem 111b, which includes the fault protection system 109b, the system monitor 112, the voltage regulator 114, and the voltage limiter 126. According to various embodiments, the subsystem 111b operates similarly to the subsystem 111a described above. Fig. 3a described, and the description of the common elements also refers to the elements in Fig. 3b. The fault protection system 109b further includes a diode 128 configured to supply the voltage VEC for the fault counter 116. In various embodiments, the supply voltage VS is supplied by the voltage limiter 126 and the diode 128 to provide the voltage VEC for the fault counter 116. As described above, a fault may occur in the regulated main voltage VDD. During a fault operating mode, the voltage VEC may be supplied by the diode 122 from the fault mode control signal FMC or by the diode 128 from the limited supply voltage VSLIM. In some embodiments, the diode 122 and the connection to the system monitor 112 may be omitted, and the voltage VEC may be supplied solely by the diode 128 from the limited supply voltage VSLIM during a fault operating mode.

[0045] In various embodiments, the voltage limiter 126 can generate the limited supply voltage VSLIM, which lies in the range of 2.5 V to 7.5 V. In one embodiment, the voltage limiter 126 can generate a limited supply voltage VSLIM of 5 V. In some embodiments, the voltage limiter 126 is implemented as a fault protection system 109b on a separate component, such as a separate IC. In other embodiments, the voltage limiter 126 is implemented as a fault protection system 109b on the same component, such as the same IC.

[0046] The Fig. Figure 3c presents a schematic diagram of a third embodiment of a subsystem 111c, which includes the fault protection system 109c, the system monitor 112, and the voltage regulator 114. According to various embodiments, the subsystem 111c operates similarly to the subsystem 111a described above. Fig. 3a described, and the description of the common elements also applies to the elements in Fig. 3c. In various embodiments, the fault protection system 109c has a different internal organization than the one described above with reference to Fig. 3a described fault protection system 109a.

[0047] The fault protection system 109c includes fault counters 117a and 117b, which operate similarly to those described herein with reference to fault counter 116. In such embodiments, fault counter 117a operates during normal operation as described above and is supplied directly by the regulated main voltage VDD. If a fault occurs in the regulated main voltage VDD, resulting in a fault operating mode, fault counter 117a can be deactivated and lose power. During a fault operating mode, fault counter 117b operates as described above and is supplied directly by the fault mode control signal FMC. In various embodiments, the logic circuit 130 receives deactivation signals from fault counters 117a and 117b and generates the deactivation signal DIS to, for example, deactivate a circuit breaker, as described above.In one specific embodiment, the logic circuit 130 is an OR gate. In various embodiments, the reset logic 118 provides the reset control for the error counter 117b, and the reset signal RS provides the reset control for the error counter 117a.

[0048] The Fig. Figure 3d shows a schematic diagram of a fourth embodiment of a subsystem 111d, which includes the fault protection system 109d, the system monitor 112, and the voltage regulator 114. According to various embodiments, the subsystem 111d operates similarly to the subsystem 111a described above. Fig. 3a described, and the description of the common elements also applies to the elements in Fig. 3d. The fault protection system 109d has several fault counters 132_1-132_n, where n is any number, for example, to protect each circuit breaker of the circuit breakers 104. In some embodiments, n is the number of circuit breakers and corresponding fault counters in a power system, such as the power switching system 100. In certain embodiments, the number n of circuit breakers and corresponding fault counters 132_1-132_n can be in the range of 1 to 32. In alternative embodiments, the number n can be greater than 32.

[0049] According to various embodiments, the fault counters 132_1-132_n operate similarly to the fault counter 116 described above. The fault counters 132_1-132_n can have internal or external combinational reset logic for controlling the reset based on the reset signals received from the undervoltage (UV) reset logic 119 or the reset signals RS1-RSn, as shown. In various embodiments, each of the fault counters 132_1-132_n is connected to a corresponding channel 1-n, each channel 1-n having correspondingly numbered reset signals RS1-RSn, fault signals ERR1-ERRn, and deactivation signals DIS1-DISn. Each channel 1-n can be connected to a power component, such as a circuit breaker, and the respective fault counters 132_1-132n deactivate the power component or the circuit breaker, as described above with reference to fault counter 116. Fig. 3a and Fig. 3b described.

[0050] According to some specific embodiments, the UV reset logic 119 has inputs connected to the power supply VEC, the regulated main voltage VDD, the fault mode control signal FMC, and the supply voltage VS, or a combination thereof. The output of the UV reset logic 119 provides a reset signal to each of the fault counters 132_1-132_n. In various specific embodiments, each of the fault counters 132_1-132_n can be reset when the power supply VEC or the regulated main voltage VDD falls below a fault threshold, when a falling edge occurs in the fault mode control signal FMC corresponding to the end of a fault operating mode, or when the supply voltage VS falls below a supply threshold. In such various embodiments, the UV reset logic 119 can have any configuration and number of the four inputs shown.

[0051] In various embodiments, the voltage limiter 126 and the diode 128 are described above with reference to Fig. 3b described, optional. In one embodiment, the voltage limiter 126 and the diode 128 may be included, and the diode 122 and the connection between the fault protection system 109d and the system monitor 112 may be omitted.

[0052] The Fig. Figure 3e presents a schematic diagram of a fifth embodiment of a subsystem 111e, which includes the fault protection system 109e, the system monitor 112, and the voltage regulator 114. According to various embodiments, the subsystem 111e operates similarly to the subsystem 111a described above. Fig. 3a described, and the description of the common elements also applies to the elements in Fig. 3e. Instead of diodes 120 and 122, the fault protection system 109e includes an active rectifier 121 configured to supply the voltage VEC for the fault counter 116. In various embodiments, the supply voltage VS is provided by the voltage regulator 114 and the active rectifier 121 to supply the voltage VEC for the fault counter 116. As described above, a fault may occur in the regulated main voltage VDD. During a fault operating mode, the active rectifier 121 may detect that the fault mode control signal FMC has a higher voltage than the regulated main voltage VDD. In such embodiments, the active rectifier 121 selects the higher voltage and supplies the voltage VEC.

[0053] The Fig. 4a, Fig. 4b, and Fig. Figure 4c presents schematic diagrams of exemplary components 140a, 140b, and 140c for embodiments of power switching systems, which include configurations for the system monitor 112. According to various embodiments, the system monitor 112 can be implemented as one of several types of system fault monitoring. In various embodiments, the system monitor 112 can be formed as a separate IC or from discrete components connected to a system circuit board. In one embodiment, the system monitor 112 is formed as a separate IC in an automotive system. In some specific embodiments, the system monitor is implemented as a system base chip (SBC) that monitors the automotive system for faults and generates control signals based on the system monitoring.

[0054] In various embodiments, the system monitor 112 is implemented as an SBC with an emergency drive input LHI, for example, for an automotive system. Component 140a represents one embodiment of the system monitor 112 implemented as an SBC. In such embodiments, component 140a includes the voltage limiter 142 and the LHI logic 144. The voltage limiter 142 receives the supply voltage VS and generates a voltage-limited supply for the LHI logic 144. The LHI logic 144 monitors the regulated main voltage VDD and controls the emergency drive input LHI with a control voltage when a fault in the regulated main voltage VDD is detected. The LHI logic 144 can have combinational logic or analog circuits. For example, the LHI logic can include a comparator for comparing the regulated main voltage VDD with a fault threshold.In various embodiments, the control voltage for the emergency drive input LHI can be, for example, 5 V. In other embodiments, the control voltage for the emergency drive input LHI can be one of the voltages described above with reference to the fault mode control signal FMC.

[0055] Component 140b represents another embodiment of the system monitor 112 implemented as an SBC. In such embodiments, component 140b includes the voltage limiter 142, as described above, the LHI logic 146, and the switch 148. The LHI logic 146 operates similarly to the LHI logic 144, but generates the switch control input SLHI for the switch 148 based on the detection of a fault in the regulated main voltage VDD. The switch 148 is controlled by the switch control SLHI to either supply 0 V as the emergency drive input LHI, corresponding to no fault in the regulated main voltage VDD, or to supply a control voltage as the emergency drive input LHI, corresponding to a fault in the regulated main voltage VDD. The control voltage can have one of the values ​​described above with reference to component 140a and the fault mode control signal FMC.

[0056] Component 140c represents another embodiment of the system monitor 112 implemented as an SBC. In such embodiments, component 140c includes voltage-limiting diodes 150_1, 150_2, ... and 150_m, the LHI logic 152, the LHI driver 154, and the series resistor 156. The voltage-limiting diodes 150_1, 150_2, ... and 150_m can have any number m of voltage-limiting diodes. Each diode of the voltage-limiting diodes 150_1, 150_2, ... and 150_m is connected in series between the supply voltage VS and a low reference terminal, such as ground. The LHI logic 152 operates in a similar manner to the LHI logic 144 to generate a logic signal for the emergency drive input LHI based on the detection of a fault in the regulated main voltage VDD.The logic signal is supplied to the LHI driver 154, which provides either 0 V as the emergency drive input LHI, corresponding to no fault in the regulated main voltage VDD, or a control voltage as the emergency drive input LHI, corresponding to a fault in the regulated main voltage VDD. The control voltage can have one of the values ​​described above with reference to component 140a and the fault mode control signal FMC. In one embodiment, the LHI driver 154 is implemented as an output buffer. In various embodiments, the supply voltage VS is connected to voltage-limiting diodes 150_1, 150_2, ... and 150_m via the series resistor 156 to limit the current through the voltage-limiting diodes 150_1, 150_2, ... and 150_m.In further embodiments, a further isolating circuit or resistor circuit may be provided to provide a separation between the supply voltage VS and the voltage-limiting function of the voltage-limiting diodes 150_1, 150_2, ... and 150_m.

[0057] In various embodiments, the system monitor 112 implemented as an SBC in components 140a, 140b, and 140c can have further functions with corresponding controls or circuits (not shown), depending on the specific system application. Those skilled in the art can readily estimate that such features may be included in intended embodiments. For example, an SBC can control watchdog functions, fail-safe operation, and under- or overvoltage protection. In some embodiments, various functions related to the Fig. 4a, Fig. 4b and Fig. The voltage-limiting functions described in section 4c are implemented outside the SBC.

[0058] The Fig. Figure 5a shows a schematic diagram of another embodiment of a power switching system 160, which includes the SPI controller 162, the fault protection system 164, the level-shifting (LS) drivers 166_1-166_n in the LS circuits 170_1-170_n, and the circuit breakers 168_1-168_n. According to various embodiments, each of the circuit breakers 168_1-168_n is controlled by control signals SDRV1-SDRVn, which are supplied by the LS drivers 166_1-166_n. The LS circuits 170_1-170_n comprise the LS drivers 166_1-166_n and combinational logic for enabling or disabling the control signals SDRV1-SDRVn. The circuit breakers 168_1-168_n are switched into line (ON) and non-line (OFF) mode to supply power from the supply voltage VS to the loads connected to the outputs OUT1-OUTn.The fault protection system 164 operates similarly to that described above with reference to the other figures and has a separate fault channel for each of the circuit breakers 168_1-168_n. The fault counters 132_1-132_n operate as described above with reference to... Fig. 3d described, with the LS circuits 170_1-170_n added.

[0059] Each of the LS circuits 170_1-170_n features AND gates 172_1-172_n, AND gate 174_1-174_n, and OR gate 176_1-176_n. Each of the AND gates 172_1-172_n combines the respective disable signal of the disable signals DIS1-DISn with the respective SPI switch control signal of the SPI switch control signals SPICTL1-SPICTLn to generate an enable or disable signal for each respective LS driver 166_1-166_n during normal operation. In one embodiment, each of the AND gates 172_1-172_n has an invert input for the disable signals DIS1-DISn. During fault mode operation, the SPI switch control signals SPICTL1-SPICTLn can be disabled. In such embodiments, the AND gates 172_1-172_n are inactive because the SPI switch control signals SPICTL1-SPICTLn are inactive.Simultaneously, each of the AND gates 174_1-174_n is activated by the emergency drive input LHI and combines the respective deactivation signal of the deactivation signals DIS1-DISn with the respective input switch control signal of the input switch control signals IN1-INn via an inverting input. In such embodiments, each of the OR gates 176_1-176_n combines signals from the respective AND gates 172_1-172_n and 174_1-174_n to generate the respective control signals SDRV1-SDRVn.

[0060] According to various embodiments, the voltage supply VEC to the fault counters 132_1-132_n is supplied by the regulated main voltage VDD during normal operation and by the emergency drive input LHI during fault operation. Diodes 120 and 122 ensure the voltage supply VEC for the fault counters 132_1-132_n during both normal and fault operation. In such embodiments, the fault operation can also be referred to as the emergency drive mode. The fault operation or emergency drive mode occurs when a fault occurs in the regulated main voltage VDD. For example, a fault in the regulated main voltage VDD can occur when the regulated main voltage VDD falls below a fault threshold. The fault threshold can be determined based on system operation. In some embodiments, the fault threshold can be in the range of 2 V to 4 V.In other alternative embodiments, the fault threshold may lie outside this range. In various embodiments, the emergency drive input LHI may be an implementation of the fault mode control signal FMC, as described above.

[0061] According to various embodiments, the SPI controller 162 generates the SPI switch control signals SPICTL1-SPICTLn based on information received via the SPI bus. In one embodiment, the SPI switch control signals SPICTL1-SPICTLn are an implementation of the normal-mode switch control signals SWNCTL, as described above with reference to the Fig. 1 and Fig. 2a described. The SPI switch control signals SPICTL1-SPICTLn are fed to the LS circuits 170_1-170_n, which generate the control signals SDRV1-SDRVn for the circuit breakers 168_1-168_n during normal operation. During fault operation, the LS circuits 170_1-170_n receive the input switch control signals IN1-INn at the AND gates 174_1-174_n, which are an implementation of the fault-mode switch control signals SWFCTL, as described above with reference to the Fig. 1 and Fig. 2a described. For example, the input switch control signals IN1-INn can be supplied by a microcontroller (not shown), such as the microcontroller 102. During a fault operating mode, the AND gates 174_1-174_n, through the OR gates 176_1-176_n and the LS drivers 166_1-166_n, generate the control signals SDRV1-SDRVn for the circuit breakers 168_1-168_n based on the input switch control signals IN1-INn. In such embodiments, the AND gates 174_1-174_n are enabled or disabled by the disable signals DIS1-DISn from the fault counters 132_1-132_n during a fault mode.

[0062] Furthermore, the LS circuit 170_1-170_n can be powered by the voltage supply VEC, which is supplied via the emergency drive input LHI during a fault operating mode. Each of the logic gates in the LS circuits 170_1-170_n and the LS drivers 166_1-166_n can be powered by the voltage supply VEC. The LS circuits 170_1-170_n can also be powered by the supply voltage VS. A specific embodiment of the LS circuits 170_1-170_n is further described herein with reference to Fig. 5b described.

[0063] In various embodiments, the UV reset logic 119 operates, as described above with reference to Fig. 3d described, and can be connected to the supply voltage VS, the emergency drive input LHI, the regulated main voltage VDD or the power supply VEC or a combination of these (connection not shown for simplification).

[0064] According to various embodiments, the fault protection system 164 maintains operation and protection during normal and fault operating modes. In certain automotive embodiments, the emergency drive input LHI, which can be generated in an SBC as a control signal indicating the emergency drive mode, is used as a regulated voltage supply during a fault mode (i.e., emergency drive mode) to supply power to the fault counters 132_1-132_n in order to maintain the protection of the circuit breakers 168_1-168_n.

[0065] In some embodiments, the fault protection system 164 is implemented on the same IC as the SPI controller 162. In other embodiments, the fault protection system 164 and the SPI controller 162 are implemented on separate ICs or separate components.

[0066] The Fig. Figure 5b presents a schematic diagram of an embodiment of an implementation of a level-changing (LS) circuit 170 for the LS circuits 170_1-170_n for the power switching system 160, as described above with reference to Fig. 5a described. The LS circuit 170 comprises transistors 180, 184 and 186 connected in series, a transistor 188 connected in parallel and in series, a deactivation inverter 178 and a current sink 190. According to various embodiments, the LS circuit 170 is an implementation of a single LS circuit of the LS circuits 170_1-170_n, such as the LS circuit 170_1 with the LS driver 166_1, the AND gate 172_1, the AND gate 174_1 and the OR gate 176_1. In such embodiments, the deactivation signal DIS, which can represent one of the deactivation signals DIS1-DISn, supplies a deactivation signal to transistor 186 to deactivate the control signal SDRV, which can represent one of the control signals SDRV1-SDRVn. The deactivation signal DIS can be controlled by inverter 178, which is supplied by the voltage supply VEC.

[0067] According to various embodiments, if the disable signal DIS does not disable, either transistors 180 and 184 control the drive signal SDRV, or transistor 188 controls the drive signal SDRV. During a fault mode, the SPI switch control signal SPICTL can be inactive if the SPI controller 162 is inactive, as described above with reference to the SPI switch control signals SPICTL1-SPICTLn. Thus, transistor 188 can be switched to a non-conducting state, while transistor 180 is switched to a conducting state by the emergency drive input LHI during a fault mode. In such embodiments, the input switch control signal IN, which can be one of the input switch control signals IN1-INn, controls transistor 184 to conduct or block the drive signal SDRV.

[0068] During normal operation, the emergency drive input LHI can be disabled, which puts transistor 180 into a non-conducting state. In such embodiments, the SPI switch control signal SPICTL can drive transistor 188 to conduct or block the drive signal SDRV. In both normal and fault modes, transistor 186 can be disabled by the disable signal DIS to disable a power transistor, such as power transistors 168_1-168_n. As described above with reference to the disable signals DIS1-DISn in Fig. As described in section 5a, the deactivation signal DIS can be generated by one of the error counters 132_1-132_n. In various embodiments, the current sink 190 represents a current sink for the control signal SDRV if a conducting path through transistors 180, 184, 186 and 188 is present.

[0069] The Fig. Figure 6 shows a schematic diagram of another embodiment of the power switching system 161. According to various embodiments, the power switching system 161 operates similarly to, for example, the power switching system 160 described above. Fig. 5a described. The description of the elements numbered together above also applies to Fig. 6 and is not repeated here for the sake of brevity. In various embodiments, the power switching system 161 includes the fault counters 132_1-132_n, the SPI controller 162, the LS circuits 170_1-170_n, the undervoltage (UV) detector 191 for the emergency start input (LHI), the overvoltage (OV) protection and voltage regulator 192, the OV protection 193, and the VDD-UV reset 194.

[0070] According to various embodiments, the LHI-UV detector 191 detects undervoltages at the emergency drive input LHI and generates a reset signal, which is logically combined with the reset signals RS1-RSn from the SPI controller 162 at the AND gates in the fault counters 132_1-132_n. The VDD-UV reset 194 detects an undervoltage in VDD and supplies the VDD reset control signal VDD_UV to the SPI controller 162. The OV protection and voltage regulator 192 receives the regulated main voltage VDD from the SPI bus and monitors it for overvoltages. In some specific embodiments, the OV protection and voltage regulator 192 receives the regulated main voltage VDD with a voltage range of 3 V to 6 V and outputs a regulated 3 V signal. In some embodiments, the OV protection 193 also monitors overvoltages at the emergency drive input LHI or the input switch control signals IN1-INn.

[0071] In some embodiments, the SPI controller 162 also receives the non-zero counter signals CNZ1-CNZn via level-shift resistors from the respective error counters 132_1-132_n. In some further embodiments, the SPI controller 162 also receives the channel error signals CHERR1-CHERRn via level-shift resistors from the respective error counters 132_1-132_n. According to various embodiments, the SPI controller 162 can receive signals from the emergency drive input LHI and the input switch control signals IN1-INn, as shown by the dashed lines on the SPI controller 162.

[0072] The Fig. Figure 7 shows a system diagram of an embodiment of the power switching system 200, which includes the microcontroller (µC) 202 and the multi-channel switching component 208, comprising the power switches 204 and the SPI controller 206. According to various embodiments, the SPI controller 206 is connected to the microcontroller 202 via the SPI bus 210 and generates switching control signals for the power switches 204. In such embodiments, the SPI controller 206 includes a fault protection system, as described above.

[0073] According to some embodiments, the power switching system 200 is implemented in an automotive system, and a fault operating mode is referred to as emergency driving mode. In various embodiments, the power switches 204 are controlled during a normal operating mode based on signals from the SPI bus 210 and the SPI controller 206. During a fault operating mode, the power switches 204 receive control signals from the parallel general-purpose interface circuit 224 at inputs IN1, IN2, IN3, and IN4. Furthermore, during a fault operating mode, the fault protection system in the SPI controller 206 operates based on the power received from the emergency driving input LHI to prevent damage to the power switches 204 using, for example, fault counters, as described above.During normal operating mode, the fault protection system in the SPI controller 206 operates based on the power received from the regulated main voltage VDD.

[0074] According to various embodiments, the circuit breakers 204 supply loads 218_1, 218_2, 218_3, and 218_4, which are connected to outputs OUT1, OUT2, OUT3, and OUT4. Various embodiments can include any number of circuit breakers and corresponding outputs. In specific embodiments, loads 218_1, 218_2, 218_3, and 218_4 are assigned various power values, such as 65 W or 27 W. The switching of the circuit breakers 204 can be controlled to deliver specific power values ​​to outputs OUT1, OUT2, OUT3, and OUT4.

[0075] In various embodiments, the multi-channel switching component 208 is implemented on a single IC, wherein both the power switches 204 and the SPI controller 206 are implemented on the single IC. In further embodiments, the power switches 204 can be implemented on a first IC and the SPI controller 206 on a second IC. In such embodiments, the first and second ICs can be stacked or connected to an identical printed circuit board that implements the multi-channel switching component 208.

[0076] According to various embodiments, the emergency drive input LHI is fed from the watchdog output WDOUT, which is provided by an SBC (not shown). In such embodiments, a fault can occur anywhere in the entire automotive system or in another type of system with the power switching system 200. Based on the fault in the entire automotive system, the SBC activates the emergency drive mode, and the watchdog output WDOUT controls the emergency drive input LHI for the SPI controller 206 and controls the parallel general-purpose interface circuit 224 for emergency drive mode operation.

[0077] In various embodiments, the power switching system 200 includes further components or circuits. A filter or stabilization circuit 220 is connected between the regulated main voltage VDD and the multi-channel switching component 208. A stabilization capacitor 222 is connected between the positive battery terminal VBAT+, which supplies the supply voltage VS, and the multi-channel switching component 208. A current sensing IS is provided by the feedback circuit 212 at the analog / digital input AD of the microcontroller 202. An overvoltage suppression (TVS) circuit 214 is connected between the positive battery terminal VBAT+ and the negative battery terminal VBAT-. A reference circuit 216 provides a stable low reference or ground voltage (GND) to the multi-channel switching component 208.The reference pin VCC of the microcontroller 202 is connected to the regulated main voltage VDD, and the reference pin VSS of the microcontroller 202 is connected to the negative battery terminal VBAT-.

[0078] According to various such embodiments, further circuits or modifications may be included in the power switching system 200. In one specific embodiment, the microcontroller 202 may be implemented as a standard microcontroller. For example, the microcontroller 202 may be a microcontroller from the Infineon XC2200 microcontroller family. In one particular embodiment, the microcontroller 202 is the Infineon XC2267 microcontroller.

[0079] In various embodiments, other configurations and interface protocols can also be used. For example, the SPI bus 210 has a control signal CS, a clock signal SCLK, an output signal SO, and an input signal SI. In other embodiments, the SPI bus 210 can have fewer signal lines, such as a single signal line or only two signal lines.

[0080] The Fig.Figure 8 presents a block diagram of an embodiment of a method for operating a fault protection system, comprising steps 302 and 304. According to various embodiments, the method for operating a fault protection system is a method for operating a fault protection system. In various embodiments, step 302 includes receiving a primary power supply from a system power supply circuit during a first mode. Operation in the first mode occurs when the primary power supply has not detected any faults. Step 304 includes receiving a secondary power supply from a fault mode control circuit during a second mode. Operation in the second mode occurs when the primary power supply has detected a fault. A detected fault may be that the primary power supply falls below a fault threshold or an operating threshold.

[0081] According to one embodiment, a fault protection system comprises a first power supply terminal, a second power supply terminal, a fault circuit configured to receive a power supply signal, and a power supply circuit connected to the fault circuit, the first power supply terminal, and the second power supply terminal. The power supply circuit is configured to supply the power supply signal from the first power supply terminal during a first operating mode and the power supply signal from the second power supply terminal during a second operating mode.

[0082] In various embodiments, the first power supply terminal is configured to be connected to a regulated system supply signal generated by a first power source, and the second power supply terminal is configured to be connected to a mode control signal generated by the first power source. In one embodiment, the regulated system supply signal is generated at a first voltage regulator connected to the first power source, and the mode control signal is generated at a voltage limiter or a second voltage regulator connected to the first power source. The mode control signal is generated at a system monitor circuit configured to detect a fault in the regulated system supply signal.

[0083] In various embodiments, the system monitor circuit is configured to detect a fault when a voltage value of the regulated system supply signal falls below a first threshold. The fault protection system may also include the system monitor circuit. In one embodiment, the first power source is a battery. In some embodiments, the fault protection system operates in the first mode when the regulated system supply signal is above a first threshold, and in the second mode when the regulated system supply signal is below the first threshold. The fault protection system can operate in the first mode when the regulated system supply signal has no detected faults, and in the second mode when the regulated system supply signal has a detected fault.

[0084] In various embodiments, the fault circuit is further configured to receive a fault signal from a circuit breaker, increment a fault count based on the fault signal, and deactivate the circuit breaker when the fault count exceeds a first fault threshold. In such embodiments, the fault circuit keeps the circuit breaker in a deactivated state until the fault count falls below the first fault threshold. The fault circuit may also include a reset circuit configured to reset the fault count. In one embodiment, the fault protection system further includes the circuit breaker. In some embodiments, the fault protection system further includes multiple circuit breakers and multiple fault circuits, and each fault circuit is configured to receive the power supply signal.

[0085] In various embodiments, the fault protection system further includes a voltage limiter connected between a first power source and the second power supply terminal. In one embodiment, the power supply circuit includes a first diode connected between the first power supply terminal and the fault circuit, and a second diode connected between the second power supply terminal and the fault circuit. The power supply circuit may include an active rectifier circuit. The implementations of the various embodiments may include, for example, a circuit, hardware, a method or process, or computing systems.

[0086] According to one embodiment, a method for operating a fault protection system comprises receiving a primary power supply from a system power supply circuit during a first mode and receiving a secondary power supply from a fault-mode control circuit during a second mode. Operation occurs in the first mode when the primary power supply has no detected faults, and operation occurs in the second mode when the primary power supply has a detected fault.

[0087] In various embodiments, the method further comprises detecting a fault in the main power supply at the fault-mode control circuit. In such embodiments, fault detection includes determining whether a voltage value of the main power supply is below a first threshold. The method may further comprise receiving a fault signal from a circuit breaker, incrementing a fault count based on the fault signal, disabling the circuit breaker when the fault count exceeds a first fault threshold, and holding the circuit breaker in a disabled state until the fault count falls below the first fault threshold. In some embodiments, the method further comprises generating the main power supply in the system power supply circuit using a voltage regulator connected to a battery.The method can also include generating the secondary power supply in the fault-mode control circuit using a voltage limiter. The implementations of the various embodiments can comprise a circuit, hardware, a method or process, or computing systems.

[0088] According to one embodiment, a power supply system comprises multiple circuit breakers configured to be connected to a power supply and to supply multiple loads, multiple switch drivers configured to supply drive signals to the multiple circuit breakers and to receive a fault-mode control signal, multiple fault protection circuits configured to supply disable signals to the multiple switch drivers, and a supply circuit connected to the multiple fault protection circuits. The multiple fault protection circuits are configured to be connected to a supply voltage and to receive multiple fault signals from the multiple circuit breakers.Furthermore, the supply circuit is configured to supply the supply voltage to the multiple fault protection circuits from a first system supply source during a first mode and to supply the supply voltage to the multiple fault protection circuits from the fault mode control signal during a second mode.

[0089] In various embodiments, the first system power supply is formed by a voltage regulator connected to the power supply. The power supply may include a battery. In some embodiments, the power supply system is an automotive system, with the multiple loads comprising multiple automotive loads, and the second mode includes an emergency driving mode for the automotive system. In one embodiment, the first mode is executed when a voltage value of the first system power supply is above an operating threshold, and the second mode is executed when the voltage value of the first system power supply is below the operating threshold.

[0090] In various embodiments, the first mode is executed when the first system power source has no detected faults, and the second mode is executed when the first system power source has a detected fault. In one embodiment, the power supply system further includes a system monitor circuit configured to detect faults and provide the fault mode control signal. The multiple fault protection circuits may include multiple fault counters. In such embodiments, each fault counter is configured to receive a fault signal from a corresponding circuit breaker among the multiple circuit breakers, increment a fault count for the corresponding circuit breaker based on the fault signal, and deactivate the corresponding circuit breaker when the fault count for the corresponding circuit breaker exceeds a first fault threshold.Each fault counter keeps its corresponding circuit breaker in a deactivated state until the fault count for that breaker falls below the first fault threshold. The implementations of the various embodiments can include a circuit, hardware, a method or process, or computing systems.

[0091] According to various embodiments described herein, the advantages can include fault protection for components, such as circuit breakers, during fault mode operation. For example, damage to the circuit breakers when power supply faults occur can be avoided by maintaining the operation of protective circuits. As another example, an advantage of various embodiments can also include fault protection during a failure of the regulated main voltage VDD.

[0092] According to various embodiments, the descriptions contained herein are primarily directed at circuit breakers. In other embodiments, fault protection systems as described herein can be applied to any type of switching device or circuit, such as those formed as lateral or vertical semiconductor devices. Thus, some embodiments are not specifically limited to power semiconductor applications.

[0093] While this invention has been described with reference to illustrative embodiments, this description should not be considered in any way limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will become apparent to persons skilled in the art when referring to the description. It is therefore intended that the appended claims also include all such modifications or embodiments.

Claims

[1] Fault protection system (108, 109a-e, 164), which includes the following: a first power supply connection; a second power supply connection; a fault circuit (116, 118) configured to receive a power supply signal; and a power supply circuit connected to the fault circuit (116, 118), the first power supply connection and the second power supply connection, wherein the power supply circuit is set up, to supply the power supply signal from the first power supply connection during a first operating mode, and during a second operating mode, the power supply signal is to be supplied from the second power supply terminal, wherein the first power supply terminal is configured to be connected to a regulated system supply signal (VDD) generated by a first power source, and the second power supply terminal is configured to be connected to an operating mode control signal (F) generated by the first power source. MC ) to be connected. [2] Fault protection system (108, 109a-e, 164) according to claim 1, wherein the regulated system supply signal is generated at a first voltage regulator (114) connected to the first power source, and the operating mode control signal (F MC ) is generated at a voltage limiter or a second voltage regulator connected to the first power source. [3] Fault protection system (108, 109a-e, 164) according to claim 2, wherein the operating mode control signal (F MC) is generated on a system monitor circuit (112) which is configured to detect a fault in the regulated system supply signal. [4] Fault protection system (108, 109a-e, 164) according to claim 3, wherein the system monitor circuit (112) is configured to detect a fault when the voltage value of the regulated system supply signal is below a first threshold. [5] Fault protection system (108, 109a-e, 164) according to one of claims 3 or 4, which further comprises the system monitor circuit (112). [6] Fault protection system (108, 109a-e, 164) according to one of claims 2-5, wherein the first power source comprises a battery. [7] Fault protection system (108, 109a-e, 164) according to one of claims 1-6, wherein the fault protection system (108, 109a-e, 164) operates in the first operating mode when the regulated system supply signal is above a first threshold, and The fault protection system (108, 109a-e, 164) operates in the second operating mode when the regulated system supply signal is below the first threshold. [8] Fault protection system (108, 109a-e, 164) according to one of claims 1-7, wherein the fault protection system (108, 109a-e, 164) operates in the first operating mode when the regulated system supply signal has no detected faults, and The fault protection system (108, 109a-e, 164) operates in the second operating mode when the regulated system supply signal has a detected fault. [9] Fault protection system (108, 109a-e, 164) according to one of claims 1-8, wherein the fault circuit (116, 118) is further configured, to receive an error signal from a circuit breaker (104), to increment an error count based on the error signal, and to deactivate the circuit breaker (104) when the number of faults exceeds a first fault threshold, wherein the fault circuit keeps the circuit breaker (104) in a deactivated state until the number of faults falls below the first fault threshold. [10] Fault protection system (108, 109a-e, 164) according to claim 9, wherein the fault circuit (116, 118) further comprises a reset circuit (118) which is configured to reset the fault count. [11] Fault protection system (108, 109a-e, 164) according to claim 9 or 10, which further comprises the circuit breaker (104). [12] Fault protection system (108, 109a-e, 164) according to one of claims 9-11, which further comprises several circuit breakers (104) and several fault circuits (116, 118), wherein each fault circuit (116, 118) is configured to receive the power supply signal. [13] Fault protection system (108, 109a-e, 164) according to one of claims 1-12, which further comprises a voltage limiter (126) connected between a first power source and the second power supply connection. [14] Fault protection system (108, 109a-e, 164) according to one of claims 1-13, wherein the power supply circuit comprises: a first diode (120) which is coupled from the first power supply terminal to the fault circuit, and a second diode (122) which is coupled from the second power supply terminal to the fault circuit. [15] Fault protection system (108, 109a-e, 164) according to one of claims 1-14, wherein the power supply circuit comprises an active rectifier circuit. [16] Method for operating a fault protection system (108, 109a-e, 164) wherein the method comprises: during a first operating mode, receiving a main power supply from a system supply circuit, wherein operation in the first operating mode is carried out if the main power supply has no detected faults; and during a second operating mode, receiving a secondary power supply from a fault mode control circuit (112) as a fault mode control signal (F MC ), whereby operation is carried out in the second operating mode if the main power supply has a detected fault. [17] Method according to claim 16, which further comprises detecting a fault in the main power supply in the fault mode control circuit (112), wherein the detection of the fault comprises determining whether a voltage value of the main power supply is below a first threshold. [18] The method of claim 16 or 17, which further comprises: Receiving a fault signal from a circuit breaker (104); Incrementing an error count based on the error signal; Deactivating the circuit breaker (104) if the number of faults exceeds a first fault threshold; and Keep the circuit breaker in a disabled state until the number of faults falls below the first fault threshold. [19] Method according to one of claims 16-18, which further comprises generating the main power supply in the system supply circuit using a voltage regulator (114) connected to a battery. [20] Method according to claim 19, which further comprises generating the secondary power supply in the fault mode control circuit using a voltage limiter (126). [21] Benefit provision system (100), which includes the following: several circuit breakers (104) which are set up to be connected to a power supply and to deliver power to several loads; multiple switch drivers for supplying control signals to the multiple circuit breakers and for receiving a fault mode control signal; Several fault protection circuits (108, 109a-e, 164) configured to supply deactivation signals to the several switch drivers, the several fault protection circuits being configured to be connected to a supply voltage and to receive several fault signals from the several circuit breakers; and a supply circuit (112, 114, 126) connected to the multiple fault protection circuits (108, 109a-e, 164), wherein the supply circuit (112, 114, 126) is configured to supply the supply voltage from a first system supply source to the multiple fault protection circuits during a first operating mode and to supply the supply voltage from the fault operating mode control signal (F) during a second operating mode MC ) to supply to the multiple fault protection circuits. [22] Power supply system (100) according to claim 21, wherein the first system supply source is generated by a voltage regulator (114) connected to the power supply. [23] Power supply system (100) according to claim 22, wherein the power supply comprises a battery. [24] Power supply system (100) according to one of claims 21-23, wherein the power supply system is an automotive system the multiple loads include multiple automotive loads, and the second operating mode includes an emergency driving mode for the automotive system. [25] Power supply system (100) according to one of claims 21-24, wherein The first operating mode is executed when a voltage value of the first system supply source exceeds an operating threshold, and The second operating mode is executed when the voltage value of the first system supply source is below the operating threshold. [26] Service provision system (100) according to one of claims 21-25, wherein The first operating mode is executed if the first system supply source has no detected faults, and The second operating mode is executed if the first system supply source has a detected fault. [27] Power supply system (100) according to claim 26, which further comprises a system monitor circuit configured to detect faults and to supply the fault mode control signal. [28] Power supply system (100) according to one of claims 21-27, wherein the multiple fault protection circuits (108, 109a-e, 164) comprise multiple fault counters (116, 117a, 117b), each of the fault counters (116, 117a, 117b) being configured, to receive a fault signal from a corresponding circuit breaker of the multiple circuit breakers (104), to increment a fault count for the corresponding circuit breaker (104) based on the fault signal, and to deactivate the corresponding circuit breaker when the fault count for the corresponding circuit breaker (104) exceeds a first fault threshold, wherein each of the fault counters (116, 117a, 117b) keeps the corresponding circuit breaker (104) in a deactivated state until the fault count for the corresponding circuit breaker (104) falls below the first fault threshold.

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