Device and method for processing an input signal voltage

Abstract

Circuit for processing an input signal voltage, comprising: an input capacitance (45) coupled between an input node (43) of the circuit and a sampling node (51) of a comparator (55); and a reference capacitance (30) coupled to the sampling node (51) of the comparator (55); a common-mode switch (54) coupled between the sampling node (51) and a reference node (52) of the comparator (55), wherein the circuit is configured such that the input node (43) is set to the input signal voltage while the common mode switch (54) is open.

Description

[0001] The present disclosure relates to a circuit for processing an input signal voltage using a threshold voltage.

[0002] In recent years, voltage comparators have become typical components in microcontrollers. Typically, the accuracy of the comparator is important.

[0003] The accuracy of a comparator can be achieved at the time of manufacture of a device containing the comparator. For a given input voltage, the comparator can be tuned to provide an expected output. However, there is a need for comparators that are accurate over the long term, that is, despite long-term effects that are negligible at the time of manufacture.

[0004] There is often a need for a comparator to continuously sample an input signal. Comparators that accurately sample an input signal continuously tend to be complex, and therefore such comparators are slow. However, there is also a need for comparators that are fast.

[0005] Furthermore, the output of continuous-time comparators tends to toggle when the input signal is close to a comparator threshold. Traditionally, a positive feedback loop is used to reduce toggle switching. However, a positive feedback loop that is accurate and fast requires a lot of area and consumes a lot of power. There is a desire to reduce the surface area required for circuitry related to positive feedback and / or to reduce the power consumption associated with suppressing toggle switching.

[0006] US 2014 / 0 184 435 A1 describes a feedback circuit that includes a comparator having a positive input coupled to a first node and a negative input coupled to a second node. The circuit includes a switch that, when closed, short-circuits the inputs of the comparator. In a path from signal inputs in the circuit to the inputs of the comparator, the circuit includes a capacitor that can be separated from the input to the circuit by a switch and from the respective input to the comparator by a switch. Feedback capacitors are coupled to the first node and the second node, respectively. In a detection phase, the converter switches are open, while those switches that allow the input voltage to be applied to the capacitors are closed. During the detection phase, switches are closed to short-circuit the input lines.

[0007] The independent claims define the invention in various aspects. The dependent claims set forth the embodiments according to the invention in various aspects. In the following, the disclosure will be further explained and described by means of specific exemplary embodiments with reference to the accompanying drawings.

[0008] In one aspect, a circuit for processing an input signal voltage includes an input capacitance coupled between an input node of the circuit and a sampling node of a comparator, and a reference capacitance coupled to the sampling node of the comparator.

[0009] In one aspect, a method for processing an input signal voltage comprises configuring a reference capacitance coupled to an input capacitance; during a charging phase, charging the reference capacitance to a reference voltage of a first level and obtaining a threshold voltage at a sensing node between the reference capacitance and the input capacitance; during an operating phase, setting the input capacitance to the input signal voltage to obtain a sensing voltage at the sensing node; and forming a digital signal representing that the sensing voltage is above or below the threshold voltage, e.g., positive or negative.

[0010] In one aspect, a circuit for processing an input signal voltage comprises a comparator including a sensing node coupled to an input terminal for the input signal voltage and a reference capacitance coupled to the sensing node, wherein the reference capacitance is configurable based on an output signal of the comparator.

[0011] In one aspect, a method for processing an input signal voltage comprises storing charge in a reference capacitance; setting an input capacitance to the input signal voltage, wherein the reference capacitance and the input capacitance share a common node; and setting a sensing node of a comparator to a voltage at the common node, wherein charge redistribution between the input capacitance and the reference capacitance across the common node is based on an output signal of the comparator.

[0012] In one aspect, a circuit for processing an input signal voltage comprises a first comparator comprising a sensing node of the first comparator and an output node of the first comparator; a second comparator comprising a sensing node of the second comparator and an output node of the second comparator; a comparator select switch coupled between a path input terminal of the circuit and the sensing node of the first comparator and the sensing node of the second comparator; and an output circuit coupled to the output of the first comparator and the output node of the second comparator.wherein the comparator selection switch is configured to connect the path input terminal to at least one of the sampling node of the first comparator and the sampling node of the second comparator, and wherein the output circuit is configured to form a comparator output signal of the circuit based on an output signal of the first comparator received by the output node of the first comparator and / or on an output signal of the second comparator received by the output node of the second comparator;

[0013] In one aspect, a circuit for processing an input signal voltage comprises a first comparator including a sensing node of the first comparator and a reference capacitance coupled to the sensing node of the first comparator; a second comparator including a sensing node of the second comparator; and a comparator select switch coupled between a path input terminal of the circuit and the sensing node of the first comparator and the sensing node of the second comparator, the comparator select switch configured to selectively couple the path input terminal to one of the sensing node of the first comparator and the sensing node of the second comparator.

[0014] In one aspect, a circuit for processing a plurality of input signal voltages comprises a plurality of path input terminals coupled to a plurality of path output terminals via a plurality of comparators arranged in parallel, wherein the plurality of comparators comprises more comparators than there are path input terminals coupled to the path output terminals; and an output circuit coupled to a plurality of output nodes of the plurality of comparators, wherein the output circuit is configured to form a plurality of comparator output signals of the circuit based on a logical combination of a plurality of output signals received from the plurality of comparator output nodes.

[0015] In one aspect, a circuit for processing a plurality of input signals comprises a plurality of path input terminals coupled to a plurality of path output terminals via a plurality of comparators arranged in parallel, wherein the plurality of comparators comprises more comparators than there are path input terminals coupled to the path output terminals.

[0016] In one aspect, a method for processing at least one input signal voltage in a circuit, the circuit including at least one path input terminal coupled to at least one path output terminal via a plurality of comparators, and the plurality of comparators including more comparators than there are path input terminals coupled to the path output terminals, comprises, for each path input terminal, selectively establishing a coupling via one comparator of two comparators provided in parallel to form a coupling path from the path input terminal to an associated path output terminal, while interrupting the coupling via the other comparator.

[0017] The novel features believed to be characteristic of the invention are set forth in the appended claims. However, the invention itself, as well as a mode of its use, further objects, and advantages, will best be understood by reference to the following detailed description of an illustrative embodiment, when read in conjunction with the accompanying drawings, in which: Fig. 1 shows a block diagram schematically illustrating a circuit in a first embodiment. Fig. 2 shows a block diagram showing an exemplary detail of the Fig. 1 shown circuit. Fig. 3 shows a block diagram showing an exemplary detail of the Fig. 1 shown circuit. Fig. 4 shows a block diagram showing an exemplary detail of the Fig. 1 shown circuit. Fig. 5 is a schematic diagram illustrating a circuit in a third embodiment. Fig. 6 shows a table showing the states of the circuit in Fig. 5 illustrates. Fig. 7 is a schematic diagram illustrating a circuit in a third embodiment. Fig. 8 shows a table showing the states of the circuit in Fig. 7 illustrates. Fig. 9 is a schematic diagram illustrating a circuit in a second embodiment. Fig. 10 shows a table showing the states of the circuit in Fig. 9 illustrates.

[0018] The present disclosure will now be described with reference to the figures of the accompanying drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As used herein, like terms refer to like elements throughout the description. In some cases, well-known features have been omitted or simplified to clarify the description of the example implementations.

[0019] In one embodiment, a circuit in a comparator unit for processing an input signal voltage VIN using a threshold voltage VTH includes an input capacitance coupled between an input node of the circuit and a sensing node of a comparator, and a reference capacitance provided as a capacitive network coupled to the sensing node of the comparator. The comparator unit is also referred to herein as a comparator function circuit block.

[0020] Fig. 1 shows a block diagram schematically illustrating a circuit in one embodiment. The circuit is configured as a comparator function circuit block 100, also referred to as a 'comparator block' for short. The comparator function circuit block 100 includes an input section 44 coupled to an input terminal 10 of the comparator block 100 and to a ground terminal 11. The comparator block 100 includes a comparator circuit section 50 coupled to the input section 44 and to an output terminal 70. The comparator block 100 further includes a reference capacitance 30 coupled to the input section 44 and to the comparator circuit section 50 via a sampling node 40.

[0021] In some embodiments, in addition to coupling the reference capacitance 30 via the sensing node 40 to the comparator circuit section 50, a control connection 60 is provided to couple the comparator circuit section 50 to the reference capacitance 30. In some embodiments, the control connection 60 is configured to provide an output signal from the comparator circuit section 50 as a control signal of the reference capacitance 30, e.g., for use in controlling the capacitive network in the reference capacitance 30. In some embodiments, the control connection 60 includes a control unit 64 configured to process an output signal, e.g., a digital output signal voltage VOUT, received from the comparator circuit section 50 and to form the control signal based on the output signal.In some embodiments, the control unit 64 is configured to process an external control signal provided to the control unit 64 via an external control connection 62. In some embodiments, the control unit 64 is configured to control the configuration of the capacitive network of the reference capacitance 30, e.g., the switch settings, based on at least one of the output signals from the comparator circuit 50 and the external control signal. In some embodiments, the control unit 64 is configured to control the input section 44. The control unit 64 may be any processing means, e.g., a microcontroller, or a programmable logic device, specifically configured or adapted to perform the actions described herein. The control unit 64 may be co-located with the comparator block 100 or may form a portion of the comparator block 100.In some embodiments, the control unit 64 is located outside the comparator block 100.

[0022] Furthermore, the reference capacitance 30 is coupled to a first-level reference voltage node 33 and to a second-level reference voltage node 34. In some embodiments, the reference capacitance 30 is coupled to one or more (not shown) further-level reference voltage nodes, such as a third-level reference voltage node. The reference capacitance 30 may be provided as a capacitive network. Consequently, the reference capacitance 30 may include multiple capacitances. In general, the reference capacitance 30 may be configurable with respect to the size of the capacitance connected to either the first-level reference voltage node 33 or the second-level reference voltage node 34.As described in an example below, when the reference capacitance 30 is provided as a capacitive network, at least one capacitance of the plurality of capacitances of the capacitive network may be provided as a switched capacitance that is selectively controllable to configure the capacitive network.

[0023] Now, the structure and operation of the comparator function circuit block 100 (the comparator block 100) will be described in more detail.

[0024] Fig. 2 shows a block diagram showing an exemplary detail of the Fig. 1. In general, the comparator circuit section 50 may include a comparator circuit 55 configured to operate as a differential comparator having a first sampling node and a second sampling node. In some embodiments, the first sampling node of the comparator circuit 55 is also the sampling node of the comparator circuit section 50, whereas the second sampling node of the comparator circuit 55 is used as a reference node that can be maintained within the comparator circuit section 50. The comparator circuit 55 may be configured to form an output signal voltage VOUT representative of a voltage difference between the sampling node and the reference node, which is positive or negative. Consequently, the output signal is in fact digital, i.e., it represents a logical "0" and a logical "1."

[0025] Still regarding the Fig. 2, the comparator circuit section 50 includes the comparator circuit 55, which has the first sensing node 51, the second sensing node 52, and an output node 57. The first sensing node 51 may be set to a sensing node voltage VSN. The second sensing node 52 may be set to a threshold voltage VTH. The comparator circuit 55 is configured to compare the sensing node voltage VSN at the first sensing node 51 with the threshold voltage VTH at the second sensing node 52 and to output an output signal voltage VOUT at the output node 57 indicating that either the sensing node voltage VSN is greater than the threshold voltage VTH or the threshold voltage VTH is greater than the sensing node voltage VSN. Consequently, the output signal from the comparator circuit 55 is digital.

[0026] Still regarding the Fig. In the embodiment illustrated in Figure 2, the circuit may further include a common-mode switch 54 coupled between the first sensing node 51 and the second sensing node 52 of the comparator circuit 55. The first sensing node 51 and the second sensing node 52 may be connected via the common-mode switch 54.

[0027] The output node 57 is coupled to the control connection 60 via a branch node 53. Based on the output signal voltage VOUT, the control connection 60 can transmit an output signal from the comparator circuit 55. The control connection can be implemented as a wired line. A wireless implementation can also be considered, e.g., to filter noise from the output signal to be transmitted via the control connection or to otherwise reduce the effect of noise on the output signal. As described above with respect to Fig. 1, the control connection 60 can be the (in Fig. 2) control unit 64. In some embodiments, the second sampling node 52 of the comparator circuit 55 is coupled to a bias output node (not shown) of the comparator via the common-mode switch 54. At least one effect may be that an offset of the comparator circuit 55 can be adjusted using an external bias voltage.

[0028] In general, the circuit of the comparator function circuit block 100 may include an input terminal configured to be set to the input signal voltage VIN. An input switch may be coupled between the input terminal and the input node. In some embodiments, the circuit further includes a reference terminal configured to be set to a reference input voltage and a reference switch coupled between a reference terminal and the input node, wherein the reference switch is configured to be closed when the common-mode switch is closed. In some embodiments, the reference terminal is configured to be set to a supply voltage. In some embodiments, the reference terminal is configured to be set to a voltage at ground VGND.

[0029] Fig. 3 shows a block diagram showing an exemplary detail of the circuit of the Fig. 1. The input section 44 of the circuit in the comparator block 100 includes an input capacitance 45 having a first conductor coupled to the input terminal 10 via an input node 43 and an input switch 41. Furthermore, the first conductor is coupled to the ground terminal 11 via the input node 43 and a ground switch 42. The input capacitance 45 has a second conductor coupled to the sampling node 40. In some embodiments, the circuit is configured to have the input node 43 set to the input signal voltage VIN while the common mode switch 54 is open. In some embodiments, the input switch 41 is configured to be open during a charging phase of 'refreshing' the charge in the input capacitance 45 and the reference capacitance 30 and during an operating phase of the circuit, in which, for example,the input signal voltage is to be sampled. In some embodiments, the comparator block 100 is configured to have the input capacitance 45 set to a reference input voltage level VGND, while the common-mode switch 54 is closed. Consequently, if the common-mode switch 54 is closed, the first sampling node 51 and the second sampling node 52 are set to the same voltage, i.e., VTH = VSN. Furthermore, the comparator block 100 can be configured to have an input capacitance 45 set to the reference input voltage level VGND to charge the reference capacitance 30.

[0030] In some embodiments, in general, the at least one switched capacitance is coupled to a first-level reference node via a first-level switch, while being coupled to a second-level reference node via a second-level switch. In some embodiments, the first-level switch and / or the second-level switch may be selectively controlled to configure the reference capacitance. In some embodiments, the first-level switch and the second-level switch are configured so that they are not simultaneously closed or simultaneously open. Nevertheless, it should be recognized that in some implementations, during a process of switching, i.e.During a process of changing the setting of the switch from open to closed or from closed to open, a temporary open state may occur in which both the first-level switch and the second-level switch are open; similarly, in some implementations, a temporary closed state may occur in which both the first-level switch and the second-level switch are closed. In some embodiments, the first-level switch and the second-level switch are integrated to form a toggle switch configured to establish a connection between the switched capacitance and either the first-level reference node or the second-level reference node.

[0031] Fig. 4 shows a block diagram showing a further exemplary detail of the circuit in the Fig. 1. The capacitive network of the reference capacitor 30 includes a first switched capacitor 31 and a second switched capacitor 32. While in the Fig. 4, the capacitive network includes two switched capacitors, any other number of switched capacitors may be implemented as needed. In the embodiment illustrated in Fig. 4, a capacitance value of the first switched capacitance 31 and a capacitance value of the second switched capacitance 32 are equal. However, in another implementation, the capacitance value of the first switched capacitance 31 is twice the capacitance value of the second switched capacitance 32. If the capacitive network includes multiple switched capacitances, they may generally be fabricated in a thermometer style, i.e., each having the same capacitance value, or they may be dimensioned in a binary style, i.e., with capacitance values ​​that are a predetermined minimum capacitance value times a power of two, where the capacitance values ​​of no two of the switched capacitances have no capacitance value and are the same. A first conductor of the first switched capacitance 31 and a first conductor of the second switched capacitance 32 are coupled to the sensing node 40.A second conductor of the first switched capacitance 31 is coupled to a first-level reference voltage node 33 via a first-level switch 35. Furthermore, a second conductor of the first switched capacitance 31 is coupled to the second-level reference voltage node 34 via a second-level switch 36. The second conductor of the second switched capacitance 32 is coupled to the first-level reference voltage node 33 via a first-level switch 37. Furthermore, the second conductor of the second switched capacitance 32 is coupled to the second-level reference voltage node 34 via a second-level switch 38. The first-level switches 35, 37 and the second-level switches 36, 38 are coupled to the control connection 60 and configured to switch individually according to the control signal provided via the control connection 60.In some implementations, a pair of first-level switch 35 and second-level switch 36 in the case of the first switched capacitor 31 (first-level switch 37 and second-level switch 38 in the case of the second switched capacitor 32) is configured such that the first-level switch and the second-level switch cannot be closed simultaneously. In some embodiments, the first-level reference voltage node 33 is set to a first-level reference voltage, e.g., a predetermined and / or constant positive reference voltage VRP, while the second-level reference voltage node 34 is set to a second-level reference voltage, e.g., a predetermined and / or constant negative reference voltage VRN.In some implementations, the voltage difference between the first level reference voltage and the second level reference voltage may be based on a semiconductor band gap.

[0032] In some embodiments, the (in Fig. 4) is configured to control the reference capacitor 30. In particular, in some implementations, the control unit 64 is configured to control the at least one switched capacitor 31, 32. The control unit 64 may be configured to control a capacitor (not shown in Fig. 4) to process the signal received by the comparator circuit section 50 to configure the reference capacitance 30 based on the signal. The control unit 64 may, for example, be provided as a logic circuit. In some implementations, the logic circuit is configured to process the signal received by the comparator circuit section 50 as a digital signal. In some embodiments, the control unit 64 is configured to base the control of the at least one switched capacitance 31, 32 on the comparator output signal formed while the input node 43 is set to the reference input voltage level VGND. In some embodiments, the control unit 64 is configured to control the switched capacitance 31, 32 to compensate for a comparator offset voltage at the sampling node 51.In some embodiments, the switched capacitance control unit is configured to control the switched capacitance 31, 32 to set an effective threshold voltage to a predetermined value. The control unit 64 may, for example, be configured to output a plurality of digital switching signals, each digital switching signal controlling a switched capacitance of the plurality of switched capacitances 31, 32. In such an implementation, the control connection 60 may include a plurality of control lines, each to be connected to a different one of the first-level switches 35, 37 and the second-level switches 36, 38. In some embodiments, the switched capacitance control unit is configured to control the common-mode switch 54 so that the common switch 54 is closed while the first-level switch 35, 37 is closed. At least one effect may be that the reference capacitance 30, for example,during a charging phase provided to recharge the reference capacitance to the first-level reference voltage VRP. In some embodiments, the control unit is configured to repeatedly charge the reference capacitance 30. In some embodiments, the control unit is configured to periodically charge the reference capacitance 30. A duration of a period may be constant and predetermined. In some implementations, the duration may be subject to control by the control unit 64.

[0033] Now, in operation of the comparator function circuit block 100, the input terminal 10 is set to an input signal voltage VIN. Accordingly, the input signal voltage VIN is supplied to the input section 44. Furthermore, the input section 44 can tap a voltage at ground VGND using the ground terminal 11. In some embodiments, the method further comprises, during the charging phase, charging the input capacitance 45 to a reference input voltage level VGND. It should be appreciated that the voltage at ground VGND can be any reference voltage defined as ground for the purpose of a given implementation. The input section 44 contributes a sensing node voltage VSN at the sensing node 40, which is also applied to the comparator circuit section 50. The comparator circuit section 50 provides an output signal voltage VOUT to the output terminal 70 of the comparator function circuit block 100.Furthermore, the comparator circuit section 50 sets the control connection 60 to a control signal. The control signal is applied to the reference capacitance 30. The reference capacitance 30 taps the positive reference voltage VRP at the first-level reference voltage node 33 and the negative reference voltage VRN at the second-level reference voltage node 34. Furthermore, the capacitive network of the reference capacitance 30 contributes to the sensing node voltage VSN at the sensing node 40. At least two modes, states, or phases of operation can be distinguished according to how the switches in the comparator block 100 are set. A charging phase and an operating phase are discussed in more detail below. Additionally, in at least some implementations, a calibration phase and / or one or more types of transition phases can be distinguished.

[0034] First, the comparator function circuit block 100 is initialized. For this purpose, the charging phase is entered. During the charging phase, the ground switch 42 in the input section 44 is closed, while the input switch 41 is open. This will be discussed further below when refreshing the charges in the capacitors 31, 32, 45 of the circuit is described. In the comparator circuit section 50, the common-mode switch 54 is closed. Consequently, the threshold voltage VTH is set at both the first sensing node 51 and the second sensing node 52. In the capacitive network of the reference capacitor 30, the first switched capacitor 31 and the second switched capacitor 32 can be controlled by a control signal. The control signal can be based on an output signal voltage VOUT of the comparator circuit 55 and can be provided via the signal connection 60.Control of the first switched capacitance 31 may be performed using the first-level switch 35 and the second-level switch 36. Control of the second switched capacitance 32 may be performed using the first-level switch 37 and the second-level switch 38. In some implementations, control is performed such that the charge in the first switched capacitance 31 and the second switched capacitance 32 contributes to the sensing node voltage VSN to provide the effective threshold voltage of the comparator block 100 when needed. Consequently, the comparator block 100 may be set to a desired effective threshold voltage. In some implementations, the initialization phase may be performed whenever an adjustment of the effective threshold voltage is desired.

[0035] In some implementations, the initialization is extended to perform further calibration of the comparator circuit portion 50, for example, to account for a comparator offset introduced when the common mode switch 54 is opened from the closed setting during the charging phase.

[0036] Next, the operating phase is entered. During the operating phase, in the input section 44, the input switch 41 is closed, while the ground switch 42 is open. The input capacitance 45 is charged according to a difference from the sampling node voltage VSN to the input signal voltage VIN. Consequently, the input capacitance 45 effectively divides the voltage VIN to provide a voltage contribution VIN' = a * VIN at the common node 40, where a is any factor that can be less than 1. In the comparator section, the common-mode switch 54 is open. Consequently, the comparator circuit 55 is operable to compare the sampling node voltage VSN applied to the first comparator sampling node 51 with the threshold voltage VTH applied to the second comparator sampling node 52.Because the first comparator sampling node 51 and the second comparator sampling node 52 form high-resistance elements, the first comparator sampling node 51 and the second comparator sampling node 52 barely affect the sampling node voltage VSN. However, because in the capacitive network of the reference capacitance 30, the first switched capacitance 31 and the second switched capacitance 32 are individually connected to one of the first-level reference voltage VRP and the second-level reference voltage VRN, as described above with respect to initialization, the charge of the first switched capacitance 31 and the second switched capacitance 32 may contribute to the sampling node voltage VSN. One effect may be that, while the sampling node voltage VSN tracks the input signal voltage VIN, the sampling node voltage VSN may be shifted by a constant voltage VCN with respect to the input signal voltage VIN, such that VSN = a * VIN + VCN.Consequently, a difference deltaVIN in the input signal voltage is reflected in a difference deltaVSN in the sampling node voltage deltaVSN = a * deltaVIN, where the constant voltage VCN causes a constant shift of the effective threshold voltage with respect to the threshold voltage VTH. While the constant voltage VCN is constant in the sense that it is independent of the input signal voltage VIN, it can nevertheless be varied by switching the first switched capacitance 31 and by switching the second switched capacitance 32 either to the first-level reference voltage VRP or to the second-level reference voltage VRN, as explained above with respect to the initialization phase, to store a charge of the capacitive network as a sum of the charge in the first switched capacitance 31 and the second switched capacitance 32 together.There is no shift in the sampling node voltage VSN as long as the voltage across the input capacitance remains constant. If the input signal voltage VIN changes, the comparator output signal voltage may change, and the control unit 64 may provide a control signal to the capacitive network of the reference capacitance 30 to switch one or more of the first-level switches and the second-level switches.

[0037] Consequently, the charge can be redistributed between the switched capacitors 31, 32, and the input capacitor 45 can be changed. Therefore, the constant voltage VCN is changed. Due to the rebalancing of the charges in the input capacitor 45 and in the capacitive network of the reference capacitor 30, a new effective threshold voltage of the comparator function circuit block 100 is obtained. Consequently, even if the input signal voltage VIN is constant, switching one or more of the switched capacitors 31, 32 can change the output signal at the output node of the comparator 55.

[0038] During the next charging phase, in the comparator section, the common-mode switch 54 is closed again, and the comparator circuit 55 is operable to compare the sampling node voltage VSN applied to the first comparator sampling node 51 with the threshold voltage VTH applied to the second comparator sampling node 52. In some implementations, for example, by coupling the second comparator sampling node 52 to the comparator's bias output node (not shown), the threshold voltage VTH can be set to a bias point of the comparator 55. However, in the input section 44, the input switch 41 is open. Therefore, the sampling node voltage VSN is no longer based on the input signal voltage VIN.Meanwhile, the ground switch 42 is closed, and the input capacitance 45 is charged according to a difference from the sensing node voltage VSN to the ground voltage VGND, thereby in effect refreshing a charge of the input capacitance. Accordingly, the charging phase may also be referred to as a refresh phase. As described above, the charging phase is performed, for example, during initialization when the input capacitance 45 and / or the reference capacitance 30 are charged for use during the operating phase, during which the comparator circuit 55 processes the input signal voltage VIN to provide the sensing node voltage VSN for comparison with the threshold voltage VTH. Furthermore, the charging phase effects a refresh when the input capacitance 45 and / or the reference capacitance 30 are recharged to replace the charge that escaped from the respective capacitance, for example, during a previous operating phase.In contrast, in a case where the reference capacity 30 is provided as the plurality of capacities, during the operation phase, the charge can be redistributed from one capacity to another of the plurality of capacities.

[0039] An exemplary method for processing the input signal voltage VIN to provide the sampling node voltage VSN for comparison with the threshold voltage VTH includes configuring the reference capacitance 30 coupled to the input capacitance 45; during the charging phase, charging the reference capacitance 30 to the first level reference voltage VRP to obtain the sampling node voltage VSN at the sampling node 40 between the reference capacitance 30 and the input capacitance 45; during the operating phase, setting the input capacitance 45 to the input signal voltage VIN to obtain the sampling node voltage VSN at the sampling node 40; and forming an output signal voltage VOUT that is digital and represents a difference between the threshold voltage VTH and the sampling node voltage VSN, which is positive or negative.Another exemplary method for processing the input signal voltage VIN to compare the sensing node voltage VSN to the threshold voltage VTH includes storing charge in the reference capacitance 30; setting the input signal voltage VIN to the input capacitance 45, wherein the reference capacitance 30 and the input capacitance 45 share the sensing node 40 as a common node; and setting the first sensing node 51 of the comparator circuit 55 to the sensing node voltage VSN at the sensing node 40, wherein the charge of the reference capacitance 30 is based on the output signal VOUT of the comparator circuit 55. In some embodiments, configuring the reference capacitance 30 is based on the output signal VOUT of the comparator circuit 55. At least one effect may be that, depending on a configuration of the reference capacitance 30, an amount of charge in the reference capacitance 30 can be controlled.

[0040] In some embodiments, the method generally includes a first mode of operation in which the comparator performs a comparison and a second mode of operation in which the comparator performs a reset. In some implementations, the method includes, during the charging phase, configuring the reference capacitance 30 to compensate for the comparator offset voltage at the first sensing node 51 of the comparator circuit 55. In some embodiments where the reference capacitance is provided as the plurality of switched capacitances 31, 32, configuring the reference capacitance 30 includes selectively switching the switched capacitances 31, 32. The switched capacitances 31, 32, when charged, may use one of at least a first reference voltage level VRP and a second reference voltage level VRN.Thus, in some embodiments, the method further comprises selectively setting the reference capacitance 30 to the second level reference voltage VRN, wherein the second level reference voltage VRN is below the first level reference voltage VRP and the input signal voltage VIN is above the reference input voltage level VGND, or wherein the second level reference voltage is above the first level reference voltage and the input signal voltage is below the reference input voltage. In some implementations, configuring the reference capacitance is performed when the comparator performs the comparison. The method may further comprise, after storing the charge in the reference capacitance 30, redistributing the charges in the reference capacitance 30 and in the input capacitance 45.

[0041] In some embodiments, a difference between the first reference voltage level VRP and the second reference voltage level VRN is based on a bandgap voltage. In some embodiments, the method includes, during the charging phase, feeding back an output signal voltage VOUT based on the digital signal to the first sensing node 51. The method further includes, in some implementations with the comparator circuit being a differential comparator circuit, forming the digital signal to represent the voltage difference between the first sensing node and the second sensing node, which is positive or negative.

[0042] In one implementation, controlling the redistribution of charge in reference capacitance 30 and input capacitance 45 in a positive feedback scheme, sometimes referred to as hysteresis, can be used to prevent the digital output signal voltage VOUT from toggling. Conventionally, toggling can occur in a situation where an ideal input signal voltage, i.e., one that exhibits a smooth evolution over time without noise, would simply 'cross' the threshold voltage, i.e., rise close to the threshold voltage, equal to the threshold voltage, and then exceed the threshold voltage, or vice versa.In practice, however, there is a tendency for noise in the input signal voltage and / or the threshold voltage close to crossing the threshold voltage to provide a non-smooth evolution of the input signal voltage, which, when compared with the threshold voltage, results in multiple crossings within a short time interval. In this case, the digital output signal voltage switches back and forth. In contrast, the comparator function circuit block 100 described here can be configured in one implementation such that, upon detection of a change in the digital output signal voltage VOUT, the reference capacitance 30 is configured to effectively magnify a difference between the sampling node voltage VSN (the input signal voltage VIN) at the first sampling node 51 of the comparator circuit 55 and the threshold voltage VTH at the second sampling node 52 of the comparator circuit 55.In some implementations, the control unit 64 is configured to provide a control signal to the capacitive network of the reference capacitance 30, which, for example, switches the first switched capacitance 31 and / or the second switched capacitance 32. Consequently, in some embodiments, it can be achieved that most noise does not affect the input signal voltage VIN as much as the voltage difference from the sampling node voltage VSN to the threshold voltage VTH. In some implementations, the comparator function circuit block can include a switched hysteresis capacitance configured to store an amount of charge corresponding to a predetermined threshold voltage difference. In one example, the switched hysteresis capacitance forms part of the capacitive network of the reference capacitance 30. The switched hysteresis capacitance is, for example,as the second switched capacitance 32 dedicated for use in suppressing the effects of noise, which, as described above, is switched regardless of the switching states of the other first switched capacitance(s) 31 of the capacitive network of the reference capacitance 30. In some implementations, the control unit may be configured to switch back the switched hysteresis capacitance after a predetermined interval has elapsed since the switching of the switched hysteresis capacitance. Thus, after a crossing is first detected, the predetermined interval may be used for future switching of the switched hysteresis capacitance if the input signal voltage changes periodically.In particular, in some implementations, the switching may be controlled to occur even slightly before the crossing occurs to further suppress any occurrence of toggling of the digital output voltage.

[0043] More generally, in one aspect, a circuit for processing an input signal voltage comprises a voltage processing device including a sensing node coupled to an input terminal for the input signal voltage. The circuit, in some embodiments, comprises an input capacitance coupled between the sensing node and the input terminal. The circuit includes a reference capacitance coupled to the sensing node. In some embodiments, the reference capacitance and the input capacitance share a common node coupled to the sensing node. In some embodiments, the reference capacitance is configurable based on an output signal of the voltage processing device. In some embodiments, the input capacitance is configurable based on an output signal of the voltage processing device.The voltage processing device may be configured to form an output signal voltage based on a voltage at the sensing node. In some embodiments, the voltage processing device is provided as a comparator configured to form the output signal voltage based on a comparison of the voltage at the sensing node with a threshold voltage.

[0044] Some embodiments of the circuit further comprise a control unit configured to configure the reference capacitance and / or the input capacitance based on the signal received from the voltage processing device. In some embodiments, the control unit is provided as a logic circuit configured to process the signal received from the voltage processing device as a digital signal. In some embodiments, the voltage processing device is configured to operate in at least a first operating mode in which the voltage processing device performs processing of the voltage at the sensing node to form the output signal voltage. The voltage processing device may, for example, be provided as a comparator configured to perform a comparison of the voltage at the sensing node with a threshold voltage.Furthermore, the voltage processing device may be configured to operate in a second operating mode in which the circuit performs a reset. For example, the voltage processing device performs a reset. In some embodiments, the control unit is configured to configure the reference capacitance to change an amount of charge in the reference capacitance when the voltage processing device processes the voltage at the sensing node by comparing the voltage at the sensing node with the threshold voltage, e.g., when the voltage processing device is provided as a comparator.

[0045] In some embodiments, the reference capacitance is coupled to a first-level reference node via a first-level switch. In some embodiments, the reference capacitance is coupled to a second-level reference node via a second-level switch. A difference between a voltage at the first-level reference node and a voltage at the second-level reference node may be based on a bandgap voltage. In some embodiments, the difference between the voltage at the first-level reference node and the voltage at the second-level reference node is ratiometrically predetermined or is ratiometrically determined during operation of the circuit.

[0046] In some embodiments, the reference capacitance is configurable in terms of size. In some implementations, the reference capacitance is provided, for example, as a plurality of switched capacitances. In some embodiments, the input capacitance is configurable in terms of size. In some implementations, the input capacitance is provided, for example, as a plurality of switched capacitances. In some embodiments, both the reference capacitance and the input capacitance include at least one switched capacitance. The at least one switched capacitance may be controllable by the control unit. In some implementations, the control unit is provided as a logic circuit configured to output a plurality of digital switching signals, each digital switching signal to control a switched capacitance of the plurality of switched capacitances.In some embodiments, the reference capacitance or the input capacitance includes a switched hysteresis capacitance configured to contribute a predetermined charge to the charge redistribution based on the output signal voltage.

[0047] As described above with respect to the comparator functional block, controlling the redistribution of charge in the reference capacitance and in the input capacitance can generally be used in a feedforward scheme. The feedforward scheme can be implemented in embodiments of a circuit having a voltage processing device configured to form an output signal voltage based on the voltage at the sensing node to prevent the digital output signal voltage from toggling. Therefore, in one aspect, a method for processing an input signal voltage includes storing charge in a reference capacitance and setting an input capacitance to the input signal voltage. The method further includes performing charge redistribution between the reference capacitance and the input capacitance.The method further includes deriving an output signal based on the charge redistribution. In some implementations, the output signal is based on a product of the voltage across the reference capacitance and the ratio of the size of the reference capacitance to the size of the charge in the input capacitance and the size of the charge in the reference capacitance.

[0048] In some implementations, the method further comprises setting a first voltage across the input capacitance to a first predetermined reset voltage value. In some implementations, the method further comprises setting a second voltage across the reference capacitance to a second predetermined reset voltage value. In some implementations, deriving the output signal is performed during a first mode of operation. In some implementations, setting the first voltage across the input capacitance and setting the second voltage across the reference capacitance are performed during a second mode of operation that is different from the first mode of operation. In some implementations, the method further comprises scheduling the first mode of operation and the second mode of operation in an alternating sequence.

[0049] In some implementations, the method further comprises, based on the output signal, configuring the size of the reference and / or configuring the size of the input capacitance and / or setting the voltage across the reference capacitance. In some implementations, the reference capacitance is provided as a plurality of switched capacitances, wherein configuring the reference capacitance includes selectively switching the switched capacitances. In some implementations, the switched capacitances, when charged, use one of at least a first reference voltage level and a second reference voltage level. In some implementations, a difference between the first reference voltage level and the second reference voltage level is based on one of a group comprising a bandgap voltage and a ratiometrically determined voltage.

[0050] In some implementations, deriving the output signal includes comparing a voltage at a node between the input capacitance and the reference capacitance to a threshold voltage. In some implementations, the method further comprises forming the output signal based on a result of the comparison.

[0051] Further implementations of the circuits and methods described above are now disclosed in a broader perspective. In general, an exemplary circuit for processing an input signal voltage includes a first comparator including a sensing node of the first comparator and an output node of the first comparator, and a second comparator including a sensing node of the second comparator and an output node of the second comparator. The circuit further includes a comparator select switch coupled between a common input terminal of the circuit, also referred to herein as a path input terminal, and the sensing node of the first comparator and the sensing node of the second comparator. The circuit further includes an output circuit coupled to the output of the first comparator and to the output node of the second comparator.In some implementations, the comparator selection switch is configured to connect the path input terminal to at least one of the sensing node of the first comparator and the sensing node of the second comparator. Further, the output circuit is configured to form a comparator output signal of the circuit based on an output signal of the first comparator received by the output node of the first comparator and / or an output signal of the second comparator received by the output node of the second comparator. In some embodiments, the second comparator is structurally provided like the first comparator. In some embodiments, the second comparator is configured to operationally complement the first comparator.At least one effect is explained below by way of example: when the first and second comparators are used in a complementary manner, a continuous comparison operation can be achieved in a case where one or both of the first and second comparators operate discontinuously.

[0052] If the setting of the comparator selection switch in some embodiments is to connect the path input terminal to a single one of the sensing node of the first comparator and the sensing node of the second comparator, the output circuit is configured to form the comparator output signal based on a corresponding one of the output signal of the first comparator and the output signal of the second comparator. In some embodiments, the circuit further comprises an input capacitance coupled between the comparator selection switch and the sensing node of the first comparator. In some embodiments, the comparator selection switch is configured to set the input signal voltage to the input capacitance, while the at least one switched capacitance is controlled to redistribute the charge in the input capacitance and the charge in the reference capacitance.

[0053] In some embodiments, the output circuit is configured to form the comparator output signal of the circuit based on a logical combination of the output signal of the first comparator and the output signal of the second comparator. In some embodiments, the logical combination is a logical AND. In some embodiments, the output circuit is configured to form the comparator output signal based on a setting of the comparator selection switch. In some embodiments, the output circuit is configured to form the comparator output signal based on the logical combination if the setting of the comparator selection switch is such that the input terminal is connected to both the sensing node of the first comparator and the sensing node of the second comparator.

[0054] In some embodiments, the circuit further comprises a reference capacitance coupled to the sensing node of the first comparator, wherein the reference capacitance comprises at least one switched capacitance that is selectively controllable. In some embodiments, the comparator selection switch is configured to disconnect the input terminal from the sensing node of the first comparator while controlling the at least one switched capacitance to set an effective threshold voltage to a predetermined value.

[0055] Fig. 5 shows a schematic diagram illustrating a circuit 500 in one embodiment configured to process an input signal voltage VIN using an (internal) threshold voltage VTH. The circuit 500 includes a common input terminal, also referred to herein as a path input terminal 511, a first comparator function circuit block (comparator block) 515 having a first comparator sampling node 514 coupled to the path input terminal 511 via a first comparator selection switch 512, and a second comparator block 525 having a second comparator sampling node 524 coupled to the path input terminal 511 via a second comparator selection switch 522. In some embodiments, the second comparator block 525 is structurally provided like the first comparator block 515.The first comparator block 515 and / or the second comparator block 525 are as described above with respect to the . Fig. 1 to 4 described comparator function circuit block 100 is configured.

[0056] In particular, a first reference capacitance may be coupled to the sampling node 514 of the first comparator. In some embodiments, the second comparator block 525 includes a second reference capacitance; the second reference capacitance may be coupled to the sampling node 524 of the second comparator. In some embodiments, the input switch of the comparator function circuit block 515, 525 implements or forms the comparator selection switch 512, 522.

[0057] In the Fig. 5, the first comparator selection switch 512 is controllable to couple the path input terminal 511 to the sampling node 514 of the first comparator, while the second comparator selection switch 522 is controllable to couple the path input terminal 511 to the sampling node 524 of the second comparator. In some embodiments, the first comparator selection switch 512 and the second comparator selection switch 522 are provided together as a toggle switch (not shown). In some embodiments, the circuit 500 further includes a first input capacitance coupled between the comparator selection switch and the sampling node 514 of the first comparator. The first comparator selection switch 512 may be configured and / or controlled to set the input signal voltage VIN to the input capacitance while the first comparator block 515 performs the comparison.Likewise, circuit 500 may include a second input capacitance coupled between second comparator select switch 522 and second comparator sampling node 524. Second comparator select switch 522 may be configured and / or controlled to apply input signal voltage VIN to the input capacitance while first comparator block 525 performs a comparison operation.

[0058] In some embodiments, a (in Fig. 5) is coupled between the path input terminal 511 and the sampling node 514 of the first comparator and / or the sampling node 524 of the second comparator. In some implementations, the filter may be provided as a low-pass filter configured to remove high-frequency noise that results, for example, when the input switch of the comparator function circuit block and / or the first and / or second comparator selection switches are actuated. The filter may be configured to remove noise during the switching of the first comparator selection switch 512 and / or the second comparator selection switch 522. In some embodiments, the filter is controllable. At least one effect may be that a filter bandwidth can be controlled. In some embodiments, the filter comprises a plurality of switchable resistive elements.

[0059] The circuit 500 further includes an output multiplexer 518 coupled to an output node 516 of the first comparator block 515 and to an output node 526 of the second comparator block 525. The output multiplexer 518 is configured to form a multiplexed output signal, ie, to selectively output a voltage signal output VOUT received from the first comparator block 515 and / or the second comparator block 525 to a common output terminal, also referred to herein as a path output terminal 519, coupled to the output multiplexer 518.

[0060] The first comparator block 515 and / or the second comparator block 525 are configured to operate at least in a first operating mode in which the first comparator block 515 (the second comparator block 525) performs a comparison, and in a second operating mode in which the first comparator block 515 (the second comparator block 525) performs a reset. Furthermore, the first comparator block 515 (the second comparator block 525) is configured to alternate the first operating mode and the second operating mode, such that the first comparator block 515 (the second comparator block 525) performs the comparison intermittently. The term 'reset' as used herein includes recharging the capacitors, e.g., to replace a charge that has escaped from the capacitor during the first operating mode; Reloading the capacities is also referred to as a 'capacity refresh'.A reset may also include a readjustment, e.g., to account for a fluctuation in the comparator offset due to a change in the temperature of the comparator. In some cases, a reset may also include a reconfiguration of the reference capacitance. While an interval during which the first comparator block 515 operates in the first operating mode is referred to herein as an 'operating phase' of the first comparator block 515, an interval during which the first comparator block 515 operates in the second operating mode is also referred to as a 'charging phase' of the first comparator block 515.While an interval during which the second comparator block 525 operates in the first operating mode is referred to herein as an operating phase of the second comparator block 525, similarly, the interval during which the second comparator block 525 operates in the second operating mode is also referred to as a 'charging phase' of the second comparator block 525. In some embodiments, the first comparator select switch 512 is configured to disconnect the path input terminal 511 from the sensing node 514 of the first comparator while the first comparator block 515 performs the reset. Likewise, the second comparator select switch 522 is configured to disconnect the path input terminal 511 from the sensing node 524 of the second comparator while the second comparator block 525 performs the reset.

[0061] Fig. 6 shows a table 600 showing the states of the circuit in Fig. 5. Table 600 provides an example overview of the settings of both the first comparator selection switch (labeled COMP_SEL_1 in the table) 512 and the second comparator selection switch (labeled COMP_SEL_2 in the table) 522, as well as the states of the first comparator block 515 and the second comparator block 525. In one phase (PHASE_1 in the table), both the first comparator selection switch 512 and the second comparator selection switch 522 are closed. Accordingly, both the first comparator block 515 and the second comparator block 525 are in an operating mode (labeled SAMPLING in the table). However, in some embodiments, the second comparator block 525 is configured to operationally complement the first comparator block 515.This can be seen in the other phases (in the table: PHASE_2 and PHASE_3), in which the first comparator selection switch 512 is closed while the second comparator selection switch 522 is open (PHASE_2), and in which, accordingly, the first comparator block 515 is in the operating mode (SAMPLING) while the second comparator block 525 is in the charging mode (referred to as REFRESH in the table), or vice versa (PHASE_3). At least one effect may be that, as long as the circuit 500 is operated according to one of the modes described above, the output multiplexer 518 can select an output signal voltage VOUT provided at the path output terminal 519 based on the input signal voltage VIN. In yet another phase (in the table: PHASE_4), both the first comparator selection switch 512 and the second comparator selection switch 522 are open.In some implementations, this may occur during startup of the circuit 500 or other initialization of the circuit 500 when no comparator block 515, 525 is operational. If this mode of operation is implemented during further operation of the circuit, a (in . Fig. 5 not shown) further comparator to the one in Fig. 5 to provide an output signal voltage at the path output terminal 519 that is continuously based on the input signal voltage VIN. This will be explained below with respect to a circuit shown in Fig. 7 illustrated implementation.

[0062] In general, an example circuit for processing multiple input signal voltages includes a plurality of path input terminals coupled to a plurality of path output terminals via a plurality of comparators arranged in parallel, wherein the plurality of comparators includes more comparators than there are path input terminals coupled to the path output terminals. The example circuit further includes an output circuit coupled to a plurality of output nodes of the plurality of comparators. The output circuit is configured to form a plurality of comparator output signals of the circuit based on a logical combination of a plurality of output signals received from the plurality of comparator output nodes. At least one effect may be a reduction in error in a digital output signal. One effect may be the provision of a continuous-time digital output signal regardless of discontinuous comparator operation.Because some discontinuous comparator concepts, such as those described above with regard to the ones in . Fig. 1 to Fig. 5 illustrated embodiments provide more accurate comparison results than conventional continuous-time comparators, one effect in continuous-time operation may be to achieve more accurate comparison results.

[0063] In some embodiments, each path input terminal is associated with a different path output terminal via a coupling path that is uniquely associated with the path input terminal. Each of the coupling paths may be configured to establish a connection between the path input terminal and the path output terminal. Consequently, each path output terminal is uniquely associated with a different path input terminal via the respective coupling path. In some implementations, the circuit further comprises, in each coupling path between the path input terminals and the path output terminals, at least two comparators and a comparator selection switch coupled between the path input terminal and the comparators. The comparator selection switch may be controllable to establish the connection from the path input terminal to at least one of the comparators.

[0064] In some implementations, in each coupling path, at least one of the at least two comparators is provided with a reference capacitance coupled to an input node of the comparator. In some implementations, the reference capacitance comprises at least one switched capacitance that is selectively controllable. The circuit may further comprise a control unit configured to selectively interrupt a connection between the path input terminal and the path output terminal via the at least one comparator, wherein at least one switched capacitance is controlled to set an effective threshold voltage to a predetermined value. In some embodiments, at least two coupling paths comprise a common comparator.In some implementations, the at least two coupling paths further comprise an input multiplexer coupled between the path input terminals of the at least two coupling paths and the common comparator, the input multiplexer configured to combine the input received at the path input terminals of the at least two coupling paths into a combined input to be provided to the common comparator.

[0065] In some embodiments, the at least two coupling paths include an output selection switch coupled between the common comparator and the output circuits of the at least two coupling paths. The output selection switch may be controllable to establish a connection from the common comparator to a selected one of the output circuits of the at least two coupling paths. In some implementations, the output circuit is configured to form a comparator output signal for each coupling path based on a setting of the comparator selection switch. The output circuit may be configured in each coupling path to form the comparator output signal based on the logical combination of the output signals received from the multiple comparator output nodes of the at least two comparators if the setting of the comparator selection switch is such as to connect the path input terminal to more than one comparator.In some implementations, the output circuit is configured to form the comparator output signal in each coupling path based on an output signal of only one of the multiple comparators if the comparator selection switch in each coupling path is set to connect the path input terminal to only one of the comparators. Examples of the embodiments described above and example implementations of the underlying concepts will now be described with respect to FIG. Fig. 7 to 10 discussed.

[0066] Fig. Figure 7 shows a schematic diagram illustrating a circuit 700 in a third embodiment. The circuit is configured to process multiple input signal voltages VIN_1 and VIN_2 using multiple associated threshold voltages. The circuit 700 includes multiple path input terminals (in the Fig. 7, these are a first path input terminal 711 and a second path input terminal 721), which are connected via several comparators arranged in parallel (in the example shown in Fig. 7, these are a first comparator block 715, a second comparator block 725 and a third comparator block 735) to several output terminals (in the example shown in Fig. 7, these are a first path output terminal 719 and a second path output terminal 729). It should be noted that the number of comparator function circuit blocks 715, 725, 735 (three in the example according to Fig. 7) the number of path input terminals 711, 721, which in the example are connected to a first path output terminal 719 and a second path output terminal 729 (hence two path terminals in the example according to Fig. 7). In general, each of the path input terminals 711, 721 is assigned to a different path output terminal 719, 729. The assignment is made via a respective coupling path 710, 720 (which is shown in Fig. 7 is only schematically indicated by an elliptical dashed line) that is uniquely assigned to the path input terminal 711, 721. Consequently, each path output terminal 719, 729 is uniquely assigned to a different path input terminal 711, 721 via the respective coupling path 710, 720.

[0067] The coupling paths between the path input terminals 711, 721 and the path output terminals 719, 729 each include at least two comparators. In some implementations, each coupling path is configured to selectively establish a connection between the path input terminal and the path output terminal through only one comparator. Fig. 7, the first path input terminal 711 is coupled to the first path output terminal 719 via a first coupling path 710. Generally, the coupling paths for each of the at least two comparators include an associated comparator selection switch coupled between the path input terminal and an associated one of the at least two comparators. The comparator selection switch may be controllable to establish the connection from the path input terminal to the associated one of the at least two comparators of the coupling path. As described with respect to the Fig. 7, the first coupling path 710 extends via a first comparator selection switch 712 to a sampling node 714 of the first comparator in the first comparator block 715 and via a second comparator selection switch 722 and an input multiplexer 713 to a sampling node 724 of the second comparator in the second comparator block 725. Generally, in some embodiments, the at least two coupling paths further comprise an input multiplexer coupled between the input terminals of the at least two coupling paths and the common comparator. In some embodiments, the input multiplexer may be configured to select the input received at the input terminals of the at least two coupling paths into a multiplexed input to be provided to the common comparator.

[0068] In Fig. 7, the first comparator block 715 and the second comparator block 725 are now both coupled to the first path output terminal 719 via a first output multiplexer 718 to complete the first coupling path 710. Similarly, the second path input terminal 721 is coupled to the second path output terminal 729 via a second coupling path 720. The second coupling path 720 extends via a third comparator selection switch 732 and the input multiplexer 713 to the sampling node 724 of the second comparator in the second comparator block 725 and via a fourth comparator selection switch 742 to a sampling node 734 of the third comparator in a third comparator block 735. The second comparator block 725 and the third comparator block 735 are both coupled to the second path output terminal 729 via a second output multiplexer 728.In general, the output multiplexer is configured to select one of the outputs received from the at least two comparators to form a multiplexed output signal provided at the path output terminal.

[0069] In general, at least two coupling paths may include a common comparator. While both the first coupling path 710 and the second coupling path 720 include two comparators, the two coupling paths also share a comparator (the second comparator block 725). Accordingly, a (in Fig. 7) configured to control the settings of the comparator selection switches 722, 732 to avoid a situation in which the second comparator block 725 is simultaneously connected to the first coupling path 710 and the second coupling path 720, at least at the time when the first input signal voltage VIN_1 and the second input signal voltage VIN_2 are applied to the first path input terminal 711 and the second path input terminal 721, respectively. In general, the control unit may be configured to control the comparator selection switch and / or the output selection switch to selectively establish or interrupt the coupling path via the common comparator between the path input terminal and the path output terminal.The control unit may be configured to control the comparator selection switches such that the multiplexed output signal seamlessly combines the output from the comparators of the coupling path. At least one effect may be that the multiplexed output signal is continuously based on the input signal at the path input terminal associated with the respective path output terminal. As described above, the control unit may be configured to control the comparator selection switch and / or the output selection switch such that the combined output consists of the output of only one comparator at a time. In some implementations, the control unit is provided as a state machine.

[0070] In general, at least one of the at least two comparators in a coupling path may be configured to operate at least in a first operating mode in which the at least one of the at least two comparators performs a comparison, and in a second operating mode in which the at least one of the at least two comparators performs a reset, which is also referred to herein as a refresh. As already described above with respect to the example in Fig. 7 illustrated circuit has been discussed, the (in Fig. 7) control unit may be further implemented to control the settings of the comparator selection switches 712, 722, 732 and 742 to allow the first comparator block 715, the second comparator block 725 and / or the third comparator block 735 a period of time to refresh the reference capacity, where such a capacity is implemented, e.g., in an implementation of the respective comparator according to the exemplary embodiment shown in FIGS. Fig. 1 to 4 and described above. Indeed, in the illustrated implementation, while one comparator block 715 is allowed a period of time for refresh, the other comparator blocks 725, 735 are each connected to a different one of the first coupling path 710 and the second coupling path 720. In some implementations, the at least two coupling paths generally include an output select switch coupled between the common comparator and the path output terminals of the at least two coupling paths. In some embodiments, the output select switch is controllable to connect from the common comparator to a selected one of the path output terminals of the at least two coupling paths.

[0071] Fig. 8 shows a table 800 that shows the states of the circuit in Fig. 7, for example, when operated as described above. Table 800 provides an exemplary overview of the settings of the first comparator selection switch 712 (referred to as COMP_SEL_1 in table 800), the second comparator selection switch 722 (COMP_SEL_2), the third comparator selection switch 732 (COMP_SEL_3), and the fourth comparator selection switch 742 (COMP_SEL_4). In an exemplary implementation discussed above, the operation of the circuit 700 includes, for each path input terminal 711, 721, selectively establishing a coupling via one comparator of the two comparator blocks 715 and 725, 725 and 735 provided in parallel to establish a coupling path 710, 720 from the path input terminal 711, 721 to an associated output terminal 719, 729 when the coupling via the other comparator is interrupted.This is illustrated in table 800, which provides an exemplary overview of the states of the first comparator block 715, the second comparator block 725, and the third comparator block 735. In a first phase (labeled PHASE_1 in table 800), the first comparator selection switch 712 (COMP_SEL_1) is open, while the second comparator selection switch 722 (COMP_SEL_2) is closed. Accordingly, the first comparator block 715 (labeled COMP_1 in table 800) is in charging mode (labeled REFRESH in table 800). The first input signal voltage VIN_1 is thus provided to the second comparator block 725 (COMP_2), which is in operating mode (labeled SAMPLING in table 800). Meanwhile, the third comparator selection switch 732 (COMP_SEL_3) is open. Consequently, the second input signal voltage VIN_2 is kept away from the first coupling path 710.The fourth comparator selection switch 742 (COMP_SEL_4) is closed, providing the second input signal voltage VIN_2 to the third comparator block 735 (COMP_3), which is in the operating mode (SAMPLING).

[0072] However, in some embodiments, the second comparator block 725 is configured to operationally complement the first comparator block 715 and / or the third comparator block 735. This can be seen in the other phases (PHASE_2 and PHASE_3). In the second phase (PHASE_2), the first comparator selection switch 712 and the fourth comparator selection switch 742 are closed, while the second comparator selection switch 722 and the third comparator selection switch 732 are open. Accordingly, the first comparator block 715 and the third comparator block 735 are in the operating mode (SAMPLING), while the second comparator block 725 is in the charging mode (REFRESH). Furthermore, in a third phase (PHASE_3), the fourth comparator selection switch 742 is open, while the third comparator selection switch 732 is closed. Accordingly, the third comparator block 735 (COMP_3) is in load mode (REFRESH).The second input signal voltage VIN_2 is thus provided to the second comparator block 525 (COMP_2), which is in the operating mode (SAMPLING). Meanwhile, the second comparator selection switch 722 is open. Consequently, the first input signal voltage VIN_1 is kept away from the second coupling path 720. The first comparator selection switch 712 is closed, thereby providing the first input signal voltage VIN_1 to the first comparator block 715 (COMP_1), which is in the operating mode.It may at least have the effect that, as long as the circuit 700 is operated according to one of the above-mentioned modes, in the first coupling path 710, the first output multiplexer 718 may substantially continuously receive, from either the first comparator block 715 or the second comparator block 725, an output signal voltage VOUT_1 provided to the first path output terminal 719 based on the first input signal voltage VIN_1. Similarly, in the second coupling path 720, the second output multiplexer 728 may substantially continuously receive, from either the second comparator block 725 or the third comparator block 735, an output signal voltage VOUT_2 provided to the second path output terminal 729 based on the second input signal VIN_2.

[0073] In a fourth phase (PHASE_4), the first comparator selection switch 712, the third comparator selection switch 732, and the fourth comparator selection switch 742 are closed, while the second comparator selection switch 722 is open. The first coupling path 710 uses the first comparator block 715 to form the first output signal voltage VOUT_1. With regard to the second coupling path 720, both the second comparator block 725 and the third comparator block 735 are used, wherein the second output multiplexer 728 can select an output signal voltage VOUT_2 from either the second comparator block 725 or the third comparator block 735, which is provided to the second path output terminal 729. The operation of the second coupling path 720 is thus similar to the operation during the fourth phase PHASE_4 according to table 600 in Fig. 6, which above with regard to Fig. 5. In some implementations, a (in Fig. 7) logic circuit, the output signal voltage VOUT_2 is based on a logical combination, e.g., an AND combination, of the output signal provided by the second comparator block 725 and the output signal provided by the third comparator block 735.

[0074] In a fifth phase (PHASE_5), the first comparator selection switch 712 and the fourth comparator selection switch 742 are closed as in the fourth phase (PHASE_4), but the third comparator selection switch 732 is open and the second comparator selection switch 722 is closed. The difference from operation in the fourth phase (PHASE_4) is therefore that the roles of the first coupling path 710 and the second coupling path 720 are reversed. In one implementation, the fourth and / or fifth phases may be transition phases that occur during a transition between the first and second phases and / or during a transition between the second and third phases and / or during a transition between the third and first phases.It should be recognized that the term 'transition' as used here is not intended to be restrictive in terms of relative length; in particular, the duration of the transition phase (PHASE_4, PHASE_5) should be significantly shorter than the duration of the other phases (PHASE_1, PHASE_2, PHASE_3). Furthermore, the sequential numbering should not be considered restrictive. For example, a transition phase could also be implemented to occur between the third phase and the second phase, or between the third phase and the first phase, or between the second phase and the first phase.

[0075] Fig. Figure 9 shows a schematic diagram illustrating a circuit 900 in a fourth embodiment. The circuit 900 is configured to process a plurality of input signal voltages VIN_1, VIN_2, VIN_3 using a plurality of associated threshold voltages. The circuit 900 includes a first path input terminal 911, a second path input terminal 921, and a third path input terminal 931, which are connected via a plurality of comparators (in the embodiment shown in Fig. 9, these are a first comparator block 915, a second comparator block 925, a third comparator block 935, and a fourth comparator block 945 (arranged in parallel) connected to a first path output terminal 919, a second path output terminal 929, and a third path output terminal 939. The circuit 900 is similar to both the circuit shown in FIG. 9 and an example in Fig. 7 illustrated circuit 700 as well as the one shown as a basic example in Fig. 5. In particular, it should be noted that the number of comparator blocks 915, 925, 935, 945 (four in the example according to Fig. 9 as assumed three in the example after Fig. 7) the number of input ports 911, 921, 931 coupled to the path output ports 919, 929, 939 exceeds by one. In general, each of the input ports 911, 921, 931 is associated with a different path output port 919, 929, 939 via a coupling path 910, 920, 930, each of which is uniquely associated with one of the path input ports 911, 921, 931, whereby each path output port 919, 929, 939 is uniquely associated with a different input path input port 911, 921, 931 via the respective coupling path 910, 920, 930. The structure of the exemplary circuit 900 is conceptually similar to the structure of the exemplary circuits 500 and 700 discussed in detail above. Therefore, a detailed description will be omitted. Instead, reference is made to the examples described above.

[0076] Fig. 10 shows a table 1000 containing some exemplary states of the circuit in Fig. 9, for example, when operated as described above. Table 1000 provides an exemplary overview of the settings of the six comparator selection switches 912, 922, 932, 942, 952, 962 (referred to in Table 1000 as COMP SEL_1, ..., COMP_SEL_6). In an exemplary implementation, the operation of the circuit 900 comprises, for each input terminal 911, 921, 931, selectively establishing a coupling via one in a pair of comparator blocks 915 and 925, 925 and 935, 935 and 945 provided in parallel to form a coupling path 910, 920, 930 from the input terminal 911, 921, 931 to an associated output terminal 919, 929, 939, while interrupting the coupling via the other comparator block in the respective pair.This is illustrated in table 1000, which provides an exemplary overview of the states of the first to fourth comparator blocks 915, 925, 935, and 945. In a first phase (referred to as PHASE_1 in table 800), the first comparator selection switch 912 is open, while the second comparator selection switch 922 is closed. Accordingly, the first comparator block 915 (COMP_1) is in charging mode (REFRESH). Consequently, the first input signal voltage VIN_1 is provided to the second comparator block 925 (COMP_2), which is in operating mode (SAMPLING). Consequently, during the first phase, the first coupling path 910 (referred to as PATH_1 in table 1000) uses the second comparator block 925 (COMP_2), but not the first comparator block 915. Meanwhile, the third comparator selection switch 932 is open. Consequently, the second input signal voltage VIN_2 is kept away from the first coupling path 910.The fourth comparator selection switch 942 is closed, providing the second input signal voltage VIN_2 to the third comparator block 935 (COMP_3), which is in the operating mode. Consequently, during the first phase, the second coupling path 920 (PATH_2) uses the third comparator block 935 (COMP_3), but not the second comparator block 925. Similarly, the fifth comparator selection switch 952 is open. Consequently, the third input signal voltage VIN_3 is kept away from the second input coupling path 920. The sixth comparator selection switch 962 is closed, providing the third input signal voltage VIN_3 to the fourth comparator block 945 (COMP_4), which is in the operating mode. Consequently, during the first phase, the third coupling path 930 (PATH_3) uses the fourth comparator block 945 (COMP_4), but not the third comparator block 935.

[0077] As above regarding the Fig. 7 and Fig. 8, in some embodiments, the second comparator block 925 may be configured to operatively complement the first comparator block 915 and / or the third comparator block 935. In the Fig. 9, the third comparator block 935 may further be configured to operationally complement the second comparator block 925 and / or the fourth comparator block 945. An exemplary operation of the first through fourth phases (PHASE_1, PHASE_2, PHASE_3, PHASE_4) will now be discussed. During the first phase (PHASE_1), the second comparator block 925 (COMP_2) is in the operating mode (SAMPLING) and is used in the first coupling path 910 (PATH_1), whereby the first comparator block 915 (COMP_1) may be in the charging mode (REFRESH), for example, to recharge its capacitances. During the third phase (PHASE_3), the second comparator block 925 (COMP_2) is in the operating mode (SAMPLING), being used in the second coupling path 920 (PATH_2), whereby the third comparator block 935 (COMP_3) may be in the charging mode (REFERESH), e.g., to recharge its capacitances.In contrast, during the second phase (PHASE_2), the second comparator block 925 is cut off from any input signal voltage because the second comparator selection switch 922 (COMP_SEL_2) and the third comparator selection switch 932 (COMP_SEL_3) are both open. This allows the second comparator selection block 925 (COMP_2) to be in charge mode (REFRESH), for example, to recharge its capacitors. Still during the second phase (PHASE_2), the third comparator block 935 (COMP_3) is in operation mode (SAMPLING), being used in the second coupling path 920 (PATH_2), allowing the second comparator block 925 (COMP_2) to be in charge mode (REFRESH), for example, to recharge its capacitors.During the fourth phase (PHASE_4), the third comparator block 935 (COMP_3) is in the operating mode (SAMPLING), being used in the third coupling path 930 (PATH_3), which allows the fourth comparator block 945 (COMP_4) to be in the charging mode (REFRESH), for example, to recharge its capacitors. In contrast, during the third phase (PHASE_3), the third comparator block 935 is cut off from any input signal voltage because the fourth comparator selection switch 942 (COMP_SEL_4) and the fifth comparator selection switch 952 (COMP_SEL_5) are both open. This allows the third comparator block 935 (COMP_3) to be in the charging mode (REFRESH), for example, to recharge its capacitors.Consequently, while each of the comparator blocks 915, 925, 935, 945 does not operate continuously in the operating mode, a continuous output signal voltage VOUT_1, VOUT_2, VOUT_3 is still provided based on an associated input signal voltage VIN_1, VIN_2, VIN_3 for each coupling path 910, 920, 930.

[0078] In general, a method for processing at least one input signal voltage in a circuit is disclosed herein. The circuit comprises, as with respect to the examples described above and in the Fig. 5, Fig. 7 and Fig.9, at least one path input port coupled to at least one path output port via a plurality of comparators, the plurality of comparators comprising more comparators than there are path input ports coupled to the path output ports. The method comprises, for each path input port, selectively coupling via one comparator of two comparators provided in parallel to form a coupling path from the path input port to an associated path output port while breaking the coupling via the other comparator. In some implementations, the method further comprises sharing the one comparator between at least a first coupling path from a first path input port to a first path output port and a second coupling path from a second path input port to a second path output port.In some implementations, in the second coupling path, establishing the coupling via one comparator in the first coupling path comprises breaking the coupling via one comparator, and in the first coupling path, establishing the coupling via the other comparator. In some implementations, the method further comprises charging a reference capacitance coupled to a sensing node of the other comparator while breaking the coupling via the other comparator.

[0079] The arrangements and procedures of the described implementations may be implemented in a sensor system, a special-purpose computer, a programmed microprocessor or microcontroller and in a peripheral integrated circuit element(s), an ASIC or other integrated circuit, a digital signal processor, a flashable device, a hardwired electronic or logic circuit, such as a circuit in discrete elements, a programmable logic device such as a PLD, PLA, FPGA, PAL, a modem, a transceiver, any comparable device, or the like. The disclosed arrangements may be implemented partially or entirely in hardware using logic circuits or a VLSI package.

[0080] In the above description of the example implementations, specific numbers, material configurations, and other details are set forth for the purpose of explanation in order to better explain the invention as claimed. However, it will be apparent to one of ordinary skill in the art that the claimed invention may be practiced using details other than the example details described herein. The example implementations / embodiments discussed herein may include various components assembled together; however, it should be recognized that the components of the assemblies may be combined into one or more devices. The terms 'circuit block' and 'circuit portion' as used herein should be understood functionally.Therefore, in some implementations, a circuit block may structurally appear as such in a circuit arrangement of a product; the elements of the circuit block may be distributed at various locations in the circuit arrangement of the product. Similarly, a circuit section may be distributed.

[0081] The word 'exemplary,' as used herein, means serving as an example, instance, or illustration. Any aspect or construction described herein as 'exemplary' is not necessarily to be construed as preferred or advantageous over other aspects or constructions. Rather, the use of the word exemplary is intended to illustrate the concepts and techniques in a concrete manner. The term 'techniques' can refer to, for example, one or more devices, one or more apparatuses, one or more systems, one or more methods, one or more articles of manufacture, and / or one or more computer-readable instructions, as indicated by the context described herein.

[0082] The terms 'coupled' and 'connected' as used herein may have been used to describe how various elements are connected. Unless explicitly stated or at least otherwise implied, such described connecting of various elements may be either direct or indirect.

[0083] The terms 'comprising,' 'containing,' 'comprising,' 'with,' or their variations and similar terms, as used herein, are open-ended terms intended to be inclusive. These terms indicate the presence of the stated elements or features, but do not preclude additional elements or features.

[0084] The terms 'first,' 'second,' and the like, as used herein, are also used to describe various elements, regions, sections, etc., and are not intended to be limiting. Where some implementations have been described above in terms of first and second functionality, other implementations not illustrated may include only the first functionality (and not the second functionality) or may include only the second functionality (and not the first functionality).

[0085] The phrase "continuously execute" as used herein is not necessarily meant to mean "always." Conditions, such as a prerequisite for a particular continuous mode of operation, may be defined to be met as a requirement for continuous execution. Continuous execution may be defined to continue as long as the conditions are met. A condition may be the activation of a continuous mode of operation that has a predetermined condition for deactivation, such as the completion of a predetermined duration.

[0086] The term 'or', as used herein, is intended to mean an inclusive 'or' rather than an exclusive 'or'. That is, unless otherwise specified or clear from the context, 'X uses A or B' is intended to mean any of the natural inclusive permutations. That is, if X uses A; X uses B; or X uses both A and B, then under each of the preceding cases, 'X uses A or B' is satisfied.

[0087] The articles 'a' and 'an', as used herein, should generally be construed to mean 'one or more' unless otherwise specified or it is clear from the context that they refer to a singular form.

[0088] The term 'reset' as used here includes recharging the capacitances to replace the charge that escaped from the capacitance, for example, during the first operating mode; recharging the capacitances is also referred to as 'capacitance refresh'. A reset may also include readjustment, for example, to account for a fluctuation in the comparator offset due to a change in the comparator temperature. In some cases, a reset may also include reconfiguration of the reference capacitance.

[0089] In some embodiments, a programmable logic device (e.g., a field-programmable gate array) may be used to perform some or all of the functionality of the methods described herein. In some embodiments, a field-programmable gate array may cooperate with a microprocessor to perform any of the methods described herein. In general, the methods may be performed by any hardware device.

[0090] While the invention has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. Specifically, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, systems, etc.), it is intended that the terms (including reference to 'means') used to describe such components correspond to any component or structure that performs the specified function of the described component (e.g., that is functionally equivalent), unless otherwise indicated, even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention illustrated herein.It should be appreciated that the features of the various embodiments described herein may be combined with one another unless specifically stated otherwise.

Claims

[1] Circuit for processing an input signal voltage, comprising: an input capacitance (45) coupled between an input node (43) of the circuit and a sampling node (51) of a comparator (55); and a reference capacitance (30) coupled to the sampling node (51) of the comparator (55); a common-mode switch (54) coupled between the sampling node (51) and a reference node (52) of the comparator (55), wherein the circuit is configured such that the input node (43) is set to the input signal voltage while the common mode switch (54) is open. [2] The circuit of claim 1, wherein the circuit is configured such that the input capacitance (45) is set to a reference input voltage while the common mode switch (54) is closed. [3] The circuit of claim 2, wherein the circuit is configured such that the input capacitance (45) is set to the reference input voltage while the reference capacitance (30) is being charged. [4] Circuit according to one of claims 1 to 3, wherein the reference capacity (30) comprises a plurality of capacities (31, 32) and wherein at least one capacitance of the plurality of capacitances (31, 32) is provided as a switched capacitance which is selectively controllable to configure the plurality of capacitances (31, 32). [5] Circuit according to claim 4, wherein the at least one switched capacitor (31) is coupled to a first level reference node (33) via a first level switch (35) and is coupled to a second level reference node (34) via a second level switch (36) and wherein the first level switch (35) and / or the second level switch (36) can be selectively controlled to configure the reference capacitance (30). [6] The circuit of claim 5, wherein the first level switch (35) and the second level switch (36) are configured not to be closed or open at the same time. [7] The circuit of claim 6, wherein the first level switch (35) and the second level switch (36) are integrated to form a changeover switch adapted to establish a connection between the switched capacitance (31) and either the first level reference node (33) or the second level reference node (34). [8] A circuit according to any one of claims 6 to 7, wherein the circuit further comprises: a control unit (64) designed to control the at least one switched capacitor (31, 32). [9] The circuit of claim 8, wherein the control unit (64) is configured to base the control of the at least one switched capacitor (31, 32) on a comparator output signal voltage formed when the input node (10) is set to the reference input voltage. [10] A circuit according to claim 8 or 9, wherein the control unit (64) is designed to control the switched capacitance (31, 32) such that a comparator offset voltage is compensated at the sampling node (51). [11] A circuit according to any one of claims 8 to 10, wherein the control unit (64) is adapted to control the switched capacitance (31, 32) such that an effective threshold voltage is set to a predetermined value. [12] A circuit according to any one of claims 8 to 11, wherein the control unit (64) is adapted to control the common mode switch (54) such that the common mode switch (54) is closed while the first level switch (35, 37) is closed. [13] Circuit according to one of claims 8 to 12, wherein the control unit (64) is designed to repeatedly charge the reference capacitance (30). [14] Circuit according to claim 13, wherein the control unit (64) is designed to periodically charge the reference capacitance (30). [15] A circuit according to any one of claims 5 to 14, wherein a difference between a voltage at the first level reference node (33) and a voltage at the second level reference node (34) is based on a bandgap voltage. [16] Circuit according to one of claims 1 to 15, further comprising: an input terminal (10) adapted to be set to the input signal voltage, and an input switch (41) coupled between the input terminal (10) and the input node (43). [17] A circuit according to claim 16, wherein the input switch (41) is designed to be open during a charging phase of charging the input capacitance (45) and the reference capacitance (30) and closed during an operating phase of the circuit. [18] Circuit according to one of claims 1 to 17, further comprising: a reference terminal (11) adapted to be set to a reference input voltage, and a reference switch (42) coupled between the reference terminal (11) and the input node (43), wherein the reference switch (42) is configured to be closed while the common mode switch (54) is closed. [19] A circuit according to claim 18, wherein the reference terminal (11) is adapted to be set to a ground voltage. [20] A circuit according to any one of claims 2 to 19, wherein the sampling node of the comparator (51) is coupled to a bias output node of the comparator (55) via the common mode switch (54). [21] A method for processing an input signal voltage performed by an input signal voltage processing circuit according to any one of claims 1 to 20, the method comprising: Configuring a reference capacitance (30) coupled to an input capacitance (45) at a sensing node (40); Charging the reference capacitance (30) during a charging phase to a first level reference voltage; Setting the input capacitance (45) to an input signal voltage during an operating phase while the common mode switch is open to obtain a sampling voltage at the sampling node (40); and Forming a digital signal representing a difference between the sampling voltage and a threshold voltage that is positive or negative. [22] The method of claim 21, further comprising: Charging the input capacitance (45) to a reference input voltage level during the charging phase. [23] The method of claim 21 or 22, further comprising: Configuring the reference capacitance (30) during the charging phase so that a comparator offset voltage is compensated at the sampling node (40). [24] A method according to any one of claims 21 to 23, further comprising: selectively setting the reference capacitance (30) to a second level reference voltage, wherein the second level reference voltage is below the first level reference voltage and the input signal voltage is above the reference input voltage or wherein the second level reference voltage is above the first level reference voltage and the input signal voltage is below the reference input voltage. [25] The method of any one of claims 21 to 24, wherein a difference between the first level voltage and the second level voltage is based on a bandgap voltage. [26] A method according to any one of claims 21 to 25, further comprising: Feeding back an output voltage based on the digital signal to the sampling node during the charging phase. [27] A method according to any one of claims 21 to 26, further comprising: Using a differential comparator (55), wherein the sampling node of the comparator (55) is a first sampling node (51) and the comparator (55) comprises a second sampling node (52), and Forming the digital signal to represent a voltage difference between the first and second sampling nodes that is positive or negative.

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