Semiconductor memory device and method for its production

Abstract

Method for manufacturing a semiconductor memory device, comprising the following steps: Producing a lower cover layer (141a) over a substrate (100) in a first region (100A) and a second region (100B); Etching an opening (131') in the lower cap layer in the first region (100A) and forming a lower electrode (131) of a memory cell in the opening; Forming the memory cell (135) over the lower electrode (131) and forming an upper electrode (133) over the memory cell (135); Exposing a top surface of the upper electrode (133) of the memory cell; Producing an upper covering layer (141b) on top of the upper electrode (133); Etching a portion of the upper cap layer (141b) to form a first trench (123A) extending to the top of the upper electrode (133); and Producing a first metal line (123') in the first trench (123A) to make contact with the upper electrode (133), which also includes the following steps: Producing a photoresist layer (120) on the upper cover layer (141b_1) in the first region; Etching the upper cover layer (141b_2) in the second region to expose the lower cover layer (141a); Removing the photoresist layer (120); Producing a third cover layer (141b') on the upper cover layer (141b_1) in the first region and the lower cover layer (141a).

Description

Background of the invention

[0001] Semiconductors are used in integrated circuits for electronic applications, including radio and television sets, mobile phones, and personal computers. One well-known type of semiconductor device is semiconductor memory, such as dynamic random access memory (DRAM) or flash memory, both of which use charge to store information.

[0002] A recent development in semiconductor memory devices is spin electronics, which combines semiconductor technology with magnetic materials and components. Instead of electron charge, the spin polarization of electrons is used to indicate the "1" or "0" state. One such spin electronic device is a spin-transfer torque (STT) device with a magnetic tunneling junction (MTJ).

[0003] An MTJ device has a free layer, a tunnel layer, and a pinned layer. The magnetization direction of the free layer can be reversed by applying a current through the tunnel layer, causing the injected polarized electrons in the free layer to exert so-called spin torques on the magnetization of the free layer. The pinned layer has a fixed magnetization direction. When a current flows in the direction from the free layer to the pinned layer, electrons flow in a reverse direction, that is, from the pinned layer to the free layer. The electrons are polarized to the same magnetization direction as the pinned layer after passing through the pinned layer. They flow through the tunnel layer and then into the free layer, where they accumulate.Ultimately, the magnetization of the free layer is parallel to that of the pinned layer, and the MTJ device is in a low-resistance state. This electron injection caused by the current is called the main injection.

[0004] When a current is applied, flowing from the pinned layer to the free layer, electrons flow in the direction from the free layer to the pinned layer. Electrons with the same polarization as the pinned layer's magnetization direction can flow through the tunnel layer and into the pinned layer. Conversely, electrons with a polarization different from the pinned layer's magnetization are reflected (blocked) by the pinned layer and accumulate in the free layer. Eventually, the free layer's magnetization becomes antiparallel to that of the pinned layer, and the MTJ device is in a high-resistance state. This electron injection caused by the current is called side injection.

[0005] Semiconductor memory devices with two regions for MJT memory and logic are described, for example, in US 2015 / 0 171 314 A1 and US 2012 / 0 032 287 A1. US 2007 / 0 228 511 A1 discloses the formation of a ferroelectric capacitor structure. An IrO2 film and an IrOx film, which are components of a top electrode layer, are sequentially formed on a capacitor film. By RTA treatment at 600°C to 750°C, in this case at 725°C for approximately one minute under an O2 atmosphere, only a surface layer of the IrOx film is oxidized, forming a highly oxidized layer with a higher degree of oxidation than the rest of the IrOx film.

[0006] The invention provides methods according to claims 1 to 5 and a semiconductor memory device according to claims 7 to 12. Short description of the drawings

[0007] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 is a cross-sectional view of a semiconductor memory device according to some embodiments of the present invention. The Fig. 2 to 19 are cross-sectional views of a CMOS MRAM structure at various stages of fabrication, according to some embodiments of the present invention. Detailed description

[0008] Notwithstanding that the numerical ranges and parameters indicating the broad scope of the invention are approximate, the numerical values ​​recited in the specific examples are given as accurately as possible. However, a numerical value inherently contains certain errors that inevitably result from the standard deviation found in the particular test measurements. In addition, the term "about" as used herein generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable standard error of the mean as viewed by one skilled in the art.Other than in the working examples, or unless expressly stated otherwise, all numerical ranges, amounts, values, and percentages, such as for amounts of material, durations of time, temperatures, operating conditions, proportions, and the like, given herein should in all cases be construed as modified by the term "about." Therefore, unless otherwise stated, the numerical parameters given in the present invention and the appended claims are approximate values ​​that are subject to change if desired. At a minimum, each numerical parameter should be interpreted in light of the number of significant figures given and by applying normal rounding techniques. Ranges may be represented herein as being from one endpoint to another endpoint or as being between two endpoints. All ranges recited herein include the endpoints unless otherwise stated.

[0009] MRAM cells embedded in a CMOS structure have been continuously developed. A semiconductor memory device with embedded MRAM cells includes an MRAM cell region and a logic region. The MRAM cell region may include a plurality of MRAM cells. The logic region may include a plurality of conductive lines or metal lines. The plurality of conductive lines may be the routing for the plurality of MRAM cells. The logic region and the MRAM cell region may be arranged in different regions within the semiconductor memory device. For example, the MRAM cell region may be arranged in the center of the semiconductor memory device, while the logic region may be arranged at the periphery of the semiconductor memory device. However, this example is not intended to be limiting.Other arrangements of the MRAM cell region and the logic region are within the intended scope of the present invention.

[0010] In the MRAM cell region, a transistor structure may be arranged beneath an MRAM structure. In some embodiments, an MRAM cell is embedded in a metallization layer formed in a back-end-of-line (BEOL) process. In some embodiments, transistor structures in the MRAM cell region and the logic region are arranged in the same semiconductor substrate and formed in a front-end-of-line (FEOL) process and are thus substantially identical. The MRAM cell may be embedded in any position in the metallization layer, for example, between adjacent metal line layers that run parallel across the semiconductor substrate. The embedded MRAM cell may be arranged, for example, between a 4th metal line layer and a 5th metal line layer in the MRAM cell region. In the logic region, the 4th metal line layer is connected to the 5th metal line layer via a 4thA metal via located between the 4th metal line layer and the 5th metal line layer. In other words, considering the MRAM cell region and the logic region, the embedded MRAM cell has a thickness of at least a portion of the 5th metal line layer and the 4th metal via. The number provided here for the metal line layer is exemplary and not limiting. In general, those skilled in the art will understand that the MRAM cell is disposed between an Nth metal line layer and an (N+1)th metal line layer, where N is an integer greater than or equal to 1.

[0011] The embedded MRAM cell comprises a magnetoresistive cell. In some embodiments, the magnetoresistive cell is a magnetic tunnel junction (MTJ) made of ferromagnetic materials. The MTJ further includes a bottom electrode and a top electrode. The bottom electrode and the top electrode are electrically connected to the MTJ for signal / bias transmission. Following the example above, the bottom electrode is further connected to the Nth metal conductive layer, while the top electrode is further connected to the (N+1)th metal conductive layer. When a bias voltage is applied across a combined structure of the (N+1)th metal conductive layer, the top electrode, the MTJ, the bottom electrode, and the Nth metal conductive layer, the series resistance R S of the combined structure when a current flowing through this structure is measured. The series resistance RS in an MRAM cell must be reduced or kept at a desired value that is as low as possible.

[0012] However, due to the non-conductive layers in the aforementioned combined structure, a high series resistance R Sto be expected. For example, an oxide layer may be located between the top electrode and the (N+1)th metal conductive layer. The formation of the oxide layer may be due to the high oxidation rate of a conventional material used for the top electrode. The top electrode may be a capping layer on the MTJ. The capping layer may be a non-ferromagnetic material or an insulator. Such materials include silver (Ag), gold (Au), copper (Cu), tantalum (Ta), tantalum nitride (TaN), tungsten (W), manganese (Mn), platinum (Pt), palladium (Pd), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), iridium (Ir), rhenium (Re), osmium (Os), aluminum oxide (Al 2 O 3), magnesium oxide (MgO), tantalum oxide (TaO), ruthenium oxide (RuO), or a combination thereof. In some embodiments, Ta is often used for the top electrode because the selectivity between this material (Ta) and a hard mask is relatively high. Post-deposition bombardment can be used to remove the oxide layer and reduce the series resistance R S Due to the simultaneous formation of the MRAM cell region and the logic region, post-deposition bombardment may be effective for removing the oxide layer in the MRAM cell region, but it may damage the exposed metal line layers of the logic region. Therefore, post-deposition bombardment may not be an effective solution for removing the oxide layer.

[0013] The present invention provides a method for fabricating a semiconductor memory device in which little or no oxide layer is formed as a by-product in the top electrode of an MTJ. Therefore, no post-deposition bombardment is required to remove the oxide layer to reduce the series resistance R S of the MTJ.

[0014] Fig. 1 is a cross-sectional view of a semiconductor memory device 10 according to some embodiments of the present invention. Fig. 1, the semiconductor memory device 10 includes a first region 100A and a second region 100B. The first region may be an MRAM cell region, and the second region may be a logic region. The MRAM cell region 100A and the logic region 100B each include a transistor structure 101 in a semiconductor substrate 100. In some embodiments, the transistor structures 101 in the MRAM cell region 100A and in the logic region 100B are substantially identical. In some embodiments, the semiconductor substrate 100 may be, for example, a silicon substrate, among others. In the case of a silicon substrate, the semiconductor substrate 100 may further include other semiconductor materials, such as silicon germanium, silicon carbide, or gallium arsenide. In the present embodiment, the semiconductor substrate 100 is a p-type semiconductor substrate (p-substrate) or an n-type semiconductor substrate (n-substrate) comprising silicon.Alternatively, the semiconductor substrate 100 may comprise: another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In yet another alternative, the semiconductor substrate 100 is a semiconductor on insulator (SOI). In further alternatives, the semiconductor substrate 100 may be a doped epitaxial layer, a gradient semiconductor layer, and / or a semiconductor layer over another semiconductor layer of a different conductivity type, such as a silicon layer over a silicon germanium layer.

[0015] The semiconductor substrate 100 further includes heavily doped regions, such as sources 103 and drains 105, located at least partially within the semiconductor substrate 100. A gate 107 is disposed over a top surface of the semiconductor substrate 100 between the source 103 and the drain 105. Contact pins 108 are formed in an interlayer dielectric (ILD) 109 and may be electrically connected to the transistor structure 101. In some embodiments, the ILD 109 is formed on the semiconductor substrate 100. The ILD 109 may be formed using various methods for forming these layers, such as chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, physical vapor deposition (PVD), thermal growth, and the like. Suitable materials for the ILD 109 can be, for example, oxides (e.g. Ge oxide), oxide nitrides (e.g. GaP oxide nitride), silicon dioxide (SiO2 ), nitrogen-containing oxides (e.g. nitrogen-containing SiO 2 ), nitrogen-doped oxides (e.g. N 2 -implanted SiO 2 ), silicon oxide nitrides (Si x O y N z ) or a combination thereof.

[0016] Fig. 1 shows a planar transistor with a doped region in the semiconductor substrate 100, but the present invention is not limited thereto. A non-planar transistor, such as a FinFET structure, may also have raised doped regions.

[0017] In some embodiments, a shallow trench isolation (STI) 111 is provided to define and electrically separate adjacent transistors. A number of STIs 111 are formed in the semiconductor substrate 100. The STI 111, which may be made of suitable dielectric materials, may be provided to electrically separate a transistor from adjacent semiconductor devices, such as other transistors. The STI 111 may, for example, comprise oxides (e.g., Ge oxide), oxide nitrides (e.g., GaP oxide nitride), silicon dioxide (SiO 2 ), nitrogen-containing oxides (e.g. nitrogen-containing SiO 2 ), nitrogen-doped oxides (e.g. N 2 -implanted SiO 2 ), silicon oxide nitrides (Si x O y N z) or a combination thereof. The STI 111 may also be made of a suitable high dielectric constant or high-k material, where k is greater than or equal to about 8, such as titanium oxide (Ti x O y , e.g. TiO 2 ), tantalum oxide (Ta x O y , e.g. Ta 2 O 5 ) and barium strontium titanate (BST, BaTiO 3 / SrTiO 3 ). Alternatively, the STI 111 may be made of a suitable low-dielectric-constant or low-k material, where k is less than or equal to about 4.

[0018] In Fig. 1, a metallization structure 101' with an Nth metal layer 121 is arranged above the transistor structure 101. Since the Nth metal layer 121 may not be the first metal layer above the transistor structure 101, the intermediate part between the metallization structure 101' and the transistor structure 101 has been omitted for illustrative purposes. In the MRAM cell region 100A, a plurality of MTJ structures are arranged between an Nth metal line 121' of the Nth metal layer 121 and an (N+1)th metal line 123' of an (N+1)th metal layer 123. For brevity, only one exemplary MTJ structure 130 is shown. In the logic region 100B, the conductive lines are also simplified for description. In the logic area 100B, the N-th metal line 121' is connected to the (N+1)-th metal line 123' by an N-th metal via 122 of the N-th metal layer 121.In some embodiments, the metal lines and metal vias are filled with an electrically conductive material, such as copper, gold, or another suitable metal or alloy. The metal lines and metal vias in different metal layers form an interconnect structure made of substantially pure copper (e.g., having a copper content of greater than about 90 mass % or greater than about 95 mass %) or copper alloys, and they may be fabricated using a single or dual damascene process. Metal lines and metal vias may or may not be substantially free of aluminum. An interconnect structure includes a plurality of metal layers, namely M. 1 , M 2 ... M N . Throughout this specification, the term “metal layer” refers to a patterned conductive layer in which metal lines are fabricated. The metal layers M1 to M Nare separated by intermetal dielectrics (IMDs) 125, which may include oxides such as undoped silicate glass (USG), fluorosilicate glass (FSG), low-k dielectric materials, or the like. The low-k dielectric materials of the IMDs 125 may have k values ​​less than or close to 3.8. In some embodiments, the k values ​​of the low-k dielectric materials are less than about 3.0 and may be less than about 2.5. The Nth metal via 122 may be formed using various methods, e.g.,Electroplating, electroless plating, high-density ionized metal plasma deposition (IMP), high-density inductively coupled plasma deposition (ICP), sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0019] In the MRAM cell region 100A of the semiconductor structure 10, the MTJ structure 130 includes at least a bottom electrode 131, a top electrode 133, and an MTJ 135. In some embodiments, the bottom electrode 131 is in the form of a recess into a composite layer comprising a silicon carbide (SiC) layer 141a and a silicon rich oxide (SRO) layer 142. The SiC layer 141a may be a capping layer for covering the Nth metal line 121' during manufacturing. The recess may be a quadrilateral or a trapezoidal recess. Alternatively, the SRO layer 142 may be replaced by or combined with tetraethyl orthosilicate (TEOS). In some embodiments, the bottom electrode 131 may comprise nitrides, such as TiN or TaN, or Ta or Ru. In some embodiments, the upper electrode 133 comprises Ag, Au, Cu, Ta, TaN, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, Ir, Re, Os, Al 2 O 3, MgO, TaO, RuO or a combination thereof.

[0020] As in the MRAM cell area 100A of Fig. 1, in the present embodiment, the (N+1)-th metal line 123' is surrounded not only by the IMDs 125 but also by a SiC layer 141b, while the (N+1)-th metal line 123' and the N-th metal via 122 in the logic region 100B are surrounded only by the IMDs 125. The SiC layer 141b may be a capping layer for covering the upper electrode 133 during manufacturing. As shown in Fig. 1, a sidewall of the MTJ 135 is protected by a protection layer 127, such as a nitride layer. In some embodiments, the protection layer 127 comprises silicon nitride (SiN). The thickness of the protection layer 127 may be about 25 nm. In some embodiments, a dielectric layer 129 may be disposed over the protection layer 127. The dielectric layer 129 may be a TEOS layer. In some embodiments, another TEOS layer 143 may be disposed over the SiC layer 141b surrounding the (N+1)th metal line 123'. The thickness of the TEOS layer 143 may be about 15 nm.

[0021] In some embodiments, the bottom electrode 131 of the MTJ structure 130 is electrically connected to the doped region. In some embodiments, the doped region is a drain 105 or a source 103. In other embodiments, the bottom electrode 131 of the MTJ structure 130 is electrically connected to the gate 107. In some embodiments, the gate 107 of the semiconductor structure 10 is a polysilicon gate or a metal gate.

[0022] In some embodiments, the SiC layer 141b extends from the MRAM cell region 100A to the logic region 100B. The SiC layer 141b and the SiC layer 141a are connected at a boundary B between the MRAM cell region 100A and the logic region 100B. For illustration, the SiC layer 141b is divided into three parts. A first part 141b_1 is located in the MRAM cell region 100A, a second part 141b_2 is located in the logic region 100B, and a third part 141b_3 connects the first part 141b_1 and the second part 141b_2. The third portion 141b_3 may include a sloped portion that covers or conforms to the edges of the SRO layer 142, the sources 103, and the dielectric layer 129. The elevation of the first portion 141b_1 is at a position P1, and the elevation of the second portion 141b_2 is at a position P2. The position P1 is higher than the position P2.The elevation difference between positions P1 and P2 is approximately equal to the thickness of the MTJ structure 130.

[0023] The first part 141b_1, the second part 141b_2, and the third part 141b_3 may have different thicknesses. The thickness of the first part 141b_1 is greater than the thickness of either the second part 141b_2 or the third part 141b_3. The thickness of the third part 141b_3 may be non-uniform. In some embodiments, the thickness of the first part 141b_1 may be greater than 10 nm or about 20 nm. The thickness of the second part 141b_2 may be less than 20 nm. The thickness of the third part 141b_3 may be about 10 nm. Furthermore, the thickness of the SiC layer 141a is about 10 nm.

[0024] In the MRAM cell region 100A, the (N+1)th metal line 123' passes through the IMDs 125, the TEOS layer 143, and the first portion 141b_1 of the SiC layer 141b to contact the upper electrode 133. Consequently, the (N+1)th metal line 123' is embedded in the IMDs 125, the TEOS layer 143, and the first portion 141b_1 of the SiC layer 141b.

[0025] In the logic region 100B, the Nth metal via 122 extends through the IMDs 125, the TEOS layer 143, and the second portion 141b_2 of the SiC layer 141b to contact the Nth metal line 121'. The (N+1)th metal line 123' comes into contact with the Nth metal via 122. Consequently, the Nth metal via 122 is embedded in the IMDs 125, the TEOS layer 143, and the second portion 141b_2 of the SiC layer 141b.

[0026] During the manufacturing process for the MRAM cell region 100A, when the top electrode 133 of the MTJ structure 130 is formed, a SiC layer is immediately deposited over the top electrode 133 to prevent oxidation of the top electrode 133. Therefore, the first portion 141b_1 of the SiC layer 141b may be the portion of the SiC layer remaining after the formation of the (N+1)th metal line 123'.

[0027] During the manufacturing process for the logic region 100B, when the dielectric layer 129, the protection layer 127, and the SRO layer 142 in the cell region 100A are etched, the Nth metal line 121' may be exposed. This is because the SiC layer 141a located above the Nth metal line 121' in the logic region 100B may also be etched. If the Nth metal line 121' is exposed, it may deform during subsequent manufacturing processes. Then, another SiC layer is deposited over the Nth metal line 121' to re-cap or repair the SiC layer 141a to prevent the Nth metal line 121' from being exposed. Therefore, the second part 141b_2 of the SiC layer 141b may be the part of the further SiC layer that remains after the formation of the Nth metal via 122'.

[0028] The following describes the formation of the SiC layer 141b with reference to the Fig. 2 to 19. The Fig. 2 to 19 are cross-sectional views of a CMOS MRAM structure at various stages of fabrication, according to some embodiments of the present invention. Fig. 2, a semiconductor structure is provided having a defined MRAM cell region 100A and a logic region 100B. In some embodiments, a transistor structure is formed in a semiconductor substrate (in Fig. 2 not shown). The semiconductor structure may be further processed using CMOS or MOS technology to produce various structural elements. For example, one or more contact pins, such as silicide regions, may be formed. The contact elements may be connected to the source or the drain. The contact elements comprise silicide materials such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), other suitable conductive materials, and / or a combination thereof. In one example, the contact elements are formed using a sacilicid (self-aligned silicide) process.

[0029] The Nth metal line 121' is patterned in a dielectric layer 136 above the transistor structure. In some embodiments, the Nth metal line 121' may be formed by electroplating with a Cu seed layer deposited over the patterned dielectric layer 136. In other embodiments, the Nth metal line 121' may be formed using various methods, such as electroless plating, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). Planarization is performed to expose the top surface of the Nth metal line 121' and the top surface of the dielectric layer 136.

[0030] In Fig. 3, a barrier layer 140 in the form of a stacked layer comprising a SiC layer 141a and a TEOS / SRO layer 142 is deposited as protection over the top surface of the Nth metal line 121' and the top surface of the dielectric layer 136 in both the MRAM cell region 100A and the logic region 100B. The barrier layer 140 can be formed using various methods, e.g., chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), sputtering, physical vapor deposition (PVD), and thermal growth.

[0031] In Fig. 4, a photoresist layer (not shown) is patterned over the stack layer to expose a bottom electrode region of the MTJ structure. As shown in Fig. 4, a bottom electrode via opening 131' is formed in the barrier layer 140 using a suitable dry etching process. In some embodiments, the dry etching process comprises reactive ion etching (RIE) using fluorine-containing gases. In some embodiments, the dry etching comprises a suitable etch of the dielectric to form via trenches in a metallization structure in conventional CMOS technology. In the logic region 100B shown in Fig. 4, the barrier layer 140 is protected by the photoresist layer (not shown) so that, unlike the counterpart in the MRAM cell region 100A, the top surface of the N-th metal layer 121' is not exposed.

[0032] In Fig. 5, a diffusion barrier layer 161 is deposited as protection over the bottom electrode via opening 131' in the MRAM cell region 100A and over the barrier layer 140 in the logic region 100B. Subsequently, deposition of a bottom electrode material 131 is performed over the diffusion barrier layer 161 and the barrier layer 140. The bottom electrode material 131 can be deposited using various methods, such as high density ionized metal plasma (IMP) deposition, high density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). The diffusion barrier layer 161 and the deposited bottom electrode material 131 are then etched back to be level with the top of the barrier layer 140, as shown in Fig. 6 is shown.

[0033] Fig. Figure 7 shows an MTJ 135 and the fabrication of the top electrode of an MTJ structure. In Fig. 7, an MTJ 135 in the form of a multi-material stack is deposited over the bottom electrode 131. In some embodiments, the MTJ 135 has a thickness in the range of about 15 nm to about 25 nm. The MTJ 135 can be fabricated using various methods, such as high density ionized metal plasma (IMP) deposition, high density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), and plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the MTJ 135 can include a free layer, a tunneling layer, and a pinned layer. The free layer can be a ferromagnetic material. The tunneling layer can be a first spacer layer composed of an insulator.The fixed layer may comprise two ferromagnetic layers and a second spacer layer. In the MTJ 135, the ferromagnetic material may be a metal or metal alloy, for example, Fe, Co, Ni, CoFeB, FeB, CoFe, FePt, FePd, CoPt, CoPd, CoNi, TbFeCo, and CrNi. The first spacer may be an insulator, for example, Al. 2 O 3, MgO, TaO and RuO. The second spacer may be a non-ferromagnetic material, for example, Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc and Ru. The free layer has a magnetic polarity or magnetic orientation that can be changed during a write process of its associated MRAM cell. The pinned layer has a magnetic orientation that cannot be changed during operation of its associated MRAM cell. In further embodiments, it is contemplated that the MTJ 135 may include an antiferromagnetic layer. After the MTJ 135 is formed, a top electrode layer 133 is deposited over the MTJ 135. The top electrode layer 133 may be formed using various methods, e.g.High-density ionized metal plasma deposition (IMP deposition), high-density inductively coupled plasma deposition (ICP deposition), sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the top electrode layer 133 is made of TiN.

[0034] In Fig. 8, a mask layer (not shown) is formed over the top electrode layer 133 for the subsequent formation of the MTJ structure. The mask layer may have a multi-layer structure, which may include, for example, an oxide layer, an advanced patterning film (APF) layer, and another oxide layer. The oxide layer, the APF layer, and the another oxide layer may each be formed using various methods, such as high density ionized metal plasma (IMP) deposition, high density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), low pressure chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the mask layer is configured to pattern the MTJ 135, the top electrode 133, and the bottom electrode 131.For example, the width of the masking region is determined according to the desired MTJ diameter. In some embodiments, the MTJ 135 and the top electrode 133 are fabricated by RIE to have a trapezoidal shape in a cross-sectional view.

[0035] In Fig. 9, a protective layer 127 is conformally deposited over the MTJ 135 and the top electrode 133. In some embodiments, the protective layer 127 has a thickness of about 5 nm to about 30 nm. Note that a sidewall of the MTJ 135 and the sidewall of the bottom electrode 131 are surrounded by the protective layer 127 to prevent oxidation or other contamination. Then, a dielectric layer 129, such as a TEOS layer, is conformally deposited over the protective layer 127. In some embodiments, the thickness of the dielectric layer 129 must be determined according to the elevation of its top surface relative to the top surface of the top electrode 133.

[0036] In Fig. 10, planarization is performed on the dielectric layer 129 such that the top surface of the dielectric layer 129 is substantially planar across the MRAM cell region 100A. In some embodiments, after planarization, the top surface of the dielectric layer 129 in the logic region 100B is lower than, or substantially level with, the top surface of the dielectric layer 129 in the MRAM cell region 100A. As in Fig. As shown in Figure 10, the top surface of the upper electrode 133 has been exposed from the dielectric layer 129 by planarization. Planarization may be achieved by etching back or chemical mechanical polishing (CMP) of the dielectric layer 129.

[0037] Once the top surface of the top electrode 133 of the MTJ structure 130 has been exposed from one side (e.g., the dielectric layer 129) of the MTJ structure 130, a SiC layer 141b is immediately deposited over the side (i.e., the top surface of the top electrode 133) to protect the top electrode 133 from oxidation. As discussed above, oxidation may increase the contact resistance of the top electrode 133 of the MTJ structure 130. Therefore, forming the SiC layer 141b is equivalent to SiC re-capping to insulate the top surface of the top electrode 133. The thickness of the SiC layer 141b is about 10 nm to about 30 nm. In some embodiments, the SiC layer 141b is deposited over the dielectric layer 129 of the MRAM cell region 100A and the logic region 100B. The SiC layer 141b can be formed using various methods, e.g.chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, physical vapor deposition (PVD) and thermal growth.

[0038] In Fig. 12, a photoresist layer 120 is patterned over the portion of the SiC layer 141b in the MRAM cell region 100A such that a portion of the SiC layer 141b in the logic region 100B remains exposed. Then, the portions of the SiC layer 141b, the dielectric layer 129, the protective layer 127, and the SRO layer 142 in the logic region 100B are etched back to form trenches for metal lines and metal vias in the logic region 100B. Therefore, the MRAM cell region 100A is at a higher level than the logic region 100B. In some situations, the etch back may damage or thin the SiC layer 141a in the logic region 100B. This damage creates a trench 122 in the Nth metal line 121', so that the Nth metal line 121' is exposed.The exposed Nth metal line 121' in the logic region 100B may protrude from the trench 122 and may therefore deform during a process with relatively high temperatures. The deformation due to the thermal process may, for example, cause the material, e.g., Cu, of the Nth metal line 121' to protrude from the trench 122, thereby causing a short circuit between two different conductive lines in the logic region 100B.

[0039] Then in Fig. 13, another SiC layer 141b' is conformally deposited over the SiC layer 141b in the MRAM cell region 100A and the sloped portion 144 and the SiC layer 141a in the logic region 100B after the photoresist layer 120 has been removed. The sloped portion 144 includes the edges of the SRO layer 142, the protection layer 127, and the dielectric layer 129. The Si layer 141b' is intended to re-cap or repair the SiC layer 141a to avoid exposing the Nth metal line 121'. The thickness of the SiC layer 141b' is about 100 Å to about 300 Å. In some embodiments, the SiC layer 141b' can be formed using various methods, e.g., by using a sintering technique. E.g. chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma-assisted CVD (PECVD), sputtering, physical vapor deposition (PVD) and thermal growth.

[0040] In Fig. 14, a TEOS layer 143 is deposited over the SiC layer 141b' in the MRAM cell region 100A and the logic region 100B. The thickness of the TEOS layer 143 may be approximately 150 Å.

[0041] In Fig. 15, a dielectric composite structure 180 comprising a dielectric layer, a low-k dielectric layer, and another dielectric layer is fabricated to conformally cover the TEOS layer 143 in the MRAM cell region 100A and the logic region 100B. In Fig. 15 a step difference of 181 can be seen. Therefore, a back etching, which is Fig. 16, to obtain a substantially planar top surface for the subsequent trench formation in the MRAM cell region 100A and the logic region 100B. Note that a dielectric layer 183 of the dielectric composite structure 180 actually remains in the logic region 100B after the aforementioned planarization. The dielectric layer 183 is intentionally left to act as a protective layer for the subsequent trench formation. The dielectric layer 183 can prevent the acidic solution from damaging the low-k dielectric layer during photoresist stripping.

[0042] In Fig. 17, a photoresist (not shown) is patterned over the planarized dielectric surface to form trenches for metal lines and metal vias. For example, in the MRAM cell region 100A, an (N+1)th metal line trench 123A is formed over the MTJ structure 130, exposing the top surface of the upper electrode 133 of the MTJ structure 130. A portion of the IMDs 125, a portion of the TEOS layer 143, a portion of the SiC layer 141b', and a portion of the SiC layer 141b are etched to form the (N+1)th metal line trench 123A. Thus, the (N+1)th metal line trench 123A forms an opening passing through the IMDs 125, the TEOS layer 143, the SiC layer 141b', and the SiC layer 141b.In the logic region 100B, an Nth metal via trench and an (N+1)th metal line trench (collectively designated 123B) are formed over the Nth metal line 121', exposing the top surface of the Nth metal line 121'. A portion of the IMDs 125, a portion of the TEOS layer 143, a portion of the SiC layer 141b', and a portion of the SiC layer 141a are etched to form the trench 123B. Thus, the trench 123B forms an opening extending through the IMDs 125, the TEOS layer 143, the SiC layer 141b', and the SiC layer 141a.

[0043] In the Fig. 18 and Fig. 19, the metal line trench and the metal via trench (hereinafter referred to as "trenches") are filled with a conductive metal, for example, by a conventional dual damascene process. The patterned trenches are filled with a conductive material by electroplating, and excess portions of the conductive material are removed from the surface by chemical mechanical polishing (CMP), etching, or a combination thereof. Details of the electroplating of the trenches are set forth below. The (N+1)th metal line 123' may be made of tungsten (W) and, more preferably, copper (Cu), such as AlCu (collectively referred to as Cu). In one embodiment, the (N+1)th metal lines 123' are formed using a damascene process. First, trenches are etched through the low-k dielectric layer, for example, by plasma etching, such as inductively coupled plasma (ICP) etching.A dielectric capping layer (not shown) may then be deposited on the sidewalls of the trenches. In some embodiments, the capping materials may be silicon oxide (SiO). x ) or silicon nitride (SiN x ), which may be deposited by plasma deposition, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD), including plasma-enhanced chemical vapor deposition (PECVD). Then, a seed layer of Cu is plated in the trenches. Note that the seed layer of Cu may be plated over the top surface of the top electrode 133. Then, a layer of copper is deposited in the trenches, followed by planarization of the copper layer, such as by chemical mechanical polishing (CMP), down to the top surface of the low-k dielectric layer. The exposed copper surface and the dielectric layer may be coplanar.

[0044] After excess conductive material has been removed by planarization, as shown in Fig. 19, an (N+1)th metal line 123' is formed in the MRAM cell region 100A and the logic region 100B, and an Nth metal via 122 is formed in the logic region 100B. Consequently, the (N+1)th metal line 123' passes through the IMDs 125, the TEOS layer 143, the SiC layer 141b', and the SiC layer 141b. The SiC layer 141b' and the SiC layer 141b are the remaining portions that serve to prevent oxidation of the upper electrode 133. The SiC layer 141b' and the SiC layer 141b surrounding the (N+1)th metal line 123' form the first portion 141b_1 of the semiconductor memory device 10 of Fig. 1.

[0045] Furthermore, in the logic region 100B, the Nth metal via 122 extends through the IMDs 125, the TEOS layer 143, the SiC layer 141b', and the SiC layer 141a. The SiC layer 141b' and the SiC layer 141a are the remaining parts that serve to prevent exposure of the Nth metal line 121'. The SiC layer 141b' and the SiC layer 141a surrounding the Nth metal via 122 form the second part 141b_2 of the semiconductor memory device 10 of Fig. 1.

[0046] In short, the present MRAM manufacturing process comprises two SiC re-encapping processes to improve the electrical properties of an MRAM device. The first SiC re-encapping process is performed in Fig. 11, in which the SiC layer 141b is deposited over the top surface of the top electrode 133 to protect the top electrode 133 from oxidation. The first SiC re-encapping process reduces the contact resistance of the top electrode 133 and thereby increases the signal-to-noise ratio (SNR) of the MRAM device. The second SiC re-encapping process is performed in Fig. 13, in which the SiC layer 141b' is deposited over the SiC layer 141a in the logic region 100B to re-cap or repair the SiC layer 141a to prevent exposure and oxidation of the Nth metal line 121'. The second SiC re-capping process reduces yield loss and increases the reliability of the MRAM device.

Claims

[1] A method for manufacturing a semiconductor memory device, comprising the following steps: Producing a lower cover layer (141a) over a substrate (100) in a first region (100A) and a second region (100B); Etching an opening (131') in the lower cap layer in the first region (100A) and forming a lower electrode (131) of a memory cell in the opening; Forming the memory cell (135) over the lower electrode (131) and forming an upper electrode (133) over the memory cell (135); Exposing a top surface of the upper electrode (133) of the memory cell; Producing an upper covering layer (141b) on top of the upper electrode (133); Etching a portion of the upper cap layer (141b) to form a first trench (123A) extending to the top of the upper electrode (133); and Producing a first metal line (123') in the first trench (123A) to make contact with the upper electrode (133), which also includes the following steps: Producing a photoresist layer (120) on the upper cover layer (141b_1) in the first region; Etching the upper cover layer (141b_2) in the second region to expose the lower cover layer (141a); Removing the photoresist layer (120); Producing a third cover layer (141b') on the upper cover layer (141b_1) in the first region and the lower cover layer (141a). [2] The method of claim 1, further comprising the step of: Producing a tetraethylorthosilicate (TEOS) layer (143) on the upper cover layer (141b), wherein etching the portion of the upper cap layer (141b) to form the first trench (123A) comprises: Etching the part of the upper cap layer (141b) and a part of the TEOS layer (143) to form the first trench. [3] The method of claim 1 or 2, further comprising: Creating a TEOS layer on the third cover layer. [4] A method according to any one of claims 2 and 3, further comprising the following steps: Etching a portion of the lower capping layer (141a), a portion of the third capping layer (141b'), and a portion of the TEOS layer (143) to form a second trench (123B) extending to a second metal line (121'); and Forming a third metal line (123') in the second trench (123B) to make contact with the second metal line (121'). [5] Method according to claim 4, wherein the second metal line (121´) is exposed when the upper cover layer is etched in the second region (141b_2), and producing the third cover layer (141b') on the upper cover layer (141b_1) in the first region and the lower cover layer (141a) comprises: Producing the third cover layer (141b') on the upper cover layer (141b_1) in the first region, the lower cover layer (141b') on the upper cover layer (141b_1) in the first region, and the second metal line (121'). [6] Method according to one of the preceding claims, wherein the first region (100A) is arranged over a logic region of the semiconductor memory device and the second region (100B) is arranged over a magnetoresistive cell region of the semiconductor memory device. [7] Semiconductor memory device having a first region (100A) and a second region (100B), comprising: a cover layer (141b) extending through the first region (100A) and the second region (100B), a memory structure having an electrode (133) in the first region; wherein a first part (141b_1) of the cover layer (141b) lies in the first region (100A) and is arranged above the electrode (133); and a first metal line (123') in contact with the electrode (133), wherein the first metal line (123') is arranged to pass through the first part (141b_1) of the cover layer (141b); wherein a second part (141b_2) of the cover layer (141b) lies in the second region (100b) and lies deeper than the first part (141b_1) of the cover layer (141b); and with a second metal line (121') arranged under the second part (141b_2) of the cover layer (141b); and a third metal line (122) in contact with the second metal line (121'), the third metal line (122) being arranged to pass through the second part (141b_2) of the cover layer (141b), which also has the following: a third part (141b_3) of the cover layer (141b) arranged to connect the first part (141b_1) of the cover layer (141b) and the second part (141b_2) of the cover layer (141b), the third part (141b_3) of the cover layer (141b) comprising an inclined portion. [8] Semiconductor memory device according to claim 7, wherein the first part (141b_1) of the cover layer (141b), the second part (141b_2) of the cover layer (141b) and the third part (141b_3) of the cover layer (141b) consist of silicon carbide (SiC). [9] A semiconductor memory device according to claim 7 or 8, wherein the first region (100A) is an MRAM cell region and the second region (100B) is a logic region. [10] A semiconductor memory device according to any one of claims 7 to 9, further comprising: a TEOS layer (143) arranged on the first part (141b_1) of the cover layer (141b), the second part (141b_2) of the cover layer (141b) and the third part (141b_3) of the cover layer (141b). [11] The semiconductor memory device according to claim 10, wherein the first metal line (123') is arranged to pass through the first part (141b_1) of the cap layer (141b) and the TEOS layer (143). [12] A semiconductor memory device according to claim 10 or 11, wherein the third metal line (122) is arranged to pass through the second part (141b_2) of the cap layer (141b) and the TEOS layer (143).

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