Semiconductor processes

Abstract

Semiconductor process methods, including: conformal formation of a spacer layer (121) over several spikes (110) arranged over a mask layer (210), wherein sections of the spacer layer (121) arranged over opposite side walls of adjacent of the several spikes (110) define grooves (123) between them, Filling the trenches (123) with dummy material (131), Removing first sections of the dummy material (131) in the trenches (123), thereby forming several openings (133) in the dummy material (131), Filling the multiple openings (133) with a first material (170), Removing a remaining section (130) of the dummy material (131) in the trenches (123), and Removing the multiple prongs (110) after removing the dummy material (131); including the removal of the first sections of the dummy material (131): Forming one or more mask layers (140, 150) over the spacer layer (121), the dummy material (131) and the multiple prongs (110), Forming a photoresist (160) over one or more mask layers (140, 150), Structuring the photoresist (160) to form a first structure (143) which has a first length and a first width, Transferring the first structure to one or more mask layers (140, 150), and selective removal of the dummy material (131) exposed by the first structure, thereby forming one or more of the multiple openings; and wherein the formation of one or more mask layers (140, 150) comprises forming a first mask layer (140) comprising carbon and a second mask layer (150) comprising silicon oxide carbide, successively over the spacer layer (121), the dummy material (131) and the multiple mandrels (110), including filling the multiple openings (133): Deposition of the first material (170) over the spacer layer (121) and the dummy material (131), wherein the first material (170) fills the multiple openings (133) in the dummy material (131), wherein the first material is selected from the group consisting of silicon nitride, silicon oxide and titanium oxide, wherein the first material (170) is conformally formed and provides a flat upper surface over the upper surfaces of the mandrels (110), the upper surfaces of the spacers (120) and the upper surfaces of the dummy material (131), and recessing upper sections of the first material (170) to expose the spacer layer (121) and the dummy material (131).

Description

STATE OF THE ART

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvements in integration density have resulted from gradual reductions in minimum feature size, allowing more components to be integrated into a given area.

[0002] As feature sizes continue to shrink in advanced semiconductor manufacturing processes, conventional photolithography may not provide sufficient resolution for the desired pitch sizes. Multiple patterning techniques, such as self-aligned double-patterning (SADP) and self-aligned quadruple patterning (SAQP), can be used to pattern mask layers with small pitch sizes. The mask layer structures defined by multiple patterning may need to be cut, for example, if the patterned mask layer is used to form conductive features in subsequent processing. Cut masks are used to form the cut structures. Challenges exist in the formation of cut masks. There is a need in the art for improved methods for forming cut masks.

[0003] US 9 484 258 B1 discloses a method for producing self-aligned vias (SAV), wherein an ILOS layer is formed over a dielectric layer and spacer pairs are formed over the ILOS layer, each spacer pair having a first filler formed between adjacent spacers and a second filler formed between each spacer pair.

[0004] US 2015 / 0 155 171 A1 discloses a method embodiment for patterning a semiconductor device, comprising patterning a dummy layer over a hard mask to form one or more dummy lines.

[0005] JP 2008-311623 A discloses a semiconductor device which enables precise alignment of a contact plug and a wiring line, and a manufacturing method thereof.

[0006] JP 2008-103719 A discloses a method for forming a close-pitch hard mask pattern, with which the formation of a close-pitch pattern by means of which exceeding a resolution limit in a photolithography process can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 shows a cross-sectional view of a semiconductor device according to some embodiments. Fig. 2 shows a cross-sectional view of another semiconductor device according to some embodiments. Fig. 3 to 18 show cross-sectional views of a semiconductor device at various stages of a semiconductor process according to an embodiment. Fig. 19 to 34 show cross-sectional views of a semiconductor device at various stages of a semiconductor process according to another embodiment. Fig. 35 to 37 show perspective views of a semiconductor device at various stages of a semiconductor process according to yet another embodiment. Fig. 38 shows a flow diagram of a semiconductor process according to some embodiments. DETAILED DESCRIPTION

[0008] The invention is defined by the independent claims. The dependent claims relate to further embodiments. The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.

[0009] In addition, terms relating to spatial relativity, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0010] The embodiments discussed herein relate to semiconductor processing and, more particularly, to forming mask layers used for patterning (e.g., for creating cut structures) in advanced semiconductor process nodes (e.g., 24 nm, 14 nm, 10 nm, 7 nm, or even smaller).

[0011] Fig. 1 shows a cross-sectional view of a semiconductor device 100 at a particular stage of a semiconductor process according to some embodiments. As shown in Fig. As shown in Figure 1, the semiconductor device 100 includes an etch stop layer (ESL) 610 over one or more semiconductor layers 710, a dielectric layer 510 (e.g., a low-k dielectric layer 510) over the ESL 610, and three mask layers (e.g., hard mask layers 210, 310, and 410) sequentially formed over the dielectric layer 510. A mandrel layer 115 is formed over the hard mask layer 210.

[0012] The one or more semiconductor layers 710 may be or include a semiconductor substrate (also referred to as a substrate). The substrate may comprise a crystalline silicon substrate (e.g., a wafer), although other suitable elemental semiconductors, such as suitable compound semiconductors (e.g., gallium arsenide, silicon carbide, indium arsenide, indium phosphide, or the like) or a suitable alloy semiconductor (e.g., silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide), or the like, may also be used. Additionally, the substrate may include an epitaxial (epi) layer, may be strained for performance enhancement, and / or may include an SOI (silicon on an insulator) structure. Electrical devices, such as active devices (e.g., transistors) and / or non-active devices (e.g., resistors, capacitors, diodes, and the like), may be formed in or on the substrate.In addition, the one or more semiconductor layers 710 may include metal layers over the semiconductor substrate and the electrical devices. The metal layers may include interconnect structures (e.g., electrically conductive lines and / or vias) that connect the electrical devices to implement certain functions according to the desired design. The processing disclosed in the present disclosure may be used to form, for example, conductive features (e.g., conductive lines and / or vias) that connect to the electrical devices and / or interconnect structures in the one or more semiconductor layers 710. As another example, the one or more semiconductor layers 710 may include semiconductor fin structures (e.g.,Fin structures of fin field effect transistors (FinFETs) formed in a previous patterning process, and the processing disclosed in the present disclosure may be used to form cut structures for the fin structures.

[0013] The ESL 610 is formed from a material that has high etch selectivity to the overlying dielectric layer 510, and therefore, the ESL 610 can be used to halt the etching of the dielectric layer 510. The ESL 610 may comprise silicon carbide (SiC), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), or the like. The dielectric layer 510 may comprise silicon oxide, silicon nitride, a low-k dielectric material having a dielectric constant (k value) lower than approximately 3.0, approximately 2.5, or even lower, or another suitable material.

[0014] The hard mask layer 210, in some embodiments, comprises SiO, SN, or a metal oxide, such as TiO, ZrO, ZrTiO, and may have a thickness ranging from about 5 nm to about 22 nm. The hard mask layer 310, as examples, comprises TiN or a metal oxide, such as TiO, ZrO, ZrTiO, and may have a thickness ranging from about 5 nm to about 22 nm. The hard mask layer 410, in one embodiment, comprises SiO or SN, and has a thickness ranging from about 5 nm to about 22 nm.

[0015] The mandrel layer 115 comprises silicon, such as amorphous silicon, and may be approximately 50 nm thick, as one example. The mandrel layer 115 may comprise SiC or SiOC, as another example, and may be formed using a spin-on deposition process or a chemical vapor deposition (CVD) process. The mandrel layer 115 is patterned, in some embodiments, to form mandrels 110 in Fig. 3, which are used in subsequent processing to pattern other underlying layers (e.g., the hard mask layers 210).

[0016] Fig. 2 shows a cross-sectional view of another semiconductor device 200 at a particular stage of a semiconductor process according to another embodiment. The semiconductor device 200 in Fig. 2 is the semiconductor device 100 in Fig. 1, but it includes a hard mask layer 103 and a mandrel layer 113 formed sequentially over the mandrel layer 115. The hard mask layer 103 comprises, in some embodiments, silicon oxide (SiO), SN, or a metal oxide, such as TiO, ZrO, ZrTiO. A thickness of the hard mask layer 103 may range from approximately 5 nm to approximately 22 nm. The mandrel layer 113 may have a similar composition and dimensions as the mandrel layer 115, although other compositions and dimensions are also possible. Materials and dimensions of other layers of the semiconductor device 200 in Fig. 2 can be that of Fig. 1, and therefore details are not repeated. A person skilled in the art will recognize variations and modifications of the semiconductor devices of Fig. 1 and Fig. 2. For example, the number of hard mask layers may be increased or decreased according to factors such as the desired design and processing technology. As an example, the hard mask layer 210 and the hard mask layer 410 in Fig. 1 and Fig. 2 can be omitted.

[0017] Fig. 3 to 18 show cross-sectional views of a semiconductor device 100 at various stages of a semiconductor process (e.g., a patterning process) according to one embodiment. In Fig. 3 to 18 represents a figure number with a “B” (e.g. Fig. 9B) a plan view of the semiconductor device, and a figure number with an “A” (e.g. Fig. 9A) represents a cross-sectional view along a line AA of the corresponding plan view figure (e.g. Fig. 9B). A figure number (e.g. Fig. 3) without “A” or “B” illustrates the same cross-sectional view as Fig. 9A. It should be noted that for the sake of simplicity, not all layers of the semiconductor device 100 are shown in all figures. For example, Fig. 3 only the mandrels 110 and the hard mask layer 210 are shown, and other layers underlying the hard mask layer 210 are not shown. One of ordinary skill in the art will readily recognize layers of the semiconductor device 100 that have been omitted from the figures upon reading the present disclosure.

[0018] With reference to Fig. 3, a plurality of mandrels 110 are formed over the hard mask layer 210, e.g., by patterning a mandrel layer, such as the mandrel layer 115 in Fig. 1 or the spinous layer 115 in Fig. 2. For example, the mandrel layer 115 can be Fig. 1 using a photolithographic and etching process to pattern the mandrels 110 in Fig. 3. Patterning the mandrel layer 115 may use a dry etching process with an etching process gas comprising fluorine (F) or chlorine (Cl). In one embodiment where the mandrel layer 115 comprises silicon, the mandrel layer 115 is etched using an etching process gas comprising Cl. In particular embodiments, the etching process gas is a combination of gases and may include Cl2, HBr, N2, CH4, He, and Ar. In another embodiment where the mandrel layer 115 comprises carbon, the mandrel layer 115 is etched using an etching process gas comprising F, H, or O. In particular embodiments, the etching process gas may be a combination of gases including N2, H2, NH3, and Ar. An anisotropic plasma etching process may be used to pattern the mandrel layer 115. A width W of the mandrels 110 may depend on the semiconductor process nodes used.For example, W is approximately 22 nm for a particular process node, and is approximately 14 nm for another, more advanced process node. A height H of the mandrel 110 may be approximately 50 nm, as an example, although other dimensions are also possible. Although . Fig. 3 shows only four mandrels 110, it is understood that more or fewer than four mandrels may be formed depending on the design of the semiconductor device.

[0019] The embodiments of the etching process gases described herein are merely examples and are not intended to be limiting. Other suitable etching process gases, including gas(es) different from the embodiments described herein, are also possible and are intended to be fully included within the scope of the disclosure.

[0020] As another example, the mandrel layer 115 in Fig. 1 be structured using a SADP process to Fig. 3. An SADP process can be used to form structures with dimensions smaller than those that could be achieved with the conventional photolithographic process. In the SADP process, another mandrel layer (not shown) is first deposited over the mandrel layer 115 in Fig. 1 is patterned using a photolithographic and etching process to form a plurality of mandrels (not shown) disposed on a mask layer (not shown) between the other mandrel layer and the mandrel layer 115. Next, a spacer layer (not shown) is conformally deposited over the plurality of mandrels and the mask layer. An etching process, such as an isotropic etching process, is performed to remove portions of the spacer layer disposed on the top surface of the mask layer and the top surfaces of the plurality of mandrels without significantly removing the spacer layer disposed on sidewalls of the plurality of mandrels. A subsequent selective etching process removes the plurality of mandrels. The remaining portions of the spacer layer that were disposed on sidewalls of the plurality of mandrels before the plurality of mandrels were selectively removed form a plurality of spacers (not shown) with small pitches (which, for example,half the critical dimension of the semiconductor process node). The spacer structures are transferred to the mask layer overlying the mandrel layer 115 (e.g., using an anisotropic etching process), and the patterned mask layer is used to pattern the mandrel layer 115. Fig. 1 used to insert the mandrels 110 into Fig. 3 to train.

[0021] In another embodiment, the mandrels 110 are Fig. 3 formed by a SAQP process for structuring the mandrel layer 115 in Fig. 2. A SAQP process can be implemented by performing the processing in a SADP process twice. For example, for the Fig. 2, a first SADP process similar to that described above for patterning the mandrel layer 115 in Fig. 1 described SADP process is carried out to form the mandrel layer 113 in Fig. 2 to form a plurality of mandrels (not shown) over the mask layer 103. The plurality of mandrels are used in a second SADP process used to pattern the mandrel layer 115 of Fig. 2 is carried out, which leads to the Fig. 3. An SAQP process can produce structures (e.g., mandrels 110) with finer spacing than those of an SADP process.

[0022] With reference to Fig. 4, a spacer layer 121 is formed over the mandrels 110 and the hard mask layer 210. The spacer layer 121 comprises, in some embodiments, SiO, SN, or a metal oxide (e.g., TiO). In the illustrated embodiment, the spacer layer 121 is conformal and is formed using a conformal deposition process, such as ALD. Other suitable deposition processes, such as chemical vapor deposition (CVD), may also be used. The thickness of the spacer layer 121, in one embodiment, ranges from approximately 5 nm to approximately 22 nm, although other dimensions are also possible. In another embodiment, the thickness of the spacer layer 121 is determined by the semiconductor process node used. For example, the spacer layer 121 is approximately 22 nm thick for a particular semiconductor process node, and is approximately 14 nm thick for another, more advanced semiconductor process node. As shown in Fig. 4, trenches 123' (e.g., recesses, openings, or empty spaces) are formed between adjacent mandrels 110 after the deposition of the spacer layer 121.

[0023] Next, with reference to Fig. 5, the spacer layer 121 is recessed, for example, using a dry etching process, such as an anisotropic plasma etching, to expose the upper surfaces of the mandrels 110 and the upper surface of the hard mask layer 210. In embodiments where the spacer layer 121 comprises SiO or SN, the spacer layer 121 is etched using an etching process gas comprising F. In particular embodiments, an etching process gas may be a combination of gases comprising CF4, CHF3, CH3F, N2, CH4, O2, He, and Ar. In embodiments where the spacer layer 121 comprises a metal oxide (e.g., TiO), the spacer layer 121 is etched using an etching process gas comprising Cl. In particular embodiments, an etching process gas may be a combination of gases comprising Cl2, HBr, CH4, N2, H2, He, Ar, and O2.The anisotropic plasma etching process removes portions of the spacer layer 121 disposed over top surfaces of the mandrels 110 and the top surface of the hard mask layer 210 without substantially removing remaining portions of the spacer layer 121 over sidewalls of the mandrels 110, as shown in FIG. Fig. 5. The remaining portions of the spacer layer 121 on the sidewalls of the mandrels 110 are also referred to as spacers 120. The empty spaces between adjacent spacers 120 arranged on opposite sidewalls of adjacent mandrels 110 are referred to as trenches 123.

[0024] With reference to Fig. 6, a dummy material 131 (also referred to as sacrificial material) is formed over the spacers 120, the mandrels 110 and the hard mask layer 210 and fills the trenches 123 (shown in Fig. 5). The portions of the dummy material 131 inside the trenches 123 are referred to as dummy plugs, the portions of which are replaced by a different material in subsequent processing. In some embodiments, the dummy material 131 comprises a suitable dielectric material, such as a spin-on glass (SOG) (e.g., SiOC), a spin-on dielectric (SOD) (e.g., SiO), or a spin-on metal oxide (SOM) (e.g., TiO), and is deposited using a spin-on deposition process. In other embodiments, the dummy material 131 comprises a flowable oxide (e.g., SiO) deposited using an FCVD (Flowable Chemical Vapor Deposition) process. A suitable curing process(es) may follow the deposition process to cure the deposited dummy material 131.

[0025] Different regions of the wafer comprising the semiconductor device 100 may have different feature densities (e.g., densities of spikes, trenches, etc.). The difference in feature densities may cause the dummy material 131 to have different thicknesses over different areas of the wafer (e.g., due to a different amount of the dummy material 131 that the trenches 123 can accommodate in different areas of the wafer), resulting in a loading effect. A planarization process, such as a chemical mechanical planarization (CMP) process, may be performed to planarize the top surface of the dummy material 131. In another embodiment, the wafer has a substantially uniform feature density, therefore there is little or no loading effect, in which case the planarization process may be omitted.

[0026] However, by using the above-disclosed materials for the dummy material 131, the loading effect can be effectively reduced or eliminated by the CMP process in the presently disclosed method. For example, the dummy material 131, after being cured, is sufficiently hard and responds well to the CMP process (e.g., resulting in a substantially flat top surface after the CMP process). In contrast, conventional processing may use spin-on carbon (SOC) to fill the trenches 123. Because the SOC is relatively soft, the CMP process is not effective in planarizing an uneven top surface of the SOC, and therefore, conventional processing may not be effective in managing the loading effect.

[0027] With reference to Fig. 7, upper portions of the dummy material 131 are removed to expose upper surfaces of the mandrels 110 and upper surfaces of the spacers 120. The remaining portions of the dummy material 131 within the trenches 123 (see Fig. 5) are also referred to as dummy plugs 130. An etch-back process, such as a dry etch process, may be performed using an etch process gas comprising F or Cl to remove the upper portions of the dummy material 131. In one embodiment where the dummy material 131 comprises a SOG (e.g., SiOC) or a SOD (e.g., SiO), the dummy material 131 is etched using an etch process gas comprising F. In particular embodiments, the SOG is etched using an etch process gas comprising CH3F, C4F6, O2, CF4, He, and Ar. In another embodiment, where the dummy material 131 comprises a SOM (e.g., TiO), the dummy material 131 is etched using an etch process gas comprising Cl. In particular embodiments, an etching process gas may be a combination of gases including Cl2, HBr, CH4, N2, He, and Ar. In addition to the etch-back process disclosed above, other suitable processes, such asCMP can also be used to remove the upper portions of the dummy material 131. After removal of the upper portions of the dummy material 131, upper surfaces of the mandrels 110, upper surfaces of the dummy plugs 130, and upper surfaces of the spacers 120 are substantially flush with one another, as shown in FIG. Fig. 7 shown.

[0028] Fig. 8 to 11B show processing steps for removing the dummy plugs 130 at first positions (e.g., positions passing through an opening 143 in Fig. 9A, or structures P1, P2 and P3 in Fig. 9B are exposed). In Fig. 8, a first mask layer 140, e.g. a SOC layer (spin-on carbon) comprising carbon (C), and a second mask layer 150, e.g. a SOG layer comprising SiOC, are successively deposited over the layer shown in Fig. 7 using a suitable formation method, such as a spin-on deposition process. In an embodiment in which the first mask layer 140 is an SOC layer and the second mask layer 150 is an SOG layer, a thickness of the SOC layer 140 is in a range from approximately 40 nm to approximately 200 nm, and a thickness of the SOG layer 150 is in a range from approximately 10 nm to approximately 40 nm. Next, a photoresist (PR) 160 is formed over the second mask layer 150 and patterned, for example, using a lithographic process. The patterned PR 160 has an opening 143 with a length X. In some embodiments, the length X is approximately one to three times the thickness of the spacers 120, where the thickness of the spacers 120 (also referred to as the thickness of the spacer layer 121) is measured in a direction perpendicular to the sidewalls of the mandrels 110.

[0029] In Fig. 9A, the structure (e.g., the opening 143) of the PR 160 is transferred to the first mask layer 140 (e.g., an SOC layer) and the second mask layer 150 (e.g., an SOG layer) using suitable etching processes, e.g., anisotropic plasma etching processes, and the PR 160 is removed, e.g., using an ashing process or a stripping process. In some embodiments where the second mask layer 150 is an SOG layer, the second mask layer 150 is etched using a plasma process using an etching process gas comprising F. An etching process gas may be used that is similar to that used to remove the upper portions of the dummy material 131 comprising a SOG (described with reference to Fig. 7). Furthermore, in some embodiments where the first mask layer 140 is an SOC layer, the first mask layer 140 is etched using a plasma process using an etching process gas comprising H2, N2, O2, NH3, He, and Ar. After the first mask layer 140 and the second mask layer 150 are etched, the opening 143 extends into the second mask layer 150 and the first mask layer 140, exposing portions of the dummy plugs 130 within the opening 143.

[0030] Fig. 9B shows the top view of the Fig. 9A. As mentioned above, Fig. 9A of the cross-sectional view of Fig. 9A along the line AA. Three structures (e.g. openings) P1, P2 and P3 are in Fig. 9B, where the structure P2 of the Fig. 9A. In plan view, each structure has the length X (also in Fig. 8) and a width Y. While each structure (e.g., P1, P2, or P3) may have a different length X within the range described above, all structures (e.g., P1, P2, and P3) may have a same width Y. The width Y may be in a range from approximately 5 nm to approximately 50 nm, e.g., 20 nm. According to embodiments of the present disclosure, the width Y equals the critical dimension (CD) of the semiconductor process node used in the fabrication of the semiconductor device 100. Using the same width Y for all structures enables the use of a conformal deposition process, such as ALD, to form openings 133 (see Fig. 11A, Fig. 11B and Fig. 12) and a flat upper surface for the cutting material 170 (see Fig. 12) after ALD deposition in subsequent processing, as will be described in more detail below.

[0031] It should be noted that the structures P1, P2, and P3 may not be formed simultaneously (e.g., in the same processing step or using the same photolithographic step). For example, the distance between P2 and P2 and the distance between P2 and P3 may be too small for the resolution of the photolithography, which is why all three structures P1, P2, and P3 could not be formed simultaneously using one photolithographic process. Instead, the structure P2 may be formed in one photolithographic process, and the structures P1 and P3 may be formed in another photolithographic process. For example, in Fig. 8 to 11B are performed as a first iteration to create the structure P2 and to remove the dummy plugs 130 exposed by the structure P2. Then, the processing steps shown in Fig. 8 to 11B are performed as a second iteration to create the structures P1 and P3 and to remove the dummy plugs 130 exposed by the structures P1 and P3. Details regarding the removal of the dummy plugs 130 exposed by the structures (e.g., P1, P2, or P3) are described below with reference to Fig. 10, Fig. 11A and Fig. 11B. Although Fig. 9B shows three structures (e.g., P1, P2, and P3), one skilled in the art will recognize that other numbers of structures and other numbers of iterations are possible, and that the structure(s) generated in each iteration can be adjusted, e.g., based on a desired design.

[0032] With reference to Fig. 10, the second mask layer 150 is removed from the semiconductor device 100 (e.g., using an etching process or a CMP process), and an etching process is performed to expose portions of the layer formed by the opening 143 (see also the structure P2 in Fig. 9B), thus forming one or more openings 133 at positions where the previously removed portions of the dummy plugs 130 were located. In some embodiments, the dummy plugs 130 exposed by the opening 143 are removed using a dry etching process (e.g., a plasma process) using an etching process gas comprising Cl or F. In one embodiment, where the dummy plugs 130 comprise a SOG (e.g., SiOC) or a SOD (e.g., SiO), the dummy plugs 130 are etched using an etching process gas comprising F. In another embodiment, where the dummy plugs 130 comprise a SOM (e.g., TiO), the dummy plugs 130 are etched using an etching process gas comprising Cl. In the illustrated embodiments, the etching process gas has a high selectivity of the dummy plugs 130 compared to the spacers 120 (e.g.the selectivity of the dummy plugs 130 relative to the spacers 120 is greater than 50), which is why the etching process gas removes the dummy plugs 130 exposed through the opening 143 without significantly attacking the spacers 120.

[0033] With reference to Fig. 11A and Fig. 11B, the first mask layer 140 is removed using an etching process. A dry etching process using an etching process gas comprising H2, N2, or O2 may be used to remove the first mask layer 140 (e.g., an SOC layer). Fig. 11B shows the corresponding top view for Fig. 11A. It should be noted that only the portions of the dummy plugs 130 exposed through the opening 143 (e.g., the structure P2) in Fig. 10 are removed, which is why the openings 133 are shown as small rectangles / squares within the remaining sections of the dummy plugs 130. Although the openings 133 are shown as rectangles or squares in Fig. 11B, the openings 133 may have a shape of imperfect rectangles or squares, and the openings 133 may have other shapes. Since the openings 133 may expose the underlying hard mask layer 210 (see Fig. 11A), the hard mask layer 210 is also visible in the openings 133, as in the top view of Fig. 11B.

[0034] It should be noted that not all openings 133 in Fig. 11B in a same processing step or iteration as described above with reference to Fig. 9B. For example, the openings 133 arranged on the line AA are processed in a first iteration using the structure P2 (see Fig. 9B), with each iteration representing the Fig. 8 to 11B. Then, in another iteration, other openings 133 (e.g., openings not located on line AA) are processed using the structures P1 and P3 (see Fig. 9B) are trained.

[0035] Next, with reference to Fig. 12, a cutting material 170 (also referred to as a first material) is formed over the mandrels 110, the spacers 120, (the remaining portions of) the dummy plugs 130, and the hard mask layer 210. The cutting material 170 also fills the openings 133 created by the dummy plug removal process described above. The cutting material 170 comprises, in one embodiment, SiO, SN, a metal oxide such as TiO, combinations thereof, or the like. A conformal deposition process, such as an ALD process, is used in the illustrated embodiment to conformally deposit the cutting material 170 and fill the openings 133 with the cutting material 170. It is recalled that during the creation of the structures P1, P2, and P3 (see Fig. 9B) The widths Y of all structures may have a small dimension and be equal, which is the critical dimension of the semiconductor process node. Therefore, the ALD deposition is able to fill the opening 133 and achieve a substantially planar top surface for the cutting material 170, as discussed below.

[0036] Using ALD to fill the openings 133 offers several advantages. Since ALD forms a conformal layer, and since top surfaces of the mandrels 110, top surfaces of the spacers 120, and top surfaces of the dummy plugs 130 are at the same height with each other, the conformally formed cutting material 170 also has a planar top surface above the top surfaces of the mandrels 110, the top surfaces of the spacers 120, and the top surfaces of the dummy plugs 130, with a small depression (not shown separately due to its small nature) in the planarity of the cutting material 170 appearing above the openings 133. As an example, for the openings 133 with a pitch of 40 nm (e.g., along a direction perpendicular to line AA in Fig. 11B) the size of the opening 133 (e.g. along the direction perpendicular to the line AA in Fig. 11B) may be 20 nm, and the cutting material 170 with a thickness of approximately 15 nm may be used to fill the opening 133. As another example, for the openings 133 with a pitch of 28 nm, the size of the opening 133 may be 14 nm, and the cutting material 170 with a thickness of approximately 10.5 nm may be used to fill the opening 133. After the openings 133 are filled with the cutting material 170 using ALD, the cutting material 170 may have a flat surface, except for a small depression having a depth of approximately 50 nm. By having such a flat surface, the loading effect problem associated with conventional processing is avoided by using ALD deposition for the cutting material 170, and no planarization of the cutting material 170 after ALD deposition is required.By using the dummy material 131 and the cutting material 170 in the processing, there is no longer a need for an SOC layer beneath the deposited cutting material 170, which relaxes the requirements for a low-temperature deposition process (e.g., less than approximately 200°C). This improvement, together with the ALD deposition process used, offers a wider selection of materials for the cutting material 170, which was previously unavailable with the conventional process (e.g., using an SOC layer beneath the cutting material 170).

[0037] Next, with reference to Fig. 13A, upper portions of the cutting material 170 are removed to expose the mandrels 110, the spacers 120, and the dummy plugs 130. The removal process of the cutting material 170 is controlled to stop at the upper surfaces of the spacers 120. A dry etching process using an etching process gas comprising Cl or F may be used. In one embodiment, where the cutting material 170 comprises SiO or SN, the cutting material 170 is etched using an etching process gas comprising F. In another embodiment, where the cutting material 170 comprises a metal oxide (e.g., TiO), the cutting material 170 is etched using an etching process gas comprising Cl. The etching process gas may be the same as the etching process gas used for removing the spacer layer 121, which comprises the same material, as described with reference to Fig. 5. In some embodiments, the etching process gas has an etch selectivity of the cutting material 170 relative to the spacers 120 that is greater than 10. Fig. 13B shows the corresponding top view of Fig. 13A after removing the upper sections of the cutting material 170. As in Fig. 13B, portions of the dummy plugs 130 are inserted into the first positions (e.g., the positions corresponding to the openings 133 in Fig. 11A and Fig. 11B) is replaced by the cutting material 170, which is why the cutting material 170 is embedded in the dummy plugs 130.

[0038] With reference to Fig. 14A and Fig. 14B, the remaining portions of the dummy plugs 130 are removed, and the top surface of the hard mask layer 210 is exposed. A dry etching process using an etching process gas comprising Cl or F may be used. In one embodiment where the dummy plugs 130 comprise a SOG (e.g., SiOC) or a SOD (e.g., SiO), the dummy plugs 130 are etched using an etching process gas comprising F. In another embodiment where the dummy plugs 130 comprise a SOM (e.g., TiO), the dummy plugs 130 are etched using an etching process gas comprising Cl. In the illustrated embodiments, the etching process gas has an etching selectivity of the dummy plugs 130 relative to the spacers 120 and the cutting material 170 that is greater than 50. Therefore, the etching process gas removes the remaining portions of the dummy plugs 130 without significantly attacking the spacers 120 and the cutting material 170.

[0039] Next, as in Fig. 15A and Fig. 15B (additionally illustrating the hard mask layer 310), the mandrels 110 are removed. After the mandrels 110 are removed, the spacers 120 and the cutting material 170 remain above the hard mask layer 210. The structure defined by the spacers 120 and the cutting material 170 will be transferred to the hard mask layer 210 and used to etch the underlying layers. In some embodiments, the mandrels 110 are removed using a dry etching process using an etching process gas comprising Cl or F. In one embodiment where the mandrels 110 comprise silicon, the mandrels 110 are etched using an etching process gas comprising Cl. In another embodiment where the mandrels 110 comprise carbon, the mandrels 110 are etched using an etching gas comprising F, H, or O.The etching process has a high selectivity of the mandrels 110, for example, a selectivity of the mandrels 110 relative to the spacers 120 and the cutting material 170 is greater than 50.

[0040] Etch selectivity is advantageously used in some of the previous processing steps to remove a target material without attacking other materials, e.g., during the removal of the dummy plugs 130 and the removal of the mandrels 110. The etch selectivity may be achieved by using different materials for different layers of the semiconductor device 100 and by using etching process gases that have different etch rates for different materials. In one embodiment, the spacer layer 121 (and the spacers 120) comprises a metal oxide (e.g., TiO) and is etched using an etching process gas that comprises Cl. The dummy material 131 (and the dummy plugs 130) comprises a SOG (e.g., SiOC) or an SOD (e.g.,SiO) and is etched using an etch process gas comprising F, the cutting material 170 comprises SiO or SN and is etched using an etch process gas comprising F, and the mandrels 110 comprise silicon and are etched using an etch process gas comprising Cl. Other combinations of materials and etch process gases are possible and are intended to be fully included within the scope of the present disclosure.

[0041] Next, Fig. 16, the structure defined by the spacers 120 and the cutting material 170 is transferred to the hard mask layer 210. An anisotropic plasma etch may be used to transfer the structure to the hard mask layer 210, although any other suitable etching method may also be used. In some embodiments, the hard mask layer 210 is etched using an etch process gas comprising F.

[0042] In Fig. 17, the spacer layer 120 and the cut material 170 are removed using a suitable method, such as etching or grinding, and the pattern of the hard mask layer 210 is transferred to the hard mask layer 310 using a suitable process, e.g., an anisotropic plasma etching process. In some embodiments where the hard mask layer 310 comprises TiN, the hard mask layer 310 is etched using an etching process gas comprising Cl. Fig. 17 also illustrates a hard mask layer 410 underlying the hard mask layer 310, wherein the hard mask layer 410 is patterned in subsequent processing.

[0043] Next, Fig. 18, the hard mask layer 210 is removed using a suitable method (e.g., etching or grinding), and the pattern of the hard mask layer 310 is transferred to the hard mask layer 410, e.g., using an anisotropic plasma etching process. In some embodiments where the hard mask layer 410 comprises SiO or SN, the hard mask layer 410 is etched using an etching process gas comprising F. Next, the hard mask layer 310 and the hard mask layer 410 are used to pattern the underlying dielectric layer 510. An anisotropic etching process, such as a plasma etching process, may be used to pattern the dielectric layer 510. After patterning the dielectric layer 510, openings (e.g., openings 515 and 513) are formed in the dielectric layer 510.

[0044] The openings 515 and 513 may have different depths, which may be achieved by applying a different amount of etching, e.g., in two or more processing steps. For example, a first etching process may be performed to form the openings 515 and upper portions (e.g., portions having the same depth in the dielectric layer 510 as the openings 515) of the openings 513. Next, a mask layer (e.g., a PR, not shown) is formed over the hard mask layer 310 to cover the openings 515 while leaving the openings 513 exposed, and then a second etching process is performed to extend (e.g., deepen) the openings 513, e.g., until the ESL 610 is exposed, at which time a third etching process may be used to remove portions of the ESL 610 exposed by the openings 513. As in Fig. 18, the opening 513 extends through the dielectric layer 510 and the ESL 610, while the opening 515 extends into the dielectric layer 515 without extending through the dielectric layer 515. One skilled in the art will recognize that the various openings may be used to form various conductive features (e.g., conductive lines, vias), and additional processing may be performed on the Fig. 18. For example, openings 515 and 513 may be formed as part of a multi-stage dual damascene process.

[0045] Fig. 19 to 34 show cross-sectional views of a semiconductor device 100 at various stages of fabrication according to another embodiment. Fig. The processing steps shown in Figures 19 to 34 are the same as the processing steps in Fig. 3 to 18, with similar reference numerals referring to similar elements, although some differences exist between the embodiments. Fig. The processing steps illustrated in Figures 19 to 34 are briefly discussed below, highlighting details of some of the differences between the various embodiments. One of ordinary skill in the art, upon reading this disclosure, will recognize the Fig. Fully understand the processing steps shown in Figures 19 to 34.

[0046] In Fig. 19, mandrels 110 are formed over the hard mask layer 210. A spacer layer 121 is conformally deposited over the mandrels 110 in Fig. 20, wherein trenches 123' are present between adjacent mandrels 110 (also between portions of the spacer layer 121 arranged on opposite side walls of adjacent mandrels 110). Fig. 21, a dummy material 131 is deposited over the spacer layer 121 and fills the trenches 123'. It should be noted that in Fig. 21, the deposition of the dummy material 131 is carried out without etching the spacer layer 121. In comparison with the Fig. 3 to 18 is particularly the embodiment shown in Fig. 5 is omitted in the present embodiment, which is why upper surfaces of the mandrels 110 are covered with the spacer layer 121 in the subsequent processing steps, up to the point shown in Fig. 30A, in which the upper portions of the spacer layer 121 are removed to expose the mandrels 110.

[0047] In Fig. 22, the upper sections of the dummy material 131 are removed using an etch-back process, which is discussed in Fig. 7, and the remaining sections of the dummy material 131 in the trenches 123' (see Fig. 20) form a plurality of dummy plugs 130). After recessing the upper portions of the dummy material 131, a substantially planar upper surface is achieved between the spacer layer 121 and the dummy plugs 130. An optional planarization process (e.g., a CMP process) may be performed prior to recessing the dummy material 131, similar to the discussion in Fig. 6 be carried out.

[0048] Fig. 23 to 26B show processing steps required for removing portions of the dummy plugs 130 at first positions (e.g., positions of the opening 133' in Fig. 25). Details are given in Fig. 8 to 11B. It should be noted that, in comparison with the openings 133 in Fig. 10, the openings 133' do not expose the hard mask layer 210 due to the presence of the spacer layer 121 at the bottom of the openings 133'. Next, as in Fig. 27, the cutting material 170 is deposited over the spacer layer 121 and fills the openings 133' left by the removal of the (sections of) the dummy plugs 130, similar to the processing of Fig. 12.

[0049] Fig. 28A and Fig. 28B show the structure in Fig. 27 e.g. after etching back the cutting material 170. Subsequently, the remaining sections of the dummy plugs 130 are Fig. 29 away. In Fig. 30A and Fig. 30B, the spacer layer 121 is recessed to expose the mandrels 110 and the hard mask layer 210. The recessing of the spacer layer 121 may be performed using a dry etching process using an etching process gas comprising Cl or F. The dry etching gas may have a high etch selectivity of the spacer layer 121 relative to the hard mask layer 210 and the cut material 170, e.g., an etch selectivity of the spacer layer 121 relative to the hard mask layer 210 and the cut material 170 is higher than 50. Consequently, a top surface 170U of the cut material 170 after the dry etching process is higher (e.g., extends further away from the hard mask layer 210) than top surfaces of the mandrels 110 and the top surface of the remaining portions (see markings 122A and 122B) of the spacer layer 121.In other embodiments, the dry etching gas has a high etch selectivity of the spacer layer 121 relative to the hard mask layer 210, but has a similar etch selectivity as the cutting material 170, in which case the upper surface 170U of the cutting material 170 after the dry etching process may be at the same level (not shown) with upper surfaces of the mandrels 110 and the upper surface of the remaining portions (see markings 122A and 122B) of the spacer layer 121.

[0050] After the spacer layer 121 has been removed, the remaining portions of the spacer layer 121 on the side walls of the mandrels 110 are referred to as spacers 122 (e.g., spacers 122A and spacers 122B). The spacers 122A are arranged in Fig. 14A, e.g., the spacers 122A on opposite sidewalls of the mandrels 110 are spaced from each other, and there is no spacer layer 121 between a first spacer 122A on one sidewall of the first mandrel 110 and a second spacer 122A on an opposite sidewall of a second mandrel 110. In contrast, the spacers 122B on opposite sidewalls of two adjacent mandrels 110 are connected by a remaining portion of the spacer layer 121 under the cut material 170. Therefore, the spacers 122B on opposite sidewalls of two adjacent mandrels 110 and the remaining portion of the spacer layer 121 under the cut material 170 form a U-shaped structure comprising a same material (e.g., a material used to form the spacer layer 121).The U-shaped structure represents portions of the spacer layer 121 that extend continuously from a first sidewall of a first mandrel 110 to an opposite sidewall of a second mandrel 110 adjacent to the first mandrel.

[0051] Next, the mandrels 110 are removed as shown in Fig. 31A and Fig. 31B. The spacers 120 and the cutting material 170 define a structure that will be used to pattern the underlying layers.

[0052] Fig. 32 to 34 show the transfer of the structure defined by the spacers 120 and the cutting material 170 to the hard mask layers (e.g., the hard mask layers 210, 310 and 410) and the structuring of the dielectric layer 510, similar to the processing of Fig. 16 to 18

[0053] Fig. 35 to 37 show cross-sectional views of a semiconductor device 300 at various stages of processing according to another embodiment of the present disclosure. The semiconductor device 300 is similar to the semiconductor device 100, with similar reference numerals referring to similar elements. In particular, the semiconductor device 300 is located in Fig. 35, Fig. 36 and Fig. 37 for processing steps that exceed the Fig. 31A / 31B, Fig. 33 and Fig. 34 are similar. However, there are differences between the semiconductor device 300 and the semiconductor device 100. In comparison with the semiconductor device 100 in Fig. 31A / 31B, for example, shows the semiconductor device 300 in Fig. 35 different structures, which are defined by the cutting material 170 and the spacer 122'. While the Fig. 31A / 31B may have a planar upper surface, the spacers 122' in Fig. 35 has no flat upper surface.

[0054] Fig. 38 shows a flow diagram of a semiconductor process 1000 according to some embodiments. It should be understood that the Fig. 38 is an example of many possible embodiments. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as shown in Fig. 38 can be represented, added, omitted, replaced, rearranged and repeated.

[0055] With reference to Fig. 38, at step 1010, a spacer layer is conformally formed over a plurality of mandrels disposed over a mask layer, wherein portions of the spacer layer disposed over opposite sidewalls of adjacent ones of the plurality of mandrels define trenches therebetween. At step 1020, the trenches are filled with a dummy material. At step 1030, first portions of the dummy material in the trenches are removed, thereby forming a plurality of openings in the dummy material. At step 1040, the plurality of openings are filled with a first material. At step 1050, a remaining portion of the dummy material in the trenches is removed. At step 1060, the plurality of mandrels are removed after the removal of the dummy material.

[0056] Embodiments of the methods in the present disclosure have many advantages. For example, by using SOG, SOD, or SOM as the dummy material 131, better physical properties (e.g., hardness) are achieved, and a CMP can be used to achieve a flat top surface, thereby reducing or solving the loading effect problem. By thus controlling the width Y dimension in the PR structures (e.g., structures P1, P2, P3 in Fig. 9B) to have a fixed dimension (e.g., the critical dimension of the process node), a conformal deposition process, such as ALD, may also be used to form the cut material 170 and fill the openings (e.g., the opening 133 in Fig.10) created by the dummy plug removal process. The ALD process naturally forms a flat top surface due to the underlying flat top surface, so no planarization process is required after deposition of the cutting material. Furthermore, the methods disclosed herein enable a wider selection of materials for the cutting material 170, which was previously unavailable.

[0057] In some examples, a method of a semiconductor process comprises conformally forming a spacer layer over a plurality of mandrels disposed over a mask layer, wherein portions of the spacer layer disposed over opposite sidewalls of adjacent ones of the plurality of mandrels define trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further comprises filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after removing the dummy material.

[0058] In other examples, a method of forming a mask structure includes forming a plurality of mandrels over a mask layer, forming a plurality of spacers over sidewalls of the plurality of mandrels, wherein spacers on opposite sidewalls of adjacent ones of the plurality of mandrels form trenches therebetween, and filling the trenches with a sacrificial material. The method further includes replacing a first portion of the sacrificial material with a first material, removing a remaining portion of the sacrificial material, removing the plurality of mandrels, and transferring a first structure from the spacers and the first material to the mask layer.

[0059] In yet another example, a method of semiconductor processing comprises conformally forming a spacer layer over a plurality of mandrels disposed on a mask layer, depositing a sacrificial material over the spacer layer and the mask layer using at least in part spin-on deposition or flowable chemical vapor deposition (FCV), wherein the sacrificial material comprises silicon oxide carbide, silicon oxide, or a metal oxide, the sacrificial material filling trenches between adjacent ones of the plurality of mandrels, and removing upper portions of the sacrificial material to expose a top surface of the spacer layer. The method also comprises performing at least one patterning and etching process to remove a first portion of the sacrificial material, thereby forming openings in the sacrificial material.Performing at least one patterning and etching process includes forming a first etch mask to expose the sacrificial material at first positions, the first etch mask having a first length and a first width, and selectively removing the sacrificial material at the first positions after forming the first etch mask. The method further includes filling the openings using a first material. Filling the openings includes depositing a first material over the spacer layer and the mask layer using atomic layer deposition, the first material comprising silicon nitride, silicon oxide, or titanium oxide, and removing upper portions of the first material to expose an upper surface of a remaining portion of the sacrificial material. The method further includes removing the remaining portion of the sacrificial material and removing the plurality of mandrels.

Claims

[1] A method of a semiconductor process, comprising: conformally forming a spacer layer (121) over a plurality of mandrels (110) disposed over a mask layer (210), wherein portions of the spacer layer (121) disposed over opposite sidewalls of adjacent ones of the plurality of mandrels (110) define trenches (123) therebetween, Filling the trenches (123) with a dummy material (131), Removing first portions of the dummy material (131) in the trenches (123), thereby forming a plurality of openings (133) in the dummy material (131), Filling the plurality of openings (133) with a first material (170), Removing a remaining portion (130) of the dummy material (131) in the trenches (123), and Removing the plurality of mandrels (110) after removing the dummy material (131); wherein removing the first portions of the dummy material (131) comprises: Forming one or more mask layers (140, 150) over the spacer layer (121), the dummy material (131) and the plurality of mandrels (110), Forming a photoresist (160) over the one or more mask layers (140, 150), Structuring the photoresist (160) to form a first structure (143) having a first length and a first width, Transferring the first structure to the one or more mask layers (140, 150), and selectively removing the dummy material (131) exposed by the first structure, thereby forming one or more of the plurality of openings; and wherein forming the one or more mask layers (140, 150) comprises forming a first mask layer (140) comprising carbon and a second mask layer (150) comprising silicon oxide carbide sequentially over the spacer layer (121), the dummy material (131) and the plurality of mandrels (110), wherein filling the plurality of openings (133) comprises: Depositing the first material (170) over the spacer layer (121) and the dummy material (131), wherein the first material (170) fills the plurality of openings (133) in the dummy material (131), wherein the first material is selected from the group consisting of silicon nitride, silicon oxide and titanium oxide, wherein the first material (170) is conformally formed and forms a planar upper surface over the upper surfaces of the mandrels (110), the upper surfaces of the spacers (120) and the upper surfaces of the dummy material (131), and recessing upper portions of the first material (170) to expose the spacer layer (121) and the dummy material (131). [2] The method of claim 1, further comprising: after removing the plurality of mandrels (110), transferring a structure defined by the first material (170) and the spacer layer (121) to the mask layer (210). [3] The method of claim 1 or 2, wherein conformally forming the spacer layer (121) comprises forming the spacer layer (121) using at least in part an atomic layer deposition. [4] The method of any preceding claim, further comprising: after conformally forming the spacer layer (121) and before filling the trenches (123), performing an anisotropic etching process, wherein the anisotropic etching process exposes a top surface of the mask layer (210) and top surfaces of the plurality of mandrels (110). [5] Method according to one of the preceding claims, wherein filling the trenches (123) comprises: Depositing a dummy material (131) in the trenches (123) and over the spacer layer (121), wherein the dummy material (131) is selected from the group consisting of silicon oxide carbide, silicon oxide and a metal oxide, and Removing upper portions of the dummy material (131) to expose an upper surface of the spacer layer (121), wherein after removing the upper portions, the upper surface of the spacer layer (121) and the upper surface of the dummy material (131) are flush with each other. [6] The method of claim 5, wherein the deposition is carried out at least partially using a spin-on deposition or a flowable chemical vapor deposition. [7] The method of claim 1, wherein the first width is equal to a critical dimension of the semiconductor process. [8] A method according to any one of the preceding claims, wherein depositing the first material (170) uses atomic layer deposition. [9] The method of any preceding claim, further comprising: after removing the dummy material (131) and before removing the plurality of mandrels (110), performing an anisotropic etching process to expose a top surface of the mask layer (210) and top surfaces of the plurality of mandrels (110). [10] A method of forming a mask structure, comprising: Forming a plurality of mandrels (110) over a mask layer (210), Forming a plurality of spacers (120) over side walls of the plurality of mandrels (110), wherein spacers (120) on opposite side walls of adjacent ones of the plurality of mandrels (110) form trenches (123) therebetween, Filling the trenches (123) with a sacrificial material (131), Replacing a first portion of the sacrificial material (131) with a first material (170), Removing a remaining portion of the sacrificial material (131), Removing the plurality of mandrels (110), and Transferring a first structure from the spacers (120) and the first material (170) to the mask layer (210); wherein removing the first portion of the sacrificial material (131) comprises: Forming one or more mask layers (140, 150) over the spacer layer (121), the sacrificial material (131) and the plurality of mandrels (110), Forming a photoresist (160) over the one or more mask layers (140, 150), Structuring the photoresist (160) to form a first structure (143) having a first length and a first width, Transferring the first structure to the one or more mask layers (140, 150), and selectively removing the sacrificial material (131) exposed by the first structure, thereby forming one or more of the plurality of openings (133); and wherein forming the one or more mask layers (140, 150) comprises forming a first mask layer (140) comprising carbon and a second mask layer (150) comprising silicon oxide carbide sequentially over the spacer layer (121), the sacrificial material (131) and the plurality of mandrels (110), where the replacement includes: Forming a first etching mask over the plurality of spacers (120) and the sacrificial material (131), the first etching mask having an opening (143) with a first length and a first width, selectively removing the sacrificial material (131) exposed by the first etching mask, thereby forming a plurality of first openings in the sacrificial material (131), Forming a second etching mask over the plurality of spacers (120) and the sacrificial material (131), the second etching mask having another opening with a second length and a first width, selectively removing the sacrificial material (131) exposed by the second etching mask, thereby forming a plurality of second openings in the sacrificial material (131), and Filling the plurality of first openings and the plurality of second openings with the first material (170), and , wherein filling the plurality of first openings (143) and the plurality of second openings (133') comprises depositing the first material (170) over the plurality of spacers (120) and the sacrificial material (131) using atomic layer deposition, wherein the first material (170) is selected from the group consisting of silicon nitride, silicon oxide, and titanium oxide, wherein the first material (170) is conformally formed and forms a planar top surface over the top surfaces of the mandrels (110), the top surfaces of the spacers (120), and the top surfaces of the dummy material (131). [11] The method of claim 10, wherein forming the plurality of spacers (120) comprises: Depositing a spacer layer (121) over the plurality of mandrels (110) and the mask layer (210), and Removing portions of the spacer layer (121) over the mask layer (210) and upper surfaces of the plurality of mandrels (110) while leaving portions of the spacer layer (121) over the sidewalls of the plurality of mandrels (110). [12] The method of claim 10 or 11, wherein filling the trenches (123) comprises filling the trenches (123) with the sacrificial material (131) using at least in part a spin-on deposition or an FCV deposition, and wherein the sacrificial material (131) is selected from the group consisting of silicon oxide carbide, silicon oxide and titanium oxide. [13] The method of claim 10, 11 or 12, wherein the first length and the second length are approximately one to approximately three times a thickness of the plurality of spacers (120). [14] A method of semiconductor processing, comprising: conformal formation of a spacer layer (121) over a plurality of mandrels (110) arranged on a mask layer (210), Depositing a sacrificial material (131) over the spacer layer (121) and the mask layer (210) using at least in part a spin-on deposition or an FCV deposition, wherein the sacrificial material (131) comprises silicon oxide carbide, silicon oxide or a metal oxide, wherein the sacrificial material (131) fills trenches (123) between adjacent ones of the plurality of mandrels (110), Removing upper portions of the sacrificial material (131) to expose an upper surface of the spacer layer (121), Performing at least one patterning and removal process to remove a first portion of the sacrificial material (131), thereby forming openings (123) in the sacrificial material (131), wherein performing the at least one patterning and etching process comprises: Forming a first etching mask to expose the sacrificial material (131) at first positions, the first etching mask having a first length and a first width, and selectively removing the sacrificial material (131) at the first positions after forming the first etching mask, Filling the openings (123) using a first material (170), wherein filling the openings comprises: Depositing a first material (170) over the spacer layer (121) and the mask layer (210) using atomic layer deposition, wherein the first material (170) comprises silicon nitride, silicon oxide or titanium oxide, and Removing upper portions of the first material (170) to expose an upper surface of a remaining portion of the sacrificial material (131), Removing the remaining portion of the sacrificial material (131), and Removing the plurality of mandrels (110); wherein removing the first portion of the sacrificial material (131) comprises: Forming one or more mask layers (140, 150) over the spacer layer (121), the sacrificial material (131) and the plurality of mandrels (110), Forming a photoresist (160) over the one or more mask layers (140, 150), Structuring the photoresist (160) to form a first structure (143) having a first length and a first width, Transferring the first structure to the one or more mask layers (140, 150), and selectively removing the sacrificial material (131) exposed by the first structure, thereby forming one or more of the plurality of openings; and wherein forming the one or more mask layers (140, 150) comprises forming a first mask layer (140) comprising carbon and a second mask layer (150) comprising silicon oxide carbide sequentially over the spacer layer (121), the sacrificial material (131) and the plurality of mandrels (110), wherein the first material (170) is conformally formed and forms a planar upper surface over the upper surfaces of the mandrels (110), the upper surfaces of the spacers (120) and the upper surfaces of the dummy material (131). [15] The method of claim 14, wherein performing the at least one patterning and etching process further comprises: after selectively removing the sacrificial material (131) at the first positions, forming a second etching mask to expose the sacrificial material (131) at second positions, the second etching mask having a second length and the first width, and selectively removing the sacrificial material (131) at the second positions after forming the second etching mask.

Images