Integrated voltage regulator with built-in process, temperature and aging compensation

Abstract

A method for regulating a voltage for a processor(114), wherein the method comprises: - Requesting a target frequency value (550, 650), wherein the target frequency value (550, 650) determines a target clock frequency (608) for clocking the processor (114); - Comparing the target clock frequency (608) with an initial signal to generate an error signal (509); - using the error signal (509), generating a duty cycle control signal, wherein the duty cycle control signal is used to generate a periodic waveform (510); and - Generating an output regulator voltage (526) using the periodic waveform (510), wherein the output voltage (526) serves to supply power to the processor (114).

Description

Field of invention

[0001] Exemplary embodiments according to the present invention generally relate to a power supply and, in particular, voltage regulators for supplying power to microprocessors. background

[0002] The power supply of a microprocessor typically consists of an external voltage regulator (VRM) to supply power to the on-chip devices. Normally, the supply voltage for these on-chip devices is not ideal and can fluctuate due to sudden changes in circuit activity within the microprocessor, such as those found in the... Fig. 1A and Fig. Figure 1B shows temporal variations with varying frequency content (-1KHz to >1GHz). Fig. Figure 1A illustrates a frequency response of a typical microprocessor power supply network, whereas Fig. Figure 1B illustrates a transient response of a typical microprocessor power supply network. The typical off-chip voltage regulator module typically lacks a sufficiently high bandwidth to suppress voltage variations with a frequency content above ~1 MHz, even with decoupling capacitors at various points in the power supply network (PDN).

[0003] A typical microprocessor system consists of many different frequency domains, which generally require many different VRMs (or multi-output VRMs) and a large number of off-chip components that consume valuable board space. Accordingly, it is inefficient to have several different voltage regulator modules on dedicated chips. Furthermore, efficient dynamic voltage and frequency scaling (DVFS) requires a fast voltage transition time, which is limited to approximately 10 mV / ms for external VRMs.

[0004] Another weakness of conventional voltage regulators is that the regulated voltage can be independent of environmental variations that may occur in the chip's internal devices during operation. For example, temperature variations and aging effects can significantly impact the speed of these devices and cause malfunctions. Conventional regulators are not designed to account for variations in activity, temperature, and aging, and are therefore unsuitable for modern high-performance microprocessor systems.

[0005] US Patent 2004 / 0263212A1 discloses a control method that adjusts the supply voltage based on the delay of a ring oscillator. US Patent 2013 / 0311799A1 discloses an adaptive system with multiple weighted monitors for voltage regulation. US Patent 2014 / 0266377A1 discloses a hybrid voltage regulator with combined analog transient control and digital fine control. Brief summary

[0006] Accordingly, the task is to provide an integrated voltage control system that is digitally controlled and can compensate for voltage fluctuations, process variations, temperature variations, and aging.

[0007] This problem is solved by the method according to claim 1 and by the devices according to claims 9 and 15.

[0008] In one embodiment of the present invention, all or part of the voltage regulation module is integrated on the same chip as the processor (or the load) and is digitally controlled using a desired operating frequency as an input parameter. Furthermore, in one embodiment of the present invention, the digitally controlled voltage regulator advantageously generates the minimum supply voltage required for current operation at the target frequency. This generally results in higher energy efficiency and battery life.

[0009] In addition, in one embodiment, the voltage regulator of the present invention compensates for delay variations of a critical path due to temperature changes during operation and increases in a critical path due to a decrease in transistor speed as a result of aging. This also results in higher energy efficiency and improved battery life for mobile applications.

[0010] It should be noted that, while some prior art systems employ temperature and aging compensation circuits in series with the voltage regulation module, embodiments of the present invention are more space-efficient because they integrate these compensation circuits into the feedback loop within the voltage regulation module (VRM), thus eliminating the need for a space-intensive analog-to-digital converter. Having the capacitor in the regulator's feedback loop results in lower compensation latency.

[0011] In one embodiment, a method for regulating a voltage for a processor is disclosed. The method comprises requesting a target frequency value, wherein the target frequency value determines a target clock frequency for clocking a processor. The method also comprises comparing the target clock frequency with a first signal to generate an error signal. Furthermore, the method comprises using the error signal to generate a duty cycle control signal, wherein the duty cycle control signal is used to generate a periodic waveform. The method also comprises generating an output regulator voltage using the periodic waveform, wherein the output voltage is used to supply power to the processor.

[0012] In one embodiment, a device for regulating a processor voltage is disclosed. The device comprises a comparator which has a first input that is set to a target frequency value, and wherein the target frequency value determines a target clock frequency for clocking a processor. The device also comprises a dynamic voltage-controlled oscillator (DVCO) which is used to generate a clock signal with a first frequency, wherein the first frequency is an operating frequency of the processor and a second input to the comparator, wherein the DVCO is driven by the output regulator voltage, and wherein the first frequency is compared with the target clock frequency using the comparator to generate an error signal.Furthermore, the device includes a circuit which serves to generate an output regulator voltage using the error signal, the output regulator voltage being used to supply power to the processor.

[0013] In another embodiment, a device for regulating a processor voltage is disclosed, wherein the device comprises a plurality of circuits for monitoring critical paths, which operate at an output regulator voltage. The device also includes a plurality of phase detectors, which serve to compare a plurality of delay values ​​corresponding to the plurality of critical path monitoring circuits with a target clock frequency in order to generate an error signal, wherein each of the plurality of delay values ​​represents a delay of a critical path for a respective critical path of a processor. Finally, the device includes a circuit which serves to generate the output regulator voltage using the error signal, wherein the output regulator voltage serves to supply power to the processor.

[0014] The following detailed description, together with the accompanying drawings, will provide a better understanding of the nature and advantages of the present invention. Brief description of the drawings

[0015] Exemplary embodiments of the present invention are illustrated in the figures of the accompanying drawings by way of example and without limitation, and in these, the same reference numerals refer to the same elements. Fig. Figure 1A illustrates a frequency response of a typical microprocessor power supply network. Fig. Figure 1B illustrates a transient response of a typical microprocessor power supply network. Fig. Figure 2 is a block diagram of an example of a computer system suitable for implementing embodiments of the present invention. Fig. 3 is a conventional voltage regulator with digital control. Fig. Figure 4 illustrates a voltage protection strip for temperature and aging in a system with conventional integrated voltage regulators. Fig. Figure 5 illustrates a process-, temperature-, voltage-, voltage-noise-, and aging-tolerant feedback control for voltage regulators using a dynamic voltage-controlled oscillator according to an embodiment of the present invention. Fig. Figure 6 illustrates a process-, temperature-, voltage-, and aging-tolerant feedback control for voltage regulators according to an embodiment of the present invention. Fig. Figure 7 illustrates how the delays of the Critical Path Monitoring Devices (CPMs), which are in Fig. Figure 6 illustrates how the values ​​can be compared to the reference PLL clock to generate an error signal. Fig. Figure 8 shows a flowchart of an exemplary process for regulating a voltage according to an embodiment of the present invention, which compensates for process variations, voltage variations, temperature variations and aging. Detailed description of the invention

[0016] Reference will now be made in detail to the various embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0017] Fig. Figure 2 is a block diagram of an example of a computing system 110, which can implement embodiments of the present invention. The computing system 110 essentially represents a single-processor or multi-processor computing device or system capable of executing computer-readable instructions. Examples of the computing system 110 include, without limitation, workstations, laptops, client-side terminals, servers, distributed computing systems, portable devices, or any other computer system or device. In its simplest embodiment, the computing system 110 can comprise at least one processor 114 and a system memory 116.

[0018] The processor 114 generally represents any type or form of processing unit capable of processing or interpreting data and executing instructions. In certain embodiments, the processor 114 can receive instructions from a software application or module. These instructions can cause the processor 114 to perform the functions of one or more exemplary embodiments described and / or illustrated herein. In one embodiment, the power supply network of the computing system 110 uses the voltage regulator mechanism of the present invention to supply power to the processor 114 and onboard devices included therein.

[0019] System memory 116 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or other computer-readable instructions. Examples of system memory 116 include, without limitation, RAM, ROM, flash memory, or any other suitable storage device. Although not required, in certain embodiments the computer system 110 may include both a volatile storage unit (such as, for example, system memory 116) and a non-volatile storage device (such as, for example, a primary storage device 132).

[0020] The computing system 110 can also comprise one or more additional components or elements besides the processor 114 and the system memory 116. For example, in the embodiment of the Fig. 2 a memory controller 118, an input / output (I / O) controller 120, and a communication interface 122, each of which can be interconnected via a communication infrastructure 112. The communication infrastructure 112 generally represents any type or form of infrastructure that can enable communication between one or more components of a computing device. Examples of a communication infrastructure 112 include, without limitation, a communication bus (such as Industry Standard Architecture (ISA), Peripheral Component Interconnect (PCI), PCI Express (PCIe), or a similar bus) and a network.

[0021] The memory controller 118 generally represents any type or form of device that can handle memory or data, or control communication between one or more components of the computing system 110. For example, the memory controller 118 can control communication between the processor 114, the system memory 116, and the I / O controller 120 via the communication infrastructure 112.

[0022] The I / O controller 120 generally represents any type or form of module that can coordinate and / or control the input and output functions of a computer device. For example, the I / O controller 120 can control or enable the transfer of data between one or more elements of the computing system 110, such as the processor 114, the system memory 116, the communication interface 122, the display adapter 126, the input interface 130, and the memory interface 134.

[0023] The communication interface 122 generally represents any type or form of communication device or adapter that enables communication between, for example, the computer system 110 and one or more additional devices. For example, the communication interface 122 can enable communication between a computer system 110 and a private or public network, including additional computer systems. Examples of a communication interface 122 include, without limitation, a wired network interface (such as a network interface card), a wireless network interface (such as a wireless network interface card), a modem, and any other suitable interface. In one embodiment, the communication interface 122 establishes a direct connection to a remote server via a direct connection to a network, such as the Internet.The communication interface 122 can also provide such a connection indirectly through any other suitable connection.

[0024] The communication interface 122 can also represent a host adapter configured to enable communication between the computer system 110 and one or more additional network or storage devices via an external bus or communication channel. Examples of host adapters include, but are not limited to, Small Computer System Interface (SCSI) host adapters, Universal Serial Bus (USB) host adapters, IEEE (Institute of Electrical and Electronics Engineers) 1394 host adapters, Serial Advanced Technology Attachment (SATA) and External SATA (eSATA) host adapters, Advanced Technology Attachment (ATA) and Parallel ATA (PATA) host adapters, Fibre Channel interface adapters, Ethernet adapters, or similar devices. The communication interface 122 can also enable the computer system 110 to participate in distributed or remote processing.For example, the 122 communication interface can receive instructions from a remote device or send instructions to a remote device for execution.

[0025] As in Fig. As shown in Figure 2, the computer system 110 can also include at least one display device 124, which is connected to the communication infrastructure 112 via a display adapter 126. The display device 124 generally represents any type or form of device that can visually display information transmitted by the display adapter 126. Similarly, the display adapter 126 generally represents any type or form of device configured to transmit graphics, text, and other data for display on the display device 124.

[0026] As in Fig. As shown in Figure 2, the computer system 110 can also include at least one input device 128, which is coupled to the communication infrastructure 112 via an input interface 130. The input device 128 generally represents any type or form of input device that can provide input, either computer-generated or human-generated, to the computer system 110. Examples of an input device 128 include, without limitation, a keyboard, a pointing device, a speech recognition device, or any other input device.

[0027] As in Fig. As shown in Figure 2, the computer system 110 can also include a primary storage device 132 and a backup storage device 133, which are coupled to the communication infrastructure 112 via a storage interface 134. The storage devices 132 and 133 generally represent any type or form of storage device or media capable of storing data and / or other computer-readable instructions. For example, the storage devices 132 and 133 can be a magnetic disk drive (e.g., a hard disk drive), a floppy disk drive, a magnetic tape drive, an optical drive, a flash drive, or the like. The storage interface 134 generally represents any type or form of interface or device for transferring data between the storage devices 132 and 133 and other components of the computer system 110.

[0028] In one example, a database 140 can be stored in the primary storage device 132. Databases 140 can be parts of a single database or computing device, or they can represent multiple databases or computing devices. For example, databases 140 can be part of the computing system 110 and / or parts of an example network architecture 200. Fig. 2 (below) represent (be stored on). Alternatively, databases 140 can represent (be stored on) one or more physically separate devices, which can be accessed by a computing device, such as the computing system 110 and / or parts of the network architecture 200.

[0029] Further with reference to Fig. 2. The storage devices 132 and 133 can be configured to read from or write to a removable storage unit configured to store computer software, data, or other computer-readable information. Examples of suitable removable storage units include, but are not limited to, a floppy disk, magnetic tape, optical media, flash memory device, or the like. The storage devices 132 and 133 can also include other similar structures or devices capable of loading computer software, data, or other computer-readable instructions into the computer system 110. For example, the storage devices 132 and 133 can be configured to read and write software, data, or other computer-readable information. The storage devices 132 and 133 can also be part of the computer system 110 or separate devices accessed through other interface systems.

[0030] Many other devices or subsystems can be connected to the computer system 110. On the other hand, not all components and devices that are in Fig. The equipment and subsystems shown in Figure 2 must be available to carry out the embodiments described herein. The devices and subsystems to which reference is made may also be connected to each other in ways other than those shown in Figure 2. Fig. 2 are shown. The computing system 110 can also have any number of software, firmware, and / or hardware configurations. For example, the exemplary embodiments disclosed herein can be encoded as a computer program (also referred to as computer software, software application, computer-readable instructions, or computer control logic) on a computer-readable medium.

[0031] The computer-readable medium containing the computer program can be loaded into the computing system 110. All or part of the computer program stored on the computer-readable medium can then be stored in the system memory 116 and / or multiple parts of the storage devices 133 and 134. When executed by the processor 114, a computer program loaded into the computing system 110 can cause the processor 114 to perform, or act as a means of performing, the functions of the exemplary embodiments described and / or illustrated herein. Additionally or alternatively, the exemplary embodiments described and / or illustrated herein can be implemented in firmware and / or hardware.

[0032] For example, a computer program running on processor 114 may request a different frequency than the one at which processor 114 is currently running, in which case the computer program would make a frequency request from the voltage regulation embodiment of the present invention, which in turn will vary the voltage at which processor 114 is running in order to meet the request for a higher frequency.

[0033] Integrated voltage regulators with built-in process, temperature and aging compensation

[0034] Embodiments of the present invention provide an integrated voltage regulation system that is digitally controlled and can compensate for voltage fluctuations, process variations, temperature variations, and aging. In one embodiment of the present invention, all or part of the voltage regulation module is integrated on the same chip as the processor (or the load) and is digitally controlled using a desired operating frequency as an input parameter. In this embodiment, the digitally controlled voltage regulator of the present invention eliminates the use of a voltage identification code as an input parameter and instead uses the desired operating frequency as the input parameter to the regulator control logic.

[0035] Furthermore, in one embodiment of the present invention, the digitally controlled voltage regulator optimally generates the minimum supply voltage required for operation at the target frequency. This generally results in higher energy efficiency and battery life.

[0036] Furthermore, in one embodiment, the voltage regulator of the present invention advantageously compensates for delay variations of the critical path due to temperature changes during operation, and increases in the critical path due to transistor speed degradation resulting from aging. This results in higher energy efficiency and improved battery life.

[0037] Fig. 3 is a conventional voltage regulator with digital control. Integrated voltage regulators (IVRs) integrate all or part of the VRM functionality onto the same chip as the load. A typical single-phase IVR system with a separate inductor within the package and on-chip control logic is shown in Fig. Figure 4 shows (Earth 302 has been idealized for clarity). Multiple such IVRs are used to operate several voltage domains with improved transient response time, reduced board area and component costs, and increased efficient dynamic voltage and frequency scaling (DVFS). The control logic of an IVR can be implemented with analog or digital / semi-digital circuitry.

[0038] A solution according to the present invention, as in Fig. Figure 3, which is based on digital control, includes an analog-to-digital (A / D) converter 303, which samples the output regulated voltage and compares it to a reference voltage. The reference voltage 304 is derived from a voltage identification code (VID) 305 and determines the nominal output voltage of the VRM. The error signal 306 from the A / D converter is compensated by a PID controller 307 to generate a duty cycle control signal, which is fed to a digital pulse width modulation (DPWM) block 308 to generate a periodic waveform (VPWM) 310 with the desired duty cycle using the power MOSFET 380. VPWM is used to periodically switch the disconnected inductor 311 either to a high voltage (VDDH) or ground to generate the desired output voltage, VREG 315.

[0039] The challenge with conventional chip-external or integrated voltage regulation modules, such as the one used in Fig. As shown in Figure 3, the goal is to generate a regulated voltage with minimal deviation from the desired VID code 305, and that the generated regulated voltage is independent of environmental variations that the chip's internal devices may experience during operation. However, temperature variations and aging effects can significantly impact the speed of the chip's internal devices during operation and can cause malfunctions.

[0040] Fig. Figure 4 illustrates a voltage protection band for temperature and aging in a system with conventional integrated voltage regulators. A voltage protection band is typically added for temperature, process, and aging variations to ensure the correct functioning of the logic circuits under all conditions. Critical path delay is the minimum clock period required for the processor to operate without errors. As shown in the figure, the critical path delay changes over time due to changes in voltage, temperature, and aging. Because the critical path delay is related to the voltage, the voltage required to operate at a given critical path delay also changes over time, as shown.With a conventional voltage regulator, the voltage must be set so that it is sufficient to meet the worst-case delay of the critical path. If the critical path delay is not the worst-case value, then the overvoltage is known as the voltage protection band. This added protection band (as in...) Fig. (4 shown) causes a power loss in traditional current-controlled or voltage-controlled feedback controllers, which affects the average power output and degrades battery life. The proposed embodiments of the present invention will allow the voltage change to track changes in the critical path delay, as shown in Fig. Figure 4 shows. Accordingly, an embodiment of the present invention provides a voltage regulation module which compensates for process variations, temperature variations, aging and voltage noise, thereby improving energy efficiency.

[0041] Fig. Figure 5 illustrates a process-, temperature-, voltage-, voltage-noise-, and aging-tolerant feedback control for voltage regulators using a dynamic voltage-controlled oscillator according to an embodiment of the present invention. The advantage of the circuit, which is described in Fig. As shown in section 5, in addition to compensating for process, temperature, and aging variations, e.g., voltage noise, the circuit in Fig. 5 is efficient at responding to rapidly changing noise caused by a change in the current drawn by the controller, for example, when a CPU or GPU rapidly changes its current draw.

[0042] Power supply noise has been a major problem for chips designed in recent years. In the worst case, power supply noise limits the maximum frequency the chip can achieve, thus reducing the effective performance of the product, even if worst-case noise events are very rare. To solve this problem, embodiments of the present invention use elastic clocking techniques in which the clock generator is a dynamic voltage-controlled oscillator (DVCO) 514 (as in related United States Patent Application No. 14 / 323787, filed on 3.July 2014, entitled “CLOCK GENERATION CIRCUIT THAT TRACKS CRITICAL PATH ACROSS PROCESS, VOLTAGE AND TEMPERATURE VARIATION,” which names Kalyana Bollapalli and Tezaswi Raja as inventors, and which bears attorney file number NVID-PSC-13-0308-US1, hereinafter referred to as “the DVCO application,” incorporated herein by reference), which is connected to the same voltage supply as the chip that receives the clock signal. In this circuit, during a noise event, when the voltage drops, the DVCO reduces the clock frequency, also to prevent the chip from failing. This only happens when there is a noise event. The rest of the time, when there is no noise event, the chip runs at a higher effective frequency and power. Accordingly, the design, which is described in… Fig. As illustrated in section 5, this leads to higher performance and improved performance.

[0043] As explained above, applying a fixed VID-determined output voltage is energy-inefficient due to its inability to track voltage fluctuations. The reference voltage 304 for the circuit in Fig. The reference voltage (V) typically needs to be set higher to compensate for voltage fluctuations and ensure the processor receives a minimum voltage to support its operating frequency. For example, if the processor requires at least 1 volt to run at 1 GHz, and the voltage ripple is 0.1 V, the reference voltage must be set to 1.1 V to ensure the processor receives a minimum of 1 V to run at 1 GHz. As a result, additional performance costs must be incurred to compensate for this voltage fluctuation.

[0044] In comparison, embodiments of the present invention avoid the power costs by using a dynamic voltage-controlled oscillator (DVCO) and a comparator 515 to link the processor's operating frequency to the voltage. Embodiments of the present invention therefore completely eliminate the VID code and instead use the desired operating frequency as an input parameter to the controller control logic. The desired operating frequency is entered using the target frequency 550 input parameter. PLL 574 is used to convert the entered target frequency value into a clock signal, which is then fed into the comparator module 515, using the reference clock 551 (which can specify the duration over which the comparison is made). The desired operating frequency is determined by the software applications running on the processor.For example, if a processor-intensive application is running on the processor, a higher target frequency of 550 will be requested by the application.

[0045] To achieve the best performance for a given power range, the chip must run at the maximum frequency it can reach at a given voltage. In the circuit, which is in Fig. As illustrated in Figure 5, the software application must request a voltage from the controller and, based on this voltage, request the maximum safe frequency at that voltage from the DVCO. However, the controller voltage could contain a shift due to controller tolerances, and the frequency must be provided with a safety factor to account for this shift. In the scheme shown in the exemplary embodiment of the Fig. As suggested in section 5, a frequency can be requested from the controller instead of a voltage, from the DVCO using the target frequency parameter 550. If the DVCO 514 achieves the exact requested frequency, the loop is stable. However, if the DVCO frequency differs from the requested frequency, the comparator 515 determines the frequency error 509, which is fed to the PID 507 as feedback.

[0046] The PID converts the frequency error into a duty cycle adjustment, which then directly controls the output voltage VREG 526 of the integrated controller. Changing the voltage alters the DVCO frequency until it matches the frequency requested by the software application. This differs from the conventional approach, which in Fig. Figure 3 illustrates the embodiment of the invention, which is shown in Fig. Figure 5 presents similar problems with quantization of the controller voltage requirement and also controller tolerances. Because embodiments of the present invention require a duty cycle instead of a voltage, they are not subject to any voltage granularity problems like the prior art design. Therefore, the design of the Fig. 5 any potential voltage errors due to controller tolerances, controller granularity, etc.

[0047] As mentioned in the DVCO application, the clock generation circuit disclosed therein follows a critical path of an integrated circuit across process, voltage, and temperature variations. Such a clock generation circuit enables higher performance, when conditions permit, compared to conventional techniques. Additionally, the approach disclosed therein produces a variable clock signal, for example, a clock signal that changes its frequency according to manufacturing variations and / or operating conditions. This variable clock signal contrasts with conventional techniques, which have aimed for a very stable clock signal, e.g., a quartz-controlled one, that does not vary with manufacturing variations and / or operating conditions. Accordingly, the voltage regulation system, which is described in Fig. As shown in Figure 5, process, temperature and aging variations can be compensated for by using the DVCO, which is described in the aforementioned DVCO application.

[0048] Further, as in Fig. As shown in Figure 5, the DVCO module 514 takes a voltage value, VREG 526 (which is the voltage at which the processor operates), as input and outputs a frequency related to the input voltage. The frequency 527 output by the DVCO module 514 is compared to the frequency output by the PLL module 574 using a comparator module 515. It should be noted that clock dividers can be used to split the frequency 527 and the output of PLL 574 before they are input to the comparator module 515. The frequency error 509, which is determined by the comparator module 515, is then fed to the PID 507 controller to generate a duty cycle control signal, which is fed to a digital pulse width modulation block (DPWM) 508 to generate a periodic waveform (VPWM) 510 with the desired duty cycle using the power FETs 580.VPWM is used to periodically switch the disconnected inductor 511 either to a high voltage (VDDH) or to ground in order to generate the desired output voltage, VREG 526. In this way, the exemplary embodiment of the . Fig. 5. The additional step of requesting a voltage, which is converted to a frequency and then back to a voltage (as in the design of the Fig. 3).

[0049] Nor is there a reference voltage 304 (as in the design of the Fig. 3) addresses the voltage ripple problem because the reference voltage, which can be rippled, is replaced by a frequency requirement via parameter 550. Additionally, removing analog components, such as the A / D converter 304 (and its associated analog inputs, e.g., Vref 304) and also the PID 307 with its digital components, helps to eliminate additional voltage noise in the circuit.

[0050] The DVCO 514 serves to synchronize the processor voltage with the processor frequency. The input voltage of the DVCO 514 is VREG 526, which is the same voltage at which the processor runs. Furthermore, the output frequency of the DVCO 514 is also the frequency at which the processor runs. In other words, the output of the DVCO is used as the system clock in this embodiment. By synchronizing the voltage and frequency of the processor, the voltage ripple problem is eliminated because if the voltage 526 fluctuates due to ripple, the frequency 527 at the output of the DVCO 514 will also fluctuate. For example, if the voltage 526 increases, the processor frequency 527, which is output by the DVCO, will also increase to accommodate the demand for a higher voltage. Accordingly, unlike the setup described in Fig. As illustrated in Figure 3, no additional power costs need to be paid to compensate for voltage fluctuations.

[0051] When a software application running on the processor requests a different voltage, the request is made using the target frequency input 550. The PLL 574 converts the numerical value into a clock frequency, and the comparator module 515 determines the frequency difference between the frequency 527 and the output of the PLL 574. This is then converted, using the power FETs 580, into a periodic waveform (VPWM) 510 with the desired duty cycle, which then produces the desired output voltage, VREG 526, as discussed above. Accordingly, the system, which is in Fig. As shown in Figure 5, it is simply a closed feedback loop with a frequency request. Furthermore, the system regulates itself by binding the voltage 526 to the frequency 527. This eliminates the VID code of the Fig. 3 and the power costs associated with adjusting the reference voltage 304 to a higher value to compensate for any voltage noise that may occur.

[0052] Fig. Figure 6 illustrates a process-, temperature-, voltage-, and aging-tolerant feedback control for voltage regulators according to an embodiment of the present invention. As shown in Fig. As shown in Figure 6, the proposed controller consists of several Critical Path Monitors (CPMs) (610A, 610B ... 610N) in its feedback path, the delays of which are compared against the reference PLL clock 608 to generate an error signal 609. Similar to the Fig. In section 5, module 674 is used to convert the numerical value 650 of the target frequency into a frequency 608 using the reference clock 651 (as explained above, the reference clock can indicate a time period). In one embodiment, the DVCO circuit 514 and the comparator module 515 of the Fig. 5 can also be used instead of the PLL 674 circuit, which is in Fig. Figure 6 shows how to perform the same function.

[0053] In this embodiment, the voltage is not tied to the frequency as in Fig. 5. Instead, the clock signal 608 is simply used as a monitor. A fixed frequency can be requested by the target frequency input parameter 650. The PLL 674 converts this numerical value into a fixed clock frequency 608, which is used to clock the rest of the chip, including the CPM circuits. The voltage VREG 680, which is used to operate the CPM circuits, can then be reduced until just before one of the critical path monitors 610A to 610N signals a fault. In other words, in this embodiment, the processor voltage 680 is reduced until just before a failure can be observed at one of the critical path monitors, 610A to 610N. Subsequently, the processor is operated at the lowest possible voltage at a threshold just before a failure can occur.An OR gate can be used to mark a failure if any of the inputs from CPMs 610A to 610N experience a critical failure. Accordingly, in this embodiment, the voltage is not tied to the frequency; instead, the voltage is set at a given fixed frequency until just before a critical threshold is reached, at which point one of the critical paths fails.

[0054] The comparison can be performed using an array of 620 phase detectors, or other well-known digital techniques. This is instead of having an A / D converter to compare the output voltage with a fixed voltage reference (as in Fig. 3 shown). The rest of the control logic remains the same as in the circuit shown in Fig. As shown in Figure 5, for example, the PID controller 607 is used to generate the duty cycle control signal using the error signal 609. Having CPMs 610A to 610N in the feedback loop allows for continuous adjustment of the output voltage, such that the worst-performing CPM path always corresponds to the target operating frequency over all temperature and aging variations. For example, if the transistors in a CPM degrade and the CPM delay increases, the controller increases the regulated output voltage accordingly to ensure correct operation at the transmitted frequency.

[0055] The CPMs 610A to 610N can be composed of various Critical Path Replica Canary circuits or can consist of in-situ Critical Path Delay Monitors. It is important to mitigate the safety requirements due to the variation in CPM delays across all PVT corners and aging scenarios. To ensure reliability and robustness, a lower and upper limit (Vmin and Vmax) is applied to the system. The operating system or power management unit should not request a frequency high enough to require the regulated voltage to exceed the system's Vmax. Similarly, at very low operating frequencies, the regulated voltage should never fall below the Vmin limit to ensure sufficient voltage headroom for proper circuit operation.

[0056] Fig. Figure 7 illustrates how the delays in CPMs, which are in Fig. Figure 6 illustrates how the clock signal can be compared to the reference PLL clock to generate an error signal. Assuming the clock is 708 in Fig. If clock 7 is the PLL clock and the configurable delay chain 710 is the critical path, then the receiving flop(s) at the end will register the correct value if the delay of the critical path is less than the clock period. If the critical path is slower than the clock period, then the receiving flop(s) will register the incorrect value. Accordingly, based on the value registered in the receiving flop(s), it can be determined whether clock 708 is too fast for the critical path. The additional flops at the end of the path (e.g., flops 720, 721, 712) are intended to signal when the path is about to fail. For example, if the rightmost flop 712 fails but the leftmost flop 719 does not, it indicates that a failure is imminent but has not yet occurred.For example, if the flop on the far right, 712, falls but the one on the far left, 719, does not, this indicates that a fall is imminent but has not yet occurred. Accordingly, the canary paths, which are in... Fig. The numbers shown in 7 indicate a failure before the circuit actually fails.

[0057] The digital feedback, as in Fig. Figure 6 illustrates how this helps reduce device binning time by automatically adjusting the regulated voltage based on the inherent silicon velocity of the critical paths. The devices can be coarsely binned for shipment based on representative ring oscillator or CPM velocities. The proposed feedback control can further fine-tune the system to the minimum voltage required to achieve the target frequency. Accordingly, embodiments of the present invention can reduce binning time and binning margins by fine-tuning the device voltage within a coarse bin.

[0058] The approach using digital feedback, which is in Fig. The circuit shown in Figure 6 has several advantages. As shown above, it eliminates VID decoders and optimally generates the minimum supply voltage required for current operation at the target frequency. This generally results in higher energy efficiency and battery life. The circuit of Fig. 6 also compensates for delay variations of the critical path due to temperature changes during operation. Furthermore, it compensates for an increase in the critical path delay due to transistor speed degradation resulting from aging.

[0059] Exemplary embodiments of the present invention also take into account the sensitivity of a delay of the critical path to a supply voltage, compensating for low-frequency supply fluctuations where a supply noise frequency is lower than a bandwidth of the closed-loop controller control.

[0060] It should be noted that, while some prior art systems operate temperature and aging compensator circuits in series with the voltage regulator modules, the embodiments of the present invention are more space-efficient because they integrate these compensation circuits into the feedback loop of the VRM, thus eliminating the need for a space-intensive A / D converter. Having the capacitor in the feedback loop of the regulator results in a lower compensation latency.

[0061] Fig. Figure 8 shows a flowchart of an exemplary process for regulating a voltage according to an embodiment of the present invention, which compensates for process variations, voltage variations, temperature variations and aging.

[0062] In step 802, a target frequency is requested, the target frequency value determining a frequency for clocking a processor. For example, embodiments of the present invention, as described in the Fig. 5 and Fig. Figure 6 shows, and as explained above, in comparison to conventional VRMs, instead of a voltage value, a target frequency value (e.g., by inputs 550 and 650) is specified using VIDs.

[0063] In step 804, the target clock frequency is compared with a first signal to generate an error signal. For example, the first signal in the embodiment of the Fig. 5. An output from the DVCO 514, which displays the frequency at which the processor is currently operating. In the exemplary embodiment of the Fig. 6 The target clock frequency 608 is compared with the delays of the critical path monitors 610A to 610N using phase detectors 620 to generate an error signal 609.

[0064] In step 806, a duty cycle control signal is generated, which is used to generate a periodic waveform using digital pulse width modulation. As explained above, the error signal 509 or 609 is used to generate a duty cycle control signal using a respective PID controller 507 or 607.

[0065] In step 808, the periodic waveform is used to periodically switch the disconnected inductor, e.g., inductor 511, to either a high voltage (VDDH) or ground to generate the desired output voltage, VREG.

[0066] While the preceding disclosure presents various embodiments using specific block diagrams, flowcharts, and examples, each block diagram component, flowchart step, operation, and / or component described and / or illustrated herein can be implemented individually and / or collectively using a wide variety of hardware, software, or firmware configurations (or any combination thereof). Additionally, each disclosure of components contained within other components should be considered as an example because many other architectures can be implemented to achieve the same functionality.

[0067] The process parameters and sequence of steps described and / or illustrated herein are given only as examples. For instance, while the steps illustrated or described herein are shown or discussed in a particular order, they need not necessarily be performed in that order. The various example procedures described and / or illustrated herein may also omit one or more of the steps described or illustrated herein or include additional steps beyond those disclosed.

[0068] While various embodiments are described and / or illustrated herein in the context of fully functional computer systems, one or more of these exemplary embodiments can be distributed as a program product in a variety of forms, irrespective of the specific type of computer-readable media used to actually carry out the distribution. The embodiments disclosed herein can also be implemented using software modules that perform specific tasks. These software modules may comprise script, batch, or other executable files that can be stored on a computer-readable storage medium or in a computing system. These software modules can configure a computing system to execute one or more of the exemplary embodiments disclosed herein.One or more of the software modules disclosed herein may be implemented in a cloud computing environment. Cloud computing environments can provide various services and applications over the internet. These cloud-based services (e.g., Software-as-a-Service, Platform-as-a-Service, Infrastructure-as-a-Service, etc.) may be accessible through a web browser or other remote interface. Various functions described herein may be provided through a remote desktop environment or any other cloud-based computing environment.

Claims

[1] A method for regulating a voltage for a processor(114), wherein the method comprises: - Requesting a target frequency value (550, 650), wherein the target frequency value (550, 650) determines a target clock frequency (608) for clocking the processor (114); - Comparing the target clock frequency (608) with an initial signal to generate an error signal (509); - using the error signal (509), generating a duty cycle control signal, wherein the duty cycle control signal is used to generate a periodic waveform (510); and - Generating an output regulator voltage (526) using the periodic waveform (510), wherein the output voltage (526) serves to supply power to the processor (114). [2] The method according to claim 1, further comprising: - Providing the output voltage (526) as input to a dynamic voltage-controlled oscillator. [3] The method according to claim 2, wherein the dynamic voltage-controlled oscillator generates a first signal (527), wherein the first signal (527) is a clock signal with a first frequency, wherein the first frequency is an operating frequency of the processor (114), and wherein the first frequency is directly related to the output regulator voltage. [4] The method according to any of the preceding claims, further comprising: - Compensating for the error signal (509) by a proportional-integral-differential (PID) controller to generate the duty cycle control signal; and - Generating the periodic waveform (510) from the duty cycle control signal using digital pulse width modulation and power FETs. [5] The method according to any of the preceding claims, wherein requesting a target frequency value (550, 650) comprises a software application program running on the processor (114) requesting the target frequency value (550, 650). [6] The method according to any of the preceding claims, further comprising: - Providing the output regulator voltage (526) as an input to a critical path monitoring circuit (610A-610N), wherein the target clock frequency (608) is not tied to the output regulator voltage (680), and wherein furthermore the first signal is a delay value (612) of the critical path monitoring circuit (610A-610N). [7] The method according to claim 6, wherein the comparison is carried out by a phase detector. [8] The method according to claim 7, further comprising: - Setting the output regulator voltage (680), with the critical path monitoring circuit maintaining the clock target frequency over all temperature and aging variations. [9] A device for regulating a processor voltage, the device comprising: - a comparator which has a first input which is used to be set at a target frequency value (550, 650), and wherein the target frequency value (550, 650) determines a target clock frequency (608) for clocking a processor (114); - a dynamic voltage-controlled oscillator (DVCO) which serves to generate a clock signal with a first frequency, wherein the first frequency is an operating frequency of the processor (114) and a second input of the comparator, wherein the first frequency is a function of the output regulator voltage, wherein the DVCO is driven by the output regulator voltage, and wherein the first frequency is compared with the target clock frequency (608) using the comparator to generate an error signal (509); and - a circuit which serves to generate an output regulator voltage using the error signal (509), wherein the output regulator voltage serves to supply power to the processor (114). [10] The device according to claim 9, wherein the circuit comprises: - a Proportional Integral Differential (PID) controller, which serves to compensate the error signal (509) in order to generate a duty cycle control signal. [11] The device according to claim 10, wherein the circuit further comprises: - a digital pulse width modulation block and a pair of power FETs, which serve to convert the duty cycle control signal into a periodic waveform (510). [12] The device according to claim 11, wherein the circuit further comprises: - a separate inductor, wherein the periodic waveform (510) is used to periodically switch the separate inductor to generate the output regulator voltage. [13] The device according to any one of claims 9 to 12, wherein the target frequency value (550, 650) is derived from a software application running on the processor (114). [14] The device according to any one of claims 9 to 13, wherein the target frequency value (550, 650) is converted to the target clock frequency (608) using a phase-locked loop (PLL) module. [15] A device for controlling a processor voltage, the device comprising: - a variety of circuits for monitoring critical paths (610A-610N) which operate at an output regulator voltage (680); - a plurality of phase detectors (620) configured to compare a plurality of delay values ​​assigned to the plurality of critical path monitoring circuits (610A-610N) with a target clock frequency (608) to generate a fault signal (609), each of the plurality of delay values ​​representing a critical path delay for a respective critical path of a processor (114); and - a circuit configured to generate the output regulator voltage (680) using the error signal (609), wherein the output regulator voltage (680) is configured to supply power to the processor (114). [16] The device according to claim 15, wherein the circuit comprises: - a proportional-integral differential (PID) controller configured to compensate for the error signal (609) in order to generate a duty cycle control signal; - a digital pulse width modulation block (508) and a pair of power FETs (580) configured to convert the duty cycle control signal into a periodic waveform (510); and - a separate inductor (511) wherein the periodic waveform (510) is formed, to periodically switch the separate inductor (511) to generate the output regulator voltage (680). [17] The device according to claim 15 or 16, further comprising: - a PLL module which is trained to convert a target frequency value (550, 650) which has been entered into the PLL module into a target clock frequency (608). [18] The device according to one of claims 15 to 17, wherein the output regulator voltage (680) is configured to be adapted, wherein the plurality of circuits for monitoring critical paths (610A-610N) meet the target clock frequency (608) over all temperature and aging variations. [19] The device according to any one of claims 15 to 18, wherein the target clock frequency (608) is a fixed frequency. [20] The device according to one of claims 15 to 19, wherein the plurality of circuits for monitoring critical paths (610A-610N), the plurality of phase detectors (620), the circuit and the processor (114) are integrated on the same chip.

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