Wafer for a power transistor and power transistor

Abstract

Wafer (100) for a power transistor (10) with a substrate (300) and a source metallization (400) on a first side of the substrate (300), wherein a sandwich (700) of electrically insulated interconnected copper plates (710, 720) is arranged on the source metallization (400) in an at least thermally conductive manner, wherein the substrate (300) comprises contact holes (610) which are filled with an electrically conductive filling, and the source metallization (400) is electrically connected to the filling.

Description

The present invention relates to a wafer for a power transistor and a power transistor.Prior ArtPower transistors, for example metal oxide semiconductor field effect transistors (MOSFETs), are usually based on a wafer. The wafer includes a substrate having a first side to which a source metallization is applied. Furthermore, a gate metallization is applied to the first side, which is electrically separated from the source metallization and is also referred to as a gate runner.On a second side opposite the first side, a drain metallization is applied. Between the source metallization and the drain metallization, an active region of the power transistor is formed in the substrate.For contacting the source metallization or the gate metallization, through-holes through the silicon substrate can be used, which are filled in an electrically conductive manner. Such filled through-holes are also referred to as silicon through-vias, STV for short, and are described, for example, in U.S. Pat. No. 7,683,459 B2 or in U.S. Pat. No. 7,633,165 B2. Reference is also made to DE 102 21 082 A1 and US 2013 / 0 140 684 A1.There is basically an effort to reduce the package size of power transistors. One possibility for this is offered by a chip embedding packaging technology, which is mentioned in "DrLade 1.0 The Revolutionary Next Packaging Generation", Infineon, 2013; URL: https: / / www.infineon. com / dgdl / Infineon-Package_DrBlade_1.0-PB-v01_00-EN.pdf?fileId=db3a30433d68e984013d7cde0cf05948 Germany.As the size is reduced, the need to remove heat from the power transistor is increased.Disclosure of the InventionAccording to the present invention, there is provided a wafer according to claim 1 for a power transistor and a power transistor according to claim 7.The wafer includes a substrate and a source metallization on a first side of the substrate. The wafer is characterized in that a sandwich of copper plates connected to one another in an electrically insulated manner is arranged on the source metallization at least in a thermally conductive manner.The wafer allows a low thermal impedance Z th and low thermal resistance R th. slug-up mounting. The wafer also makes possible a power transistor with heat dissipation on both sides, which can be connected with extremely low inductance.The wafer further enables the formation of a power transistor with low wafer requirements and thus low manufacturing costs and low further processing costs. Finally, the wafer also enables the formation of a power transistor, the installation space requirements of which are at the lower limit of the physically feasible one.In a preferred embodiment, the source metallization is also electrically conductively thermally connected to the copper sandwich. This enables a particularly efficient heat dissipation.Surfaces of the copper plates at which they are connected to one another can have a heat-transferring structure, such that the copper plates are connected in a thermally conductive manner. This enables even more efficient heat dissipation.The substrate may comprise a silicon layer and / or the source metallization may comprise copper. Thereby, an extremely thin substrate can be formed.According to the invention, the substrate comprises contact holes which may be filled with an electrically conductive filling, and the source metallization may be electrically connected to the filling. Thus, the substrate is prepared for contacting the source metallization from a second side opposite the first side.The substrate may be so thin that the contact holes pass through the substrate, wherein the substrate may comprise a split metallization on the second side opposite the first, and the split metallization may be split at least into a source terminal electrically connected to the filling and into a drain metallization electrically separate from the source terminal. Thus, the source metallization of the wafer can be contacted from the second side.The substrate may comprise further electrically conductively filled contact holes filled with a further electrically conductive filling, and a gate metallization may be arranged on the first side, wherein the gate metallization may be electrically connected to the further filling. Thus, the wafer for the power transistor may be pre-patterned.The power transistor according to the invention comprises the prestructured wafer, wherein the split metallization further comprises a gate terminal on the second side, which is electrically separated from the drain metallization and the source terminal by the split and is electrically connected to the further filling.The power transistor has low requirements and thus low manufacturing costs. The power transistor also allows low thermal impedance Z th and low thermal resistance R th. slug-up mounting. The power transistor also permits heat dissipation on both sides and can be connected with extremely low inductance. Finally, the power transistor also enables a design with space requirements that are at the lower limit of the physically feasible one.In a preferred embodiment, the power transistor is singulated and / or passivated.In this case, in the power transistor, the gate terminal, the source terminal and the drain metallization can be conductively connected to a printed circuit board. This is a simple form of configuring the power transistor to be drivable.Advantageous refinements of the invention are specified in the dependent claims and described in the description.DRAWINGSExemplary embodiments of the invention are explained in more detail on the basis of the drawings and the following description. The following are shown: FIG. 1 shows a chip for a power transistor, FIG. 2 shows a detail from FIG. 1, FIG. 3 shows a layer stack with a first copper layer and a second copper layer, which is connected to the chip in the exemplary embodiment of the invention, FIG. 4 shows a chip according to an embodiment of the invention, FIG. 5 shows a power transistor according to an embodiment of the invention, FIG. 6 shows a power transistor according to a further exemplary embodiment of the invention, FIG. 7 shows a power transistor according to yet another exemplary embodiment of the invention, FIG. 8 shows a chip in section, FIG. 9 shows the chip from FIG. 8 after epitaxial in-situ n++doping, FIG. 10 shows the chip from FIG. 9 after an n doping, FIG. 11 shows a detail of the chip from FIG. 10 after a front-end process, FIG. 12 shows the chip from FIG. 9 after the front-end process and the production of silicon through vias, FIG. 13 shows the chip from FIG. 12 after the production of contact vias, FIG. 14 shows the chip from FIG. 1 formed from the chip from FIG. 13 by applying a source metallization and a gate runner in section, FIG. 15 shows the chip according to the exemplary embodiment of the invention in section, FIG. 16 shows a chip according to a further exemplary embodiment of the invention in section, FIG. 17 shows the power transistor according to the exemplary embodiment of the invention from FIG. 5 in section, and FIG. 18 shows the power transistor according to the further exemplary embodiment of the invention from FIG. 6 in section.Embodiments of the InventionIn FIG. 1, a chip for a power transistor 10 is shown. FIG. 2 shows a detail of FIG. 1 in more detail. FIG. 14 shows the chip from FIG. 1 in section. The chip 100 includes a source metallization 400 on a first side of a substrate 300. The substrate 300 is, for example, a silicon substrate or a gallium nitride substrate.In FIG. 2, it can be seen that the chip 100 further comprises a gate gun 500 arranged on the first side with passivation. By means of contact holes 610 in the silicon substrate 300 which are provisionally still formed as blind holes, the source metallization 400 can be connected to a source terminal on the second side after the chip has been thinned back. By means of at least one further contact hole 620, also provisionally still formed as a blind hole, in the silicon substrate 300, the gate metallization 500 (gate tuner) can be connected to a gate connection on the second side after the chip has been thinned back. The contact holes 610, 620 are therefore designed to form silicon through vias, or STV for short, or through silicon vias, or TSV for short.FIG. 3 shows a layer stack. The layer stack 700 comprises a first copper layer 710 and a second copper layer 720, one side of which is thermally conductively connected, for example sintered, soldered or bonded, to one side of the first copper layer 710. A further copper layer can be thermally conductively connected, for example sintered, soldered or bonded, to the other side of the first copper layer 710.FIG. 4 shows a chip according to an embodiment of the invention. In this case, the chip from FIG. 1 is connected to the layer stack from FIG. 3. The source metallization 400 is in this case connected to an opposite side of the second copper layer 720 in a thermally conductive and electrically insulated manner, such that the second copper layer 720 is arranged between the source metallization 400 and the first copper layer 710. FIG. 15 shows the chip from FIG. 4 in section. Above the source metallization 400, and optionally above the gate gunner 500, the layer stack 700 with the first copper layer 710 and the second copper layer 720 is arranged. The second copper layer 720 is electrically insulated at least from the gate gunner 500.FIG. 16 shows the chip according to a further exemplary embodiment of the invention in section. The chip is additionally thinned back from a second side opposite the first side. Through holes have been formed by thinning the chip back from the second side out of the contact holes 610, 620 preliminarily formed as blind holes. In particular, this allows the electrical contacting of a conductive filling in the contact holes 610, 620 from the second side. Thanks to the stabilization by the copper layers 710, 720, extremely strong redilferring is possible without risk of bending or breaking the chip.FIG. 5 shows a power transistor 10 according to an embodiment of the invention. FIG. 17 shows the power transistor 10 according to the exemplary embodiment of the invention from FIG. 5 in section.By metalization the red-thinned second side and electrically separating a portion of the metalization from other portions of the metalization in the drain metalization 200, which is gate terminal 220 and source terminal 210, the power transistor 10 is formed. All electrical connections are thus on one side. Direct mounting by direct copper bonding or onto a printed circuit board (PCB) is thus possible. The compact construction makes possible an extremely low-inductive and low-ohmic connection.FIG. 6 shows the power transistor 10 according to a further embodiment of the invention. FIG. 18 shows the power transistor 10 according to the further exemplary embodiment of the invention from FIG. 6 in section. The power transistor 10 is singulated, for example by sawing, and passivated, for example by molding.FIG. 7 shows a power transistor according to yet another embodiment of the invention. The power transistor 10 of FIG. 6 has been passivated. Subsequently, the second side of the chip was connected to printed circuit board 960 (PCB). The power transistor 10 may be soldered or directly mounted and / or directly contacted on the PCB. A heat-removing element 950 is arranged on the copper layers 700 in a slug-up assembly.FIG. 8 shows a chip for producing the power transistor in section. The chip comprises a base material which is only weakly n-doped at most and can therefore be produced at low cost. FIG. 9 shows the chip of FIG. 8 after an epitaxial in situ n++doping. A stronger in situ n++ epitaxial layer 120' is introduced into the chip 100.FIG. 10 shows the chip from FIG. 9 after an n doping. Here, a lightly n doped epitaxial layer 110 has been formed in the stronger in situ n++ epitaxial layer 120'. A thinner situ n++ epitaxial layer 120 remains underneath.The chip of FIG. 10 comprises, adjacent to the first side, an n epitaxial layer 110 of, for example, 9-11 μm, preferably 10 μm thickness, which is in turn adjoined thereunder by an in situ n++ epitaxial layer 120 of, for example, 18-22 μm thickness, preferably 20 μm thickness.FIG. 11 shows a detail of the chip of FIG. 10 after a front end process in which an implantation has been performed in a region of the n epitaxial layer 110 and the in situ n++ epitaxial layer 120. The front end process can already be optimized for a future package.FIG. 12 shows the chip of FIG. 10 after the front end process and the generation of trench isolation 630 (shallow trench isolation, STI). By means of an etched trench, for example, the front-end processed region is insulated in such a way that the region can form an active region 800.FIG. 13 shows the chip from FIG. 12 after the production of contact holes. In other regions of the n epitaxial layer 110 and the in situ n++ epitaxial layer 120 isolated from the region by the STI, the vias 610, 620 preliminarily formed as blind holes are formed and conductively filled.The source metallization 400 is disposed on the n epitaxial layer 110 over the active region 800 and further in conductive contact with the fill in the contact holes 610. The gate tuner 500 is arranged only over the further contact holes 620, but not over the active region. The gate tuner 500 is furthermore arranged in conductive contact with the filling in the further contact holes 620. Gate tuner 500 and source metallization 400 are insulated from one another.This form of processing the chip results in a low oxide thickness and high insulation strength.In one embodiment, the invention comprises a power MOSFET with drain metallization on the back side and source metallization on the front side. The front-side source metallization is connected to the rear side via a number of through-silicon vias (STV).A gate runner is also connected to the back side via one or more STVs. A first copper layer is electrically insulatingly bonded (for example sintered) to a second copper layer. The second copper layer is connected to the source metallization. In the exemplary embodiment, surfaces of the two joining surfaces are provided with a structure which ensures improved heat transfer. However, this is optional.In the exemplary embodiment, the power MOSFET is singulated by two sawing steps ("dual dicing") carried out, for example, with a laser, and the copper silicon die is subsequently passivated. However, this is optional.The resulting chip size package consists essentially of two copper layers and the active component. The contacting of source, gate and drain can be effected as follows:The drain metallization is on an accessible side of the chip size package and may be soldered directly or sintered directly, for example.For contacting the source metallization, TSVs conductively filled with Si 2 O 3 are applied, for example, and go through the entire chip to the source metallization.For contacting the gate tuner, for example, further TSVs conductively filled with Si 2 O 3 are applied, which likewise pass through the entire chip as far as the gate tuner.The electrical fill of the TSV is not connected to the front side metallization.Copper layers which are electrically insulated from one another, are electrically conductively sintered, soldered, or bonded to the chip top side on this TSV chip. The two copper layers may have a surface structure for low thermal resistance.The stack of two copper, insulation, copper and silicon is thinned back to such an extent that only a very thin silicon layer remains. The strong redelowing is possible because the Cu-Si construction is mechanically very stable and no problems due to chip bending or breakage occur. The very thin silicon layer is structured opposite the source metallization by a full-area applied metallization and subsequently divided up metallization into gate terminal, source terminal and drain metallization, for example by dual dicing.A laser sawing method can be used here. In a first sawing step, the substrate around the TSV and gate region is removed. Gate terminal, source terminal and drain metallization are thereby electrically separated.In a second sawing step, the chip-layer stack composite is singulated. The resulting single die may optionally be passivated.A further possible exemplary embodiment of the invention relates to a method and is based on a weakly n-doped base material. This offers significant cost advantages compared to a special highly doped base material.A highly doped n++ layer is applied into the base material from one side by in situ doped epitaxy. A low-doped n-region is then deposited thereon.On the side, an active region is then formed, for example, by trench etching, implantation and insulation, for example by STI. Furthermore, silicon through vias (STV) are formed or prepared.An insulated metal substrate (IMS) is bonded, sintered, soldered or bonded over the whole area of the processed chip.In an optional development of the method, the bonded silicon chip is thinned back. A substantial advantage due to the mechanical stabilization of the IMS chip is a very strong rediluted (for example to a residual Si thickness of 20-30.mu.m) without problems.The method may further comprise metallization of the thinned-back chip on the second side opposite the one side and structuring of the metallization. The chip can be sawn or singulated differently. The singulated device may be molded. All contacts are now located on the accessible side opposite the copper layer stack. In the upward direction, insulated slug-up heat dissipation is possible.

Claims

Wafer (100) for a power transistor (10) having a substrate (300) and a source metallization (400) on a first side of the substrate (300), wherein a sandwich (700) made of copper plates (710, 720) which are electrically connected to one another in an electrically insulated manner is arranged at least thermally conductively on the source metallization (400), wherein the substrate (300) comprises contact holes (610) which are filled with an electrically conductive filling, and the source metallization (400) is electrically connected to the filling.The wafer of claim 1, wherein the source metallization (400) is also electrically conductively connected to the sandwich (700).The wafer of claim 2, wherein surfaces of the copper plates (710, 720) at which they are connected to each other have a heat transfer structure, such that the copper plates (710, 720) are thermally conductively connected.Wafer according to one of the preceding claims, wherein the substrate (300) comprises a silicon layer and / or the source metallization (400) comprises copper.The wafer of claim 1, wherein the substrate (300) is so thin that the contact holes (610) pass through the substrate (300), and wherein the substrate (300) comprises a split metallization on a second side opposite the first, and the split metallization is split into at least a source terminal (210) electrically connected to the fill and a drain metallization (200) electrically separate from the source terminal (210).The wafer of claim 5, wherein the substrate (300) comprises further electrically conductively filled vias (620) filled with a further electrically conductive filling and having a gate metallization (500) on the first side, the gate metallization (500) being electrically connected to the further filling.The power transistor (10) with a wafer of claim 6, wherein the split metallization further comprises a second side gate terminal (220) electrically separated from the drain metallization (200) and the source terminal (210) by the split and electrically connected to the further fill.The power transistor (10) of claim 7, wherein the power transistor (10) is singulated and / or passivated.The power transistor (10) of claim 7 or 8, wherein the power transistor (10), the gate terminal (220), the source terminal (210), and the drain metallization (200) are conductively connected to a printed circuit (960).

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