Collision detection for slave storage devices

Abstract

Procedure that includes: Sending (308), using a control device (122) of a memory device (107), a first bit on a data line; in response to transmitting a first bit on the data line, determining (310) a line level of the data line using the controller (122); in response to determining the line level of the data line, determining (316), using the control device, whether the line level of the data line corresponds to the first bit, and in response to determining that the line level of the data line does not correspond to the first bit, determining (318), using the controller, that a collision has occurred on the data line; Receiving (302) an indication of a transmit buffer empty event using firmware executed on a processor of the control device and from a bus data transmission unit of the control device, and in response to receiving (302) the indication of the transmit buffer empty event, outputting (304) the first bit into a transmit holding register of the control device using the firmware, wherein sending (308) the first bit on the data line occurs in response to outputting the first bit to the transmit holding register.

Description

TECHNICAL FIELDThe disclosure relates generally to memory devices.BACKGROUNDA bus is a data transfer system that transfers data between memory devices. Buses may be parallel buses which transmit data words in parallel on multiple wires, or serial buses which transmit data in bit serial form. Collisions may occur when multiple memory devices on a bus are transmitting data at the same time, which may result in corruption of the data on the bus. As an attempt to avoid such collisions, the storage devices may be configured with specialized hardware that supports various arbitration schemes.U.S. Pat. No. 6,625,163 B1 relates to collision detection on a differential bus. US 2015 / 0 032 936 A1 relates to methods for identifying read / write access collisions for a storage medium. US 2014 / 0 173 162 A1 relates to a command queue for a communication bus. The document US 2010 / 0 153 601 A1 relates to a method for avoiding transaction collisions on a bus. The object is to improve the detection of collisions on a data line.SUMMARYAccording to the invention there is provided a method, a storage device, a non-transitory computer readable storage medium and a system having the features of the independent claims; dependent claims relate to preferred embodiments.In one example, a method includes transmitting a first bit on a data line using a controller of a memory device. The method further includes, in response to transmitting the first bit on the data line, determining a line level of the data line using the controller. The method further includes, in response to determining the line level of the data line, determining, by the controller, whether the line level of the data line corresponds to the first bit, and in response to determining that the line level of the data line does not correspond to the first bit, determining, by the controller, that a collision has occurred on the data line.In another example, a storage device (storage device) includes a plurality of storage devices (memory devices) logically divided into a plurality of blocks and a control device. The controller is configured to transmit a first bit on a data line and determine a line level of the data line in response to transmitting the first bit on the data line. The controller is further configured to determine whether the line level of the data line corresponds to the first bit in response to determining the line level of the data line, and determine that a collision has occurred on the data line in response to determining that the line level of the data line does not correspond to the first bit.In another example, a non-transitory computer readable storage medium is encoded with instructions that, when executed, cause one or more processors of a memory device to transmit a first bit on a data line and determine a line level of the data line in response to transmitting the first bit on the data line. The instructions further configure one or more processors of the memory device to determine whether the line level of the data line corresponds to the first bit in response to determining the line level of the data line, and determine that a collision has occurred on the data line in response to determining that the line level of the data line does not correspond to the first bit.In another example, a system includes means for transmitting a first bit on a data line, means for determining a line level of the data line in response to transmitting the first bit on the data line, means for determining whether the line level of the data line corresponds to the first bit in response to determining the line level of the data line, and means for determining that a collision has occurred on the data line in response to determining that the line level of the data line does not correspond to the first bit.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a conceptual and schematic block diagram illustrating an example storage environment in which multiple storage devices may interact with a host device, in accordance with one or more techniques of this disclosure. FIG. 2 is a conceptual and schematic block diagram illustrating an example storage environment in which a storage device may interact with a host device, in accordance with one or more techniques of this disclosure. FIG. 3 is a conceptual diagram illustrating an example technique that may implement at least one processor for collision detection according to one or more techniques of this disclosure. FIG. 4 is a flow chart illustrating an example technique that may implement at least one processor for collision detection according to one or more techniques of this disclosure.DETAILED DESCRIPTIONThe techniques of this disclosure enable devices without specialized hardware to detect collisions on a shared bus. For example, a slave device may write to a shared bus and determine a line level of the shared bus to determine whether the line level is the expected line level. If the line level is not the expected line level, the slave device may determine that a collision has occurred and end another data exchange on the bus until a next start condition. In particular, techniques of this disclosure may enable a controller of a memory device to execute code that causes the controller to read a system bus data line of a shared bus, determine a current line level of the system bus data line, compare the current line level to an expected line level, and if the current line level and the expected line level are sufficiently different, determine that a collision has occurred. In this way, slave devices may be configured to detect collisions without specialized collision detection hardware, which may allow multiple devices to operate on a single shared bus while maintaining data integrity.FIG. 1 is a conceptual and schematic block diagram illustrating an example storage environment 10 in which multiple storage devices may interact with a host device 102, in accordance with one or more techniques of this disclosure. The storage environment 10 may include the host device 102 connected to a master storage device 104 and a plurality of slave storage devices 106A- 106N (collectively, "slave storage devices 106") via a bus 108. In some examples, the bus 108 may support data exchange between the host device 102 with the master storage device 104 and multiple slave storage devices 106. In some examples, the slave storage devices 106 may share a common address on the bus 108. In some examples, bus 108 may conform to an NVME MI specification, such as the NVME MI specification described in NVM Express Management Interface Revision 1.0 of November 17, 2015, the entire contents of which are incorporated herein by reference.The master storage device 104 may be configured to control the slave storage devices 106. For example, the master storage device 104 may send a stop command to the slave storage devices 106 via the bus 108 that causes the slave storage devices 106 to cease sending on the bus 108. In some cases, the master storage device 104 may send a start command to the slave storage devices 106 via the bus 108 that causes one or more of the slave storage devices 106 to begin sending on the bus 108.The master storage device 104 may be any device capable of storing data that the host device 102 can access using the bus 108. In some examples, the master storage device 104 may include a non-volatile memory array (e.g., a solid-state drive (SSD)) for storing the data that the host device 102 may access using the bus 108. For example, the master memory device 104 may include a controller, a non-volatile memory array, a cache, and an interface. In some examples, the master storage device 104 may include a magnetic recording (e.g., a hard disk drive (HDD)) for storing the data that the host device 102 can access using the bus 108. For example, the master storage device 104 may include a controller, a magnetic recording with overlapping magnetic recording, a buffer, and an interface.In some examples, the master storage device 104 may be substantially similar to the slave storage devices 106 except that the master storage device 104 is treated as a master device on the bus 108. For example, the master memory device 104 may generate a clock signal that may be used by the slave memory devices 106. In some cases, the master storage device 104 may include an arbitration module. In some examples, the master storage device 104 and the slave storage devices 106 may be different. For example, the master storage device 104 may omit an arbitration module. In some examples, the master storage device 104 may conform to the System Management (SM) bus (SMBus), such as the SMBus described in the "System Management Bus (SMBus) Specification Version 3.0" of the System Management Interface Forum, Inc., of December 20, 2014, the entire contents of which are incorporated herein by reference. For example, the master storage device 104 may be configured to perform arbitration with other master storage devices on the bus 108.The host device 102 may use storage devices included in the master storage device 104 and the slave storage devices 106 to store and retrieve data. The host device 102 may be any computing device, such as, but not limited to, a computer server, a network attached storage unit (NAS), a desktop computer, a notebook computer (e.g., a laptop), a tablet computer, a set-top box, a mobile computing device such as a "smartphone," a television, a camera, a display device, a digital media player, a video game console, a video streaming device, or the like. The host device 102 may include a computing device, which may refer to any form of hardware capable of processing data, and may be a general purpose computing device (such as a central processing unit (CPU)), dedicated hardware (such as an application specific integrated circuit (ASIC)), configurable hardware such as a field programmable gate array (FPGA), or any other form of computing device configured using software instructions, microcode, firmware, or the like.The bus 108 may include a data line for sending data between the host device 102, the master storage device 104, and the slave storage devices 106. For example, bus 108 may include a serial data line (SDA). Bus 108 may conform to any suitable protocol and standard. For example, bus 108 may conform to the SMBus. In some cases, bus 108 may conform to the Inter-Integrated Circuit (I2C), such as the I2C described in "I2C-Bus Specification and User Manual" Rev. 6, April 4, 2014, the entire contents of which are incorporated herein by reference. In some examples, bus 108 may include a clock line for timing a data transfer. For example, bus 108 may include a serial clock line (SCL). In some examples, the clock line may indicate a timing for transferring data on a data line. For example, the host device 102 may read data during a rising edge of a clock signal transmitted on the clock line of the bus 108.In some examples, each slave storage device 106 performs collision detection using a corresponding one of the arbitration modules 110A-N (collectively, "arbitration modules 110"). For example, the arbitration module 110A of the slave storage device 106A may recognize an arbitration issue (e.g., a collision) between the slave storage devices 106 and terminate another sending to prevent data corruption on the bus 108. In some examples, arbitration modules 110 may be implemented in software. For example, arbitration module 110A may include firmware that, when executed, detects a collision. In some examples, arbitration modules 110 may operate with a bus communication device. For example, firmware of arbitration module 110A may determine whether a collision has occurred on the data line of bus 108, and the bus communication unit may determine when to send data on the data line of bus 108 (e.g., at a rising edge of a clock line of bus 108).Arbitration modules 110 may synchronize with bus 108 to determine when to send data. In some examples, arbitration modules 110 may initiate transmission of data in response to a transmit buffer empty event. For example, upon receiving an indication of the transmit buffer empty event, arbitration module 110A may monitor bus 108 for an acknowledgement and begin monitoring transmission of data on bus 108 one clock cycle after detecting the acknowledgement. In this way, arbitration module 110 may synchronize with bus 108 to detect a collision.After synchronization with the bus 108, the arbitration modules 110 may determine whether a collision has occurred on the bus 108. For example, arbitration module 110A may determine that a collision has occurred on bus 108 if a line level (e.g., a logical '1') on bus 108 does not match an expected line level (e.g., a logical '1') output to a transmit hold register. In some examples, the line level and the expected line level may not match when more than one slave storage device of the slave storage devices 106 is transmitting on the bus 108. For example, a line level of bus 108 may indicate a logical '0' when arbitration module 110A sends a logical '1' and arbitration module 110B sends a logical '0' during the same clock cycle.The slave storage devices 106 may end sending on the bus 108 when a collision has occurred on the bus 108. For example, if arbitration module 110A determines that a collision has occurred on bus 108, arbitration module 110A may cause slave storage device 106A to end sending on bus 108. In this way, arbitration modules 110 may perform arbitration by attempting to access bus 108 and terminating output for transmission on bus 108 in response to detecting a collision on bus 108.FIG. 2 is a conceptual and schematic block diagram illustrating an example storage environment 12 in which a slave storage device 107 may interact with the host device 102, in accordance with one or more techniques of this disclosure. As shown in FIG. 2, the slave storage device 107 may include a controller 122, a storage element 126, a cache 124, and an interface 120. In some examples, the slave storage device 107 may include other components not shown in FIG. 2 for clarity. For example, the slave storage device 107 may include power supply components including, for example, a capacitor, a supercapacitor, or a battery; a printed board (PB) to which components of the slave storage device 107 are mechanically attached, and including electrically conductive traces electrically connecting components of the slave storage device 107, or the like.The slave storage device 107 may be communicatively coupled to the host device 102 via the interface 120. A mechanical connection and electrical connection, or both, may be provided to the host device 102 through the interface 120. For example, the interface 120 may be configured to connect to a data line of the bus 108. In some examples, interface 120 may be configured to connect to a clock line of bus 108. The interface 120 may operate according to a suitable protocol. For example, the interface 120 may operate in accordance with non-volatile memory (NVM) Express™ (NVMe), such as the NVM subsystem described in "NVMe Revision 1.2a", dated October 23, 2015, the entire contents of which are incorporated herein by reference. In some cases, the interface 120 may operate according to one or more of the following protocols: NVMe, NVMe MI, I2C, Advanced Technology Attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), fibre channel, small computer system interface (SCSI), serially attached SCSI (SAS), peripheral component interconnect (PCI), and PCI express. The electrical connection of the interface 120 (e.g., the data bus, the control bus, the clock bus, etc.) may be electrically connected to the controller 122, thereby providing an electrical connection between the host device 102 and the controller 122, which allows data to be exchanged between the host device 102 and the controller 122.The cache 124 may store data for transmission onto the bus 108. For example, controller 122 may write data to a transmit hold register of latch 124. Then, at a later time (e.g., during a rising clock edge of a clock signal), the interface 120 may transmit the data stored in the transmit hold register of the latch 124 to the host device 102 on the bus 108. In some examples, cache 124 may include volatile memory. In some examples, cache 124 may include non-volatile memory. For example, controller 122 may store information stored in the cache in cache 124 until information stored in the cache is written to storage element 126. Examples of the cache 124 include, but are not limited to, random-access memory (RAM), dynamic random-access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, and the like)).In some examples, the memory element 126 may include a memory array (e.g., SSD) for storing the data that the host device 102 may access using the bus 108. For example, in response to receiving a command from the host device 102 via the bus 108, the controller 122 may read from and write to a non-volatile memory array of the memory element 126. In some examples, the storage element 126 may include a magnetic record (e.g., an HHD) for storing the data that the host device 102 may access using the bus 108. For example, in response to receiving a command from the host device 102 over the bus 108, the controller 122 may read from and write to an overlapping magnetic recording (SMR) of the storage element 126. In some examples, the storage element 126 may include a combination of SSD elements and HDD elements. For example, the memory element 126 may include a magnetic recording with overlapping magnetic recording and a volatile memory array. In some examples, the storage element 126 may have a very large storage capacity, for example 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, 3 TB, or the like.In some examples, controller 122 may include a write module 142, a read module 140, an arbitration module 111, and a bus communication unit 150. In other examples, controller 122 may include additional modules or hardware units, or may include fewer modules or hardware units. The controller 122 may include a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other digital logic circuitry.The read module 140 and the write module 142 of the controller 122 may manage read and write from and to the storage element 126. For example, in response to the write module 142 receiving a command from the host device 102 instructing the slave storage device 107 to store data in the storage element 126, the write module 142 may determine a physical address and / or track of the storage element 126 to store the data.After the write module 142 writes the data to the storage element 126, the read module 140 may retrieve the data from the physical address and / or track of the storage element 126. For example, in response to the slave storage device 107 receiving a command from the host device 102 instructing the slave storage device 107 to transmit data stored in the storage element 126, the read module 140 may determine the physical address and / or trace of the storage element 126 that includes the data to be transmitted.After the read module 140 fetches the data from the storage element 126, the data may be sent to the host device 102 on the bus 108. For example, arbitration module 111 may allow write module 142 to output the data into a transmit hold register of cache 124, and arbitration module 111 may cease to allow write module 142 to output the data into the transmit hold register of cache 124 when a line level of bus 108 does not match an expected line level for the data.The bus data transfer unit 150 may determine when to send the data on a data line of the bus 108. For example, the bus data transfer unit 150 may read data stored in a transmit hold register of the latch 124, and transmit the data stored in the transmit hold register of the latch 124 serially on a data line of the bus 108 during a rising edge of a clock line of the bus 108. The bus communication unit 150 may include a microprocessor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other digital logic circuitry.The bus communication unit 150 may read data on the bus 108. For example, bus communication device 150 may read a request for data from host device 102 via bus 108. In some examples, bus communication unit 150 may monitor a clock line of bus 108 using interface 120 to determine when to read data. For example, the bus data transfer unit 150 may detect a rising edge of a clock signal on a clock line of the bus 108 via the interface 120 and read a data line of the bus 108 during rising edges of the clock signal.The bus data transfer unit 150 may determine whether a transmit hold register has data to be transmitted on the bus 108. For example, the bus communication unit 150 may recognize a status of a transmission flag and determine that the transmission holding register has data when the transmission flag is cleared. In some examples, the transmit flag may be cleared by the arbitration module 111, the write module 142, or the like.In cases where the transmit hold register is empty, the bus communication unit 150 may signal to the arbitration module 111 that the transmit hold register is empty. In some examples, bus communication unit 150 may signal that the transmit hold register is empty using an interrupt. For example, in response to bus communication unit 150 determining that the transmit buffer of cache 124 is empty, bus communication unit 150 may issue a transmit buffer empty event interrupt to arbitration module 111.In response to receiving a signal that the transmit hold register of the latch 124 is empty, the write module 142 may output data into the transmit hold register of the latch 124. For example, in response to the write module 142 receiving an indication of a transmit buffer empty event from the bus communication unit 150, the write module 142 may write a next byte of data to the transmit hold register of the cache 124.Once the write module 142 outputs the data to the transmit hold register of the cache 124, the arbitration module 111 may monitor the bus 108 for acknowledgement to synchronize with the bus 108. For example, arbitration module 110 may determine whether a data line of bus 108 indicates a logical '1' for a line level during a rising edge of the next clock cycle of a clock line of bus 108. If the line level indicates a logic '1' during the next clock cycle of the clock line of bus 108, arbitration module 110 may determine that the assertion has occurred on bus 108.After sending the signal that the transmit hold register of the latch 124 is empty, the bus communication unit 150 may determine whether data has been successfully received on the bus 108. In some examples, the bus communication unit 150 may determine whether data has been successfully received based on a number of received bits. For example, bus communication unit 150 may determine that data has been successfully received on bus 108 if exactly one byte of data has been transmitted. In some examples, the bus communication device 150 may determine whether data has been successfully received based on packet error checking. For example, the bus data transfer unit 150 may determine that data has been successfully received on the bus 108 if the bus data transfer unit 150 calculates a checksum based on the received data that is equal to a checksum sent with the data on the bus 108.In response to the bus communication device 150 determining that data was successfully received on the bus 108, the bus communication device 150 may send an acknowledgement indicating that data was successfully received. For example, the bus data transfer unit 150 may detect a rising edge of a clock signal on a clock line of the bus 108 via the interface 120 and read a last bit of a byte of a data line of the bus 108 during the rising edge of the clock signal of the clock line of the bus 108. Subsequently, after the bus communication unit 150 has determined that the data has been successfully received, the bus communication unit 150 may send an acknowledgement over the bus 108 during a rising edge of a clock cycle. For example, bus data transfer unit 150 may drive a data line of bus 108 to have a line level indicative of a logical '1' during a rising edge of the next clock cycle of a clock line of bus 108.After sending the acknowledgement, the bus communication unit 150 may load data from a transmit hold register to transmit it on the bus 108 and may transmit the loaded data on the bus 108. For example, the bus data transfer unit 150 may read a next byte in a transmit buffer of the latch 124, and may transmit the next byte on a data line of the bus 108 during a rising edge of the clock signal of a clock line of the bus 108.In response to arbitration module 111 detecting the acknowledgement sent to bus 108 and bus communication unit 150 sending the data to bus 108, arbitration module 111 may detect a line level that matches a bit of data output to the transmit hold register of latch 124. For example, the arbitration module 111 may recognize a clock cycle (e.g., rising edge, falling edge, or an area extending between the rising edge and the falling edge) on a clock line of the bus 108 that matches the acknowledgement using the interface 120 and / or the bus data transfer unit 150, and may read a line level of a data line of the bus 108 that matches a clock cycle (e.g., rising edge, falling edge, or an area extending between the rising edge and the falling edge) of the clock cycle immediately after the clock edge on a clock line of the bus 108 that matches the acknowledgement using the interface 120 and / or the bus data transfer unit 150.In response to detecting the line level that matches the bit of data output to the transmit hold register of the latch 124, the arbitration module 111 may compare the line level to an expected line level to detect a collision on the bus 108. For example, arbitration module 111 may compare a logic level (e.g., a logic '1' or '0') of a bit output to the transmit hold register of latch 124 with the line level detected on a data line of bus 108 during the clock cycle that matches the bit.If the line level matches the expected line level, arbitration module 111 may determine that no collision has occurred on bus 108. For example, if the write module 142 has output a logical '1' to the transmit hold register of the latch 124 and the interface 120 and / or the bus communication unit 150 have detected a line level with a logical '1' on a data line of the bus 108, the arbitration module 111 may determine that no collision has occurred on the bus 108.On the other hand, if a line level does not match an expected line level, arbitration module 111 may determine that a collision has occurred on bus 108. For example, if the write module 142 has output a logical '0' to the transmit hold register of the latch 124 and the interface 120 and / or the bus communication unit 150 have detected a line level with a logical '1' on a data line of the bus 108, the arbitration module 111 may determine that a collision has occurred on the bus 108.In cases where arbitration module 111 determines that a collision has occurred on bus 108, slave storage device 107 may end sending on a data line of bus 108 until a next start condition has occurred. For example, arbitration module 111 may cause write module 142 to stop outputting data into the transmit hold register of cache 124 until a next start condition has occurred if the line level and the expected line level do not match.The bus communication unit 150 may determine whether a start condition has occurred on the bus 108. For example, the bus communication unit 150 may determine that a data line of the bus 108 has been reset when the host device 102 sends a stop command (e.g., drives a data line to a logic '1') during a first clock cycle (e.g., a rising edge) of a clock line and the host device 102, and in response to determining that the data line has been reset, the bus communication unit 150 may determine that a start condition has occurred on the bus 108 when the host device 102 sends a start command (e.g., drives a data line to a logic '0') during a second clock cycle of the clock line. In some cases, the bus communication unit 150 may determine that a data line of the bus 108 has been reset when the slave storage device 107 sends a negative acknowledgement command (NACK or NAK command) during a first clock cycle (e.g., a rising edge) of a clock line, and in response to determining that the data line has been reset, the bus communication unit 150 may determine that a start condition has occurred on the bus 108 when the host device 102 sends a start command (e.g., drives a data line to a logic '0') during a second clock cycle of the clock line.In response to determining that a start condition has occurred on the bus 108, the arbitration module 111 may cause the bus communication unit 150 to retry sending the first bit to the host device 102 via the bus 108. For example, arbitration module 111 may allow write module 142 to output data into the transmit hold register of cache 124 to cause bus communication unit 150 to retry transmitting the first bit after bus communication unit 150 determines that the data line of bus 108 has been reset and / or after a start condition has occurred (and after arbitration module 111 has received another indication of a transmit buffer empty event).In cases where arbitration module 111 determines that no collision has occurred on bus 108, arbitration module 111 may continue to allow write module 142 to output data (e.g., second bit, third bit, etc.) to the transmit hold register of cache 124. For example, arbitration module 111 may compare a logic level (e.g., a logic '1' or '0') of a second bit output to the transmit hold register of latch 124 with a line level detected on a data line of bus 108 during a clock cycle that matches the second bit (e.g., one clock cycle after the clock cycle that matches the first bit). In response to the write module 142 outputting data to the transmit hold register of the cache 124, the bus communication unit 150 may continue to transmit data onto the bus 108 until the data (e.g., byte) has been transmitted to the host device 102.In cases where the bus communication unit 150 transmits on the bus 108, the bus communication unit 150 may recognize whether a stop command is being performed on the bus 108. For example, bus communication unit 150 may detect a low-to-high transition of a data signal on the data line of bus 108 while a clock signal on a clock line of bus 108 is high via interface 120. In some examples, the stop command may be sent from a master storage device (e.g., master storage device 104 of FIG. 1 ). In response to receiving the stop command, the bus communication unit 150 may end transmission on the bus 108 until the bus 108 has been reset and / or a start condition has occurred.FIG. 3 is a conceptual diagram illustrating an example technique that may implement at least one processor for collision detection according to one or more techniques of this disclosure. The technique of FIG. 3 is described with simultaneous reference to the storage environment 10 of FIG. 1 and the controller 122 of FIG. 2 for simplicity of description. Although a serial clock line is illustrated as a clock line in FIG. 3, any suitable clock signal and protocol may be used. Further, although a serial data line is illustrated as a data line in FIG. 3, any suitable data line and protocol may be used. It should be appreciated that a host data line signal 204 and a device data line signal 206 may be a same data line signal in some examples, and that the isolation of the data line signal is only to further illustrate how the data line signal may be driven by the host device 102 and the slave storage device 106A.The host device 102 may indicate a start condition 210 by driving the host data line signal 204 from logic '1' to logic '0', and the host device 102 may then send data to the slave storage device 106A using the host data line signal 204. In transmission condition 214, the slave storage device 106A may drive the device data line signal 206 to indicate an acknowledgement 220 indicating successful receipt of the data transmitted from the host device 102. In some examples, the acknowledgement 220 may occur during a state (e.g., a transmit buffer empty event) that may be used by an arbitration module (e.g., 111 of FIG. 2 ) to synchronize with the device data line signal 206. Next, during the transmit condition 214 and after the acknowledgement 220, the slave storage device 106A may drive the device data line signal 206 to transmit byte 222. In some examples, an arbitration module (e.g., 111 of FIG. 2 ) may compare the device data line signal 206 to an expected line level to determine whether a collision has occurred. As shown in FIG. 3, when a collision has not occurred, the slave storage device 106A may drive the device data line signal 206 to continue to transfer data until the host device 102 drives the host data line signal 204 to indicate a stop condition 216.FIG. 4 is a flow chart illustrating an example technique that may implement at least one processor for collision detection according to one or more techniques of this disclosure. The technique of FIG. 4 is described with simultaneous reference to the storage environment 10 of FIG. 1 and the controller 122 of FIG. 2 for simplicity of description.Arbitration module 111 may receive an indication of a transmit buffer empty event ( 302). For example, the bus communication unit 150 may send an interrupt corresponding to a transmit buffer empty event to the arbitration module 111. In response to the indication of the transmit buffer empty event, the write module 142 may output data to the transmit hold register ( 304). For example, after arbitration module 111 receives the interrupt corresponding to the transmit buffer empty event, arbitration module 111 may allow write module 142 to output data to the transmit hold register of cache 124. Next, arbitration module 111 may determine when an acknowledgement is sent from bus communication device 150 on bus 108 (306). For example, after arbitration module 111 receives the interrupt corresponding to the transmit buffer empty event and writes data to the transmit hold register of cache 124, arbitration module 111 may monitor a data line of bus 108 for acknowledgement during rising edges of a clock line of bus 108. In some cases, the acknowledgement may be sent from the bus communication unit 150 in response to detecting successful receipt of data sent to the slave storage device 107 on the bus 108. Subsequently, the slave storage device 107 may send a first bit on the data line of the bus 108 to the host device 102 ( 308). For example, the bus data transfer unit 150 may transmit a first bit on the data line of the bus 108 to the host device 102 that matches the first bit read from the transmit hold register of the latch 124. Next, the arbitration module 111 may determine a line level of the data line of the bus 108 based on when the acknowledgement was sent on the data line of the bus 108 (310). For example, the arbitration module 111 may detect a clock edge (e.g., rising edge) of a clock line of the bus 108 that matches the assertion using the interface 120 and / or the bus data transfer unit 150, and may read a line level of the data line of the bus 108 that matches a clock edge (e.g., rising) of the clock cycle immediately after the clock edge of a clock line of the bus 108 that matches the assertion.If the line level corresponds to the first bit ("YES" branch of 316), the slave storage device 107 may determine that no collision has occurred ( 322). For example, arbitration module 111 may determine that no collision has occurred in response to write module 142 outputting the first bit as a logical '0' to the transmit hold register of latch 124, and determine that the line level corresponding to the first bit indicates a logical '0'. Next, the slave storage device 107 may send a second bit on the data line of the bus 108 ( 324). For example, the write module 142 may output a value for a second bit to the transmit hold register of the latch 124, and the bus data transfer unit 150 may transmit the second bit on the data line of the bus 108 to the host device 102.On the other hand, if the line level does not correspond to the first bit ("NO" branch of 316), arbitration module 111 may determine that a collision has occurred (318). For example, arbitration module 111 may determine that a collision has occurred in response to write module 142 outputting the first bit as a logic '1' to the transmit hold register of latch 124, and determine that the line level corresponding to the first bit indicates a logic '0'. In response to determining that a collision has occurred, the slave storage device 107 may end further transmission on the bus 108. For example, arbitration module 111 may cease to allow write module 142 to output data (e.g., a second bit of a byte) to the transmit hold register of cache 124 until a start condition has occurred (320) before attempting to transmit the data again (e.g., restart to 302).The techniques described in this disclosure may be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented in one or more processors, including one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuitry, and also any combinations of such components. The term "processor" or "processing circuitry" may generally refer to any of the foregoing logic circuitry, alone or in combination with other logic circuitry, or any other equivalent circuitry. A controller including hardware may also perform one or more techniques of this disclosure.Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various techniques described in this disclosure. Furthermore, all of the described units, modules or components may be implemented together, or separately as discrete but interoperable logic devices. A representation of different features as modules or units is intended to emphasize different functional aspects, and does not necessarily indicate that such modules or units must be implemented by separate hardware, firmware, or software components. Rather, functionality associated with one or more modules or units may be executed by separate hardware, firmware, or software components or integrated into common or separate hardware, firmware, or software components.The techniques described in this disclosure may also be embodied or encoded in an article of manufacture including a computer readable storage medium encoded with instructions. Instructions embedded or encoded in an article of manufacture including an encoded computer readable storage medium may cause one or more programmable processors or other processors to implement one or more of the techniques described herein, for example, when instructions included or encoded in the computer readable storage medium are executed by the one or more processors. Computer readable storage media may include random access memory (RAM), read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electronically erasable read only memory (EEPROM), flash memory, a hard disk, a compact disc read only memory (CD-ROM), a floppy disk, a cartridge, magnetic media, optical media, or other computer readable media. In some examples, the product may be one or more computer readable storage media.In some examples, a computer readable storage medium may be a non-transitory medium. The term non-transitory may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. In some examples, a non-transitory storage medium may store data that may change over time (e.g., in RAM or cache).Various examples have been described. These and other examples are within the scope of the following claims.

Claims

A method comprising: transmitting (308), by a controller (122), a memory device (107), a first bit on a data line; responsive to transmitting a first bit on the data line, determining (310), by the controller (122), a line level of the data line; responsive to determining the line level of the data line, determining (316), by the controller, whether the line level of the data line corresponds to the first bit; and responsive to determining that the line level of the data line does not correspond to the first bit, determining (318), by the controller, that a collision has occurred on the data line; receiving (302) an indication of a transmit buffer empty event using firmware executed on a processor of the controller and from a bus communication device of the controller, and in response to receiving (302) the indication of the transmit buffer empty event, outputting (304) the first bit to a transmit hold register of the controller using the firmware, wherein transmitting (308) the first bit on the data line is in response to outputting the first bit to the transmit hold register.The method of claim 1, comprising: responsive to determining (318) that the collision has occurred on the data line, determining (320), using the controller (122), whether a start condition has occurred on the data line, and terminating transmission of data on the data line using the controller, and responsive to determining that the start condition has occurred on the data line, transmitting the first bit on the data line using the controller.The method of claim 1, comprising: responsive to determining that the line level of the data line corresponds to the first bit, determining (322), with the controller (122), that no collision has occurred on the data line, and responsive to determining that no collision has occurred on the data line, transmitting (324), with the controller, a second bit on the data line.The method of claim 1, comprising: detecting, by the controller (122), a rising edge of a clock signal on a clock line, wherein transmitting (308) the first bit on the data line comprises transmitting the first bit on the data line during the rising edge.The method of claim 4, wherein: determining that the line level corresponds to the first bit occurs prior to a falling edge of the clock signal on the clock line, and the rising edge and the falling edge are on the clock line within a single clock cycle of the clock signal.The method of claim 1, wherein: determining (316) whether the line level corresponds to the first bit comprises determining, using the firmware, whether the line level corresponds to the first bit output to the transmit hold register, and determining (322) that no collision has occurred on the data line comprises determining, using the firmware, that the collision has not occurred on the data line in response to determining the firmware that the line level corresponds to the first bit output to the transmit hold register.The method of claim 1, wherein: transmitting (308) the first bit on the data line drives the line level of the data line to indicate a first logic level, and determining that the line level does not correspond to the first bit comprises determining, using the controller (122) and after transmitting the first bit on the data line, that the line level of the data line indicates a second logic level different than the first logic level.A memory device (107) comprising: a memory element (126); an interface (120) coupled to a bus (108); and a controller (122) configured to: transmit (308) a first bit on a data line of the bus (108); responsive to transmitting the first bit on the data line, determine (310) a line level of the data line, responsive to determining the line level of the data line, determine (316) whether the line level of the data line corresponds to the first bit, and responsive to determining that the line level of the data line does not correspond to the first bit, determine (318) that a collision has occurred on the data line; wherein the controller (122) comprises firmware executed on a processor of the controller and a bus communication unit, the firmware configured to: receive (302) an indication of a transmit buffer empty event; and in response to receiving the indication of the transmit buffer empty event, output (304) the first bit to a transmit hold register of the controller, wherein transmitting (308) the first bit on the data line is in response to outputting the first bit to the transmit hold register.The memory device of claim 8, wherein the controller (122) is further configured to: responsive to determining (318) that the collision has occurred on the data line, determine (320) whether a start condition has occurred on the data line and end transmission of data on the data line, and responsive to determining that the start condition has occurred on the data line, transmit the first bit on the data line.The memory device of claim 8, wherein the controller (122) is further configured to: responsive to determining that the line level of the data line corresponds to the first bit, determine (322) that no collision has occurred on the data line, and responsive to determining that no collision has occurred on the data line, transmit (324) a second bit on the data line.The memory device of claim 8, wherein the controller (122) is further configured to: detect a rising edge of a clock signal on a clock line of the bus (108), wherein transmitting (308) the first bit on the data line comprises transmitting the first bit on the data line during the rising edge.The memory device of claim 11, wherein: the controller is further configured to determine that the line level corresponds to the first bit prior to a falling edge of the clock signal on the clock line, and the rising edge and the falling edge are within a single clock cycle of the clock signal on the clock line.The memory device of claim 8, wherein the firmware is further configured to: determine whether the line level corresponds to the first bit output to the transmit hold register; and determine (322) that no collision has occurred on the data line in response to determining the firmware that the line level corresponds to the first bit output to the transmit hold register.A non-transitory computer readable storage medium encoded with instructions that, when executed, cause the one or more processors of a storage device (107) to: transmit (308) a first bit on a data line; responsive to transmitting the first bit on the data line, determine (310) a line level of the data line; responsive to determining the line level of the data line, determine (316) whether the line level of the data line corresponds to the first bit, and responsive to determining that the line level of the data line does not correspond to the first bit, determine (318) that a collision has occurred on the data line; receiving (302) an indication of a transmit buffer empty event using firmware executed on a processor of a controller (122) and from a bus communication device of the controller, and in response to receiving the indication of the transmit buffer empty event, outputting (304) the first bit to a transmit hold register of the controller using the firmware, wherein transmitting (308) the first bit on the data line is in response to outputting the first bit to the transmit hold register.The non-transitory computer readable storage medium of claim 14, further encoded with instructions that, when executed, cause the one or more processors of the storage device (107) to: responsive to determining (318) that the collision has occurred on the data line, determine (320) whether a start condition has occurred on the data line and end sending data on the data line, and responsive to determining that the start condition has occurred on the data line, send the first bit on the data line.The non-transitory computer readable storage medium of claim 14, further encoded with instructions that, when executed, cause the one or more processors of the storage device (107) to: responsive to determining that the line level of the data line corresponds to the first bit, determine (322) that no collision has occurred on the data line, and responsive to determining that no collision has occurred on the data line, send (324) a second bit on the data line.A system comprising: means for transmitting (308) a first bit on a data line; means for determining (310) a line level of the data line in response to transmitting the first bit on the data line; means for determining (316) whether the line level of the data line corresponds to the first bit in response to determining the line level of the data line; and means for determining (318) that a collision has occurred on the data line in response to determining that the line level of the data line does not correspond to the first bit; means for receiving (302) an indication of a transmit buffer empty event using firmware executed on a processor of a controller (122) and from a bus communication device of the controller, and means for outputting (304) the first bit to a transmit hold register of the controller using the firmware in response to receiving the indication of the transmit buffer empty event, wherein transmitting (308) the first bit on the data line is in response to outputting the first bit to the transmit hold register.The system of claim 17, further comprising: means for determining (320) whether a start condition has occurred on the data line; means for terminating transmission of data on the data line; and means for transmitting the first bit on the data line in response to determining that the start condition has occurred on the data line.

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