Semiconductor device and method

Abstract

A method of manufacturing a semiconductor device, comprising: Forming a gate stack (115) over a semiconductor fin, the semiconductor fin overlying a substrate (101); selectively growing a source / drain region (201) adjacent to the gate stack (115), wherein the selective growth of the source / drain region (201) comprises growing a first portion of the source / drain region (201) on the semiconductor fin and growing a second portion of the source / drain region (201) on a second semiconductor fin, wherein the selective growth of the source / drain region (201) further comprises merging the first portion of the source / drain region (201) with the second portion of the source / drain region (201); and Reshape the source / drain region (201) after selectively growing the source / drain region (201), wherein reshape the source / drain region (201) comprises selectively etching the source / drain region (201), wherein an etching rate in a direction (301) parallel to a main surface of the substrate (101) is greater than an etching rate in a direction (303) substantially perpendicular to the main surface of the substrate (101), wherein during the selective etching the width (W2, W3) of the source / drain region (201) is reduced and the height (H1, H2) of the source / drain region (201) is only minimally reduced, wherein reshape the source / drain region (201) forms a substantially vertical sidewall.

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by depositing insulating or dielectric layers, conductive layers, and semiconductor layers of various materials one after the other over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, reducing the minimum feature size creates additional problems that need to be addressed.

[0003] A method for manufacturing a semiconductor device is known from US 2014 / 0183605 A1. Another method and a semiconductor device are known from US 2016 / 0 126 093 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with common industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. The Fig. 1A-1C illustrate a FinFET device according to some embodiments. The Fig. 2A-2E illustrate a growth process of source / drain regions according to some embodiments. The Fig. 3A-3B illustrate a forming process of the source / drain region according to some embodiments. The Fig. 4A-4B show an embodiment with isolation structures having different depths according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to other element(s) or feature(s) as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0007] With reference to the Fig. 1A-1B, a substrate 101 is shown with first trenches 103 formed therein, wherein the Fig. 1B a cross-sectional view of the Fig. 1A along line BB'. The substrate 101 may be a silicon substrate, although other substrates, such as semiconductor-on-insulator (SOI), strained SOI, and silicon germanium-on-insulator, could be used. The substrate 101 may be a p-type semiconductor, although in other embodiments it could be an n-type semiconductor.

[0008] The first trenches 103 may be formed as a first step in the later formation of first isolation regions 107. The first trenches 103 may be formed using a masking layer (not separately in the Fig. 1A-1B) along with a suitable etching process. For example, the masking layer may be a hard mask comprising silicon nitride formed by a process such as chemical vapor deposition (CVD), although other materials, such as oxides, oxynitrides, silicon carbide, combinations thereof, or the like, and other processes, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or even silicon oxide formation followed by nitriding, may be used. Once formed, the masking layer may be patterned by a suitable photolithographic process to expose those portions of the substrate 101 that will be removed to form the first trenches 103.

[0009] Once a masking layer is formed and patterned, the first trenches 103 are formed in the substrate 101. The exposed portion of the substrate 101 may be removed by a suitable method, such as reactive ion etching (RIE), to form the first trenches 103 in the substrate 101, although any suitable method may be used. In one embodiment, the first trenches 103 may be formed to have a first depth of less than about 500 nm (about 5000 Å) from the surface of the substrate 101, for example, about 250 nm (about 2500 Å).

[0010] However, as one skilled in the art will appreciate, the above-described method for forming the first trenches 103 is merely one possible method and is not intended to be the only embodiment. Rather, any suitable method by which the first trenches 103 can be formed may be used, and any suitable method, including any number of masking and removal steps, may be used.

[0011] In addition to forming the first trenches 103, the masking and etching process forms ribs 105 from those portions of the substrate 101 that were not removed. For simplicity, the ribs 105 have been shown in the figures as being separated from the substrate 101 by a dashed line, although a physical feature of separation may or may not be present. These ribs 105 can be used, as described below, to form the channel region of multi-gate FinFET transistors. While the Fig. 1A-1B show only two ribs 105 formed from the substrate 101, any number of ribs 105 may be used.

[0012] The fins 105 may be formed to have a first width W1 at the surface of the substrate 101 between about 5 nm and about 80 nm, for example, 30 nm. Additionally, the fins 105 may be separated from each other by a first distance D1 between about 10 nm and about 100 nm, for example, about 50 nm. By spacing the fins 105 in this way, the fins 105 may each form a separate channel region while still being close enough to share a common gate (as described further below).

[0013] Once the first trenches 103 and the ribs 105 are formed, the first trenches 103 may be filled with a dielectric material, and the dielectric material may be recessed within the first trenches 103 to form the first isolation regions 107. The dielectric material may be an oxide material, a high-density plasma (HDP) oxide, or the like. The dielectric material may be formed after optional cleaning and lining of the first trenches 103 using either a chemical vapor deposition (CVD) process (e.g., the HARP process), a high-density plasma CVD process, or another suitable formation method known in the art.

[0014] The first trenches 103 may be filled by overfilling the first trenches 103 and the substrate 101 with the dielectric material and then removing the excess material outside the first trenches 103 and the fins 105 by a suitable method, such as chemical mechanical polishing (CMP), etching, a combination of these, or the like. In one embodiment, the removal method also removes any dielectric material located above the fins 105, so that the removal of the dielectric material exposes the surface of the fins 105 to further processing steps.

[0015] Once the first trenches 103 are filled with the dielectric material, the dielectric material may then be recessed away from the surface of the fins 105. The recessing may be performed to expose at least a portion of the sidewalls of the fins 105 adjacent to the top surface of the fins 105. The dielectric material may be recessed using a wet etch by immersing the top surface of the fins 105 in an etchant such as HF, although other etchants such as H2 and other processes such as a reactive ion etch, a dry etch using etchants such as NH3 / NF3, chemical oxide removal, or dry chemical cleaning may be used.The dielectric material may be recessed to a second distance D2 from the surface of the ridges 105 of between about 5 nm (about 50 Å) and about 50 nm (about 500 Å), for example, about 40 nm (about 400 Å), and may have a height of about 150 nm, although any suitable dimensions may be used. Additionally, recessing may also remove any remaining dielectric material located above the ridges 105 to ensure that the ridges 105 are exposed for further processing.

[0016] However, as those skilled in the art will appreciate, the steps described above may be only a portion of the overall process flow used to fill and recess the dielectric material. For example, lining steps, cleaning steps, annealing steps, gap filling steps, combinations thereof, and the like may also be used to form the first trenches 103 and fill them with the dielectric material. All possible process steps are intended to be fully included within the scope of the present embodiment.

[0017] After the first isolation regions 107 have been formed, a gate dielectric 109, a gate electrode 111 over the gate dielectric 109, and first spacers 113 over each of the fins 105 may be formed. In one embodiment, the gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other methods known in the art for forming a gate dielectric. Depending on the technique for forming the gate dielectric, the thickness of the gate dielectric 109 on top of the fins 105 may differ from the thickness of the gate dielectric on the sidewall of the fins 105.

[0018] The gate dielectric 109 may comprise a material such as silicon dioxide or silicon oxynitride with a thickness ranging from about 0.3 nm to about 10 nm (3 angstroms to about 100 angstroms), for example, about 1 nm (10 angstroms). The gate dielectric 109 may be formed from a high-k material (e.g., having a dielectric constant greater than about 5) such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), or zirconium oxide (ZrO2), or combinations thereof, with an equivalent oxide thickness of about 0.05 nm to about 10 nm (0.5 angstroms to about 100 angstroms), such as about 1 nm (10 angstroms) or less. Additionally, a combination of silicon dioxide, silicon oxynitride and / or high-k materials may also be used for the gate dielectric 109.

[0019] The gate electrode 111 may comprise a conductive material and may be selected from a group consisting of polycrystalline silicon (poly-Si), polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, metals, combinations of these, and the like. Examples of metallic nitrides include tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride, or combinations thereof. Examples of metallic silicides include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or combinations thereof. Examples of metal oxides include ruthenium oxide, indium tin oxide, or combinations thereof. Examples of metal include tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, etc.

[0020] The gate electrode 111 may be deposited by chemical vapor deposition (CVD), sputtering, or other techniques known in the art for the deposition of conductive materials. The thickness of the gate electrode 111 may range from about 20 nm to about 400 nm (200 angstroms to about 4000 angstroms). The top surface of the gate electrode 111 may have a non-planar top surface and may be planarized prior to patterning the gate electrode 111 or the gate etch. Ions may be introduced into the gate electrode 111 at this time. The ions may be introduced, for example, through ion implantation techniques.

[0021] Once formed, the gate dielectric 109 and the gate electrode 111 may be patterned to form a series of gate stacks 115 above the fins 105. The gate stacks 115 define a plurality of channel regions located on either side of the fins 105 below the gate dielectric 109. The gate stacks 115 may be formed by depositing and patterning a gate mask (not shown) on the gate electrode 111 using, for example, deposition and photolithography techniques known in the art. The gate mask may include commonly used masking materials such as (without limitation) photoresist material, silicon oxide, silicon oxynitride, and / or silicon nitride. The gate electrode 111 and the gate dielectric 109 may be etched using a dry etching process to form the patterned gate stacks 115.

[0022] Once the gate stacks 115 have been patterned, the first spacers 113 may be formed. The first spacers 113 may be formed on opposite sides of the gate stacks 115. The first spacers 113 are typically formed by blanket deposition of a spacer layer (which is not separated into Fig. 1A) is formed on the previously formed structure. The spacer layer may comprise SiN, oxynitride, SiC, SiON, oxide, and the like, and may be formed by methods used to form such a layer, such as chemical vapor deposition (CVD), plasma-enhanced CVD, sputtering, and other methods known in the art. The spacer layer may comprise a different material with different etch characteristics or the same material as the dielectric material in the first isolation regions 107. The first spacers 113 may then be patterned, for example, by one or more etches, to remove the spacer layer from the horizontal surfaces of the structure to form the first spacers 113.

[0023] Fig. 1C shows a removal of the fins 105 from those regions not protected by the gate stacks 115 and the first spacers 113. The removal of the fins 105 from those regions not protected by the gate stacks 115 and the first spacers 113 may be performed by a reactive ion etching (RIE) using the gate stacks 115 and the first spacers 113 as hard masks or by any other suitable removal method. The removal may continue until the fins 105 are either planar with or below the surface (as shown) of the first isolation regions 107 to form holes with a defined depth, for example, as deep as the first isolation regions 107.

[0024] The Fig. 2A-2D show growth of material on the fins 105 to form source / drain regions 201, wherein the Fig. 2C-2D show a growth progression in the growth process. In an embodiment where the fins 105 comprise silicon, the source / drain regions 201 may be grown on the fins 105 by a selective epitaxial process using a doped material such as silicon phosphorus (SiP), phosphorus-doped silicon carbon (SiCP), combinations of these, or the like. However, any suitable material may be used.

[0025] In one embodiment, the epitaxial growth process used to form the source / drain regions 201 may use an epitaxial growth system 200 as described in Fig. 2A. The epitaxial growth system 200 may be used to receive precursor materials from a first precursor delivery system 205, a second precursor delivery system 206, and a third precursor delivery system 208 and to grow materials (e.g., for the source / drain regions 201) on the fins 105. In one embodiment, the first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208 cooperate to deliver the plurality of different precursor materials to an epitaxial growth chamber 203 in which the substrate 101 (and thus the fins 105) are placed. However, the first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208 may have similar physical components.

[0026] For example, the first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208 may each include a gas system 207 and a flow regulator 209 (in Fig. 2A with respect to the first precursor delivery system 205, but not labeled with respect to the second precursor delivery system 206 and the third precursor delivery system 208 for clarity. In one embodiment in which the first precursor is stored in a gaseous state, the gas system 207 may supply the first precursor to the epitaxial growth chamber 203. The gas system 207 may be a container, such as a gas storage tank, that may be located either near the epitaxial growth chamber 203 or remote from the epitaxial growth chamber 203. In another embodiment, the gas system 207 may be a device that independently prepares and supplies the first precursor to the flow controller 209. Any suitable source of the first precursor may be used as the gas system 207, and all such sources are intended to be fully encompassed within the scope of the embodiments.

[0027] The gas system 207 can supply the desired precursor to the flow regulator 209. The flow regulator 209 can be used to control the flow of the precursor to the precursor gas controller 213 and ultimately to the epitaxial growth chamber 203, which also helps control the pressure within the epitaxial growth chamber 203. The flow regulator 209 can be, for example, a proportional valve, a modulating valve, a needle valve, a pressure regulator, a mass flow controller, combinations thereof, or the like. However, any suitable method for controlling and regulating the flow of the first precursor can be used, and all such components and methods are intended to be fully encompassed within the scope of the embodiments.

[0028] Additionally, in an embodiment where the first precursor is stored in a solid or liquid state, the gas system 207 may also store or receive a carrier gas, and the carrier gas may be introduced into a precursor container (not shown separately) that stores the first precursor in the solid or liquid state. The carrier gas is then used to move and carry the first precursor as it either vaporizes or sublimates into a gaseous portion of the precursor canister before being sent to the precursor gas controller 213. Any suitable method and combination of units may be used to provide the first precursor, and all such combinations of units are intended to be fully encompassed within the scope of the embodiments.

[0029] However, as those skilled in the art will appreciate, while the first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208 have been described herein as having identical components, this is merely an illustrative example and is not intended to limit the embodiments in any way. Any suitable precursor delivery system having any type and number of individual components, identical or different from any of the other precursor delivery systems in the epitaxial growth system 200, may be used. All such precursor systems are intended to be fully encompassed within the scope of the embodiments.

[0030] The first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208 can deliver their individual precursor materials to the precursor gas controller 213. The precursor gas controller 213 connects and isolates the first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208 from the epitaxial growth chamber 203 to deliver the desired precursor materials to the epitaxial growth chamber 203 (described further below). The precursor gas controller 213 can include devices such as valves, flow meters, sensors, and the like to control the delivery rates of each of the precursors and can be controlled by commands received from a control unit 215 (described further below with respect to Fig. 2B).

[0031] Upon receiving commands from the control unit 215, the precursor gas controller 213 may open and close valves to connect one or more of the first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208 to the epitaxial growth chamber 203 and direct a desired precursor material through a manifold 216 into the epitaxial growth chamber 203 and to a showerhead 217. The showerhead 217 may be used to disperse one or more of the selected precursor materials into the epitaxial growth chamber 203 and may be configured to disperse the precursor material evenly to minimize undesirable process conditions that may arise from uneven dispersion.In one embodiment, the shower head 217 may have a circular shape with openings evenly distributed throughout the shower head 217 to allow dispersion of the desired precursor materials into the epitaxial growth chamber 203.

[0032] However, as one skilled in the art will appreciate, introducing the precursor materials into the epitaxial growth chamber 203 through a single showerhead 217 or through a single entry point, as described above, is intended to be illustrative only. Any number of separate and independent showerheads 217 or other openings may be used to introduce the various precursor materials into the epitaxial growth chamber 203. All such combinations of showerheads and other entry points are fully encompassed within the scope of the embodiments.

[0033] The epitaxial growth chamber 203 can accommodate the desired precursor materials and expose the substrate 101 and the ribs 105 to the precursor materials, and the epitaxial growth chamber 203 can have any desired shape suitable for dispersing the precursor materials and bringing the precursor materials into contact with the substrate 101 and the ribs 105. In the Fig. In the embodiment shown in Figure 2A, the epitaxial growth chamber 203 has a cylindrical sidewall and a bottom. However, the epitaxial growth chamber 203 is not limited to a cylindrical shape, and any other suitable shape, such as a hollow square tube, an octagonal shape, or the like, may be used. Furthermore, the epitaxial growth chamber 203 may be surrounded by a housing 219 made of a material inert to the various process materials. As such, while the housing 219 may be made of any suitable material capable of withstanding the chemicals and pressures of the deposition process, in one embodiment, the housing 219 may be made of steel, stainless steel, nickel, aluminum, alloys thereof, combinations thereof, and the like.

[0034] In the epitaxial growth chamber 203, the substrate 101 may be placed on a mounting stage 221 to position and control the substrate 101 and the fins 105 during the epitaxial growth processes. The mounting stage 221 may include heating mechanisms to heat the substrate 101 during the epitaxial growth processes. Furthermore, while in Fig. 2A, a single mounting stage 221 is shown, any number of mounting stages 221 may additionally be included in the epitaxial growth chamber 203.

[0035] Additionally, the epitaxial growth chamber 203 and the assembly stage 221 may be part of a cluster tooling system (not shown). The cluster tooling system may be used in conjunction with an automated handling system to position and place the substrate 101 in the epitaxial growth chamber prior to the epitaxial growth processes, to hold the substrate 101 during the epitaxial growth processes, and to remove the substrate 101 from the epitaxial growth chamber 203 after the epitaxial growth processes.

[0036] The epitaxial growth chamber 203 may also include an exhaust outlet 225 for exhaust gases leaving the epitaxial growth chamber 203. A vacuum pump 223 may be connected to the exhaust outlet 225 of the epitaxial growth chamber 203 to help evacuate the exhaust gases. The vacuum pump 223, under the control of the control unit 215, may also be used to reduce and control the pressure within the epitaxial growth chamber 203 to a desired pressure and may also be used to evacuate precursor materials from the epitaxial growth chamber 203 in preparation for the introduction of the next precursor material.

[0037] The Fig. Figure 2B shows an embodiment of the control unit 215 that can be used to control the precursor gas controller 213 and the vacuum pump 223 (as shown in Fig. 2A). The control unit 215 may be any form of computer processor that may be used in a commercial setting to control process equipment. In one embodiment, the control unit 215 may include a processing unit 252, such as a desktop computer, a workstation, a laptop computer, or a dedicated unit adapted for a particular application. The control unit 215 may be equipped with a display 253 and one or more input / output components 255, such as command outputs, sensor inputs, a mouse, a keyboard, a printer, combinations thereof, or the like. The processing unit 252 may include a central processing unit (CPU) 256, a memory 258, a mass storage device 260, a video adapter 264, and an I / O interface 266 connected to a bus 262.

[0038] Bus 262 may consist of any one or more of various bus architectures, such as a memory bus or memory controller, a peripheral bus, or a video bus. CPU 256 may include any type of electronic data processor, and memory 258 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM). Mass storage device 260 may include any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via bus 262. Mass storage device 260 may include, for example, one or more of a hard disk drive, a magnetic disk drive, or an optical disk drive.

[0039] The video adapter 264 and the I / O interface 266 provide interfaces for connecting external input and output devices to the processing unit 252. As shown in Fig. 2B, examples of input and output devices include display 253 connected to video adapter 264 and I / O component 255, such as a mouse, keyboard, printer, and the like, connected to I / O interface 266. Other devices may be connected to processing unit 252, and more or fewer interface cards may be used. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. Processing unit 252 may also include a network interface 268, which may be a wired connection to a local area network (LAN) or wide area network (WAN) 270 and / or a wireless connection.

[0040] Note that the control unit 215 may include other components. For example, the control unit 215 may include power supplies, cables, a motherboard, removable storage media, housings, and the like. These other components, although Fig. 2B are considered part of the control unit 215.

[0041] In preparation for forming the source / drain regions 201, a first precursor material is introduced into or formed by the first precursor delivery system 205. For example, in an embodiment in which a doped semiconductor material is to be grown, such as silicon phosphorus, the first precursor material may be a silicon-containing precursor material such as dichlorosilane (DCS), although other suitable precursors such as silane (SiH4) or disilane (Si2H6) may also be used. All suitable precursor materials are intended to be fully encompassed within the scope of the embodiments.

[0042] Additionally, a second precursor material may be introduced into or formed by the second precursor delivery system 206. In the embodiment, the second precursor may be used to provide a dopant material that complements the semiconductor material present in the first precursor material. For example, in an embodiment where a phosphorus-doped silicon (SiP) layer is to be grown as the source / drain regions 201 and the first precursor material is dichlorosilane, the second precursor material may be a material comprising the desired dopant, for example, phosphorus (P). In one particular embodiment, the second precursor material is PH3. However, any suitable dopant-containing material, such as arsenic (As) or antimony (Sb), may be used and placed in the second precursor delivery system 206.

[0043] In addition to the first precursor material and the second precursor material used together to grow the desired material (e.g., SiP), an etch precursor may also be used during the growth process and placed in the third precursor delivery system 208. In an embodiment where the material to be grown is at least partially deposited on materials other than the exposed fins 105 (e.g., by growing on the exposed surfaces of the first spacers 113), the addition of an etch precursor will tend to remove epitaxially grown material from these unwanted locations and help make the selective growth more selective. In one embodiment, the etch precursor is a precursor that removes unwanted growth of the grown material while still allowing the growth of the desired material over the fins 105 and may be an etchant such as hydrochloric acid (HCl).However, any suitable etching precursor may be used.

[0044] Once the first precursor material, the second precursor material, and the etch precursor are prepared in the first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208, respectively, the formation of the source / drain regions 201 may be initiated by the control unit 215, which sends a command to the precursor gas controller 213 to start a first step and connect the first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208 to the epitaxial growth chamber 203. After connecting, the first precursor delivery system 205, the second precursor delivery system 206, and the third precursor delivery system 208 can supply the first precursor material (e.g., dichlorosilane), the second precursor material (e.g., PH3), and the etch precursor (e.g., HCl) to the shower head 217 through the precursor gas controller 213 and the manifold 216.The shower head 217 may then disperse the first precursor material, the second precursor material, and the etch precursor into the epitaxial growth chamber 203, wherein the first precursor material and the second precursor material may react with the exposed surface of the fins 105 and begin to grow the source / drain regions 201 on the exposed portions of the fins 105.

[0045] In an embodiment in which the source / drain regions 201 are made of SiP, for example, the first precursor material (e.g., dichlorosilane) may be flowed into the epitaxial growth chamber 203 at a flow rate of between about 10 sccm and about 10,000 sccm, for example, about 500 sccm, while the second precursor material (e.g., PH3) is flowed into the epitaxial growth chamber 203 at a flow rate of between about 10 sccm and about 1,000 sccm, for example, about 100 sccm. Additionally, during the first step, the epitaxial growth chamber 203 may be maintained at a pressure between about 667 Pa and about 133322 Pa (5 Torr and about 1000 Torr), such as about 13332 Pa (100 Torr), and a temperature between about 400°C and about 1000°C, such as about 600°C.However, as one skilled in the art will appreciate, these process conditions are intended to be exemplary only, as any suitable process conditions may be used while remaining within the scope of the embodiments.

[0046] Additionally, as the first precursor material and the second precursor material are introduced into the epitaxial growth chamber 203, the first precursor material and the second precursor material not only react with the fins 105 (where growth is desired), but may also occur on other structures, such as the first spacers 113 (where growth is not desired). To remove this unwanted growth, the etch precursor is also added during the first step of the growth process along with the first precursor material and the second precursor material. In one embodiment where the source / drain regions 201 are SiP and the etch precursor is hydrochloric acid, the etch precursor may be flowed into the epitaxial growth chamber 203 at a flow rate of between about 10 sccm and about 30,000 sccm, such as about 100 sccm.Such a flow rate is effective for removing grown material from surfaces where it is unwanted. However, any suitable flow rate may be used.

[0047] In one embodiment, the growth of the source / drain regions 201 is continued in the first step to grow the source / drain regions 201. For example, the first step may be continued for a period of about 10 seconds to about 1000 seconds, such as about 500 seconds. However, any suitable time or scale may be used.

[0048] Additionally, as one skilled in the art will appreciate, the method described above is merely exemplary. For example, the epitaxial growth system 200 may also include a purge gas supply system 214 for supplying a purge gas to the epitaxial growth chamber 203. In one embodiment, the purge gas supply system 214 may be a gas tank or other device that introduces a purge gas such as nitrogen, argon, xenon, or another non-reactive gas into the epitaxial growth chamber 203. Additionally, during a purge, the controller 215 may also turn on the vacuum pump 223 to apply a pressure differential to the epitaxial growth chamber 203 to assist in removing the precursor materials between the various steps. The purge gas, together with the vacuum pump 223, may purge the precursor materials from the epitaxial growth chamber 203.

[0049] The Fig. 2C-2D show different stages of the growth process of the source / drain regions 201 on the fins 105. First, considering the structure of Fig. 2C, in one embodiment, the growth of the source / drain regions 201 begins by increasing the volume of the fins 105 in each direction. In addition, as the deposited material continues to spread, facets begin to form (in Fig. 2C by the dashed circle labeled 251), resulting in the source / drain regions 201 beginning to form in a diamond shape with facets 251 having specific angles. In a particular embodiment, the facets 251 form with faces exhibiting a (110) crystalline orientation of the material.

[0050] Fig. Figure 2D shows that as the growth of the source / drain regions 201 continues in each direction along the now-formed crystalline orientations, the separated source / drain regions 201 physically touch each other. The subsequent growth causes the source / drain regions 201 grown on adjacent fins 105 to begin merging into a single source / drain region 201 overlying several of the fins 105. Additionally, at this point, the facets 251 are clearly formed along their directions and along the (110) crystalline orientation.

[0051] The Fig. 2E shows continued growth of the source / drain regions 201 until the growth is stopped. In one embodiment, growth may continue until the merging of the source / drain regions 201 into a single source / drain region 201 is complete. In a particular embodiment, the single source / drain region 201 has a top surface that is minimally, if at all, curved. Since the facets are unable to continue growing along the (110) direction, the top surface of the single source / drain region 201 is forced into a different crystallographic orientation, for example, a (100) orientation.

[0052] In one embodiment, the single source / drain region 201 may have a second width W2 after formation of between about 20 nm and about 2000 nm. Additionally, the single source / drain region 201 may also have a first height H1 above the first isolation regions 107 of between about 10 nm and about 2000 nm. However, any suitable dimensions may be used.

[0053] The Fig. 3A-3B show that after the epitaxial growth of the source / drain regions 201 has been completed and stopped, the shape of the single source / drain regions 201 formed by the growth process may be modified by a second step. In one embodiment, the shape of the combined source / drain regions 201 may be modified using, for example, a selective etching process having a first etch rate in a first direction 301 (e.g., parallel to a main surface of the substrate 101) and a second etch rate, smaller than the first etch rate, in a second direction 303 perpendicular to the substrate 101.

[0054] For example, in a particular embodiment, the selective etching process may be initiated by the control unit 215, which sends a command to the precursor gas controller 213 to start the selective etching step and connect the third precursor delivery system 208 to the epitaxial growth chamber 203. After connection, the third precursor delivery system 208 may supply the etch precursor (e.g., HCl) without the first precursor or the second precursor via the precursor gas controller 213 and the manifold 216 to the shower head 217. The shower head 217 may then scatter the etch precursor into the epitaxial growth chamber 203, wherein the etch precursor may react with the exposed surface of the one source / drain regions 201 and begin to reshape the one source / drain regions 201.

[0055] In another embodiment, instead of using the etch precursor alone, the etch precursor may be supplied to the epitaxial growth chamber 203 as part of a mixture of gases. For example, the etch precursor may be mixed with the first precursor material to form a gas mixture, for example, HCl and SiH4. In another embodiment, the etch precursor may be mixed with a completely different precursor material to form a gas mixture, for example, HCl and GeH4. Any suitable combination of gases may be used.

[0056] During the selective etching process, the etch precursor may be flowed into the epitaxial growth chamber 203 at a flow rate of between about 0.1 sccm and about 100,000 sccm, such as about 1,000 sccm. Additionally, the pressure within the epitaxial growth chamber 203 may be maintained at a pressure between about 0.00001 Pa and about 101,325 Pa (0.0000001 Torr and about 760 Torr), such as about 19,998 Pa (150 Torr), while the temperature of the chamber 203 may be maintained between about 400°C and about 1,000°C, such as about 600°C. However, any suitable methods and chamber conditions may be used to perform the selective etching process.

[0057] In one particular example, in an embodiment where the etchant is HCl and the source / drain regions 201 are composed of silicon with phosphorus, the etchant preferentially reacts with the silicon along the surface with a (110) crystalline orientation rather than the surface with a (100) crystalline orientation. Since the surfaces with the (110) crystalline orientation are the surfaces along the facets 251 and the surfaces with the (100) crystalline orientation face away from the substrate 101, the etchant preferentially etches in a lateral direction parallel to the substrate 101 and less in a vertical direction.For example, the etchant may preferably etch in the lateral direction parallel to the substrate 101 at a first etch rate of between about 1 nm / s and about 100 nm / s, such as about 20 nm / s, while the etchant may etch less vigorously in the vertical direction at a second etch rate of between about 0.0001 nm / s and about 0.1 nm / s, such as about 0.01 nm / s. However, any suitable etch rates may be used.

[0058] Additionally, as the selective etching process proceeds to reduce the width of the source / drain regions 201 in a lateral direction while only minimally reducing the height of the source / drain regions 201, the selective etching process does not separate the merged source / drain regions 201 that have already been merged together. In particular, the merger of the source / drain regions 201 acts to limit the exposure of the inner surfaces of the source / drain regions 201, so that these surfaces are minimally etched, if etched at all.

[0059] By using the growth and selective etching processes as described above with reference to the Fig. 2A-3B, the facets 251 of the source / drain regions 201 may be removed and the overall shape of the source / drain regions 201 may be reshaped into a structure without the facets 251, such as a box-shaped structure having sidewalls that are substantially vertical or perpendicular to a main surface of the substrate 101. In one embodiment, the box-shaped structure may have relatively straight sidewalls and a third overall width W3 that is smaller than the second width W2, for example, between about 20 nm and about 2000 nm. Additionally, the source / drain regions 201 may have a second overall height H2 (above the first isolation regions 107) between about 10 nm and about 2000 nm. However, any suitable dimensions may be used.

[0060] In another embodiment, the first step (selective growth) and the second step (selective etching) may be repeated. For example, while the method described above utilizes the first step and the second step, in other embodiments, the first step and the second step may be repeated. In a particular embodiment, the first step and the second step may be repeated one or more times, for example, between about 1 and about 200 times. However, the first step and the second step may be repeated any number of times.

[0061] After the growth of the source / drain regions 201, additional processing may be performed to complete and connect the FinFET device formed using the source / drain regions 201. For example, an interlayer dielectric may be formed over the gate stacks 115, a replacement gate may optionally be formed, and contacts to the source / drain regions 201 and the gate electrode 111 may be formed. Any suitable method or structures may be configured to use and connect the FinFET device, and all such methods and structures are intended to be fully encompassed within the scope of the embodiments.

[0062] By reshaping the source / drain regions 201 to remove the facets 251 so that the source / drain regions 201 do not have a diamond shape, bridging, which may otherwise occur if epitaxial growth occurs in any direction, can be avoided. As such, the source / drain regions 201 can be formed with a larger dimension. A larger source / drain region 201 further enables a reduction in the channel resistance (R ch ) and the parasitic resistance (R p ), which allows an improvement of the device.

[0063] The Fig. 4A-4B show another embodiment in which the first isolation regions 107 are used to isolate the fins 105 from each other, and second isolation regions 401 are used to isolate the fins 105 from other portions of the substrate 101, such as separate groups of fins 105 (not shown separately), where Fig. 4B a cross-sectional view of Fig. 4A along lines BB'. In this embodiment, the second isolation regions 401 may be formed by initially forming second trenches 403. The second trenches 403 may be formed before, after, or even partially together with the first trenches 103, for example, by using a photolithographic masking and etching process similar to the process described above with respect to forming the first trenches 103. For example, in one embodiment, openings for the second trenches 403 may first be formed in the substrate 101 using a first masking and etching process, and then these openings may be extended at the same time as the first trenches 103 are formed using a second masking and etching process.However, the second trenches 403 may be formed to have a third distance D3 from the top surface of the substrate 101 (prior to the growth of the source / drain regions 201 shown in FIG. Fig. 4A by a dashed outline), which is greater than that of the first trenches 103. In a particular embodiment, the first trenches 103 may be formed to have a depth between about 10 nm (about 100 Å) and about 150 nm (about 1500 Å), such as about 100 nm (about 1000 Å), and the second trenches 403 may be formed such that the third distance D3 is between about 20 nm (about 200 Å) and about 700 nm (about 7000 Å), such as about 319 nm (about 3190 Å). However, any suitable depths may be used.

[0064] Once the second trenches 403 have been formed together with the first trenches 103, the first trenches 103 and the second trenches 403 may be filled with the dielectric material to form the first isolation regions 107 and the second isolation regions 401. In one embodiment, the first trenches 103 and the second trenches 403 may be filled as described above with reference to the Fig.1A-1B. For example, the dielectric material may be deposited such that the dielectric material fills the first trenches 103 and the second trenches 403, and then the dielectric material may be recessed to expose the top surfaces of the fins 105 and form the first isolation regions 107 and the second isolation regions 401. Once the first isolation regions 107 and the second isolation regions 401 are formed, processing may continue as described above to form the gate stacks 115 and the source / drain regions 201.

[0065] By using the second isolation regions 401 together with the first isolation regions 107, a better tuning of the isolation can be achieved. For example, the first isolation regions 107 can be tuned to the specific requirements of intra-fin isolation (between fins 105 covered by the same gate stack 115), while the second isolation regions 401 can be tuned to the specific requirements of inter-fin isolation (between fins 105 covered by separate gate stacks, not shown separately). Such an ability to tune the isolation regions enables greater process flexibility.

[0066] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] A method of manufacturing a semiconductor device, comprising: Forming a gate stack (115) over a semiconductor fin, the semiconductor fin overlying a substrate (101); selectively growing a source / drain region (201) adjacent to the gate stack (115), wherein the selective growth of the source / drain region (201) comprises growing a first portion of the source / drain region (201) on the semiconductor fin and growing a second portion of the source / drain region (201) on a second semiconductor fin, wherein the selective growth of the source / drain region (201) further comprises merging the first portion of the source / drain region (201) with the second portion of the source / drain region (201); and Reshape the source / drain region (201) after selectively growing the source / drain region (201), wherein reshape the source / drain region (201) comprises selectively etching the source / drain region (201), wherein an etching rate in a direction (301) parallel to a main surface of the substrate (101) is greater than an etching rate in a direction (303) substantially perpendicular to the main surface of the substrate (101), wherein during the selective etching the width (W2, W3) of the source / drain region (201) is reduced and the height (H1, H2) of the source / drain region (201) is only minimally reduced, wherein reshape the source / drain region (201) forms a substantially vertical sidewall. [2] The method of claim 1, wherein after selectively growing the source / drain region (201) and before reshaping the source / drain region (201), the source / drain region (201) has a diamond shape. [3] The method of claim 1 or 2, wherein the source / drain region (201) comprises silicon and phosphorus. [4] The method of any preceding claim, wherein said forming of said source / drain region (201) comprises contacting said source / drain region (201) with an etch precursor. [5] The method of claim 4, wherein the etching precursor is hydrogen chloride. [6] Method according to one of the preceding claims, wherein the growth of the first source / drain region (201) is carried out at least partially using an epitaxial growth process. [7] Method, wherein the etching rate in the direction (301) parallel to a main surface of the substrate (101) is between 1 nm / s and 100 nm / s, and the etching rate in the direction (303) substantially perpendicular to the main surface of the substrate (101) is between 0.0001 nm / s and 0.1 nm / s. [8] A method of manufacturing a semiconductor device, comprising: Growing a first source / drain region (201) over a first fin and a second source / drain region (201) over a second fin, the first fin and the second fin being disposed over a substrate (101); Combining the first source / drain region (201) and the second source / drain region (201) to form a combined source / drain region (201); and Reshaping the combined source / drain region (201), wherein the reshaping of the combined source / drain region (201) comprises selectively etching the combined source / drain region (201), wherein an etching rate in a direction (301) parallel to a main surface of the substrate (101) is greater than an etching rate in a direction (303) substantially perpendicular to the main surface of the substrate (101), wherein the selective etching reduces the width (W2, W3) of the combined source / drain region (201) and only minimally reduces the height (H1, H2) of the combined source / drain region. [9] The method of claim 8, wherein the growth of the first source / drain region (201) is carried out at least partially using an epitaxial growth process. [10] The method of claim 8 or 9, wherein reshaping the combined source / drain region (201) removes facets from the combined source / drain region (201). [11] The method of claim 10, wherein the facets have a surface with a (110) crystallographic orientation. [12] The method of any one of claims 8 to 11, wherein after forming the combined source / drain region (201), the combined source / drain region (201) has substantially vertical sidewalls. [13] The method of any one of claims 8 to 11, wherein forming the combined source / drain region (201) comprises contacting the combined source / drain region (201) with a gaseous etchant. [14] The method of claim 13, wherein the gaseous etchant is hydrogen chloride. [15] A semiconductor device comprising: a first semiconductor fin over a substrate (101); a second semiconductor fin above the substrate (101); an isolation region (107) above the substrate (101), the isolation region (107) surrounding lower portions of the first and second semiconductor fins or being disposed between the first semiconductor fin and the second semiconductor fin; a gate stack (115) over the first semiconductor fin and the isolation region; a spacer formed on opposite sides of the gate stack (115); a source / drain region (201) on the first and second semiconductor fins adjacent to the spacer, the source / drain region (201) being a combined source / drain region (201) transitioning from the first semiconductor fin to the second semiconductor fin and extending over a surface of the isolation region, the source / drain region (201) comprising: a surface facing away from the substrate (101); a first side wall, the first side wall being substantially vertical; a second side wall, the second side wall being substantially vertical, the surface extending from the first side wall to the second side wall; and a bottom surface facing the substrate (101), the bottom surface being spaced from the surface of the isolation region (107), the bottom surface of the source / drain region (201) having a plurality of facets. [16] The semiconductor device according to claim 15, wherein the source / drain region (201) has a first width (W2, W3) of not more than 2000 nm. [17] A semiconductor device according to any one of claims 15 to 16, wherein the source / drain region (201) is made of an epitaxial material. [18] The semiconductor device of any one of claims 15 to 17, wherein the second semiconductor fin is spaced from the first semiconductor fin by a distance of between about 10 nm and about 100 nm. [19] A semiconductor device according to any one of claims 15 to 18, wherein the source / drain region (201) has a box-shaped structure. [20] A semiconductor device according to any one of claims 15 to 19, wherein the semiconductor device is manufactured by a method according to any one of claims 1 to 14.

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