METHOD FOR REDUCING STRESS LOSS AND STRUCTURES FOR THIS

Abstract

Semiconductor component (500) with: a substrate (508) with a substrate fin part (508A), wherein the substrate fin part comprises a first material; a first area (502) which is manufactured over a first part of the substrate fin part (508A), wherein the first area (502) has a second material which is different from the first material; a second area (504) which is manufactured over a second part of the substrate fin section (508A); and an anchoring (511) which is made over a third part of the substrate fin part (508A), wherein the anchoring is arranged between the first area (502) and the second area (504) and adjoins each of them; where the first area (502) provides a channel area of ​​a multi-gate transistor.

Description

BACKGROUND

[0001] The electronics industry has experienced a steadily growing demand for smaller and faster electronic components capable of supporting a greater number of increasingly complex and demanding functions. Consequently, the semiconductor industry has a persistent trend toward producing cost-effective, high-performance, low-power integrated circuits (ICs). To date, these goals have been largely achieved by reducing the dimensions of semiconductor ICs (e.g., the smallest feature size), thereby improving production output and reducing associated costs. However, this miniaturization has also made the semiconductor manufacturing process more complex. Therefore, realizing further advances in semiconductor ICs and components requires similar advances in semiconductor manufacturing processes and technologies.

[0002] Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). One such multi-gate device is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure extending from the substrate on which it is fabricated, which is used to create the FET channel. FinFETs are compatible with conventional CMOS (complementary metal-oxide-semiconductor) processes, and their three-dimensional structure allows for aggressive miniaturization while maintaining gate control and attenuating SCEs. Furthermore, strain-channel FinFET devices are currently being investigated as a way to improve carrier mobility (e.g.,to improve electron or hole mobility and increase transistor performance. However, for devices utilizing a strained channel, one of the major challenges in transistor fabrication is maintaining the channel voltage throughout the fabrication process. Voltage relaxation, for example in a transistor channel, can lead to reduced carrier mobility and a decrease in device performance. Thus, existing methods have not proven entirely satisfactory in every respect. US 9893186 B2 describes conventional methods for fabricating a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The invention relates to semiconductor devices according to claims 1 and 11, and to a method as specified in claim 17. Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 is a perspective view of an embodiment of a FinFET device according to one or more aspects of the present invention. Fig. Figure 2 shows a layout design of at least part of a standard FinFET cell. Fig. Figure 3 shows an isometric representation of a FinFET device, where the cross-section C - C' corresponds to the cross-section C - C' of Fig. 2 corresponds. Fig. Figure 4 shows a layout design of at least part of a standard FinFET cell with an anchoring, according to some embodiments. Fig. Figure 5 shows an isometric representation of a FinFET device with an anchorage according to some embodiments, wherein the cross-section D - D' corresponds to the cross-section D - D' of Fig. 4 corresponds to. Fig. Figure 6 is a flowchart of a method for manufacturing a FinFET device according to one or more aspects of the present invention. The Fig. 7, Fig. 8, Fig. 9 and Fig. Figure 10 shows isometric representations of an embodiment of a FinFET device, which includes one or more steps of the method of Fig. 6 correspond. DETAILED DESCRIPTION

[0004] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and it may also include embodiments in which additional elements can be formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the component in use or operation beyond the orientation shown in the figures. The device can be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0006] It should also be noted that the present invention provides embodiments in the form of multi-gate transistors or fin multi-gate transistors, referred to herein as FinFET devices. Such a device may be a p-metal oxide semiconductor FinFET device or an n-metal oxide semiconductor FinFET device. The FinFET device may be a dual-gate device, a tri-gate device, a bulk device, or a silicon-on-insulator (SOI) device, and / or have another configuration. A person skilled in the art should recognize other embodiments of semiconductor devices that may benefit from aspects of the present invention. For example, some embodiments described herein may also be used for gate-all-around (GAA) devices, omega (Ω)-gate devices, or pi (Π)-gate devices.

[0007] In Fig. Figure 1 shows a FinFET device 100. The FinFET device 100 comprises one or more multi-gate fin field-effect transistors (FETs). The FinFET device 100 has a substrate 102, at least one fin element 104 extending from the substrate 102, separation areas 106, and a gate structure 108 arranged on and around the fin element 104. The substrate 102 can be a semiconductor substrate, such as a silicon substrate. The substrate can have various layers, such as conductive or insulating layers, fabricated on a semiconductor substrate. Depending on design requirements, the substrate can have different doping configurations, as is known in the field. The substrate can also comprise other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate can consist of a compound semiconductor and / or an alloy semiconductor.In addition, in some embodiments the substrate may have an epitaxial layer, the substrate may be strained to improve performance, the substrate may have a silicon-on-insulator (SOI) structure, and / or the substrate may have other suitable improvement elements.

[0008] The fin element 104, like the substrate 102, can be silicon or comprise: another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. The fins 104 can be fabricated using suitable processes, such as photolithography and etching. The photolithography process can include the following steps: fabricating a photoresist layer (resist) over the substrate (e.g., on a silicon layer); exposing the resist to form a structure; performing a curing process after exposure; and developing the resist to produce a masking element that incorporates the resist.In some embodiments, the resist can be structured to fabricate the masking element by electron beam lithography. The masking element can then be used to protect areas of the substrate while recesses are created in the silicon layer by an etching process, leaving a protruding fin 104. The recesses can be etched by dry etching (e.g., chemical oxide removal), wet etching, and / or other suitable etching processes. Numerous other embodiments of methods for fabricating the fins 104 on the substrate 102 can also be used.

[0009] The fins 104 each also have a source region 105 and a drain region 107, wherein the source / drain regions 105 and 107 are produced in, on, and / or around the fin 104. The source / drain regions 105 and 107 may be epitaxially grown over the fins 104. In some embodiments, one or more layers of a material with a low Schottky barrier height (SBH) are produced over the source / drain regions 105 and 107 to reduce the source / drain contact resistance. In some examples, the low SBH material is a III-V material, such as GaAs, In x Ga 1-x As or Ni-InAs, and / or another suitable material. A channel region of the transistor is arranged in the fin 104 beneath the gate structure 108 along a plane that is substantially parallel to a plane defined by the cross-section B - B' of Fig. 1 is defined. In some embodiments, the channel region of the fin comprises a material with high electron mobility, such as germanium, as well as one of the aforementioned compound semiconductors or alloy semiconductors and / or combinations thereof. Materials with high electron mobility are materials with an electron mobility greater than that of silicon, which has an intrinsic electron mobility at room temperature (300 K) of approximately 1350 cm⁻¹. 2 / Vs and a hole movement of approximately 480 cm 2 / Vs has. In some embodiments, the channel region has a strained channel material. The strained channel material can be produced, for example, by using different materials for the fin element 104 and the substrate 102, resulting in a lattice mismatch between the fin element 104 and the substrate 102. This lattice mismatch can, in turn, generate stress (e.g., tensile or compressive stress) in the channel region. In various embodiments, this strained channel material enables higher carrier mobility (e.g., electron or hole mobility) and improved transistor performance. Therefore, in some embodiments, the high-electron-mobility material discussed above can, in some cases, be a strained channel material.

[0010] The separation areas 106 can be STI structural elements (STI: shallow trench insulation). Alternatively, a field oxide, a LOCOS element, and / or other suitable separation elements can be implemented on and / or in the substrate 102. The separation areas 106 can consist of silicon oxide, silicon nitride, silicon oxide nitride, fluorosilicate glass (FSG), a low-k dielectric, a combination thereof, and / or another suitable material known in the field. In one embodiment, the separation structures are STI structural elements and are produced by etching trenches into the substrate 102. The trenches are then filled with an insulating material, and subsequently, chemical-mechanical polishing (CMP) is performed. However, other embodiments are also possible. In some embodiments, the separation areas 106 can have a multilayer structure, for example, with one or more cover layers.

[0011] The gate structure 108 comprises a gate stack consisting of an intermediate layer 110, which is fabricated over the channel region of the fin 104, a dielectric gate layer 112, which is fabricated over the intermediate layer 110, and a metal layer 114, which is fabricated over the dielectric gate layer 112. The intermediate layer 110 can be made of a dielectric material such as silicon dioxide (SiO2) or silicon nitride (SiON). The intermediate layer 110 can be fabricated by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or another suitable process. The dielectric gate layer 112 can be a high-k dielectric layer, such as hafnium oxide (HfO2). Alternatively, the dielectric high-k layer can comprise other high-k dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2 or combinations thereof, or another suitable material.In further embodiments, the dielectric gate layer can comprise silicon oxide or another suitable dielectric. The dielectric gate layer can be produced by ALD, physical vapor deposition (PVD), oxidation, and / or other suitable methods. The metal layer 114 can be a conductive layer, such as W, TiN, TaN, WN, Re, Ir, Ru, Mo, Cu, Ni, or combinations thereof, and / or it can have other suitable compositions. In some embodiments, the metal layer 114 can comprise a first metal material for n-FinFETs and a second metal material for p-FinFETs. Thus, the FinFET device 100 can have a dual exit metal gate configuration. For example, the first metal material (e.g.,For n-type devices, the metal layer 114 may comprise metals with a work function that is substantially matched to the work function of the substrate conduction band or at least substantially matched to the work function of the conduction band of the channel region of the fin 104. Similarly, for example, the second metal material (e.g., for p-type devices) may comprise metals with a work function that is substantially matched to the work function of the substrate valence band or at least substantially matched to the work function of the valence band of the channel region of the fin 104. Thus, the metal layer 114 can provide a gate electrode for the FinFET device 100, which comprises n-type and p-type FinFET devices 100. In some embodiments, the metal layer 114 may alternatively be a polysilicon layer. The metal layer 114 may be fabricated by PVD, CVD, electron beam evaporation, and / or another suitable method.In some embodiments, sidewall spacers are fabricated on sidewalls of the gate structure 108. The sidewall spacers can comprise a dielectric material, such as silicon oxide, silicon nitride, silicon carbide or silicon oxide nitride, or a combination thereof.

[0012] The use of materials with high electron mobility, including strained channel materials, has garnered significant attention, at least in part due to the higher electron and / or hole mobility achievable with these materials compared to silicon. Advantages of using high electron mobility materials include higher device drive current, lower intrinsic latency, improved high-frequency performance (e.g., for high-frequency applications), and other benefits. Furthermore, devices employing strained channel materials offer an attractive opportunity for performance improvement, particularly in highly scaled devices. However, maintaining channel voltage throughout the fabrication process has been one of the major challenges in transistor manufacturing for devices using strained channel materials.Voltage relaxation, for example in a transistor channel, can lead to reduced carrier mobility and a decrease in component performance.

[0013] For example, certain aspects of FinFET design can lead to voltage relaxation in a FinFET channel. Consider, for instance, the design of a conventional standard cell. In semiconductor design, the standard cell methodology is a procedure for designing application-specific integrated circuits (ASICs) with primarily digital logic structural elements. The standard cell methodology is an example of design abstraction, where a low-level VLSI (very large-scale integration) layout is encapsulated in an abstract logic representation (such as a NAND gate). The cell-based methodology—the general class to which standard cells belong—allows one designer to focus on the high-level aspect (logical function) of the digital design, while another designer focuses on the implementation aspect (the physical aspect).Along with advances in semiconductor manufacturing, the standard cell methodology has helped developers scale ASICs from relatively simple single-function ICs (with several thousand gates) to complex SoC (system-on-a-chip) devices with several million gates. In various examples, a standard cell (which may be referred to as a functional cell and / or logic cell) can contain a group of transistors and interconnects that can provide a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverter) or a memory function (flip-flop or latch). The simplest cells are direct representations of the elementary Boolean NAND, NOR, and XOR functions, although cells of much greater complexity are frequently used (such as 2-bit full adders or multiplexed D-input flip-flops).

[0014] Let's now take a closer look at the standard cell example. Fig. Figure 2 shows a layout design 200 of at least part of a standard FinFET cell. As shown, the layout design 200 has a plurality of active fin regions 202 and a receiving region 204 located between the active fin regions 202. In some cases, the term "active fin region" used here can be used to denote a fin region with a FinFET channel. A dashed line 206 is used to denote an active p-region. Thus, in some embodiments, the plurality of active fin regions 202 can include active p-fin regions. In some embodiments, regions outside the dashed line 206, such as regions 210, can be active n-regions. Polysilicon structural elements 208 are also shown.Of course, the embodiments described here are not limited to a specific doping configuration, and the examples provided are for illustrative purposes only. For example, in some cases, the dashed line 206 may alternatively be used to designate an active n-region, and the regions outside the dashed line 206 (e.g., regions 210) may be active p-regions. In various examples, the receiving region 204 may be a heavily doped region, which may have the same conductivity type as the underlying substrate. In general, the receiving region may provide a low-resistance contact with the underlying substrate. In one example, if the substrate is a doped n-substrate, the receiving region may be a heavily doped n-region. Alternatively, if the substrate is a doped p-substrate, the receiving region may be a heavily doped p-region.If in the example of . Fig. 2. If the recording area 204 is an active n-area, then the recording area 204 can be an n-recording area.

[0015] Fig. Figure 3 shows an isometric representation of a FinFET device 300, where the cross-section C - C' is essentially the cross-section C - C' of Fig. 2 corresponds. As shown, the FinFET device 300 has an active fin region 302 (similar, for example, to the plurality of active fin regions 202), a receiving region 304 (similar, for example, to the receiving region 204), an STI region 306, and a substrate 308. In some examples, the substrate 308 may have a substrate fin portion 308A extending from the substrate 308. In some embodiments, the active fin region 302 and the receiving region 304 may have epitaxial layers that are produced over the substrate fin portion 308A, wherein these epitaxial layers have been deposited, structured, and etched to produce the active fin region 302 and the receiving region 304. In various embodiments, the active fin area 302 can be an active p-area or an active n-area, and the receiving area 304 can be a p-receiving area or an n-receiving area.For the sake of simplicity, it is assumed that the active fin region 302 is a p-type active region and the receiving region 304 is an n-type receiving region. It is further assumed that the active fin region 302 has a strained channel material that can be used to fabricate a strained FinFET channel. For example, in some cases, the active fin region 302 and the substrate 308 (and the substrate fin portion 308A) may be fabricated using different materials, resulting in a lattice mismatch that induces stress in the active fin region 302 (e.g., the channel region of a FinFET). The active fin area 302 can, for example, be made from an epitaxial silicon germanium (SiGe) layer, and the substrate 308 (and the substrate fin part 308A) can be made from silicon (Si), so that the active fin area 302 can have a strained SiGe layer.In at least some common designs there is a gap 311 (which corresponds, for example, to gap 211 of . Fig. 2 similarly) between the active fin region 302 and the receiving region 304 along the plane defined by the cross-section C - C'. In some aspects, the gap 311 represents a discontinuity in the active region (e.g., in the active fin region 302 and the active region defined by the receiving region 304). While the gap 311 can be used to switch (e.g., jump) between an active fin region (e.g., the active fin region 302) and a receiving region (e.g., the receiving region 304), the gap 311 introduces a discontinuity into these adjacent epitaxial layers (e.g., in the active fin region 302 and the receiving region 304), which can lead to stress relaxation in the strained SiGe layer (e.g., in the active fin region 302). This eliminates the voltage in the transistor channel, which can lead to reduced carrier mobility and a decrease in component performance.

[0016] Embodiments of the present invention offer advantages over the prior art, but it should be clear that other embodiments may offer other advantages, not all advantages are necessarily discussed here, and no specific advantage is required for all embodiments. For example, embodiments discussed here may include methods and structures for reducing voltage drop (e.g., in a FinFET channel) to avoid a reduction in mobility and a reduction in device performance. In some embodiments, an anchoring connection may be provided between an active fin area and a receiving area.In various embodiments, the anchoring can serve to reduce stress relaxation in the active fin region by physically connecting or contacting the active fin region with the receiving region, thereby avoiding a gap and / or discontinuity between these adjacent epitaxial layers. In some cases, the anchoring can be a silicon (Si) anchor. In some embodiments, the anchoring can be defined, for example, in a layout design as an active dummy region. For example, a "dummy" structure used here, such as an active dummy region, is to be understood as a structure used to simulate a physical property of another structure (e.g.,An anchor is used to simulate the physical dimensions of adjacent active areas (such as the active fin area or the receiving area) and has no function in the circuit of the finished manufactured device (i.e., it is not part of a circuit current flow path). Although an anchor is not necessarily part of a circuit current flow path, its fabrication adjacent to and in contact with the active fin area, which may have a strained material layer, serves to reduce stress relaxation in the active fin area. For example, in some embodiments, the anchor may be a silicon anchor fabricated adjacent to the active fin area, where the active fin area has a strained SiGe layer.Thus, embodiments of the present invention support the maintenance of improved mobility and component performance, which are made possible by the tensioned channel material in the active fin area. Those skilled in the art will likely recognize further advantages and benefits of the methods and structures described herein, and the described embodiments are not intended to be limiting beyond what is expressly set forth in the following claims.

[0017] Fig. Figure 4 shows a layout design 400 of at least part of a standard FinFET cell with an anchoring feature, according to some embodiments. As shown, the layout design 400 has a plurality of active fin regions 402 and a receiving region 404 arranged between the active fin regions 402. A dashed line 406 is used to indicate an active p-region. Thus, in some embodiments, the plurality of active fin regions 402 may include active p-fin regions. In some embodiments, regions outside the dashed line 406, such as regions 410, may be active n-regions. Polysilicon structural elements 408 are also shown. Furthermore, unlike at least some common designs, the layout design 400 also includes a plurality of anchors 412 arranged between adjacent active fin regions and receiving regions.By providing the anchorages 412, in embodiments of the present invention a gap or discontinuity between adjacent active fin areas and receiving areas (e.g. the gap 211 of . Fig. 2) should be avoided, which can lead to tension relaxation in the active fin areas.

[0018] As stated above, the embodiments described here are not intended to be limited to a specific doping configuration, and the examples provided are for illustrative purposes only. For example, in some cases, the dashed line 406 may alternatively be used to designate an active n-region, and the regions outside the dashed line 406 (e.g., regions 410) may be active p-regions. The receiving region 404, like receiving region 204, may be a heavily doped region that may have the same conductivity type as the underlying substrate. In the example of Fig. 4 can be an n-recording area if area 410 is an active n-area.

[0019] Fig. Figure 5 shows an isometric representation of a FinFET device 500 with an anchorage according to some embodiments, wherein the cross-section D - D' of Fig. 5 essentially the cross-section D - D' of Fig. 4 corresponds. As shown, the FinFET device 500 has an active fin region 502 (similar, for example, to the plurality of active fin regions 402), a receiving region 504, an STI region 506, and a substrate 508. In some examples, the substrate 508 may have a substrate fin portion 508A extending from the substrate 508. Furthermore, the FinFET device 500 has an anchor 511 located between and adjacent to the active fin region 502 and the receiving region 504. In some embodiments, the anchor 511 may physically connect or contact the active fin region 502 and the receiving region 504. Thus, the anchor 511 creates a gap or discontinuity between adjacent active fin regions and receiving regions (e.g., the gap 311 of Fig. 3) avoided, which can lead to stress relaxation in the active fin region 502, as explained above. In other words, the anchor 511 allows for continuity of the active region, in contrast to the discontinuity in the active region in devices with a gap. In various embodiments, the anchor 511, like the active fin region 502 and the receiving region 504, can have epitaxial layers that are produced over the substrate fin portion 508A, wherein these epitaxial layers have been deposited, structured, and etched to produce the anchor 511, the active fin region 502, and the receiving region 504. The active fin region 502 can be an active p-region or an active n-region, the receiving region 504 can be a p-receiving region or an n-receiving region, and the anchor 511 can be undoped or doped.In some embodiments, the anchor 511 can be essentially electrically inactive. For the sake of simplicity, it is assumed that the active fin region 502 is an active p-region, the receiving region 504 is an n-receiving region, and the anchor 511 is an undoped or doped epitaxial Si layer. It is further assumed that the active fin region 502 comprises a strained channel material, such as strained SiGe, which can be used to fabricate a strained FinFET channel. In some examples, the substrate 508 (and the substrate fin portion 508A) can be made of Si, resulting in a lattice mismatch (e.g., strain) between the substrate 508 and the active fin region 502. In some embodiments, the anchoring 511 (e.g., a Si anchoring) is produced adjacent to and in contact with the active fin area 502, which is a tensioned material layer (e.g.,a stressed SiGe layer) may have, to reduce stress relaxation in the active fin area 502. For example, a continuity at the interface between the active fin area 502 and the anchorage 511, as opposed to the gap or discontinuity (e.g., the gap 311 of . Fig. 3), which have been discussed above, to maintain the tension in the active fin area 502. Thus, embodiments of the present invention support the maintenance of improved mobility and component performance, which are made possible by the tensioned channel material in the active fin area. In a further aspect, instead of using a gap or discontinuity for switching (e.g., jumping) between an active fin area (e.g., the active fin area 502) and a receiving area (e.g., the receiving area 504), embodiments of the present invention use an anchor for switching (e.g., jumping) between an active fin area and a receiving area, whereby the tension in adjacent layers is maintained.

[0020] Fig. Figure 6 discloses a method 600 for fabricating a semiconductor device comprising a FinFET device. Method 600 can be used to implement a fin-based semiconductor device with methods and structures (e.g., anchors) for reducing voltage drop (e.g., in a FinFET channel) to avoid a reduction in mobility and a reduction in device performance. In some embodiments, method 600 can be used to fabricate the device 100 or the device 500 described above with reference to Figure 6. Fig. 1 or Fig. 5 have been described. Thus, one or more aspects outlined above may also apply to Procedure 600. Furthermore, the Fig. 7, Fig. 8, Fig. 9 to Fig. 10 isometric representations of an exemplary component 700, which is manufactured according to one or more steps of the method 600 of Fig. 6 was manufactured.

[0021] It should be clear that parts of the process 600 and / or the semiconductor device 700 can be manufactured using a known CMOS technology process flow (CMOS: complementary metal-oxide semiconductor), and therefore some processes are only briefly described here. Furthermore, the semiconductor device 700 can comprise various other components and structural elements, such as additional transistors, bipolar transistors, resistors, capacitors, diodes, fuses, etc., but for a better understanding of the inventive concept of the present invention, it is simplified. The semiconductor device 700 also comprises a plurality of semiconductor components (e.g., transistors) that can be interconnected.

[0022] The component 700 can be an intermediate component produced during the machining of an integrated circuit, or part thereof, which may include: static random access memory (SRAM) and / or other logic circuitry; passive components, such as resistors, capacitors, and inductors; and active components, such as p-channel field-effect transistors (PFETs), n-channel FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), CMOS transistors (CMOS: complementary metal-oxide-semiconductor), bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, or combinations thereof.

[0023] Let's now turn to process 600. Process 600 begins with a block 602, in which a recess is created in a substrate. In the example of Fig. Figure 7 shows an embodiment of block 602 comprising a semiconductor device 700 with a semiconductor substrate 702 in which a recess 704 is formed. The substrate 702 can be substantially similar to the substrate described above with reference to Fig. 1 has been discussed. In one embodiment, the recess 704 can be produced by a photolithography and etching process. In some cases, the recess 704 defines a SiGe channel area, as will be described in more detail later.

[0024] The process 600 continues to block 604, where a SiGe layer is produced in the recess. In the example of the Fig. 7 and Fig. In one embodiment of block 604, a SiGe layer 802 is produced in the recess 704. In various embodiments, the SiGe layer 802 can be grown epitaxially in the recess 704. In some embodiments, the SiGe layer 802 can be made of Si (1-x) Gex exist where x is a percentage of Ge and x is greater than 0% and less than 100%. In some embodiments, if the substrate 702 contains, for example, Si, a lattice mismatch (e.g., voltage) occurs between the semiconductor substrate 702 and the SiGe layer 802. This can, in some cases, cause the SiGe layer 802 to become strained.

[0025] The process 600 continues to block 606, where a fin structure is produced. In the example of the Fig. 8 and Fig. 9 In one embodiment of block 606, a fin structure 902 is produced. In some embodiments, the fin structure 902 can be produced as described above with reference to Fig. 1 has been described. In some aspects, the fin structure 902 can have an active fin area 904, a receiving area 906, and an anchor 911. In some examples, the active fin area 904 can be similar to the active fin area discussed above (e.g., the active fin area 502), the receiving area 906 can be similar to the receiving area discussed above (e.g., the receiving area 504), and the anchor 911 can be similar to the anchor discussed above (e.g., the anchor 511). Furthermore, the active fin area 904 is manufactured from the strained SiGe layer 802. Thus, in some embodiments, the active fin area 904 can be a strained SiGe area that can serve as a FinFET channel. As described in Fig. As shown in Figure 9, the anchor 911 is arranged between and adjacent to the active fin region 904 and the receiving region 906. In some embodiments, the anchor 911 can physically connect or contact the active fin region 904 and the receiving region 906. Furthermore, since the fin structure 902 is made from a continuous layer of material (e.g., Si and SiGe), the active fin region 904, the receiving region 906, and the anchor 911 are adjacent to one another. As a result, the anchor 911 prevents stress relaxation (e.g., in the active fin region 904), as described above. In some cases, doping of the active fin region 904, the receiving region 906, or the anchor 911 can be carried out during or after the epitaxial growth of the respective layer or region.In various examples, the active fin area 904 can be an active p-area or an active n-area, the uptake area 906 can be a p-uptake area or an n-uptake area (which depends, for example, on the type of doping of the substrate), and the anchorage 511 can be an undoped or a doped (e.g., an n- or p-) area.

[0026] In at least some examples, the active fin region 904 can be an active p-region, the receiving region 906 can be an n-receiving region, and the anchoring 911 can comprise an undoped or doped epitaxial Si layer. Furthermore, in at least some examples, depending on the material used to fill the recess 704, the active fin region 904 can comprise a strained channel material, such as strained SiGe or strained Ge, or another strained material that can be used to fabricate a strained FinFET channel. In general, the active fin region 904 can comprise a material having a different composition than the semiconductor substrate 702 in order to induce a strain in the active fin region 904.According to embodiments of the present invention, the anchoring 911 being located adjacent to and in contact with the active fin area 904 serves to reduce stress relaxation in the active fin area 904. Thus, embodiments of the present invention support the maintenance of the improved mobility and component performance enabled by the tensioned channel material in the active fin area.

[0027] The process 600 continues to block 608, where an STI area is manufactured. In the example of the Fig. 9 and Fig. In one embodiment of block 608, an STI area 1002 is produced. In some cases, the STI area 1002 is a recessed STI area. Furthermore, in some embodiments, the recessed STI area 1002 can be substantially the same as the one described above. Additionally, according to block 608, the component 700 can be substantially the same as the component 500 described in Fig. 5 is shown.

[0028] The semiconductor device 700 can undergo further processing to fabricate various structural elements and regions known in the field. For example, subsequent processing can fabricate a gate stack, sidewall spacers, source / drain regions, various contacts, vias or traces, and multilayer interconnects (e.g., metal layers and interlayer dielectrics) on the substrate 702, configured to connect the various structural elements into a functional circuit that may include one or more FinFET devices. Furthermore, a multilayer interconnect, for example, can include vertical connections, such as vias or contacts, and horizontal connections, such as metal traces. Various conductive materials, such as copper, tungsten, and / or silicide, can be used for the different interconnects.For example, a single or dual damascene process can be used to fabricate a multilayer copper-based compound structure. Furthermore, additional process steps can be implemented before, during, and after Process 600, and some of the process steps described above can be substituted or omitted in various embodiments of Process 600.

[0029] The various embodiments described here offer several advantages over the prior art. It should be clear that not all advantages are necessarily discussed here, no specific advantage is required for all embodiments, and other embodiments may offer different advantages. For example, embodiments discussed here include methods and structures for reducing voltage relaxation (e.g., in a FinFET channel) to avoid a reduction in mobility and a decrease in device performance.In some embodiments, an anchor formed between an active fin region and a receiving region is used to reduce stress relaxation in the active fin region by physically connecting and contacting the active fin region and the receiving region, thereby avoiding a gap and / or discontinuity between these adjacent epitaxial layers. In various embodiments, the production of the anchor adjacent to and in contact with the active fin region, which may include a strained material layer, serves to reduce stress relaxation in the active fin region. In some embodiments, the anchor may, for example, be a silicon anchor produced adjacent to the active fin region, wherein the active fin region includes a strained SiGe layer.Thus, embodiments of the present invention support the maintenance of the improved mobility and component performance enabled by the strained channel material (e.g., the strained SiGe layer) in the active fin area.

[0030] One embodiment of the present invention describes a semiconductor device comprising: a substrate with a substrate fin portion; an active fin area formed over a first portion of the substrate fin portion; a receiving area formed over a second portion of the substrate fin portion; and an anchoring element formed over a third portion of the substrate fin portion. In some embodiments, the substrate fin portion comprises a first material, and the active fin area comprises a second material that is different from the first material. In various embodiments, the anchoring element is arranged between and adjacent to the active fin area and the receiving area.

[0031] In another embodiment, a semiconductor device is discussed that has a substrate with a recessed fin. The substrate consists of a first material. The semiconductor device further comprises an active p-fin region arranged above the recessed fin, the active p-fin region being made of a second material different from the first material. The semiconductor device further comprises an n-receiving region arranged above the recessed fin and adjacent to the active p-fin region, the n-receiving region and the active p-fin region being separated by a gap. In addition, the semiconductor device has a silicon (Si) anchor arranged above the recessed fin in the gap, the Si anchor being adjacent to and contacting both the active p-fin region and the n-receiving region.

[0032] In yet another embodiment, a method is discussed that includes producing a recess in a substrate, wherein the substrate comprises a first material. In some embodiments, a channel layer is grown in the recess, the channel layer comprising a second material that is different from the first material. In various examples, the channel layer and an adjacent part of the substrate are structured to form a continuous fin structure comprising a first region, a second region, and an anchor located between the first region and the second region. In some embodiments, the first region comprises the structured channel layer, and the second region and the anchor comprise the structured adjacent part of the substrate.

Claims

[1] Semiconductor device (500) with: a substrate (508) with a substrate fin part (508A), wherein the substrate fin part comprises a first material; a first area (502) which is manufactured over a first part of the substrate fin part (508A), wherein the first area (502) has a second material which is different from the first material; a second area (504) which is manufactured over a second part of the substrate fin section (508A); and an anchoring (511) which is made over a third part of the substrate fin part (508A), wherein the anchoring is arranged between the first area (502) and the second area (504) and adjoins each of them; where the first area (502) provides a channel area of ​​a multi-gate transistor. [2] Semiconductor device (500) according to claim 1, wherein the anchoring (511) physically contacts the first area (502) and the second area (504). [3] Semiconductor device (500) according to claim 1 or 2, wherein the first region (502) comprises an active p-region and the second region (504) comprises a second n-region. [4] Semiconductor device (500) according to one of the preceding claims, wherein the first region (502), the second region (504) and the anchoring (511) each comprise epitaxially grown layers. [5] Semiconductor device (500) according to one of the preceding claims, wherein the first region (502) comprises a strained SiGe layer and the anchoring (511) comprises a silicon layer. [6] Semiconductor device (500) according to claim 5, wherein the anchoring (511) prevents stress relaxation in the strained SiGe layer (502). [7] Semiconductor device (500) according to any of the preceding claims, wherein the first material (502) comprises silicon and the second material (504) comprises SiGe. [8] Semiconductor device (500) according to one of the preceding claims, wherein the anchoring (511) comprises an undoped Si layer. [9] Semiconductor device (500) according to one of the preceding claims, wherein the anchoring (511) has no function for the circuit. [10] Semiconductor device (500) according to one of the preceding claims, wherein the second area (504) has the same conductivity type as the substrate fin part (508A). [11] Semiconductor device (700) with: a substrate (702) with a recessed fin (902), wherein the substrate consists of a first material; a first p-area (904) arranged above the recessed fin, wherein the first p-area consists of a second material that is different from the first material; a second n-region (906) arranged above the recessed fin and adjacent to the first p-region, the second n-region and the first p-region being separated by a gap; and comprising a silicon anchor (911) which is arranged above the recessed fin in the gap, wherein the Si anchor is adjacent to and contacts the first p-region (904) and the second n-region (906). [12] Semiconductor device (700) according to claim 11, wherein the first p-region (904), the second n-region (906) and the silicon anchoring (911) each comprise epitaxial layers. [13] Semiconductor device (700) according to claim 11 or 12, wherein the first p-region (904) comprises a strained SiGe layer or a strained Ge layer. [14] Semiconductor device (700) according to one of claims 11 to 13, wherein the silicon anchoring (911) reduces voltage relaxation in the first p-region (904). [15] Semiconductor device (700) according to any one of claims 11 to 14, wherein the first material (702) comprises silicon and the second material (802, 904) comprises SiGe. [16] Semiconductor device (700) according to one of claims 11 to 15, wherein the second n-region (906) enables a low-resistance contact with the substrate. [17] Procedure (600) with the following steps: Producing (602) a recess (704) in a substrate (702), wherein the substrate comprises a first material; Growth (604) of a channel layer (802) in the recess (704), wherein the channel layer comprises a second material that is different from the first material; and Structuring (606) the channel layer (802) and an adjacent part of the substrate (702) to produce a continuous fin structure (902) having a first region (904), a second region (906) and an anchoring (911) arranged between the first region (904) and the second region (904), wherein the first region (904) has the structured channel layer and is configured to provide a channel of a multi-gate transistor, and the second region and the anchoring have the structured adjacent part of the substrate. [18] Method according to claim 17, wherein the first material (702) comprises silicon and the second material (802, 902) comprises SiGe. [19] Method according to claim 17 or 18, wherein the first region (904) has strained SiGe, the anchoring (911) has silicon and the anchoring prevents stress relaxation in the strained SiGe layer. [20] The method of claim 17, 18 or 19, further comprising: Doping the first region (904) with a p-doping agent and doping the second region (906) with an n-doping agent.

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