Switching power supply control

Abstract

Switching power supply control (10), comprising: at least one output terminal for controlling the switching of at least one switch of a switched-mode power supply, and a full switching cycle detection circuit designed to deactivate the switching of at least one switch upon receiving an error signal only after completion of a current switching cycle, wherein the at least one switch comprises a primary-side high-side switch (12) and / or a primary-side low-side switch (13).

Description

TECHNICAL AREA

[0001] The present application relates to controls for switched-mode power supplies (SMPS), corresponding switched-mode power supplies and associated methods. BACKGROUND

[0002] Switching power supplies are commonly used to deliver supply voltages to one or more circuit components. Some switching power supplies incorporate features such as power factor correction (PFC). Switching power supplies can also provide galvanic isolation, for example, by using a transformer. In such switching power supplies, power is selectively delivered to a primary side of the transformer by operating primary-side switches at a switching frequency, often using a pulse-width modulation scheme. The switching frequency of these primary-side switches is regulated to achieve a desired output voltage required for a specific application.

[0003] On the secondary side, rectifiers can be used in switched-mode power supplies. Some implementations use synchronous rectifiers, which employ switches operated synchronously with primary-side switches to provide a DC (direct current) output. Therefore, a typical switched-mode power supply (SMPS) topology might include a power factor correction circuit, a voltage converter circuit such as an LLC converter, and a synchronous rectification (SR) circuit. Other types of voltage converters besides LLC converters, such as other resonant converters, may also be used.

[0004] The switching of primary-side switches in such SMPS systems and of synchronous rectifier (SR) switches is optimized in many cases to minimize switching losses. For example, concepts such as zero-voltage switching (ZVS) for primary-side switches or zero-current switching for SR switches can be used.

[0005] Nevertheless, in some situations a shorter switching cycle, such as a shorter turn-on time of a switch, can occur than during normal operation. One example of such a situation is when the power to a system (supply voltage) is switched off, either due to a power outage or because a user shuts down the system. In such a case, the supply voltage to a controller (for example, primary-side LLC controller) can quickly drop below a threshold voltage, resulting in a reset. This, in turn, can set the output voltages of gate drivers, which in turn set the gates of primary switches or secondary synchronous rectifier switches to values ​​that immediately turn the switches off. Therefore, a final turn-on time in such an event can be shorter than previous turn-on times of the respective switch.

[0006] A different situation can arise in the case of other fault conditions. Switching power supply systems, especially when used in safety-critical environments, can employ various fault detection features such as undervoltage detection, overvoltage detection, overcurrent detection, etc. If a corresponding fault condition occurs, switching can also be stopped immediately, resulting in shorter turn-on times for one or more switches. For example, a controller for synchronous rectifier switches can be powered by an output of an LLC converter. If the LLC output is stopped, this controller is reset, which can lead to a shorter turn-on time for a synchronous rectifier switch.

[0007] Such shortened turn-on times can, in some situations, lead to voltage oscillations at the output capacitors of synchronous rectifier switches (for example, implemented as MOSFETs) and consequently to voltage spikes at the synchronous rectifier switch. Such voltage spikes can damage the switch and / or may require the switch to be designed to withstand such spikes, which increases the area required for implementing the switch and the cost.

[0008] US patent 2015 / 0 062 973 A1 discloses methods and devices for a switched-mode power supply which ensure that the synchronous rectifier switches of the switched-mode power supply complete a switching cycle before they are deactivated.

[0009] GB 2 455 568 A discloses a protection system for a resonant converter which switches off synchronous rectifiers depending on a voltage via synchronous rectifier switches. SUMMARY

[0010] According to one embodiment, a switching power supply control is provided, comprising: at least one output terminal for controlling the switching of at least one switch of a switched-mode power supply, and a full switching cycle detection circuit designed to deactivate the switching of at least one switch upon receiving an error signal only after completion of a current switching cycle, wherein the at least one switch comprises a primary-side high-side switch and / or a primary-side low-side switch.

[0011] According to another embodiment, a switching power supply control is provided, comprising: a first gate pulse generator designed to generate a control signal for a high-side switch of a switching power supply, a second gate pulse generator configured to generate a control signal for a low-side switch of the switching power supply, at least one trigger connection between the first gate pulse generator and the second gate pulse generator, wherein the first gate pulse generator is configured to start generating a gate control pulse after receiving a trigger signal via the at least one trigger signal connection from the second gate pulse generator, indicating that the second gate pulse generator has finished generating a control pulse, and wherein the second gate pulse generator is configured to start generating a gate control pulse after receiving a trigger signal via the at least one trigger signal from the first gate pulse generator, indicating that the first gate pulse generator has finished generating a gate control pulse, and a control logic designed to interrupt at least one trigger signal connection in the event of an error condition.

[0012] According to another embodiment, a method is provided comprising: Detecting a fault condition in a switched-mode power supply, and disabling the switching of at least one switch in the switched-mode power supply in response to the detection of the fault condition after completion of a current switching cycle, wherein the at least one switch comprises a primary-side high-side switch and / or a primary-side low-side switch.

[0013] According to yet another embodiment, a method is provided comprising: Detecting a fault condition in a switching power supply, and disabling a trigger connection between a high-side gate pulse generator and a low-side gate pulse generator, wherein each of the high-side gate pulse generator and the low-side gate pulse generator is designed to start generating a gate control pulse after receiving a trigger signal via the trigger connection, that the other of the first gate pulse generator and the second gate pulse generator has stopped generating a gate control pulse.

[0014] The above brief description is intended only to provide a short overview of some features of certain embodiments and should not be interpreted as limiting. In particular, other embodiments may contain features different from those listed above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a diagram that represents a switched-mode power supply as an example environment. Fig. Figure 2 illustrates parts of a control system according to one embodiment. Fig. Figure 3 illustrates part of a control system according to a further embodiment. Fig. Figure 4 illustrates part of a control system according to a further embodiment. Fig. 5 illustrates example signals for the embodiment of Fig. 4. Fig. Figure 6 illustrates part of a control system according to one embodiment. Fig. Figure 7 is a flowchart that represents a procedure according to one embodiment. Fig. 8 is part of a control system according to a further embodiment. Fig. Figure 9 is a flowchart that represents a procedure according to one embodiment. Fig. Figure 10 illustrates a part of a control system according to a comparative example. Fig. Figures 11 to 13 illustrate example signals and simulation results for a controller according to one embodiment and the comparative example of Fig. 10. DETAILED DESCRIPTION

[0015] Various embodiments are discussed in detail below with reference to the accompanying drawings. It should be noted that these embodiments are given merely as examples and are not to be interpreted as limiting. While, for example, embodiments may be described as including several features or elements, in other embodiments some of these features or elements may be omitted and / or replaced by alternative features or elements. Furthermore, in addition to the features or elements explicitly shown and described, other features or elements may be used, such as features or elements used in conventional switched-mode power supplies or switched-mode power supply controllers. In particular, parts of controllers and switched-mode power supplies are discussed below with regard to the termination (deactivation) of switching in the event of certain fault or similar conditions.Other features of such control systems or switched-mode power supply systems, in particular features or elements relating to regular operation, may be implemented as in conventional systems.

[0016] Features of different embodiments can be combined to create further embodiments. Variations and modifications described for one embodiment can also be applied to other embodiments.

[0017] In the embodiments shown and described, any direct electrical connection or coupling between elements or components, i.e., a connection or coupling without any intervening elements, can also be replaced by an indirect connection or coupling, i.e., a connection or coupling that includes one or more additional intervening elements, as long as the general purpose of the connection or coupling, for example, to provide a certain type of signal, to transmit a certain type of information, or to provide a certain type of control, is essentially maintained. In other words, the connection or coupling can be modified as long as the general function of a connection or coupling is retained.

[0018] The following description refers to switches. Switches can be implemented as transistors, for example, as MOS transistors. A switch is said to be on or closed when it provides a low-resistance connection between terminals (for example, source and drain terminals in the case of MOSFET switches). A switch is said to be off or open when it essentially provides electrical isolation between the terminals (perhaps excluding unwanted leakage currents that may occur in real-world applications).

[0019] To avoid repetition, similar components in the figures are labelled with the same reference numbers and are not repeated.

[0020] The embodiments described herein provide various techniques to ensure that a switching cycle (for example, the turn-on time of a switch) in a switched-mode power supply is completed to its full length before the switching is finished.

[0021] Now, with reference to the characters, it states Fig. Figure 1 schematically represents an implementation of a switched-mode power supply (SMPS) as an example environment in which the techniques discussed herein can be implemented. However, this is merely an example for illustrative purposes, and the techniques discussed herein can be implemented in various types and implementations of switched-mode power supplies and switched-mode power supply controls, for example, using different types of voltage converters.

[0022] The SMPS of Fig. Module 1 receives an input voltage Vbus and outputs a voltage Vout. Vbus can be a voltage from an unregulated power supply such as mains power, or it can be a voltage that has already been modified by certain circuitry, for example, a power factor correction (PFC) circuit.

[0023] The SMPS of Fig. The circuit further comprises an LLC converter. The LLC converter includes a high-side switch 12, a low-side switch 13, and a transformer 14. The switches 12 and 13 can be implemented as MOSFET switches, as shown. The switches 12 and 13 are coupled to a primary side of the transformer 14 and are actuated by a controller 10 to selectively send power to the transformer 14. The controller 10 can be implemented as a single integrated chip, but it can also be implemented in other ways, for example, as an integrated chip together with an off-chip peripheral circuit arrangement. In particular, the high-side switch 12 selectively couples the input voltage Vbus to the primary side of the transformer 14, and the low-side switch 13 selectively couples ground to the primary side of the transformer 14.

[0024] To generate the output voltage Vout, synchronous rectifier (SR) switches 15, 16 are coupled to a secondary side of the transformer 14, as shown. The SR switches 15, 16 can be implemented as MOSFET transistors. Switches 15, 16 are controlled synchronously with the switching of switches 12, 13 by the controller 10 via a driver circuit 18 to output a rectified voltage Vout. The voltage Vout is fed back to the controller 10 via a feedback loop 17 with an optocoupler to provide galvanic isolation. Based on this feedback, the controller 10 can control the switching of the primary switches 12, 13 to adjust the output voltage Vout to a setpoint and the corresponding switching of the synchronous rectifier switches 15, 16.

[0025] Switches 12, 13, 15, and 16 can be controlled in any conventional way during normal SMPS operation. Furthermore, control 10 and / or the SMPS can be controlled by... Fig. 1. Implement techniques as described below with reference to the Fig. Sections 2-13 discuss how to ensure that a switching cycle is completed (stopped, disabled) before switching is finished in the event of fault conditions such as undervoltage, overload, or SMPS shutdown. Apart from the techniques discussed here and below, control 10 can be implemented in any conventional way.

[0026] Fig. Figure 2 illustrates a block diagram of part of a control system for a switched-mode power supply according to one embodiment. As an example, the circuit of Fig. 2 in the control 10 of Fig. 1 or also outside of control 10 in the SMPS of Fig. 1 will be implemented.

[0027] In Fig. 2 will be a signal HSGD, which is used to control a high-side switch such as switch 12 of Fig. 1 is used, and a signal LSGD, which is used to control a low-side switch such as switch 13 of Fig. 1 is used and supplied to a full-cycle detection circuit 21. Furthermore, in the event of a fault condition, the full-cycle detection circuit 21 receives a fault signal. As in Fig. 2 symbolized by an OR gate 20, such an error signal can be an overload protection signal when an overload (for example, an excessive current output) is detected, an undervoltage signal VCCUVLO that detects an undervoltage in a supply voltage of a controller such as the controller 10, a bus undervoltage protection signal in response to a bus voltage such as Vbus in Fig. 1, which is below a threshold, or can be due to the deactivation of a voltage converter such as the LLC converter of Fig. This could be attributed to 1 (enabling / disabling the LLC), to name just a few examples. It should be noted that any event or error signal can be used that should trigger the shutdown of switches 12 and 13, or in other words, that should trigger the shutdown or suspension of SMPS operation.

[0028] During normal operation, the full-cycle switching detection circuit 21 forwards the HSGD and LSGD signals to the drivers 22 and 23, respectively, to control the high-side (HS) and low-side (LS) switches. If an error signal is received indicating that a switching operation should be completed, this full-cycle switching detection circuit 21 delays this completion until the current switching cycle of the high-side or low-side switch has finished (i.e., the switch's on-time is maintained at its regular duration, and no switch is turned off "midway" through its on-time). Afterward, the switching is completed by holding both the high-side and low-side switches open via the drivers 22 and 23. In particular, in some implementations, the full switching cycle detection 21 can complete the switching at the next dead time between the turn-on times of the high-side switch and the turn-on times of the low-side switch.In this respect, a dead time is the period when both the high-side switch and the low-side switch are open during normal operation. As can be seen from the HSGD and LSGD signals during normal operation, the high-side switch 12 and the low-side switch 13 open and close alternately. If both switches were to close simultaneously, a short circuit between the voltage Vbus and ground would result. Therefore, short dead times are introduced between the opening and closing of one switch to reliably prevent both switches from closing at the same time.

[0029] In some embodiments, this can reduce voltage spikes that could occur if switching is completed immediately in response to the fault signal, for example during the turn-on time of a high-side switch or a low-side switch.

[0030] Fig. Figure 3 illustrates part of a control system such as the control system 10 according to one embodiment and illustrates an implementation of a full-cycle switching detection circuit as in Fig. 2 shown.

[0031] In Fig. 3. An error signal is supplied from various sources, as symbolized by an OR gate 20, as for Fig. 2 explained. Furthermore, signals HSGD and LSGD are explained as in Fig. 2 for controlling a high-side switch and a low-side switch via drivers 22, 23 in normal operation, also as in Fig. Figure 2 shows that the signals HSGD and LSGD are supplied to drivers 22 and 23, respectively, via switches S1 and S2, which are closed during normal operation. This allows the high-side and low-side switches to be controlled according to the HSGD and LSGD signals. Furthermore, the HSGD and LSGD signals are supplied to a NOT-OR gate 31. This gate therefore outputs a signal that is high (for example, logic 1) when both HSGD and LSGD are low (indicating an open state of the respective switch) and zero otherwise. In other words, the signal output by the NOT-OR gate 31 is high during the aforementioned dead times.

[0032] The error signal and the signal output by the NOT-OR gate 31 are fed to an AND gate 32. Therefore, the AND gate 32 outputs a high signal level (e.g., corresponding to a logic 1) if the error signal indicates an error state, and the signal output by the NOT-OR gate 31 indicates a dead time and otherwise outputs a zero. The output of the AND gate 32 is fed to a set / reset flip-flop 33. An output of the set / reset flip-flop 33 controls switches S1 and S2. In this case, if an error signal indicates an error state, the set / reset flip-flop outputs a logic 1 at the next dead time when switches S1 and S2 are open, thus terminating the switching. This ensures that a current switching cycle (turn-on time of the high-side switch or the low-side switch) is completed and only then is the switching completed.This can prevent or reduce voltage spikes in some implementations.

[0033] Fig. Figure 4 illustrates a part of an SMPS controller such as the controller 10 according to another embodiment. In the embodiment of Fig. 4. An error signal from various sources, as symbolized by an OR gate 20, is again supplied to an AND gate 32. One output of the AND gate 32 is connected to the already mentioned Fig. The set / reset flip-flop 33 described in section 3 is coupled, and an output of the set / reset flip-flop can complete the switching, for example by opening switches such as switches S1, S2 in Fig. 3.

[0034] Furthermore, the embodiment of Fig. 4 a circuit 43. The circuit 43 essentially comprises an oscillator which is used to generate control signals for the high-side switch and the low-side switch, such as the previously described signals HSGD and LSGD, to directly generate a signal indicating dead times. The circuit 43 includes a charging current source 44, which powers a node V CF with a charging current I chg charges when a switch 40 is closed, and a discharge current source 411, which connects node V CF with a current I disc discharges when switch 410 is closed. The voltage at node V CF is supplied to a positive input of a first comparator 47 and to a negative input of a second comparator 48. A first threshold V CH is coupled to an input of the comparator 47 and a second threshold voltage V CLis coupled to a positive input of comparator 48. An output of comparator 47 is coupled to a reset input of a first set / reset flip-flop 46 and to a second input of a second set / reset flip-flop 49. An output of comparator 48 is coupled to a set input of the first set / reset flip-flop 46 and a reset input of the second set / reset flip-flop 49. An output of set / reset flip-flop 46 controls switch 40, and an output of set / reset flip-flop 49 controls switch 410.

[0035] The output of the set / reset flip-flop is labeled V delay This signal is marked and used to control switch 410. Simultaneously, this signal and the discharge generate the switching dead times and are used as an input to an AND gate 34 as a signal indicating dead times. The effect is essentially the same as described in... Fig. 3 explains, that is, the switching is only completed after the end of a switching cycle, so that the on-time is not shortened if a fault condition occurs.

[0036] Based on signals output by comparator 47, 48, additional control voltages V are generated. LG , V HG generated. V LG controls a low-side switch (for example, according to the LSGD signal or as a basis for it), and V HG This is a suitable voltage for the high-side switch. The voltages V LG , V HG are generated, as shown, using a D-latch 412, a set / reset flip-flop 413, an inverter 414, and AND gates 415, 416, as shown in Fig. 4 are shown coupled.

[0037] Fig. 5 illustrates example signals based on the embodiment of Fig. 4. As shown in example voltages V LG , V HG in Fig. As can be seen in Figure 5, the low-side switch and the high-side switch are alternately turned on while the voltage V CF from 1 V to 4 V in the example of Fig. 5 increases, with dead times during the unloading of V CF the voltage V delay correspond. A length of dead time is in Fig. 5 with t d marked.

[0038] Furthermore, in the example of Fig. 5. At a certain time, an error occurs, resulting in a voltage (error signal) V. fault The signal to complete the switching, output by the set / reset flip-flop 33, is delayed by a time indicated by an arrow 50 until the start of the next dead time, as shown at the bottom of Fig. 5 shown.

[0039] It should be noted that the in Fig. The five explicitly specified signal waveforms and voltages serve only as non-limiting examples to provide further illustration and should not be interpreted as limiting, as other implementations may have different signal waveforms. Furthermore, the turn-on times of the high-side and low-side switches can be varied depending on the desired output voltage of the SMPS.

[0040] In some cases, the supply voltage to a controller such as controller 10 may drop so rapidly that the switching operation would be completed before the next dead time could be reached. In this case, early detection of a falling supply voltage can be used to ensure that the switching operation can be completed only after a switching cycle has finished.

[0041] Fig. Figure 6 illustrates an embodiment that employs such techniques. Fig. 6 corresponds to circuit 43, which was already mentioned with reference to Fig. Circuit 43, as described in section 4, will not be described in detail again. Furthermore, in Fig. 6 the control supply voltage Vcc (see for example Fig. 1) The voltage is supplied to a negative input of a comparator 60 and further, via a filter comprising a resistor 61, a capacitor 63, and a voltage source 62, to a positive input of the comparator 60. If the voltage drops below a threshold slope determined by the filter 61, 62, 63, the comparator 60 outputs an error signal, which leads to the termination of switching at the next dead time, i.e., after completion of the next switching cycle. It should be noted that the output of the comparator 60 can also be supplied to an OR gate to be combined with other error signals, such as the OR gate 20 of Fig. 2.

[0042] Fig. Figure 7 is a flowchart illustrating a method according to one embodiment. For easier reference and better understanding, the method is described by Fig. 7 with reference to the Fig. 1 to 6 explained. However, it should be noted that the procedure of Fig. 7 can also be implemented in other SMPS controllers and other SMPS than those explicitly shown and referenced in Fig. 1-6 are described.

[0043] At 70 in Fig. 7. The procedure includes the detection of a fault condition in an SMPS. Such a fault condition can include an overload condition, undervoltage, a shutdown of the SMPS, or a drop in the supply voltage of a controller, as described in relation to Fig. 1-6 explained.

[0044] In section 71, the procedure involves disabling the switching of primary switches of a voltage converter of the SMPS and, optionally, also of secondary-side switches such as synchronous rectifier switches, after the next dead time of the primary-side switches. In other words, switching is only deactivated after a current switching cycle has been completed, as also explained above.

[0045] The above embodiments can be applied in particular to analog control designs or to peripheral circuit designs of digital controllers. In purely digital solutions, other approaches can be taken. An embodiment of such an approach is described in Fig. 8 shown. Fig. Figure 8 illustrates part of an SMPS control system according to an embodiment that can be used, for example, in digital control solutions.

[0046] The control of Fig. 8 comprises a first gate pulse generator 81 for generating a signal HSGD to control a high-side switch (for example, similar to the signal HSGD in previously discussed embodiments) and a second gate pulse generator 82 for generating the signal LSGD, which controls a low-side switch (similar to the signal LSGD discussed previously). The signals HSGD and LSGD are then supplied to respective drivers to control, for example, gates of MOS switches, similar to drivers 22 and 23 of Fig. 2 and Fig. 3.

[0047] After a pulse has finished (for example, at the end of the high phase of a pulse indicating that the respective switch is turned on), the gate pulse generator 81 sends a trigger signal via connection 86 to the second gate pulse generator 82. Upon receiving this trigger pulse, the second gate pulse generator 82 starts its own pulse to turn on the low-side switch. Conversely, after the pulse turning on the low-side switch, the second gate pulse generator 82 sends a trigger pulse via connection 85 to the first gate pulse generator 81, indicating that the pulse has finished. Upon receiving this trigger pulse, the first gate pulse generator 81 starts the next pulse that switches the high-side switch. Instead of separate connections 85 and 86, a single bidirectional connection can also be used.In this way, while each gate pulse generator 81, 82 waits for the trigger pulse to indicate the termination of a pulse from the respective other gate pulse generator 81, 82 before starting its own pulse, simultaneous switching times of both the high-side and low-side switches are prevented and dead times between switching are ensured.

[0048] If a fault condition is detected, a control logic 80 opens the switches 83, 84, which are closed during normal operation, thereby interrupting the connections 85, 86 and preventing the transmission of the aforementioned trigger pulses from one gate pulse generator 81, 82 to the other gate pulse generator 81, 82. Fault conditions can be, as previously discussed, overload, supply voltage or bus voltage, undervoltage, converter deactivation, a rapid drop in the control supply voltage, etc. Therefore, after one of the gate pulse generators 81, 82 has finished its pulse, no trigger pulse reaches the respective other gate pulse generator, and therefore no further pulses are generated and switching is deactivated. In this way, similar to previous embodiments, a current pulse is terminated before switching is deactivated.

[0049] Fig. Figure 9 illustrates a method according to one embodiment. The method of Fig. 9 can be used in the control of Fig. 8 can be implemented, but can also be implemented independently. At 90, the procedure comprises Fig. 9. The detection of a fault condition, for example overload, undervoltage, deactivation of the converter, etc., as previously discussed. In 91, the method, in response to the detection of the fault condition, includes deactivating a trigger connection between gate pulse generators (for example, deactivating connections 85, 86 by opening switches 83 and 84, respectively). Fig. 8) This prevents the generation of further pulses while ensuring that the current switching cycle has ended.

[0050] Next, embodiments will be further illustrated using a comparative example and example signals. It should be noted that these example signals serve only for further illustration and that signal waveforms may vary depending on the implementation and operating conditions of the SMPS. For illustrative purposes, the following is shown: Fig. 10. A comparative example without techniques such as those disclosed herein to ensure that a switching cycle is completed, for reference purposes. In the comparative example of Fig. 10 different error signals are similar Fig. 2 and Fig. The three terminals are connected in an OR gate 100 to form an error signal. In response to the error signals, switches S1 and S2, via the control signals HSGD and LSGD supplied to drivers 101 and 102, are opened, so that when an error signal occurs, the switching of the high-side and low-side switches is immediately deactivated. Therefore, switching can be deactivated midway through the on-time of a high-side or low-side switch.

[0051] Fig. Figure 11 illustrates simulated example signals for a comparison example, as in Fig. 10 shown, applied to an SMPS, as in Fig. Figure 112 shows a primary LLC current (current through the primary side of transformer 14). Fig. 1), curve 113 illustrates a gate voltage at synchronous rectifier switches, curve 114 illustrates a control supply voltage (Vcc), and curve 115 shows an example drain-source voltage Vds of a synchronous rectifier switch (for example, 15, 16 of Fig. 1) As can be seen, a voltage spike 111 occurs when switching is completed immediately during a switching cycle. This can damage the synchronous rectifier MOSFETs or require that the synchronous rectifier MOSFETs be designed to withstand such spikes.

[0052] Fig. Figure 12 illustrates example signals that may occur in some embodiments. Fig. Figure 12 shows an example of signals in the case of an undervoltage of the control supply voltage Vcc. The example of Fig. 12 uses three threshold values ​​Vcc_on, Vcc_uvlo_ and Vcc_off.

[0053] When the system is switched on, the voltage Vcc rises. At time t1, the voltage threshold Vcc_on is reached, and the controller starts operation, initiating the switching process as indicated by a switching signal 121 (e.g., HSGD or LSGD). Specifically, if Vcc_on is reached at t1, for example, a value of 12 V, the controller will start an initialization process and read firmware parameters. If no error is detected, it will initiate switching, as indicated by the switching signal 121.

[0054] After that, the controller operates normally between times t1 and t2, providing controlled switching of the high-side and low-side switches of an SMPS to regulate an output voltage.

[0055] At t2, the voltage Vcc reaches the threshold value Vcc_uvlo, for example, 9 V, for some reason (fault or other). At this point, switching of both primary-side switches and synchronous rectifier switches is disabled after the current switching cycle has finished, using techniques as discussed above, e.g., to prevent voltage spikes. In embodiments, the voltage Vcc_uvlo is chosen such that this supply voltage is still sufficient to power the gate drivers, such as a high-side gate driver, to complete the full switching cycle, i.e., above a turn-off threshold of these drivers. After t2, the voltage is still high enough for the controller to operate. Two different scenarios can occur. In one scenario, the voltage rises again and reaches Vcc_on at t3. In this case, switching resumes at t3, provided no other fault conditions are detected.In the example scenario shown, Vcc then drops to Vcc_uvlo at t4, and similar to t2, switching is stopped.

[0056] In this case, however, the voltage drops further below a threshold value Vcc_off. In this case, the control system is completely reset without switching until Vcc_on is reached again at t6.

[0057] In some embodiments, selecting Vcc_uvlo sufficiently above Vcc_off ensures that a full switching cycle can be completed.

[0058] Fig. Figure 13 shows a simulation result where sizes correspond to the simulated sizes of Fig. Figure 11 shows, i.e., curve 132 represents an LLC primary current, curve 133 represents a gate voltage of a synchronous rectifier switch, curve 134 represents a control supply voltage, and curve 135 represents an exemplary drain-source voltage. In contrast to Fig. 11 were in Fig. 13 techniques as disclosed herein are used to ensure that deactivation in the event of a fault condition only occurs after the current switching cycle has ended. As can be seen, no voltage spike occurs in curve 135 in this case. This is due to the fact that in the case of Fig. 11. The synchronous rectifier MOSFET can be switched while a current is applied to it, while in the scenario of Fig. 13. The zero-current switching of a synchronous rectifier MOSFET is maintained in such a way that a rectification current flowing through a body diode or through the synchronous rectifier switch naturally reaches zero during normal operation. Therefore, the effect of reverse recovery of the body diode is small and does not lead to a voltage spike.

Claims

[1] Switching power supply control (10), comprising: at least one output terminal for controlling the switching of at least one switch of a switched-mode power supply, and a full switching cycle detection circuit designed to deactivate the switching of at least one switch upon receiving an error signal only after completion of a current switching cycle, wherein the at least one switch comprises a primary-side high-side switch (12) and / or a primary-side low-side switch (13). [2] Switching power supply control (10) according to claim 1, wherein the full switching cycle detection circuit comprises a circuit part configured to generate a dead-time signal indicating dead times of switching of the at least one switch, wherein the full switching cycle detection circuit is configured to deactivate switching when an error signal indicates an error condition and the dead-time signal indicates a dead time. [3] Switching power supply control (10) according to claim 2, wherein the circuit part configured to generate the dead-time signal comprises a NOT-OR gate (31), wherein a first input of the NOT-OR gate (31) is configured to receive a high-side gate driver signal controlling a high-side switch of the at least one switch, and to receive a low-side gate driver signal controlling a low-side switch of the at least one switch. [4] Switching power supply control (10) according to claim 2, wherein the circuit part configured to generate the dead-time signal comprises an oscillator circuit (43). [5] Switching power supply control (10) according to one of claims 1-4, wherein the at least one switch comprises a synchronous rectifier switch. [6] Switching power supply control (10), comprising: a first gate pulse generator (81) configured to generate a control signal for a high-side switch of a switching power supply, a second gate pulse generator (82) configured to generate a control signal for a low-side switch of the switching power supply, at least one trigger connection between the first gate pulse generator and the second gate pulse generator, wherein the first gate pulse generator is configured to start generating a gate control pulse after receiving a trigger signal via the at least one Trigger signal connection from the second gate pulse generator, this indicates that the second gate pulse generator has completed a control pulse, and where the second The gate pulse generator is designed to start generating a gate control pulse after receiving a trigger signal via at least one Trigger signal connection from the first gate pulse generator, indicating that the first gate pulse generator has finished generating a gate control pulse, and a controller (80) designed to interrupt the at least one trigger signal connection (85, 86) in the event of a fault condition. [7] Switching power supply control (10) according to one of claims 1-6, further comprising a detection circuit configured to detect a decreasing control supply voltage, wherein a detected drop in the control supply voltage corresponds to a fault condition. [8] Switching power supply control (10) according to claim 7, wherein the detection circuit comprises a comparator, wherein the supply voltage is coupled to a first input of the comparator and to a second input of the comparator via a filter circuit (61, 62, 63). [9] Switching power supply control (10) according to one of claims 1-8, wherein the switching power supply control (10) is configured to detect a fault condition when a control supply voltage drops to a first threshold value which is above a second threshold value which indicates a reset of the switching power supply control (10). [10] Switching power supply, comprising: a switched-mode power supply control (10) according to one of claims 1-9, a voltage converter comprising at least one switch controlled by the switching power supply control (10), and a synchronous rectifier switch at one output of the voltage converter. [11] Procedure, encompassing: Detecting a fault condition in a switched-mode power supply, and Disabling the switching of at least one switch in the switching power supply in response to the detection of the fault condition after completion of a current switching cycle, wherein the at least one switch comprises a primary-side high-side switch (12) and / or a primary-side low-side switch (13). [12] Method according to claim 11, wherein disabling the switching comprises disabling the switching at the next dead time between a switching of the high-side switch and a switching of the low-side switch in response to the detection of the fault condition. [13] Procedures, including: Detecting a fault condition in a switched-mode power supply, and Disabling a trigger connection between a high-side gate pulse generator and a low-side gate pulse generator, wherein each of the high-side gate pulse generator and the low-side gate pulse generator is designed to start generating a gate control pulse after receiving a trigger signal via the trigger connection, that the other of the first gate pulse generator and the second gate pulse generator has finished generating a gate control pulse. [14] Method according to one of claims 11-13, wherein the detection of the fault condition comprises the detection of one or more of a control supply voltage drop, an undervoltage condition, a deactivation of at least one part of the switching power supply and an overload condition.

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