Bus device with programmable address

Abstract

Facility that has: a bus communication circuit (302) connected to a bus terminal (308); a first pin terminal (312); a memory (306) having a first register (320) with a first address stored therein and a second register (322); a state logic circuit (304) connected to the memory (306), the first pin terminal and the bus communication circuit (302), wherein the state logic circuit (304) comprises circuitry configured to detect a chip select signal at the first pin terminal and, while the chip select signal is present, to receive a first message via the bus communication circuit (302), wherein the state logic circuit (304) further comprises circuitry configured to determine that the first message indicates an address setting command and, in response to a destination address in the first message matching the first address, to store an address value in the first message as a second address in the second register (322), and wherein the state logic circuit (304) further comprises circuitry configured to process a second message received by the bus communication circuit (302) in response to a destination address of the second message matching the second address.

Description

[0001] The present application relates generally to a system and method for setting an address of a bus device and, in certain embodiments, to a system and method for setting an address of a bus device using a bus message.

[0002] Many electronic systems include a bus, and several components are connected to the bus. The bus provides a path for components to communicate with each other. In a master-slave bus arrangement such as an inter-integrated circuit bus (I2C), a serial peripheral interface bus (SPI), a system management bus (SMBus or SMB), direct memory access (DMA), a power management bus (PMBus), or the like, one or more master devices communicate with one or more slave devices. A master device communicating with a slave device initiates communication by addressing the slave device, either through an address in a message on the bus or through associated message pins off the bus.When a slave device is addressed over the bus, for example, on an I2C bus, the master device can signal control of the bus through power levels on the bus lines and can then send packets containing an address of a target slave device, a command, and data. The addresses used to communicate with the slave device over the bus can be assigned by a system bus management unit, and the addresses are generally associated with a specific type of device or class of device. Therefore, multiple devices of the same model, type, or manufacturer can be assigned the same address.

[0003] EP 691 617 A2 describes a memory device with multiple memory modules connected in parallel to a master I / O module via a DASS (Single Directional Asymmetrical Signal Swing) bus. The memory device includes a resynchronization circuit that enables both synchronous and asynchronous operation using the same pins. Each memory module has independent address and command decoders to enable independent operation. The memory device includes redundant memory modules for replacing defective memory modules. Replacement can be performed via commands on the DASS bus. The memory device can be configured to write a single input data stream to multiple memory modules simultaneously or to perform fast, interleaved read and write operations.

[0004] US Pat. No. 5,638,520 A describes a method and apparatus for distributing the bus load in a data processing system. A bit field of a bus load control register is used to determine how addresses and data are transferred across the buses, enabling a more even load distribution across the buses. There is no fixed address or data bus. Instead, each generic bus can be individually programmed on a cycle-by-cycle basis to transfer only addresses, only data, both addresses and data, or neither addresses nor data.

[0005] US 5,872,940 A discloses a system bus controller in a processor. The controller includes programmable logic for different chip enable signals per address space. This enables a seamless interface between the processor and various types of external devices, such as memory chips. A chip select register value is preprogrammed for each external device connected to the processor. This preprogrammed register value is used by the system bus controller to individually configure a read / write access signal to each of the external devices.

[0006] US 5 884 027 A describes a multifunction device that integrates a high-performance processor into a PCI-to-PCI bus bridge.

[0007] Embodiments of the invention relate to a device according to claim 1, methods according to claims 6, 11 and 16 and a system according to claim 20.

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which: Fig. 1 is a diagram illustrating a system having slave devices with programmable addresses, in accordance with some embodiments; Fig. 2 is a diagram illustrating a system having slave devices with programmable addresses, in accordance with some embodiments; Fig. 3A is a diagram illustrating a device using circuitry for programmable addressing in accordance with some embodiments; Fig. 3B is a diagram illustrating a system with a programmable, addressable slave gate driver according to some embodiments; Fig. 4 is a flowchart illustrating a method for programming an address to a slave device according to some embodiments; Fig. 5 is a flowchart illustrating a method for a slave device to set a programmable address according to some embodiments; Fig. 6 is a diagram illustrating a method for processing a message using a programmed address according to some embodiments.

[0009] As electronic devices have become increasingly sophisticated and feature-rich, the use of duplicate components such as bus slave devices within a single system has become increasingly common. However, when multiple instances of a particular type of slave device are provided on a bus, a master device must address each slave device individually. With more than one identical slave device on the bus, addresses must be defined differently for each slave device. Default addresses used in addressing slave devices across the bus may be assigned by a standards organization or system bus management entity, and the addresses are generally associated with a specific type or class of slave device.Therefore, multiple slave devices of the same model, type, or manufacturer can be assigned the same address. If multiple slave devices with the same model or part number, or from a specific manufacturer, are present in a system, the slave devices can have the same default address.

[0010] Embodiments relating to the disclosed slave device with a programmable address provide a system in which all connected slave devices can have different active addresses to prevent them from being addressed simultaneously. This avoids the need to provide slave devices with different, fixed addresses to enable multiple slave addresses of the same type on a bus. Providing a programmable address avoids the logistical overhead of increased chip area associated with fixed addresses. Additionally, the programmable address avoids the requirement for registering bus interface registers with standards organizations or management entities. Therefore, a customer or end user can assign their own addresses independently of standards organizations or management entities.Embodiments of the disclosed slave device with a programmable address further provide the ability to set the address of individual slave devices via the bus. In some embodiments, the default address is only listened to when the slave device's address is unconfigured and the chip select is set. Once an active address is configured, the chip select pins no longer act as chip select pins and can be used for additional functions. This avoids the need for additional external dedicated address pins to configure the chip to a different address, which may not be practical or economical for pin-constrained packages.

[0011] The embodiments disclosed herein provide programmable addresses at slave devices so that each slave device can be individually addressed without conflict. Therefore, slave devices that have the same default address at manufacture can be set to an active address so that if the slave device is included in a large system, the slave device will not attempt to process instructions intended for other slave devices. In some embodiments, all duplicate slave devices can power up with an identical default address. However, in order for a particular slave device to respond to the initial address, a sideband chip select can be enabled. In some embodiments, this sideband signal is a normal function pin or pins. However, the normal function pin has no effect at power up other than a chip select.Sideband refers to the fact that this chip select signal is not normally part of the bus interface specification. Once the slave device, whose chip select pins are enabled, is addressed via the bus, the slave device can be programmed to have a different address. After the slave device has been programmed with a new, unique, or active address, the slave device responds only to that address, and the chip select pin is no longer required. Once the active address has been set, the pin(s) used as chip select can be used for their original or additional functional purpose. This process can be performed for each identical slave device on the bus, so that all slave devices have different addresses.This allows identical slave devices to be provided for subsequent programming of the usable address from a default address to a unique active address for each slave device, avoiding logistical problems associated with hard-programmed addresses. Additionally, programming the address of each slave device via the bus and using a normally functional pin as a chip select eliminates the need for additional external addressing or chip select pins. Therefore, for slave devices with a small footprint and a reduced pin count solution, users, system manufacturers, or system integrators can define addresses as needed without registering the addresses.

[0012] Fig. 1 is a diagram illustrating a system 100 including slave devices 106 with programmable addresses, according to some embodiments. In one embodiment, a system 100 includes a control circuit 104 connected to a bus 102. In some embodiments, the bus 102 is an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a system management bus (SMBus or SMB), a direct memory access (DMA), a power management bus (PMBus), or the like. For example, if the bus is an I2C bus, the bus may have four conductive lines, which are a ground line or reference ground (common ground), a Vcc line, which is a supply voltage line with a voltage approximately 1.2 volts to 5.5 volts above ground, a serial data (SDA) line, and a serial clock (SCC) line.The control circuit 104 may include a master device such as a processor, a microcontroller, a logic circuit, a state machine, or the like. One or more slave devices 106, including, for example, a first slave device 106A, a second slave device 106B, or any number of other slave devices 106N, may be connected to the bus 102. The slave devices 106 may include, for example, a gate driver, light-emitting diode (LED) driver, voltage driver, processor, memory device, communication device, sensor, digital-to-analog converter (DAC), analog-to-digital converter (ADC), communication driver, or the like.For example, if the slave device is a gate driver, the gate driver can be connected to the bus and used to control the gate of a transistor or circuit. The bus can be used to issue commands to the gate driver slave device to reset the device, perform an emergency shutdown, turn the gate driver off or on, perform configuration or diagnostics on the gate driver, or the like.

[0013] The control circuit 104 may communicate with the slave device 106 using a protocol that complies with the requirements of the particular protocol of the bus 102. For example, for an I2C bus, the control circuit 104 may use the I2C protocol and may output one or more address frames carrying an address of a target slave device 106 and one or more command and data frames that are read by the slave device at the address in the address frame. In some embodiments, the slave devices 106 may be programmable so that the active addresses that identify each slave device 106 may be set via the bus.

[0014] The control circuit 104 initiates the programming of the address of each slave device 106 by applying or sending a signal to one or more chip select pins. In some embodiments, the chip select pins of the slave device 106 are pins that have other functions during normal operation of the slave device 106. The control circuit 104 drives the chip select pins for an individual slave device 106 to an active state to notify a particular slave device that address programming is incoming and to uniquely identify an individual slave device 106 that may share the same default address with one or more other slave devices 106. The chip select pins are segregated or disconnected from the bus 102, allowing the chip select pins to be driven active while messages are being sent to a slave device 106.While the chip select pins for a target slave device 106 are being brought into the active state, the control circuit 104 sends a message to the target slave device to set or program the active address in the slave device 106. In some embodiments, the message may include the default address of the target slave device 106, a command to set the active address, and / or a data value for the active address. After setting the active address for a particular slave device 106, the chip select pins may be brought out of the active state or enabled, and the process may be repeated for one or more other slave devices 106. Additionally, each slave device 106 may also have one or more programmable group addresses. The group address is separate from and in addition to the active address or default address.The slave device 106 responds to received messages with the group address. The group address allows the setting of an address shared by multiple slave devices, allowing the control circuitry to control multiple slave devices with a single command or message. For example, in a system where multiple voltage drivers are provided on the bus, each individual slave device may have a different active address but the same group address. Thus, each individual voltage driver slave device may be commanded to have a unique voltage output using the slave device's active address, but the group of voltage driver slave devices may be turned off as a group using a group turn-off command with the group address.Each voltage driver slave device receives the group shutdown message, determines that the address in the message matches the group address in the slave device, and then processes the group shutdown message. In this example, the active addresses of each voltage driver slave device are different from each other, and they all differ from the group address.

[0015] The addresses of the individual slave devices 106 can be set once or multiple times. Therefore, in some embodiments, the addresses of the slave devices 106 can be set during manufacturing, for example, to set up slave devices for use in manufacturing electronic circuits according to customer requirements. In other embodiments, when the slave devices 106 are used to manufacture a large system, the addresses of the slave devices can be set during initial use of the system or during an initialization or programming stage of system manufacturing. In other embodiments, the addresses of the slave devices 106 can be set spontaneously or during use.For example, a master device or control circuit 104 of a system may set the address of each of the slave devices 106 in response to a programming signal when the system is first booted, or the master may set or initialize the addresses of each of the slave devices 106 each time the system is started. Each slave device 106 may store the programmed address as the active address in volatile or non-volatile memory, which is accessed by logic in the respective slave device that handles the communication or logic.

[0016] Providing unique addresses for each of the slave devices 106 allows, for example, a first slave device 106A to have an address that is different from an address assigned to a second slave device 106B or other slave devices 106N. The slave device 106 determines whether an active or programmed address has been set and uses the programmed address during normal operation to process a message, rather than using the default address assigned to the slave device during manufacturing.

[0017] Fig. 2 is a diagram illustrating a system 200 having slave devices 106 with programmable addresses, according to some embodiments. The system 200 includes a control circuit 104 including, for example, a master device 202 and address logic 204 coupled to the master device 202. The master device 202 is coupled to the bus 102 and communicates with the slave device 106 via the bus 102 using a bus-compatible protocol. In some embodiments, the address logic 204 is a decoder, logic gate chain, or the like that accepts an address or other signal from the master device and converts it into a signal addressing a single slave device 106A, 106N.Additionally, in some embodiments, such as a system 200 where each slave device 106 has multiple chip select pins, address logic 204 provides signals on multiple discrete lines to simultaneously address or set all of the chip select pins for a target slave device. Thus, a first chip select pin for a slave device 106 may be driven by a signal on first lines 206, and a second chip select pin for the slave device may be driven by a signal on second lines 208 separate from first lines 206. It should be understood that the chip select pins may be addressed using any signals, and that the signals for addressing multiple pins on a target slave device may be different.For example, a gate driver control pin and a ready indicator pin may function as the chip select pins, and they may be addressed by address logic 204 by holding the gate driver control pin high and the ready indicator pin low. In such an example, the gate driver control pin for the slave device is an input pin that is driven by control circuitry 104 during normal operation to turn the output of the slave device on or off. The ready indicator pin may be an output pin of slave device 106 and may be driven by logic in slave device 106 during normal operation to indicate that slave device 106 is ready for operation or ready to receive commands.In some embodiments, the chip select pins are a combination of input pin and output pin so that the combination of pins are not inadvertently driven at the same time to indicate that the pins are being used as chip select pins.

[0018] While the chip select pins of a target slave device 106 are being driven, the master device 202 sends a command to set the active address or group address to the target slave device 106 over the bus. In some embodiments, the chip select pins for the target slave device may be maintained as discussed above while multiple commands to set the active and group addresses are issued to the target slave device. Additionally, the target slave device may confirm that the active or group address has been set correctly after setting each address.

[0019] Fig. 3A is a diagram illustrating a device 300 including circuitry for programmable addressing according to some embodiments. In this embodiment, the device 300 may be a slave device configured to receive a command to set an address and respond to messages directed to the programmed address. In some embodiments, the device 300 includes state logic 306 that controls the logical operations of the device, such as determining whether incoming messages are directed to the device, controlling the handling of received commands, and the like.In some embodiments, state logic 304 may be a logical state machine formed from discrete logic components integrated into an integrated circuit, such as an application-specific circuit, a programmable logic gate, or a gate array, implemented in software executing on a processor, a microcontroller, or other computing device, or the like. In some embodiments, state logic 304 processes or processes incoming commands and causes device 300 to respond or act on the commands.

[0020] The state logic 304 is connected to a bus communication circuit 302, which processes incoming and outgoing signals on the bus via one or more bus terminals 308. The bus communication circuit may receive data from the state logic 304 for transmission onto the bus, and it may handle the conversation for signal transmission in a bus-compatible protocol. Similarly, the bus communication circuit 302 receives messages from the bus and sends data from the message to the state logic 304 for processing. The state logic 304 may process the commands and respond via the bus using the bus communication circuit 304, or it may provide an output, signal, response, or the like, for example, via an output such as an output port, pin, display, or the like.In some embodiments, for example, when the bus is an I2C bus, bus terminals 308 include a ground line, an SDA line, an SCL line, and a Vcc line, with bus communication circuitry 302 sending and receiving data over the bus using the SDA and SCL lines. In other embodiments where other bus types or protocols are used, the number and type of bus terminal 308 reflect the requirements of the relevant bus protocol.

[0021] The device further includes a memory 306 for storing data related to the device's addresses. In some embodiments, the memory includes a default address register 320, an active address register 322, and a group address register 324 for devices 300 configured to use a group address. In some embodiments, the memory 306 may further include a configuration check bit memory or register 326. The configuration check register 326 may be used to store a configuration check value or bit indicating that the active address has been properly configured. In some embodiments, the registers 320, 322, 324, and 326 may be non-volatile memory or other computer-readable medium such that an address stored in the respective register 320, 322, 324 is retained when the memory is powered off.In some embodiments, the default address is stored in the default address register 320 by a manufacturer during a manufacturing, production, initialization, or testing phase. In some embodiments, the active address register 322 and the group address register 324 are writable memory into which the state logic 304 can write a received address to the relevant register. Additionally, the active address or the group address can be written to the relevant register by a manufacturer or user during system manufacturing. In other embodiments, the active address or the group address can be written to the relevant register by a manufacturer, distributor, or the like for customization before being delivered to a system manufacturer or user.

[0022] Device 300 further includes one or more pin terminals 312 and 314 that provide connectivity to one or more pins 316 and 318 separate from the bus or bus terminal 308. Pins 316 and 318, in some embodiments, are chip select pins, which also provide additional functionality. During power-up or another programming mode, pins 316 and 318 operate as chip select pins, and when pins 316 and 318 are addressed, state logic 304 detects the state of pins 316 and 318. When pins 316 and 318 are addressed in an address programming pattern, state logic 304 listens for messages on the bus addressed to device 300. When the bus communication circuit 304 receives a message over the bus, it is forwarded to the state logic 304, which compares the destination address from the message with the default address.If the address in the message matches the address stored in the default address register 320, the state logic 304 checks the command in the message, and if the command is to set or program the active address, the state logic 304 stores the address from the message as the active address in the active address register 322. In some embodiments, the state logic 304 may also confirm that the active address was properly stored in the active address register 322. In some embodiments, the device 300 may respond to the address set message with an acknowledgement message bit or response sent over the bus.In some embodiments, state logic 304 may additionally compare the incoming address for the active address with the default address to verify that the active address is no longer set to the same address as the default address, which would cause a conflict with other devices still using the default address. If the incoming address differs from the default address, state logic 304 may store the incoming address in the active address register as the active address and set the configuration check value to indicate that the configuration of the active address was successfully completed. The configuration check value may be verified, for example, by a master device, a control circuit, a programming device, or the like, by sending a read command to device 300 to return the value of configuration check register 326.

[0023] In an example where device 300 is a voltage driver configured to use an I2C bus, registers 320, 322, 324, and 326 may include identifiers that identify the respective register, which may be used as an identifier in a message or command sent to device 300 over the bus. The default address may be a default I2C address that may be overwritten or written over by a user. Writing over the default address with an active address may be mandatory in implementations where there are multiple slaves with the same default address. Device 300 has a default address hard-coded in default address register 320 at boot time, which may be denoted by I2CHWADD and which may be hidden from the user.For initial access to the active address register 322, which may be labeled I2CADD, the user uses the default address of the device 300 to address messages to the device and uses the first and second pins 316 and 318 as chip select pins. The first pin 316 may be a gate driver control pin labeled PWM IN, and the second pin 318 may be a ready indicator pin labeled RDYC. PWM IN can be functionally used to turn the device output ON and OFF during normal operation when PWM IN is not being used as a chip select pin. RDYC is used during normal operation to indicate when the chip is ready. RDYC is normally pulled down internally and can be pulled down externally when used as a chip select.

[0024] To access pins 316 and 318, an external device such as a control circuit or the like pulls PWM IN high and RDYC low to select the target device. At this point, the address of the slave device is the default address in the I2CHWADD register. The user configures the I2CADD register by sending an address set command over the bus that identifies the selected slave device by the default address. The address set command may include a command such as a write bit set in the message, an identifier of the target memory to be written to, such as the I2CADD identifier of the active address register 322, and a value to be stored as the active address.The state logic 304 performs an internal check to ensure that the new address stored in I2CADD is not equal to the original default address stored in I2CHWADD.

[0025] After the I2CADD register has been written, state logic 304 sets the configuration check value by setting the configuration check register, which may be labeled I2CCFGOK, to one to indicate configuration completion and lock access to the I2CADD register to prevent inadvertent changes. State logic 304 may also send an acknowledgement message or respond with an acknowledge bit on the bus if the I2ADD register was correctly written. If the active and preset addresses are the same, the I2CCFGOK value is not set and no acknowledgement is sent.

[0026] In some embodiments, the configuration check value may be overridden by sending a message to device 300 at any time by state logic 304 or the user to return to the default address or to reprogram the active address. In other embodiments, for example, when the active address is set by the manufacturer, the configuration check value may not be accessible to a user to prevent inadvertent resetting of the active address.

[0027] While the previous example was described in terms of an I2C bus interface, other bus interfaces that require an address may be used without deviating from the principles described herein.

[0028] Fig. 3B is a diagram illustrating a system 350 with a programmable, addressable slave gate driver 310, according to some embodiments. The system 350 includes a control circuit 104 including address logic 204 and a master device 202 connected to a bus 102. A gate driver 310, which is a slave device with programmable addressing circuitry, is connected to the bus 102. In some embodiments, the gate driver 310 is connected by an output connection 334 to a control port of a transistor 336 controlled or driven by the gate driver 310. A load 338 may be connected to a conduction path of the transistor 336. The system 350 may include one or more branches of the slave devices 106B connected to the bus, and the control circuit 104 may control the gate driver 310 and the second slave device 106B via the bus 102.In addition, the second slave device 106B and the gate driver may initially have the same default address, and the control circuit may assign or set active or group addresses to one or both of the second slave device 106B and the gate driver 310.

[0029] In some embodiments, gate driver 310 can be used to control an electrical signal flowing through transistor 336 to load 338. For example, in some embodiments, load 338 is an electric motor, a light-emitting diode (LED), a display, a transmitter, or other electrical circuit or device. Transistor 336 controls a power signal to the load and, in some embodiments, is capable of handling a higher voltage or current than gate driver 310. In some embodiments, transistor 336 is an NPN bipolar junction transistor (BJT), but it can also be one or more metal-oxide field-effect transistors (MOSFETs), fin-type field-effect transistors (finFETs), junction field-effect transistors (JFETs), insulated-gate bipolar transistors (IGBTs), or electrically controllable switching devices.

[0030] Gate driver 310 is connected to the bus by data lines 328A and 328B, and it is connected to the control circuitry by one or more chip select lines 330 and 332. In embodiments where the bus implements the I2C protocol, data lines 328A and 328B may be connected to SDA and SCL ports or pins of the gate driver, and they may be used to send data to gate driver 310, to assign an address to gate driver 310, or to control the operation of gate driver 310.

[0031] For example, the gate driver may be a pulse-width modulation driver that can be used to control a power transistor for an electric motor. Gate driver 310 may receive address assignment information via bus data lines 328A and 328B upon power-up, as well as a normal communication message or commands after addressing is assigned. Chip lines 330 and 332 may be used to indicate to gate driver 310 that the control circuitry is about to set an active address or group address for gate driver 310. After the address is set and confirmed, the pins to which chip select lines 330 and 332 are connected are used for additional functionality.

[0032] In one embodiment, gate driver 310 may also receive signals from control circuit 104 indicating a frequency or duty cycle for a pulse signal at transistor 336. Gate driver 310 may then process the incoming messages and provide a signal to the control port of transistor 336 at output connection 334. In another embodiment, chip select pins may receive a signal via chip select lines 330 and 332 indicating when to turn transistor 336 on or off to gate driver 310. The parameters for controlling or operating transistor 336 may be set by a device parameter message over the bus to gate driver 310.The setup parameter message may contain information or parameters that specify how gate driver 310 should operate transistor 336, but it does not necessarily control when gate driver 310 addresses transistor 336. For example, gate driver 310 may receive a setup parameter message via bus 102 instructing the gate driver to control transistor 336 to control how the transistor gate is controlled, for example, by describing the rate of change of the voltage across the transistor (dV / dt) or the rate of change of the current flowing through the transistor (di / dt). Control circuit 104 may then provide a signal on one or more of chip select lines 330 and 332 that causes gate driver 310 to drive, control, or turn on transistor 336 and operate transistor 336 according to the parameters in the setup parameter message.

[0033] In an embodiment where the transistor is a BJT, the signal sent from the gate driver 310 over the output connection 334 controls a base current of the transistor 336, which in turn controls the current flowing to the load 338. Changing the frequency or duty cycle of the signal from the transistor 336 to the load allows, for example, the speed or power of the load 338 to be controlled.

[0034] Fig. 4 is a flowchart illustrating a method 400 for programming an address on a slave device, according to some embodiments. The method may be performed using programming circuitry, such as a device programmer, a system in which the slave device resides, or any other system for programming a slave device. In block 402, the programming circuitry applies the chip select pins to the target slave device by sending signals to the chip select pins on lines separate from the bus. In block 404, the programming circuitry sets an active or group address by sending a message on the bus to the target slave device while the chip select pins are enabled.In some embodiments, the message includes the default address of the target slave device, a command to set the active address, and a data value representing the active address. The state logic then stores the active address. In some embodiments, the programming circuit may then, at block 406, set the configuration check bit or register by sending a second message to the target slave device. The second message includes the default address of the target slave device, which is still used for the second message because the configuration check value is not yet set. The second message also includes a command to set the configuration check bit and, in some embodiments, includes the value to which the configuration check bit is set. In other embodiments, the device itself may set the configuration check bit.Additionally, in some embodiments, the programming circuitry confirms that the active address is properly set at block 408. The programming circuitry may confirm the active address by examining a bit or message sent in response to the active or group address being set. In other embodiments, the programming circuitry may read the active address value stored in the active address register, send a read or write command to the target slave device using the active address, and check for a valid response. At block 410, the programming circuitry overrides the chip select pins by disabling the chip select signals to the chip select pins. The target slave device may then be used for normal operation, and at block 412, a user or system may communicate with the target slave device at the active or group address.In some embodiments, in block 414, the programming circuitry may additionally set or read the target's chip select pins during normal operation. During normal operation, the chip select pins have additional functionality beyond the chip select function, eliminating the need for dedicated address pins on the slave device.

[0035] Fig. 5 is a flowchart illustrating a method for a slave device to set a programmable address according to some embodiments. In block 502, the slave device detects that the chip select pins are being driven. In block 504, the slave device receives active or group address data on the bus. In some embodiments, the active or group address data is received in a first message specifying the default address, a command to set the active or group address, and a value identifying the active or group address to be stored in the relevant register. The slave device determines that a received message is intended for the slave device by determining that the chip select pins are being set and by determining that the destination address in the message is equal to the default address.In some embodiments, the slave device may additionally set the active address by checking the value of the configuration check bit or register. If the configuration check bit is set, the slave device may ignore the address setting message and avoid sending any acknowledgment that the command was executed. In block 506, the slave device compares the active or group address from the first message with the default address. If the active or group address and the default address differ, then in block 508 the slave device sets the active or group address to the address in the first message. Otherwise, the slave device inhibits processing of the command in the first message and avoids setting the active or group address and sending an acknowledgment message.While the setting of the active or group address in these embodiments is described as being performed in response to the active or group address in the first message being different from the default address, in other embodiments the active or group address from the first message may be stored in the relevant register and then compared with the default address and overwritten or ignored if the addresses match.

[0036] In some embodiments, at block 510, if the active or group address is successfully set, the configuration check register or bit is set. In some embodiments, the slave device sets the configuration check value in response to the slave device setting the active or group address or in response to receiving a message on the bus to set the configuration check value. Additionally, in some embodiments, at block 512, the slave device may confirm that the active or group address has been set, for example, by pulling down the bus lines to signal an acknowledgment that the set address command has been executed, by sending a message on the bus, or by another acknowledgment technique. After the active or group address is set and confirmed, the slave device resumes normal operation.In block 514, the slave device receives data or commands on the bus during normal operation in a message addressed using the set active or group address. Additionally, in some embodiments, the slave device may set or read the chip select pins during normal operation as part of the additional functionality.

[0037] Fig.6 is a diagram illustrating a method 600 for processing a message using a programmed address, according to some embodiments. After the active address or group address is set as described above, a slave device may use the method to process messages or commands using the active or group address stored on the slave device. The message includes at least a destination address indicating the specified bus device and also includes a payload that may include a command or a data value. In block 604, the slave device reads the configuration check value to determine whether the slave device should use a programmed active address or the preset default address. If the configuration check value is not set, then in block 608, the slave device compares the destination address from the message to the default address.If they match, the message was intended for the slave device and the slave device executes the command in block 610; otherwise, the command is ignored in block 612. If the configuration check value is set, the slave device uses the active or group address to process the incoming message. In block 606, the slave device compares the received destination address from the message with the value of the active address stored in the active address register. If the addresses match, the slave device executes the command in the message in block 610. If the destination address does not match the active address, the slave device checks for attempts to use the group address to process the message. In block 616, the slave device compares the slave device from the message with the value of the group address stored in the group address register.If the destination address matches the group address, the slave device executes the command from the message in block 610. If the destination address does not match the group address, the slave device 612 ignores the command in the message. Thus, the slave device uses the configuration check value to determine whether to use the default address or a programmable address. It then compares the address of the destination slave device from the message with the programmable addresses to determine whether the message is intended for the slave device and executes or ignores the command in the message accordingly.

[0038] An example device includes a bus communication circuit connected to a bus terminal, a first pin terminal, a memory having a first register with a first address stored therein and a second register, and a state logic circuit connected to the memory, the first pin terminal, and the bus communication circuit. The state logic circuit includes circuitry that detects a chip select signal on the first pin terminal and, while the chip select signal is asserted, receives a first message via the bus communication circuit. The state logic circuit further includes circuitry that determines that the first message indicates an address set command and, in response to a destination address in the first message matching the first address, stores an address value in the first message as a second address in the second register.The state logic circuit further includes circuitry that processes a second message received by the bus communication circuit in response to a destination address of the second message matching the second address.

[0039] In one embodiment, the state logic circuit further includes circuitry with additional functionality that, during normal operation, performs at least one of: supplying a signal to the first pin terminal, or detecting a function signal different from the chip select signal at the first pin terminal and performing a function associated with the function signal. In one embodiment, the circuitry that stores the address value in the first message as the second address in the second register stores the address value in the first message as the second address in the second register in response to the state logic circuit determining that the address value is different from the first address.In one embodiment, the state logic circuit further comprises circuitry that provides an acknowledgment to the bus terminal via the bus communication circuitry in response to the state logic circuitry successfully storing the address value as the second address in the second register. In one embodiment, the state logic circuitry that processes the second message includes circuitry that processes the second message received through the bus communication interface in response to the destination address of the second message matching the second address, and without considering the first address.

[0040] An example method includes applying a chip select signal to a chip select pin of a first slave device connected to a bus, wherein the chip select signal is sent to the chip select pin off-bus, and setting a first address of the first slave device by sending a first message on the bus to the first slave device while the chip select signal is asserted. The first message includes a default address of the first slave device, a command to set the first address, and a data value representing the first address. The example method further includes sending a second message to the first slave device over the bus after the chip select signal is deasserted, wherein the second message is addressed using the first address.In one embodiment, the first address is an active address, and the active address of the first slave device is different from an active address of one or more second slave devices connected to the bus. In one embodiment, the method further includes setting a second address of the first slave device by sending a third message on the bus to the first slave device while the chip select signal is asserted, the third message including the default address of the first slave device, a command to set the second address, and a data value representing the second address.The second address is a group address, and the group address of the first slave device is different from the active address of the first slave device and the active address of each of the one or more second slave devices, and the group address of the first slave device is different from the default address of the first slave device and the default address of each of the one or more second slave devices. The group address of the first slave device matches the group address of at least one of the second slave devices.In one embodiment, the method further includes receiving, from the first slave device via the bus, an acknowledgment that the command to set the second address has been completed in response to the second address being different from the default address of the first slave device and the active address of the first slave device, and further in response to the data value being successfully stored as the second address by the first slave device. In one embodiment, the method further includes receiving, from the first slave device via the bus, an acknowledgment that the command to set the first address has been completed in response to the first address being different from the default address of the first slave device and further in response to the data value being successfully stored as the first address by the first slave device.

[0041] An example method includes detecting, by a device having a bus terminal and a first pin terminal separate from the bus terminal, that a chip select signal is present at the first pin terminal, receiving, by the device on the bus terminal and while the chip select signal is present, a first message including a destination address, a command to set the first address on the device, and a data value representing the first address, and storing the data value as the first address in a first register of the device in response to the destination address of the first message matching a default address of the device.The method further includes processing, by the device, a second message received by a device during normal operation on the bus terminal in response to a destination address of the second message matching the first address.

[0042] In one embodiment, the method further includes performing at least one of the following during normal operation: supplying a signal to the first pin terminal, or detecting a function signal different from the chip select signal at the first pin terminal and performing a function associated with the function signal. In one embodiment, storing the data value as the first address in the first register is performed in response to the address value being different from the default address of the device. In one embodiment, the method further includes supplying an acknowledgment to the bus terminal in response to the data value being successfully stored as the first address in the first register.In one embodiment, the device is a gate driver having an output port connected to a control port of a transistor, and processing the second message received by the device on the bus terminal during normal operation in response to the destination address of the second message matching the first address includes sending a signal through the output port to the transistor and controlling a current through the transistor according to the second message.

[0043] An example method includes receiving, by a device coupled to the bus, a first message sent over a bus and having stored thereon a first programmable address different from a default address of the device, comparing a first destination address in the first message to the default address in response to a configuration check value not being set, and processing the first message in response to the first destination address matching the default address and the configuration check value not being set. The method further includes comparing the first destination address to the first programmable address in response to the configuration check value being set, and processing the first message in response to the first destination address matching the programmable first address and the configuration check value being set.In one embodiment, the method further includes comparing the first destination address to a second programmable address stored on the device in response to the first destination address not matching the programmable first address and the configuration check value not being set, processing the first notification in response to the first destination address matching the second programmable address and the configuration check value being set, and ignoring the first notification in response to the first destination address not matching the first programmable address, the first destination address not matching the second programmable address, and the configuration check value not being set. The second programmable address is a group address that matches a group address of another device connected to the bus.In one embodiment, the method further includes receiving, by the device, a second message sent over the bus and while a chip select signal is present at a pin of the device, the second message including a second destination address, a command to set the first programmable address on the device, and a data value representing the programmable first address, and saving the data value as the first programmable address in a first register of the device in response to the second destination address matching the default address. In one embodiment, the method further includes providing an acknowledgment over the bus in response to successfully storing the data value as the first programmable address.

[0044] An example system includes a bus, a plurality of slave devices connected to the bus, each of the plurality of slave devices having a default address and an input pin separate from the bus. Each of the plurality of slave devices is configured to receive messages over the bus. The example system further includes control circuitry connected to the bus and separately connected to the input pin of each of the plurality of slave devices by a line from a plurality of lines separate from the bus, the control circuitry configured to apply a signal to the line to a target slave device of the plurality of slave devices and, while the signal is applied, to send over the bus a first message indicating an address setting command using the default address of the target slave device.Each of the plurality of slave devices is further configured, when the signal is applied to the corresponding slave device, to store a value from the first message as the first address in response to a destination address of the first message matching the default address of the corresponding one of the plurality of slave devices.

[0045] In one embodiment, each of the plurality of slave devices is further configured to process a second message received from the control circuit via the bus in response to a destination address of the second message matching the first address. In one embodiment, the plurality of slave devices include a gate driver having an output connected to a control port of a transistor, the gate driver configured to control a current through the transistor according to the second message. In one embodiment, the first address is an active address, and the active addresses of each of the plurality of slave devices differ from each other and from the default address of each of the plurality of slave devices.In one embodiment, the control circuit is further configured to transmit, while the signal is present, a third message over the bus indicating an address setting command using the default address of the target slave device. Each of the plurality of slave devices is further configured, when the signal is present at the corresponding slave device, to store a value from the third message as a second address in response to a destination address of the third message matching the default address of the corresponding one of the plurality of slave devices.The second address is a group address, wherein the group address of each of the plurality of slave devices is different from the active address of each of the plurality of slave devices and from the default address of each of the plurality of slave devices, and wherein the group address of at least one of the plurality of slave devices matches the group address of at least one other slave device.

Claims

[1] Facility that features: a bus communication circuit (302) which is connected to a bus terminal (308); a first PIN terminal (312); a memory (306) comprising a first register (320) with a first address stored therein and a second register (322); a state logic circuit (304) which is connected to the memory (306), the first pin terminal and the bus communication circuit (302), wherein the state logic circuit (304) has a circuit technique configured to detect a chip selection signal at the first pin terminal and, while the chip selection signal is present, to receive an initial message via the bus communication circuit (302), wherein the state logic circuit (304) further comprises a circuit technique configured to determine that the first message specifies an address setting instruction and, in response to the fact that a destination address in the first message matches the first address, to store an address value in the first message as the second address in the second register (322), and wherein the state logic circuit (304) further comprises a circuit technique configured to process a second message received by the bus communication circuit (302) in response to the fact that a destination address of the second message matches the second address. [2] Device according to claim 1, wherein the state logic circuit (304) further comprises a circuit technology with additional functionality, which is configured to supply a signal to the first pin terminal (312) during normal operation and / or to detect a function signal different from the chip selection signal at the first pin terminal and to execute a function belonging to the function signal. [3] Device according to claim 1 or 2, wherein the circuitry which stores the address value in the first message as the second address in the second register, in response to the state logic circuit determining that the address value differs from the first address, stores the address value in the first message as the second address in the second register. [4] Device according to claim 3, wherein the state logic circuit (304) further comprises a circuit technology configured to provide confirmation to the bus terminal (308) via the bus communication circuit (302) in response to the fact that the state logic circuit successfully stores the address value as the second address in the second register (322). [5] Device according to one of the preceding claims, wherein the state logic circuit (304) comprises a circuit technology configured to process the second message received via the bus communication circuit (302) in response to the fact that the destination address of the second message matches the second address and without regard to the first address. [6] Method which features: Applying a chip selection signal to a chip selection pin of a first slave device (106A) connected to a bus (102), wherein the chip selection signal is sent to the chip selection pin outside the bus (102); Setting a first address of the first slave device (106A) by sending a first message on the bus (102) to the first slave device (106A) while the chip selection signal is present, wherein the first message contains a default address of the first slave device (106A), a command to set the first address, and a data value representing the first address; and Sending a second message over the bus (102) to the first slave device (106A) after the chip selection signal is removed, the second message being addressed using the first address. [7] Method according to claim 6, wherein the first address is an active address and wherein the active address of the first slave device (106A) differs from an active address of one or more second slave devices (106B) connected to the bus (102). [8] The method according to claim 7, further comprising: Setting a second address of the first slave device (106A) by sending a third message on the bus (102) to the first slave device (106A) while the chip selection signal is present, wherein the third message contains the default address of the first slave device (106A), a command to set the second address and a data value representing the second address; wherein the second address is a group address and wherein the group address of the first slave device (106A) differs from the active address of the first slave device (106A) and from the active address of each of the one or more second slave devices (106B), and wherein the group address of the first slave device (106A) differs from the default address of the first slave device (106A) and the default address of each of the one or more second slave devices (106B); and where the group address of the first slave device (106A) matches a group address of at least one of the second slave devices (106B). [9] Method according to claim 8, further comprising receiving confirmation that the command to set the second address has been executed from the first slave device (106A) via the bus (102) in response to the fact that the second address differs from the default address of the first slave device (106A) and the active address of the first slave device (106A) and further in response to the fact that the data value has been successfully stored as the second address by the first slave device (106A). [10] Method according to any one of claims 6 to 9, further comprising receiving confirmation that the command to set the first address has been executed from the first slave device (106A) via the bus (102) in response to the fact that the first address differs from the default address of the first slave device (106A) and further in response to the fact that the data value has been successfully stored as the first address by the first slave device (106A). [11] Method which features: Detect, by means of a device comprising a bus terminal (308) and a first pin terminal separate from the bus terminal (308), that a chip selection signal is present at the first pin terminal; Receiving an initial message by the device at the bus terminal (308) while the chip selection signal is present, wherein the initial message contains a destination address, a command to set an initial address on the device, and a data value representing the initial address; Securing the data value as the first address in an initial register of the institution in response to the fact that the destination address of the initial communication matches a default address of the institution; and Processing by the facility a second message received by the facility at the bus terminal (308) during normal operation in response to the fact that a destination address of the second message matches the first address. [12] Method according to claim 11, further comprising performing the following normal operation: supplying a first signal to the first pin terminal, or detecting a function signal different from the chip selection signal at the first pin terminal and performing a function associated with the function signal. [13] Method according to claim 11 or 12, wherein the storage of the data value as the first address in the first register is performed in response to the fact that the address value differs from the default address of the device. [14] Method according to claim 13, further comprising providing an acknowledgment at the bus terminal (308) in response to the successful storage of the data value as the first address in the first register. [15] Method according to any one of claims 11 to 14, wherein the device is a gate driver (310) having an output port connected to a control port of a transistor (336); and wherein the processing of the second message received by the device at the bus terminal (308) during normal operation in response to the fact that the destination address of the second message matches the first address comprises sending a signal through the output port to the transistor (336) and controlling a current through the transistor (336) according to the second message. [16] Method which features: Receiving a first message sent via a bus (102) by a device connected to the bus (102) and having stored on it a first programmable address that differs from a default address of the device; Comparing an initial target address in the first message with the default address in response to a configuration check value not being set; Processing the first message in response to the fact that the first destination address matches the default address and that the configuration check value is not set; Comparing the first target address with the first programmable address in response to the configuration check value being set; and Processing the first message in response to the first destination address matching the programmable first address and the configuration check value being set. [17] The method of claim 16, further comprising: Comparing the first destination address with a second programmable address stored on the device in response to the fact that the first destination address does not match the programmable first address and the configuration check value is set; Processing the first message in response to the fact that the first destination address matches the second programmable address and the configuration check value is set; and Ignoring the first message in response to the fact that the first target value does not match the first programmable address, the first target address does not match the second programmable address, and the configuration check value is set; where the second programmable address is a group address that matches a group address of another device connected to the bus (102). [18] Method according to claim 16 or 17, further comprising: Receiving a second message sent via bus (102) by the device while a chip select signal is applied to a pin of the device, the second message containing a second destination address, a command to set the first programmable address on the device, and a data value representing the programmable first address; and Storing the data value as the first programmable address in a first register of the device in response to the second target address matching the default address. [19] Method according to claim 18, further comprising providing an acknowledgment via the bus (102) in response to the successful storage of the data value as the first programmable address. [20] System that features: a bus (102); several slave devices (106) connected to the bus (102), each of the several slave devices (106) having a default address and an input pin separate from the bus (102), each of the several slave devices (106) being configured to receive messages via the bus (102); and a control circuit (104) which is connected to the bus (102) and which is separately connected to the input pin of each of the several slave devices (106) by one of several lines (206, 208, 330, 332) separate from the bus (102), wherein the control circuit (104) is configured to apply a signal to a target slave device (106) of the several slave devices to the line (206, 208, 330, 332) and, while the signal is present, to send a first message via the bus (102) which specifies an address setting command, using the default address of the target slave device (106); wherein each of the multiple slave devices (106) is further configured to store a value from the first message as the first address when the signal is present at the corresponding slave device, in response to the fact that a destination address of the first message matches the default address of the relevant multiple slave device. [21] System according to claim 20, wherein each of the multiple slave devices (106) is further configured to process a second message received from the control circuit (104) via the bus (102) in response to the fact that a destination address of the second message matches the first address. [22] System according to claim 21, wherein the multiple slave devices include a gate driver (310) having an output connected to a control port of a transistor (336), wherein the gate driver (310) is configured to control a current through the transistor (336) according to the second communication. [23] System according to one of claims 20 to 22, wherein the first address is an active address and wherein the active address of each of the multiple slave devices differs from each other and from the default address of each of the multiple slave devices. [24] System according to claim 23, wherein the control circuit (104) is further configured to send, while the signal is present, a third message specifying an address setting command via the bus (102) using the default address of the target slave device (106); wherein each of the multiple slave devices (106) is further configured, when the signal is present at the corresponding slave device, in response to the fact that a destination address of the third message matches the default address of the corresponding one of multiple slave devices, to store a value from the third message as a second address; and wherein the second address is a group address and wherein the group address of each of the multiple slave devices (106) differs from the active address of each of the multiple slave devices and from the default address of each of the multiple slave devices, and wherein the group address of at least one of the multiple slave devices is the same as the group address of at least one other slave device.

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