DISPLAY PANEL AND ELECTROLUMINESCENT DISPLAY USING THE SAME

Abstract

A display panel (100) configured to display frame data during a frame period including an active period (AT) and a blanking interval (VB), and modulate data of an input image based on a result of sampling the electrical properties of pixels in the blanking interval (VB), the display panel (100) comprising: a subpixel (101) comprising a light-emitting element (EL) and a driving element (DT) for driving the light-emitting element (EL), wherein the light-emitting element (EL) emits light by a current in the driving element (DT) during a driving phase (DRV); and a power circuit (30) configured to provide a first drive voltage (VDD1) to the subpixels (101) during the drive phase (DRV) in the active period (AT) and the blanking interval (VB) and to provide a second drive voltage (VDD2) to the subpixels (101) during a data write phase (WRA) of the active period and during the reset, scan and data write phases (INI, SEN, WRV) of the blanking interval (VB).

Description

Field of the InventionThe present invention relates to a display panel that can compensate for variations in the electrical characteristics of the driving elements in individual pixels in real time, and an electroluminescence display using the same.Prior ArtElectroluminescent displays can be broadly classified into inorganic light-emitting displays and organic light-emitting displays depending on the material of an emission layer. Among them, an active matrix organic light emitting display includes organic light emitting diodes (hereinafter, "OLED"), which are typically light emitting diodes that emit light by themselves, and has advantages of a fast response time, a high luminous efficiency, a high brightness, and a large viewing angle.Each pixel of an organic light emitting display includes an OLED, a capacitor, a driving element, a switching element, etc. The driving element and the switching element may be implemented by metal oxide semiconductor field effect transistors (MOSFETs) thin film transistors (TFTs). The driving element adjusts the brightness of the pixel according to data of an image by regulating the current in the OLED by the gate-source voltage that varies with the grayscale value of the image data.When the transistor used as the driving element operates in a saturation region, a driving current Ids flowing between the drain and the source of the driving element is expressed as: where μ is the electron mobility, C is the capacitance of a gate insulating film, W is the channel width of the driving element, and L is the channel length of the driving element. Vg is the gate-source voltage of the driving element, and Vth is the threshold voltage (or critical voltage) of the driving element. The gate-source voltage Vgs of the driving TFT is programmed (or set) according to a data voltage. The drain-source current Ids of the driving element flowing to the OLED is determined according to the programmed gate-source voltage Vgs.Ideally, the electrical characteristics of the driving element, such as the threshold voltage Vth, the electron mobility μ of the driving TFT, and the threshold voltage of the OLED, should be the same for each pixel because they serve as a factor for determining the current in the OLED. However, the electrical characteristics may vary between pixels due to various causes including process variation, temporal variation, etc. Such variations in the electrical characteristics of pixels may cause a decrease in image quality and a decrease in lifetime.Internal compensation and external compensation may be used to compensate for variations in the electrical properties of the drive element. In the method of internal compensation, variations in the electrical characteristics of the driving element for each pixel can be compensated in real time. In the method of external compensation, deviations in the electrical characteristics of the driving elements of pixels are compensated by sampling the driving voltage of each pixel and modulating data of an input image by an external circuit based on the sampled voltage.However, the conventional internal and external compensation methods have a problem of an IR drop effect. The IR drop causes a drop in the driving voltage of a pixel which occurs when a current I flows through a resistor R. This voltage drop varies with the position on the screen. Due to this, there may be differences in brightness between pixels depending on the position on the screen of the display panel.US 2017 / 0162114 A1 describes an organic EL display device comprising: a plurality of pixels each comprising an organic EL element emitting light according to a pixel current provided; a driving transistor supplying the pixel current to the organic EL element; and a holding capacitor connected between gate and source of the driving transistor; A control unit that applies, in a display state in which the organic EL element is caused to emit light in a part of the plurality of pixels and a voltage of the holding capacitor is changed to a threshold voltage of the driving transistor in another part of the plurality of pixels, a drain voltage of the driving transistor of a pixel in the other part regardless of the drain voltage of the driving transistor of a pixel in the one part.DE 102015210399 A1 relates to pixel circuits for amoled displays. A controller provides a program voltage that is a calibrated voltage for a known target current, reads the actual current flowing through the driver transistor to a monitor line, turns off the light emitting device during modification of the calibrated voltage to substantially match the current provided by the driver transistor to the target current, modifies the calibrated voltage to substantially match the current provided by the driver transistor to the target current, and determines a current corresponding to the modified calibrated voltage based on predetermined current-voltage characteristics of the driver transistor.US 2012 / 0293479 A1 describes a display device comprising a pixel comprising an organic light emitting diode (OLED), a drive transistor connected to the drive voltage and supplying a drive current to the OLED, a compensation capacitor connected to the gate electrode of the drive transistor, and a first storage capacitor and a second storage capacitor electrically connected to or cut off from the compensation capacitor, and a drive method thereof.US 2015 / 0294623 A1 describes a display unit comprising: a unit pixel; a switch configured to perform ON-OFF control between a second terminal and a third terminal based on a pulse signal applied to a first terminal, wherein the second terminal is supplied with a DC signal and the third terminal is connected to the unit pixel; and a nonlinear element inserted between the first terminal and the third terminal.SUMMARY OF THE INVENTIONThe present invention has been made in an effort to provide a display panel that can compensate for variations in the electrical characteristics of the driving elements in individual pixels and minimize the effect of a voltage drop on the current applied to the pixels.The objects of the present invention are achieved by the features of the independent claims. According to an embodiment, there is provided a display panel that displays frame data during a frame period including an active period and a blanking interval and modulates data of an input image based on a result of sensing the electrical characteristics of pixels in the blanking interval, the display panel preferably comprising: a subpixel including a light emitting element and a driving element for driving the light emitting element, the light emitting element emitting light by a current in the driving element during a driving phase; and a current circuit configured to provide a first driving voltage to the subpixel during the driving phase in the active period and the blanking interval and provide a second driving voltage to the subpixel during a data writing phase of the active period and during the reset, sensing and data writing phase of the blanking interval.The first drive voltage may be provided to a first power line and the second drive voltage may be provided to a second power line that is separate from the first power line.The subpixel may further include a capacitor connected to the driving element, wherein the first driving voltage is provided to a first electrode of the capacitor and a first electrode of the driving element during the driving phase of the active period and the blanking interval, and the second driving voltage is provided to the first electrode of the capacitor during the reset, sensing, and data writing phase of the blanking interval. The second electrode of the capacitor of the subpixel may be connected to the gate of the driving element via a first node, the first electrode of the driving element may be connected to the first electrode of the capacitor, and the second electrode of the driving element may be connected to a second node.The display panel may further include a first power line to which the first driving voltage may be provided and which may be commonly connected to subpixels of all pixel rows, and a plurality of second power lines to which the second driving voltage may be provided and which may be separated between the pixel rows.The power circuit may include a first pixel drive voltage switching element that may be turned on in the drive phase in response to an emission switching signal defining the duration of the drive phase and may connect the first power line to the subpixel, and a second pixel drive voltage switching element that may be turned on in response to a first scan signal defining the duration of the data write phase of the active period and the duration of the reset, scan, and data write phase of the blanking interval and may connect the first power line to the subpixel.The subpixel may include a first switching element that may be turned on in response to a second scan signal defining the duration of the scan phase and may connect the first node to the second node, a second switching element that may be turned on in response to the first scan signal and may connect a data line to the first node, a third switching element that may be turned on in response to the emission scan signal and may connect the second node to a third node, and a fourth switching element that may be turned on in response to the first scan signal and may connect a third power line to which a predetermined reset voltage is applied to the third node. The third node may be connected to the third switching element, the fourth switching element, and an anode of the light emitting element, and a data voltage of the input image may be provided to the data line during the data writing phase, and the reset voltage may be provided to the data line during the reset phase.In the data writing phase of the blanking interval and the data driving phase of the previous active period, the same previous frame data may be written to a subpixel to be scanned in the blanking interval, and in the data writing phase of the next active period, current frame data may be written to the scanned subpixel.According to another embodiment, an electroluminescence display is provided, which includes a display panel according to the embodiments of the disclosure.The display panel may include first and second sub-pixels that may be connected to different data lines and may be commonly connected to first to third gate lines, a data driver configured to provide a data voltage of the input image to the data lines during the data writing phase of the active period and the data writing phase of the blanking interval and may provide a predetermined reset voltage to the data lines during the reset phase, and a gate driver configured to provide the first gate line with a first scan signal that defines the duration of the data writing phase of the active period and the duration of the reset, scan, and data writing phase of the blanking interval, provide the second gate line with a second scan signal that defines the duration of the scanning phase, and supplying the third gate line with an EM signal defining the duration of the driving phase.The electroluminescence display may include a circuit that may output the first driving voltage and the second driving voltage, the circuit may include a first output terminal that may output the first driving voltage and a second output terminal that may output the second driving voltage, the first and second driving voltages may be output from the circuit at the same voltage level.The electroluminescence display may include a circuit that may output the first driving voltage and the second driving voltage, the circuit may output a single driving voltage to a single wire through a single output channel, the single wire may be divided into first and second branch wires, the first driving voltage may be provided to the sub-pixels through the first branch wire, and the second driving voltage may be provided to the sub-pixels through the second branch wire.The electroluminescence display may include a first power line to which the first driving voltage may be provided and which may be commonly connected to subpixels of all pixel lines, and a plurality of second power lines to which the second driving voltage may be provided and which may be separated between the pixel lines and connected to the subpixels, wherein when the second driving voltage is provided by pixel driving voltage lines to subpixels arranged in a single pixel line, the first driving voltage may be provided to the subpixels in the pixel lines other than the single pixel line.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings: FIG. 1 is a block diagram showing an electroluminescence display according to an exemplary embodiment of the present invention; FIG. 2 is a circuit diagram of an external compensation circuit according to an exemplary embodiment of the present invention; FIG. 3 is a view showing a part of a pixel array; FIG. 4 is a view showing a voltage drop caused by an IR drop; FIG. 5 is a view showing voltages applied to two ends of the capacitor of a subpixel; FIGS. 6 to 8 are enlarged views of a part of a LOG (Line On Glass, i.e., a wire formed on a glass substrate) line and a second VDD line on a part of the display panel; FIGS. 9 and 10 are views showing a voltage drop caused by an IR drop in a VDD line; FIGS. 11A and 11B are views illustrating a VDD path between a circuit and a display panel according to an exemplary embodiment of the present invention; FIG. 12 is a view showing first and second VDD lines according to an exemplary embodiment of the present invention; FIG. 13 is a view showing an example in which pixels in all pixel lines are driven by a common VDD; FIG. 14 is a view showing an example in which a VDD applied to pixel lines in a scan phase and a VDD applied to pixel lines in a drive phase are separated; FIG. 15 is a circuit diagram showing a VDD circuit and a pixel circuit according to an exemplary embodiment of the present invention; FIG. 16 is a waveform diagram showing a sub-pixel sampling phase in a vertical blanking interval; FIG. 17 is a view showing an example in which previous frame data is rewritten to a subpixel in the vertical blanking interval; FIG. 18 is a waveform diagram showing a subpixel data writing phase in an active period; FIG. 19 is a circuit diagram showing the data writing phase and driving phase of the active period; FIG. 20 is a view showing a VDD applied to a pixel circuit in the data writing phase and the driving phase, and the voltage of the storage capacitor; FIG. 21 is a circuit diagram showing how a pixel circuit functions in the reset phase and the sampling phase of the vertical blanking interval; and FIG. 22 is a view showing the active period and the vertical blanking interval.DETAILED DESCRIPTIONVarious aspects and features of the present invention and methods for achieving the same may be more fully understood by reference to the following detailed descriptions of exemplary embodiments and the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art, and the present invention is defined by the appended claims.The shapes, sizes, proportions, angles, numbers, etc. shown in the figures for describing the exemplary embodiments of the present invention are merely examples and are not limited to those shown in the figures. Throughout the specification, like reference numerals designate like elements. In describing the present invention, detailed descriptions of related well-known technologies will be omitted to avoid unnecessary obscuring the present invention.When the Begriffe,umfassen',,aufweisen',,bestehen out' and the like are used, other parts may be added as long as the term "only" is not used. The singular forms may also be interpreted as the plural forms unless expressly stated otherwise.The elements may be interpreted to include a range of errors, even if not explicitly stated.When the positional relationship between two parts is described using the Begriffe,auf',,über',,unter',,neben' and the like, one or more parts may be positioned between the two parts as long as the term "immediate" or "immediate" is not used.It will be understood that although the terms first / r / s, second / r / s, etc. may be used to describe various elements, the functions or structures of these elements should not be limited by these terms.The features of various exemplary embodiments of the present invention may be either partially or fully coupled or combined with each other, and may interact or cooperate in various ways. The example embodiments may be performed independently or in conjunction with each other.In an electroluminescence display of the present invention, a pixel circuit may include one or more of an n-type TFT (NMOS) and a p-type TFT (PMOS). A TFT is a three-electrode device having a gate, source and drain. The source (source) is an electrode that provides carriers to the transistor. The carriers in the TFT flow from the source. The drain (drain) is an electrode at which the carriers leave the TFT. That is, the carriers in the TFT flow from the source to the drain. In the case of the n-type TFT, the carriers are electrons, and thus the source voltage is lower than the drain voltage, so that the electrons flow from the source to the drain. In the n-type TFT, current flows from the drain to the source. In the case of the p-type TFT (PMOS), the carriers are holes, and thus the source voltage is higher than the drain voltage, so that the holes flow from the source to the drain. In the p-type TFT, since the holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of the TFT are not fixed in position. For example, the source and drain are interchangeable depending on the applied voltage. Accordingly, the invention should not be limited by the source and drain of the TFT. In the following description, the source and drain of the TFT are referred to as first and second electrodes.A gate signal applied to the pixel circuit oscillates between a gate-on voltage and a gate-off voltage. The gate-on voltage is set higher than the threshold voltage of the TFT, and the gate-off voltage is set lower than the threshold voltage of the TFT. The TFT turns on in response to the gate-on voltage and turns off in response to the gate-off voltage. In the n-type TFT, the gate-on voltage may be a gate high voltage VGH (gate high voltage) and the gate-off voltage may be a gate low voltage VGL (gate low voltage). In the p-type TFT, the gate-on voltage may be a gate low voltage VGL, and the gate-off voltage may be a gate high voltage VGH.Hereinafter, various exemplary embodiments of the present invention will be described in detail with reference to the drawings. The following exemplary embodiments will be described with reference to an organic light emitting display including an organic light emitting material. However, the technical idea of the present invention is not limited to the organic light emitting display, but may also be applied to an inorganic light emitting display including an inorganic light emitting material. An example of the inorganic light emitting display may include, but is not limited to, a quantum dot display.FIG. 1 is a block diagram showing an electroluminescence display according to an exemplary embodiment of the present invention. FIG. 2 is a circuit diagram of an external compensation circuit according to an exemplary embodiment of the present invention. FIG. 3 is a view showing a part of a pixel array.Referring to FIGS. 1 and 2, an electroluminescence display according to an exemplary embodiment of the present invention includes a display panel 100 and a display panel driving circuit.The display panel 100 includes an active area AA (Active Area) that displays an input image on the screen. A pixel array is disposed in the active area AA. The pixel array includes signal lines and pixels. The signal lines include data lines 102 and gate lines 104 intersecting the data lines 102. Current wires and electrodes for providing current, such as VDD, Vini, and VSS, to the pixels may be arranged in the pixel array. The pixels include pixels arranged in a matrix. In Fig. 3, LINE1 and LINE2 represent pixel lines. Pixel rows LINE1 and LINE2 each comprise a row of pixels in the pixel array sharing gate lines.Each pixel may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color display. Each pixel may further comprise a white subpixel. Each subpixel 101 includes a pixel circuit. The pixel circuit includes a light emitting element, a driving element, a plurality of switching elements, and a capacitor. The pixel circuit includes a compensation circuit capable of compensating deviations in the electrical characteristics of the driving elements in individual pixels in real time by using the switching elements. The driving element and the switching elements may be implemented by, but are not limited to, a PMOS TFT.The display panel 100 may further include a VDD line for providing a pixel driving voltage VDD (driving voltage) to the subpixels 101, Vini wiring for providing a reset voltage Vini (reset voltage) to the subpixels 101 for resetting the pixel circuit, VSS wiring, and VSS electrodes for providing a low potential supply voltage VSS (supply voltage) to the subpixels 101, VGH wiring to which a VGH is applied, VGL wiring to which a VGL is applied, and so forth. The VDD line is divided into a first VDD line 31 to which a VDD 1 is applied and a second VDD line 32 to which a VDD 2 is applied.The supply voltages such as VDD, Vini, and VSS are generated by a circuit 150. The circuit 150 generates current required to drive the pixels by using a DC-DC converter, a charge pump, a regulator, etc. The circuit 150 may be implemented as, but is not limited to, a PMIC (Power Module Integrated Circuit). The supply voltages may be set to, but not limited to, VDD= VDD1= VDD2= 4.5 V, VSS= -2.5 V, Vini= -3.5 V, VGH= 7.0 V, and VGL= -5.5 V. The supply voltages may vary depending on the driving characteristics or the model of the display panel 100.Touch sensors (not shown) may be placed on the screen of the display panel 100. A touch input may be detected using the touch sensors or by the pixels. The touch sensors may be implemented as on-cell or add-on touch sensors placed on the screen of the display panel or in-cell touch sensors embedded in the pixel array.The display panel driving circuit includes a data driver 110, a gate driver 120, VDD circuits 30, etc. The display panel driving circuit may further include a demultiplexer 112 placed between the data driver 110 and the data lines 102.The display panel driving circuit writes data of an input image to the pixels of the display panel 100 under the control of a timing controller (TCON) 130. The display panel driving circuit may further include a touch sensor driver for driving the touch sensors. The touch sensor driver is omitted in FIG. 1. In a mobile device, the display panel drive circuit, the timing controller 130, and the circuit 150 may be integrated into a single integrated circuit.Adjacent sub-pixels 101 in the same pixel row are commonly connected to a VDD circuit 30. That is, adjacent sub-pixels share a single VDD circuit 30. The VDD circuit 30 provides VDD 1 to the subpixels 101 during a driving phase of an active period AT (active period) (see FIG. 22 ) and provides VDD 2 to the subpixels 101 during a data writing phase of the active period and during the reset and sampling phase of a vertical blanking interval VB (vertical blanking interval) (see FIG. 22 ).The active time period is the time when a frame of data is written to all pixels on the screen. The vertical blanking interval is a given period between an (N-1)-th active period and an N-th active period. During the vertical blanking interval, the next frame data (Nth frame data) is not received by the timing controller 130.The driving phase is the time when VDD 1 is supplied to the driving element and a current Ids generated by the gate-source voltage Vgs (gate-source voltage) of the driving element flows to the light emitting diode. In the driving phase, the light emitting element of the subpixel may emit light.The data write phase is the time when VDD 2 is provided to a first electrode of the storage capacitor Cst (storage capacitor) and a data voltage Vdata (data voltage) generated by the data driver 110 is applied to a second electrode of the storage capacitor Cst and a gate of the driving element DT (driving element).The sampling phase is associated within the vertical blanking interval. The reset phase for resetting the subpixels occurs before the sampling phase. In the sampling phase, the electrical properties of the subpixels, for example the threshold voltage of the drive elements, are detected.The display panel driving circuit writes data of the current frame to all the subpixels in each active period. The display panel driving circuit samples the electrical characteristics of the driving elements of the sub-pixels in a preset pixel line in the vertical blanking interval, and rewrites (N-1)th frame data, i.e., previous frame data, to the sampled sub-pixels. One or more pixel lines may be sampled in the vertical blanking interval and then other pixel lines may be sampled in the next vertical blanking interval.The display panel driving circuit may operate in a slow driving mode. In the slow drive mode, an input image is analyzed, and if the input image does not change for a preset period of time, power consumption of the display device is reduced. In the long drive mode, when a still image is present for more than a certain amount of time, the intervals at which data is written to the pixels are prolonged by a decrease in the repetition rate (or frame rate) of the pixels, thereby reducing power consumption. The slow drive mode is limited to the input of a still image. For example, when the display device operates in the standby mode or no user command or input image is input to the display panel driving circuit for more than a given amount of time, the display panel driving circuit may operate in the slow driving mode.The data driver 110 converts data signals (digital data) of an input image received for each frame from the timing controller 130 into analog data voltages by a digital-to-analog converter (DAC) 22. The timing controller 130 transmits compensation data modulated by a compensation part 131 to the data driver 110. Data voltages Vdata output from the data driver 110 are provided to the data lines 102 through the demultiplexer 112. The data driver 110 may include a sensing part 20 shown in FIG. 2.The demultiplexer 112 is placed between the data driver 110 and the data lines 102, and distributes the data voltages Vdata output from the data driver 110 to the data lines 102. Due to the demultiplexer 112, the number of output channels for the data driver 110 can be reduced to half the number of data lines.The gate driver 120 outputs gate signals to the gate lines 104 under the control of the timing controller 130. The gate driver 120 may sequentially provide the gate signals to the gate lines 104 by shifting the signals through a shift register. The gate signals include the scan signals SCANA( 1) to SCANB( 2) for selecting a row of pixels to which data is to be written and the emission switching signals (hereinafter, "EM signals") EM( 1) and EM( 2) defining the emission time of pixels charged with data voltages. In FIG. 3, SCANA( 1), SCANB( 1) and EM( 1) are gate signals provided to the subpixels 101 of the first pixel row LINE 1. SCANA( 2), SCANB( 2) and EM( 2) are gate signals provided to the subpixels 101 of the second pixel row LINE 2. The gate lines 104 include a first gate line 41 to which the first scan signals SCANA( 1) and SCANA( 2) are applied, a second gate line 42 to which SCANB( 1) and SCANB( 2) are applied, and a third gate line 43 to which the EM signals EM( 1) and EM( 2) are applied.The pixel circuits of the subpixels, the demultiplexer 112, the gate driver 120, and a current circuit 140 may be directly formed on a substrate of the display panel 100 using the same manufacturing process. The transistors of the pixel circuits, the demultiplexer 112, the gate driver 120, and the current circuit 140 may be implemented as NMOS or PMOS transistors or transistors of the same type.The timing controller 130 receives digital data of an input image and timing signals synchronized with the digital data from a host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The host system may be any one of a TV (television) system, a set-top box, a navigation system, a PC, a home Kino system, and a mobile device system.The timing controller 130 selects a compensation value based on a subpixel scan result received in the vertical blanking interval, and modulates the digital data of the input image with this compensation value and transmits it to the data driver 110. Accordingly, the data driver 110 converts the data modulated based on the subpixel scan result into data voltages by the DAC 22 and outputs it to the data lines 102.The timing controller 130 may control the operation timing of the display panel drivers 110, 112, 120, and 140 by multiplying the input frame frequency (Hz) by i times (i is a positive integer greater than 0). The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) system and 50 Hz in the PAL (Phase-Alternating Line) system. In the slow drive mode, the timing controller 130 may reduce the frame frequency to a frequency of 1 to 30 Hz to reduce the repetition rate of the pixels.The timing controller 130 controls the operation timing of the display panel driving circuit by generating a data timing control signal for controlling the data driver 110, a switching control signal for controlling the demultiplexer 112, and a gate timing control signal for controlling the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system. The gate timing control signal output from the timing controller 130 may be converted into gate-on voltage or gate-off voltage by a level shifter and provided to the gate driver 120. The level shifter converts the low voltage of the gate timing control signal into the gate low voltage VGL, and converts the high voltage of the gate timing control signal into the gate high voltage VGH.The gate driver 120 may be formed in a bezel area BZ (Bezel Area) outside the active area AA. The VDD circuits 30 may be formed in the enclosure area BZ or distributed within the active area AA.A look-up table is created before shipment of the product by sampling the electrical characteristics of each pixel and deriving a compensation value for compensating deviations in the electrical characteristics of the subpixels based on a sampling result. This compensation value may be divided into a compensation value (offset) for compensating the threshold voltage of the driving elements and a compensation value (gain) for compensating the mobility of the driving elements. A look-up table of compensation values is stored in memory 132. The memory 132 may be, but is not limited to, flash memory.When current is applied to the electroluminescence display, a compensation value is transferred from the memory 132 to the memory of the compensation part 131 of the timing controller 130. The memory of the compensation portion 131 may be, but is not limited to, DDR SDRAM (Double Data Rate Synchronous Dynamic RAM) or SDRAM.As shown in FIG. 2, the data driver 110 includes a DAC 22, a sensing part 20, a first switching element SW 1 disposed between an output terminal of the DAC 22 and a data line 102, a second switching element SW 2 for supplying the Vini to the data line 102, and a third switching element SW 3 disposed between the data line 102 and an input terminal of the sensing part 20. The switching elements SW 1, SW 2, and SW 3 may be turned on or off under the control of the timing controller 130.The first switching element SW 1 may be turned on in the active period and provide a data voltage Vdata output from the DAC 22 to the data line 102. The first switching element SW 1 remains turned off during the vertical blanking interval.The second switching element SW 2 provides the Vini to the data line 102 in the vertical blanking period reset phase. The third switching element SW3 is turned on in the vertical blanking period scanning phase to connect the data line 102 to the scanning part 20. The second and third switching elements SW 2 and SW 3 remain turned off during the active period.The sensing part 20 senses the electrical characteristics of the subpixels, e.g., the threshold voltage of the driving elements, in the vertical blanking interval in real time for each frame. The sampling part 20 converts a subpixel sampling result into digital data by an analog-to-digital converter (hereinafter, "ADC"), and transmits it to the compensation part 131. The sensing part 20 may be implemented as a well-known voltage sensing circuit or current sensing circuit.The compensation part 131 inputs a subpixel scan result received from the scanning part 20 to the look-up table, selects a compensation value based on the scan result, and modulates the input image data with the compensation value, and outputs compensated data. A compensation value for compensating the threshold voltage of the driving elements may be added to the input image data, and a compensation value for compensating the mobility of the driving elements may be multiplied with the input image data. The compensation data output from the compensation part 131 is transmitted to the data driver 110. Thus, the electroluminescence display according to the present invention may compensate for variations in the electrical characteristics of subpixels in real time by sampling the electrical characteristics of the subpixels in real time in the vertical blanking period for each frame and compensating the input image data based on the sampling result.An IR drop affecting pixels will be described in conjunction with Figs. 4 to 10.As shown in FIG. 4, the IR drop refers to a voltage drop that occurs when a current I flows through a resistor R. In FIG. 4, Vext is an external input voltage (External Input Voltage), and Vin is an actual input voltage (Actual Input Voltage) provided to a load. Vout is an output voltage (Output Voltage) that has crossed through the load. The actual input voltage Vin is Vin = Vext-IR.A pixel circuit includes a storage capacitor Cst that stores the gate-source voltage of the driving element. As shown in FIG. 5, a VDD is applied to the first electrode of the storage capacitor Cst, and VDD-Vgs= VDD-DATA-Vth is applied to the second electrode thereof. DATA is a voltage corresponding to a gray value of a pixel / gray value data in the input image. Vgs is the gate-source voltage of the driving element, and Vth is the threshold voltage of the driving element.FIGS. 6 to 8 are views showing a LOG line and a VDD line on a part of the display panel 100. In FIGS. 6 to 8, "D-IC" represents a mobile device driving integrated circuit (IC). A circuit 150, a timing controller 130, a data driver 110, etc. may be integrated with the drive IC D-IC.Referring to FIGS. 6 to 8, the VDD line in the display panel 100 includes the LOG line 70 receiving the VDD from the circuit 150 through a PCB (or FPCB), and the grid-like VDD line 72 connected to the LOG line 70. The resistance of the LOG line 70 is higher than that of the VDD line 72.The VDD line 72 includes the vertical wires 72 ashown in FIG. 7 and the horizontal wires 72 bshown in FIG. 8. The vertical wires 72 aand the horizontal wires 72 bintersecate with an insulating layer therebetween and are connected to each other via contact holes crossing the insulating layer at at least some of the intersections. In FIGS. 8 to 10, the contact holes may be formed at positions B, C, D and E.An input IR drop occurs through the resistance of the LOG line. The voltage VDD may vary due to the input IR drop because the LOG line has a high resistance. Provided that the current required to drive the pixels at position B, C, D and E is Ib, Ic, Id and Ie, respectively, the current Ia at position A in the LOG lines is Ib+Ic+Id+Ie. Thus, the voltage at position A is Va= VDD-(Ra*Ia)= VDD-{Ra*(Ib+Ic+Id+Ie)}. Here, the IR drop is Ra*(Ib+Ic+Id+Ie). Ra is the resistance of the LOG line at position A. The IR drop is a voltage that varies with the amount of current required for all pixels, and the input IR drop is steeper than the IR drop in the VDD line 72 because the IR drop is a voltage that varies with the amount of current required for all pixels.The IR drop in the VDD line 72 may be divided into a vertical IR drop occurring in the vertical wires 72 aand a horizontal IR drop occurring in the horizontal wires 72 b. The vertical IR drop is an IR drop occurring in the vertical wires 72 aas shown in FIG. 7. When analyzing the vertical drop in the VDD line 72 excluding the horizontal wires 72 b, the current flowing through position B is equal to the sum of the current Ib required at position B and the current Ic required at position C. The voltage Vb at position B is Vb = Va-{Rb*(Ib+Ic)}. Rb is the resistance at position B.The horizontal IR drop is an IR drop occurring in the horizontal wires 72 bas shown in FIG. 8. When analyzing the horizontal drop in the VDD line 72 excluding the vertical wires 72 a, the current flowing through position B is equal to the sum of the current Ib required at position B and the current Id required at position D. The voltage Vb at position B is Vb = Va-{Rb*(Ib+Id)}.In the electroluminescence display, the brightness of a pixel affected by an IR drop in VDD occurring at other pixels may vary. For example, as shown in FIG. 9, when all pixels on a white level are turned on, the voltage drop in the VDD applied to the turned-on pixel at position P 1 is steeper. In contrast, when some of the pixels are on but most pixels are off, the voltage drop in the VDD applied to the on pixels at position P 1 is relatively flatter.A constant current must flow through the driving elements of the pixels to the light emitting elements so that all pixels emit light with the same brightness at the same grayscale. In the case of a high PPI (pixel per inch) model, the resistance of the VDD line is higher and the IR drop becomes steeper as it proceeds to the lower positions P1 and P2 on the display panel 100, as shown in FIG. 10. The IR drop causes a voltage drop in the VDD applied to the driving elements and, depending on the position on the display panel, causes a change in electric current flowing through the light emitting elements, which may result in uneven brightness.When the VDD is applied to the top position PO on the display panel 100, the IR drop causes the VDD to drop to VDD-α at the center position P 1 and another drop to VDD-β at the bottom position P 2.In the electroluminescence display of the present invention, the VDD is divided into VDD=VDD1 for the driving phase and VDD=VDD2 for the sampling phase and data writing phase, and variations in the electrical characteristics of subpixels are compensated by external compensation. In the present invention, when data is written to the sub-pixels in the active period and the electrical characteristics of the sub-pixels are sampled in the vertical blanking interval, VDD(=VDD2) is applied to the sub-pixels. Accordingly, the electroluminescence display of the present invention prevents variations in the gate-source voltage Vgs of the driving elements of individual subpixels without the effect of an IR drop in the scan and data writing phase, and is capable of accurately sensing the electrical characteristics of the driving elements of individual pixels because no effect of an IR drop occurs in the scan phase. The electroluminescence display of the present invention, by compensating for the IR drop in the VDD line and compensating the input image data based on a subpixel scan result, can display images with uniform brightness over the entire screen without additional development of an algorithm or a compensation circuit for compensating for the IR drop.FIGS. 11A and 11B are views illustrating a VDD path between the circuit 150 and the display panel 100 according to an exemplary embodiment of the present invention.As shown in FIG. 11A, the circuit 150 of the present invention may output VDD 1 and VDD 2 through separate output channels and provide them to the display panel 100. VDD 1 is provided by a first output terminal CH 1 of the circuit 150 and provided to the first VDD line 132 on a PCB. The first VDD line 132 on the PCB is connected to the first VDD line 31 on the display panel 100. VDD 2 is provided by a second output terminal CH 2 of the circuit 150 and provided to the second VDD line 134 on the PCB. The second VDD line 134 on the PCB is connected to the second VDD line 32 on the display panel 100. Although VDD 1 and VDD 2 may be output from the circuit 150 at the same voltage level in the case of FIG. 11A, they may be output at different levels. The voltages VDD 1 and VDD 2 may be determined depending on the driving characteristics or the application of the display panel.As shown in FIG. 11B, the circuit 150 of the present invention may output VDD 1 and VDD 2 through a single channel and provide them to the display panel 100. The VDD output by the first output terminal CH 1 of the circuit 150 is provided to a single wire 50 on the PCB. The single wire 50 is divided into two branch wires 136 and 138. The VDD applied to the first branch wire 136 is provided to the first VDD line 31 on the display panel 100. VDD 2 applied to the second branch wire 138 is provided to the second VDD line 32 on the display panel 100.The single input wire 50 in FIG. 11B should be designed to have a minimum resistance. The current It flowing through the resistor Rt of the single input wire 50 is It=I1+I2. The voltage at node X is equal to (Vx)=Rt*It=Rt*(I1+I2). The current I 1 flowing through the first branch wire 136 may cause a change in the VDD 1 provided to the sub-pixels in the data write and scan phase. Due to this, the resistance Rt of the single input wire 50 should be set to be less than 1% of the resistances R 1 and R 2 of the branch wires 46 and 48 so as to suppress changes in the VDD 2 caused by the current I 1 through the branch wire I 1 to be less than 1%. However, the invention is not limited thereto.FIG. 12 is a view showing first and second VDD lines according to an exemplary embodiment of the present invention.Referring to FIG. 12, the first VDD line 31 is formed in a grid-like pattern on the pixel array in the active area AA in which images are displayed and connected to all the subpixels. The VDD circuit 30 connects the first VDD line 31 to which VDD 1 is applied in the driving phase to the sub-pixels. The VDD circuit 30 disconnects the second VDD line 32 from the sub-pixels in the driving phase.The second VDD line 32 includes a plurality of VDD lines 321 to 324 formed in individual pixel lines. The VDD lines 321 to 324 are separated between the pixel lines. In the data write and scan phase, the VDD circuit 30 connects the sub-pixels 101 in a first pixel row to a 2-1 VDD line 321 to which VDD2 is applied. The VDD circuit 30 connects the sub-pixels 101 in a second pixel row to a 2-2 VDD line 322 to which VDD 2 is applied. In the data writing and scanning phase, the VDD circuit 30 sequentially connects the second VDD lines 321 to 324 to individual pixel lines one after another. The VDD circuit 30 disconnects the first VDD line 31 from the sub-pixels operating in the data write and scan phases.FIG. 13 is a view showing an example in which pixels in all pixel lines are driven by a common VDD. FIG. 14 is a view showing an example in which a VDD applied to pixel lines in a scan phase and a VDD applied to pixel lines in a drive phase are separated.As shown in FIG. 13, a common VDD output from the circuit 150 is provided through an input resistance Rin (input resistance) to the sub-pixels 132 operating in the driving phase. The common VDD is also provided to the sub-pixels 131 operating in the reset phase, the sampling phase, or the data writing phase through the input resistor Rin. In this case, the IR drop of the VDD applied to the sub-pixels 131 operating in the reset phase, the sampling phase, or the data writing phase is increased by the sub-pixels 132 operating in the driving phase. In FIG. 13, "Idr" is the current flowing through the driving elements of the subpixels 132 operating in the driving phase, and "Isc" is the current flowing through the driving elements of the subpixels 131 operating in the reset phase, sampling phase, or data writing phase. Provided that Isc=Idr, the voltage Vsc provided to the sub-pixels 131 shown in FIG. 13 is Vsc= VDDPMIC- (Isc*N*M*Number of sub-pixels*Rin). Here, VDDPMIC is the VDD output from the circuit 150. N*M is the resolution of the display panel 100.Referring to FIG. 14, the circuit 150 provides VDD 2 to the second VDD line 32 in the reset phase, sensing phase, or data writing phase by using a VDD switching element. When VDD 2 is supplied through the second VDD line 32 to subpixels arranged in a pixel row, VDD 1 is supplied for the driving phase to the subpixels in the pixel rows other than the pixel row to which VDD 2 is applied.As shown in FIG. 14, VDD 2 output from the circuit 150 is provided through a first input resistor Rin 1 to the subpixels 141 operating in the reset phase, the sampling phase, or the data writing phase. The VDD 1 for the driving phase output from the circuit 150 is provided through a second input resistor Rin 2 to the sub-pixels 142 operating in the driving phase. Provided that Isc=Idr, the voltage Vsc provided to the sub-pixels 141 shown in FIG. 14 is Vsc= VDDPMIC- (Isc*Rin1). Thus, as seen in FIG. 14, a voltage drop caused by an IR drop does not occur because VDD 2 provided to the subpixels 141 is not affected by other subpixels.FIG. 15 is a circuit diagram showing a VDD circuit and a pixel circuit according to an exemplary embodiment of the present invention. FIG. 16 is a waveform diagram showing a sub-pixel sampling phase in a vertical blanking interval. FIG. 17 is a view showing an example in which previous frame data is rewritten to a subpixel in the vertical blanking interval. FIG. 18 is a waveform diagram showing a subpixel data writing phase in an active period.Referring to FIGS. 15 to 18, the VDD circuit 30 includes first and second switching elements M 1 and M 2 connected to adjacent first and second subpixels 101A and 101B. The first and second subpixels 101A and 101B are connected to different data lines 102 and are commonly connected to a plurality of gate lines 41 to 43.In the present invention, the VDD switching elements M 1 and M 2 of the VDD circuit 30 are shared by the first and second subpixels 101A and 101B, so that the number of switching elements required for the VDD circuit 30 can be reduced and also the range required for the VDD circuit 30 can be reduced.The pixel circuit includes a light emitting element EL, a driving element DT, a storage capacitor Cst, and a plurality of switching elements T 1 to T 4. The VDD switching elements M 1 and M 2, the switching elements T 1 to T 4, and the driving elements DT of the pixel circuit may be implemented by PMOS TFTs.The light emitting elements EL of the subpixels emit light in the driving phase DRV (driving phase) in which the current Ids flows through the driving elements DT. The driving phase DRV occupies most of one frame, except for the data writing phase WRA (data writing phase) of the active period AT and the reset phase INI (reset phase), the sampling phase SEN (sensing phase), and the data writing phase WRV (data writing phase) of the vertical blanking interval VB.As shown in FIG. 16, the vertical blanking interval VB includes a reset phase INI, a sampling phase SEN, a data writing phase WRV, and a driving phase DRV. As shown in FIG. 18, the active period AT includes a data write phase WRA and a drive phase DRV. In the data writing phase WRA of a subpixel, which is scanned in the active period AT subsequent to the vertical blanking interval VB, current frame data are written to the subpixel. On the other hand, in the data writing phase WRV of the vertical blanking interval VB, previous frame data is rewritten to the subpixel. That is, the data written on the subpixel sampled in the previous active period AT and the data written in the vertical blanking interval VB are the same.The first VDD switching element M 1 is turned on in the driving phase DRV in response to an EM signal EM(N). The first VDD switching element M 1 connects the first VDD line 31 to the drive phase sub-pixels DRV, and provides VDD 1 to the drive elements DT and storage capacitors Cst of the sub-pixels. The first VDD switching element M 1 includes a gate connected to a third gate line 43 to which the EM signal EM(N) is applied, a first electrode connected to the first VDD line 31, and a second electrode connected to the driving elements DT and storage capacitors Cst of the pixel circuits.The second VDD switching element M 2 is turned on in response to a first scan signal SCANA(N). The second VDD switching element M 2 connects the second VDD line 32 to the sub-pixels of the data writing phase or sampling phase, and provides VDD 2 to the driving elements DT and storage capacitors Cst of the sub-pixels. The second VDD switching element M 2 includes a gate connected to the first gate line 41 to which the first scan signal SCANA(N) is applied, a first electrode connected to the second VDD line 32, and a second electrode connected to the driving elements DT and storage capacitors Cst of the pixel circuits.The light emitting element EL of a pixel circuit may be implemented as an OLED. The OLED includes organic compound layers formed between an anode and a cathode. The organic compound layers may include, but are not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When the OLED is turned on, a hole passing through the hole transport layer HTL and an electron passing through the electron transport layer ETL move to the emission layer EML, thereby forming an exciton. As a result, the emission layer EML generates visible light. The OLED emits light by an electric current generated in the driving phase DRV and controlled by the gate-source voltage Vgs of the driving element DT. The anode of the OLED is connected to the third and fourth switching elements T 3 and T 4 via a third node n 3. The cathode of the OLED is connected to a VSS electrode to which the VSS is applied. In the driving phase, the current path of the OLED is switched by the first VDD switching element M 1 and the third switching element T 3 of the pixel circuit.The first electrode of the storage capacitor Cst is connected to the second VDD line 32 through the VDD circuit 30 in the data writing phase and the sensing phase, and is connected to the first VDD line 31 through the VDD circuit 30 in the driving phase. The second electrode of the storage capacitor Cst is connected to a gate of the driving element DT, a first electrode of the first switching element T 1, and a second electrode of the second switching element T 2 via a first node n 1.The first switching element T 1 is turned on in response to a second scan signal SCANB(N) in the scan phase. In the sampling phase, the first switching element T 1 connects the first node n 1 to a second node n 2. The second node n 2 is connected to the second electrode of the first switching element T 2, a second electrode of the driving element D 2, and a first electrode of the third switching element T 3. The first switching element T 1 includes a gate connected to the second gate line 42 to which the second scan signal SCANB(N) is applied, a first electrode connected to the first node n 1, and a second electrode connected to the second node n 2.The second switching element T 2 is turned on in response to the first scan signal SCANA(N) in the data write phase WRA of the active period AT and the reset phase INI, scan phase SEN, and data write phase WRV of the vertical blanking interval VB, and connects the data line 102 to the first node n 1. The second switching element T 2 includes a gate connected to the first gate line 41 to which the first scan signal SCANA(N) is applied, a first electrode connected to the data line 102, and a second electrode connected to the first node n 1.The third switching element T 3 is turned on in response to the EM signal EM(N) in the drive phase DRV, and connects the second node n 2 to the third node n 3. The third switching element T 3 includes a gate connected to the third gate line 43 to which the EM signal EM(N) is applied, a first electrode connected to the second node n 2, and a second electrode connected to the anode of the light emitting element EL via the third node n 3.The fourth switching element T 4 is turned on in response to the first scan signal SCANA(N) in the data write phase WRA of the active period AT and the reset phase INI, scan phase SEN, and data write phase WRV of the vertical blanking interval VB, and connects the Vini wiring to the third node n 3. The fourth switching element T 4 connects the Vini wiring to the anode of the light emitting element EL in the reset phase INI, the sampling phase SEN, and the data writing phases WRA and WRV for discharging the parasitic capacitance of the light emitting element EL, thereby preventing motion blur of the subpixel. The fourth switching element T 4 includes a gate connected to the first gate line 41, a first electrode connected to the Vini wiring, and a second electrode connected to the third node n 3.Referring to FIGS. 16 and 17, in the vertical blanking interval VB, the first scan signal SCANA(N) is generated as a gate-on voltage pulse defining the reset phase INI, the scan phase SEN, and the data write phase WRV. In the vertical blanking interval VB, the second scan signal SCANB(N) is generated as a gate-on voltage pulse defining the scan phase SEN. The second scan signal SCANB(N) is generated with the gate-on voltage only in the scan phase SEN and is maintained at the gate-off voltage during the remaining time of the vertical blanking interval VB and during the active period AT. The EM signal EM(N) is generated as a pulse of the gate-off voltage in the reset phase INI, the sampling phase SEN, and the data writing phase WRV of the vertical blanking interval VB, and is generated with the gate-on voltage in the drive phase DRV.In the reset phase INI, as shown in FIG. 21, the second VDD switching element M 2, and the second switching element T 2 and fourth switching element T 4 of the pixel circuit are turned on in response to the first scan signal SCANA(N). In the reset phase INI, Vini is provided to the data line 102. Accordingly, in the reset phase INI, the first electrode of the storage capacitor Cst of the pixel circuit and the first electrode of the driving element DT are reset to VDD 2 minus IR drop, and the first node n 1 and the third node n 3 are reset to Vini.In the sampling phase SEN, as shown in FIG. 21, the second VDD switching element M 2 and the first, second and fourth switching elements T 1, T 2 and T 4 of the pixel circuit are turned on in response to the sampling signals SCANA(N) and SCANB(N). In the sampling phase INI, VDD 2 minus IR drop is provided to the first electrode of the storage capacitor Cst of the pixel circuit and the first electrode of the driving element DT, and remains on until the gate-source voltage Vgs of the driving element DT reaches a threshold voltage Vth, and the threshold voltage Vth is stored in the storage capacitor Cst. The threshold voltage Vth of the driving element DT sensed in the sensing phase SEN is converted into digital data in the sensing part 20 by the first and second switching elements T 1 and T 2 and the data line 102, and then transmitted to the compensating part 131.In the data writing phase WRV, the second VDD switching element M 2 and the first, second and fourth switching elements T 1, T 2 and T 4 of the pixel circuit are turned on in response to the first scan signal SCANA(N). In the data writing phase WRV, the data voltage Vdata of the previous frame is provided to the data line 102, and the input image data is written to the subpixel. In the data writing phase WRV, a data voltage Vdata+Vth generated by compensating the data voltage Vdata by an amount equal to the threshold voltage Vth of the driving element DT is stored in the storage capacitor Cst. In the data writing phase WRV, the Vgs of the driving element DT changes to the voltage Vdata+Vth stored in the storage capacitor Cst. In the data writing phase WRV, the data written to the subpixel is the same as the previous frame data of the previous active period. This data is the previous frame data as shown in Fig. 17.In the driving phase DRV of the vertical blanking interval VB, the first VDD switching element M 1 and the third switching element T 3 of the pixel circuit are turned on in response to the EM signal EM(N). In this case, the driving element DT generates the current Ids by the gate-source voltage Vgs. The light emitting element EL is turned on and emits light by the current Ids from the driving element DT. The VDD 1 provided to the pixel circuit in the driving phase DRV includes a voltage drop α caused by an IR drop. In the driving phase DRV, when VDD1-α is applied to the first electrode of the storage capacitor Cst and the first electrode of the driving element DT, the voltage at the first node n1 decreases by α, which does not result in a change in the Vgs of the driving element DT. Thus, the light emitting element EL is driven without the effect of an IR drop in the driving phase DRV.Referring to FIG. 17, during an (N-1)th active period VB(N-1), the previous frame data is written to the subpixel PIX(N). The subpixel PIX(N) is an arbitrary subpixel to be sampled in the vertical blanking interval VB. After data is written to all pixels during the (N-1)th active period AT(N-1), when the subpixel PIX(N) is reset and then sampled in an (N-1)th vertical blanking interval VB(N-1), the data is deleted from the subpixel PIX(N), and subsequently the subpixel PIX(N) is turned off. During a frame in which the vertical blanking interval VB(N-1) is present, after the sampling phase SEN of the vertical blanking interval VB(N-1), the same data as the previous frame data should be rewritten to the subpixel PIX(N), so that the brightness of the sampled subpixel PIX(N) may remain constant.Referring to FIG. 18, the active period AT includes a data write phase WRA defined by the first scan signal SCANA(N) and a drive phase WRA defined by the EM signal EM(N).In the active period AT, the first scan signal SCANA(N) is generated as a gate-on voltage pulse defining a data write phase WRA of about a horizontal time. In the data write phase WRA, the second scan signal SCANB(N) and the EM signal EM(N) are the gate off voltage. The second scan signal SCANB(N) is maintained at the gate-off voltage during the active period AT. As shown in FIG. 19, the second VDD switching element M 2 and the second switching element T 2 are turned on in the data writing phase WRV. In the data writing phase WRV, the data voltage Vdata of current frame data is provided to the data line 102 and the data is written to the subpixel. The data voltage Vdata is VDD-(DATA-Vth). DATA is a voltage corresponding to a gray level in the data. Therefore, VDD 2 is applied to the storage capacitor Cst and the first electrode of the driving element DT, and the data voltage Vdata is provided to the first node connected to the second electrode of the storage capacitor Cst and the gate of the driving element.In the driving phase DRV of the active period AT, as shown in FIG. 19, the first VDD switching element M 1 and the third switching element T 3 are turned on in response to the EM signal EM(N). In this case, the driving element DT generates the current Ids by the gate-source voltage Vgs. The light emitting element EL is turned on and emits light by the current Ids from the driving element DT. The VDD 1 provided to the pixel circuit in the driving phase DRV includes a voltage drop α caused by an IR drop. In the driving phase DRV, when VDD1-α is applied to the first electrode of the storage capacitor Cst and the first electrode of the driving element DT, the voltage at the first node n1 decreases by α, which does not result in a change in Vgs of the driving element DT. Thus, the light emitting element EL is driven in the driving phase DRV without the effect of IR drop.FIG. 20 is a view showing a VDD applied to a pixel circuit in the data write phase WRA and the drive phase DRV, and the voltage of the storage capacitor.Referring to FIG. 20, VDD2=VDD is applied to the first electrode of the storage capacitor Cst and the first electrode of the driving element DT, and Vdata= VDD-(DATA-Vth) is applied to the second electrode of the storage capacitor Cst. Therefore, the voltage of the storage capacitor Cst is Vgs=DATA+Vth.In the driving phase DRV, VDD 1=VDD-α, which is the VDD minus a voltage drop α caused by an IR drop, is applied to the first electrode of the storage capacitor Cst and the first electrode of the driving element DT, and the second electrode of the storage capacitor Cst floats because the first and second switching elements T 1 and T 2 are turned off. Since the first node n 1 floats, the voltage of the second electrode of the storage capacitor Cst changes by α when the voltage of the first electrode of the storage capacitor Cst changes by α. Accordingly, the potential difference between two ends of the storage capacitor Cst is maintained even when the VDD changes in the driving phase DRV. Thus, the Vgs is maintained at the same voltage as stored in the sampling phase.FIG. 22 is a view showing the active period and the vertical blanking interval according to a display timing standard by the VESA (Video Electronics Standards Association).Referring to FIG. 22, a vertical synchronization signal Vsync defines one frame. A horizontal synchronization signal Hsync defines a horizontal time. A data enable signal DE (data enable signal) defines the duration of valid data including pixel data to be displayed on the screen.The data enable signal DE is synchronized with the valid data to be displayed on the pixel array of the display panel 100. A pulse interval of the data enable signal DE is a horizontal time, and the high logic part of the data enable signal DE represents the data input timing of one pixel line. A horizontal time is the time required to write data to a pixel row of pixels on the display panel 100.The timing controller 130 receives the data enable signal DE and data of an input image during the active period AT. The data enable signal DE and the input image data are not provided during the vertical blanking interval VB. During the active period AT, one frame of data to be written to all pixels is received by the timing controller 130. One frame is the sum of the active time period AT and the vertical blanking interval VB.As can be seen from the data enable signal DE, no input data is received by the display device during the vertical blanking period VB. The vertical blanking interval VB includes a vertical synchronizing time VS, a vertical front blanking interval FP (front porch), and a vertical rear blanking interval BP (back porch). The vertical synchronizing time VS is the time from the falling edge of Vsync to the rising edge representing the start (or end) timing of an image. The vertical leading blanking margin FP is the time between the falling edge of the last DE, which is the data timing of the last line of a frame, and the start of the vertical blanking interval VB. The vertical trailing edge margin BP is the time between the end of the vertical blanking interval VB and the rising edge of the first DE, which is the data timing of the first line of a frame.As described above, in the present invention, the driving voltage VDD is divided into VDD=VDD 1 for the driving phase and VDD=VDD 2 for the sampling phase and data writing phase, and variations in the electrical characteristics of subpixels are compensated by external compensation. In the present invention, when data is written to the sub-pixels in the active period and the electrical characteristics of the sub-pixels are sampled in the vertical blanking interval, VDD(=VDD1) is applied to the sub-pixels. Accordingly, the electroluminescence display of the present invention prevents variations in the gate-source voltage Vgs of the driving elements of individual subpixels without the effect of an IR drop in the scan and data writing phase, and is capable of accurately sensing the electrical characteristics of the driving elements of individual subpixels because there is no effect of an IR drop in the scan phase.Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments may be devised by those skilled in the art that will fall within the scope of the claims. In particular, various variations and modifications are possible in the component parts and / or arrangements of the subject combination arrangement within the scope of the appended claims.

Claims

A display panel (100) configured to display frame data during a frame period including an active period (AT) and a blanking interval (VB), and modulate data of an input image based on a result of sensing the electrical characteristics of pixels in the blanking interval (VB), the display panel (100) comprising: a subpixel (101) comprising a light emitting element (EL) and a driving element (DT) for driving the light emitting element (EL), wherein the light emitting element (EL) emits light by a current in the driving element (DT) during a driving phase (DRV); and a current switching circuit (30) configured to provide a first drive voltage (VDD 1) to the sub-pixels (101) during the drive phase (DRV) in the active period (AT) and the blanking interval (VB) and to provide a second drive voltage (VDD 2) to the sub-pixels (101) during a data write phase (WRA) of the active period and during the reset, sample and data write phase (INI, SEN, WRV) of the blanking interval (VB).The display panel (100) according to claim 1, wherein the first driving voltage (VDD1) is provided to a first power line (31) and the second driving voltage (VDD2) is provided to a second power line (32) which is separated from the first power line (31).The display panel (100) according to claim 1 or 2, wherein the subpixel (101) further comprises a capacitor (Cst) connected to the driving element (DT), wherein the first driving voltage (VDD1) is provided to a first electrode of the capacitor (Cst) and a first electrode of the driving element (DT) during the driving phase (DRV) of the active period (AT) and the blanking interval (VB), and wherein the second driving voltage (VDD2) is provided to the first electrode of the capacitor (Cst) during the reset, sensing and data writing phase (INI, SEN, WRV) of the blanking interval (VB), wherein a second electrode of the capacitor (Cst) of the subpixel (101) is connected to a gate of the driving element (DT) via a first node (n1), and the first electrode of the driving element (DT) is connected to the first electrode of the capacitor (Cst), and a second electrode of the driving element (DT) is connected to a second node (n2).The display panel (100) according to claim 3, further comprising: a first power line to which the first driving voltage (VDD1) is provided and which is commonly connected to the subpixels (101) of all the pixel rows; and a plurality of second power lines to which the second driving voltage (VDD2) is provided and which are separated between the pixel rows.The display panel (100) according to claim 4, wherein the power circuit (30) comprises: a first pixel driving voltage switching element (M1) configured to be turned on in the driving phase (DRV) in response to an emission switching signal (EM) defining a duration of the driving phase (DRV), and connecting the first power line (31) to the subpixel (101); and a second pixel driving voltage switching element (M2) configured to turn on in response to a first scan signal (SCANA) defining a duration of the data writing phase (WRA) of the active period (AT) and the duration of the reset, scan and data writing phase (INI, SEN, WRV) of the blanking interval (AT), and connecting the second power line (32) to the subpixel (101).The display panel (100) of claim 5, wherein the subpixel (101) further comprises: a first switching element (T1) configured to turn on in response to a second scan signal (SCANB) defining a duration of the scan phase (SEN) and connecting the first node (n1) to the second node (n2); a second switching element (T2) configured to turn on in response to the first scan signal (SCANA) and connecting a data line (102) to the first node (n1); a third switching element (T3) configured to turn on in response to the emission switch signal (EM) and connecting the second node (n2) to a third node (n3); and a fourth switching element (T4) configured to be turned on in response to the first scan signal (SCANA), and connecting a third power line to which a predetermined reset voltage (Vini) is applied to the third node (n3), wherein the third node (n3) is connected to the third switching element (T3), the fourth switching element (T4), and an anode of the light emitting element (EL), and a data voltage (Vdata) of the input image is provided to the data line (102) during the data writing phase (WRA), and the reset voltage (Vini) is provided to the data line (102) during the reset phase (INI).The display panel (100) according to any one of claims 1 to 6, wherein in the data writing phase (WRV) of the blanking interval (VB) and the data writing phase (WRA) of the previous active period (AT), the same previous frame data is written to a subpixel (101) to be sampled in the blanking interval (VB), and in the data writing phase (WRA) of the next active period (AT), current frame data is written to the sampled subpixel (101).An electroluminescent display comprising the display panel (100) according to any one of claims 1-7.The electroluminescent display of claim 8, wherein the display panel (100) comprises: first and second sub-pixels (101A, 101B) connected to different data lines (102) and commonly connected to first to third gate lines (41, 42, 43); a data driver (110) configured to provide a data voltage of the input image to the data lines (102) during the data writing phase (WRA) of the active period (AT) and the data writing phase (WRV) of the blanking interval (VB), and to provide a predetermined (Vini) to the data lines (102) during the reset phase (INI); and a gate driver (120) configured to supply the first gate line (41) with a first scan signal (SCANA) defining a duration of the data write phase (WRA) of the active period (AT) and a duration of the reset, scan and data write phase (INI, SEN, WRV) of the blanking interval (VB), supply the second gate line (42) with a second scan signal (SCANB) defining a duration of the scan phase (SEN), and supply the third gate line (43) with an emission switch signal (EM) defining a duration of the drive phase (DRV).The electroluminescence display according to claim 8 or 9, further comprising a circuit (150) configured to output the first driving voltage (VDD1) and the second driving voltage (VDD2), wherein the circuit (150) comprises a first output terminal (CH1) configured to output the first driving voltage (VDD1) and a second output terminal (CH2) configured to output the second driving voltage (VDD2), wherein the first and second driving voltages (VDD1, VDD2) are output from the circuit (150) at substantially the same voltage level.The electroluminescence display according to claim 8 or 9, further comprising a circuit (150) configured to output the first driving voltage (VDD1) and the second driving voltage (VDD2), wherein the circuit (150) is configured to output a single driving voltage to a single wire (50) through a single output channel (CH1), wherein the single wire (50) is divided into first and second branch wires (136, 138), wherein the first driving voltage (VDD1) is provided to the sub-pixels (101) through the first branch wire (136), and the second driving voltage (VDD2) is provided to the sub-pixels (101) through the second branch wire (138).The electroluminescence display according to claim 8 or 9, further comprising: a first power line to which the first driving voltage (VDD1) is provided and which is commonly connected to the subpixels (101) of all the pixel lines; and a plurality of second power lines to which the second driving voltage (VDD2) is provided and which are separated between the pixel lines and connected to the subpixels (101), wherein when the second driving voltage (VDD2) is provided by pixel driving voltage lines to the subpixels (101) arranged in a single pixel line, the first driving voltage (VDD1) is provided to the subpixels (101) in the pixel lines other than the single pixel line.

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