System and method for dynamic and adaptive interrupt merging

Abstract

Procedure that includes: Determining that processing of one or more instructions on a data storage device (100) is complete; Analyzing one or more aspects of a completion queue (412) comprising analyzing the fill of the completion queue, wherein the analysis compares a level of fill of the completion queue to at least two levels; Determining, based on the analysis, when to generate an interrupt for a host device (252, 400), wherein the interrupt indicates to the host device that processing of one or more instructions on the completion queue has been completed, wherein in response to determining that the fill level is below a first level (708), it is determined to immediately generate the interrupt for the host device (608, 710), wherein in response to determining (712) that the fill level is above a second level, it is determined to wait with generating the interrupt for the host device, and wherein in response to determining that the fill level is between the first level and the second level, it is determined to partially merge the interrupt for the host device (610, 716); and Sending the interrupt to the host device (252, 400) in response to determining when to generate the interrupt for the host device.

Description

BACKGROUND

[0001] NVM Express (NVMe) is a standard for accessing non-volatile storage media connected via a PCI Express (PCIe) bus. NVMe can be used with a variety of non-volatile storage media, such as solid-state drives (SSDs). One focus of NVMe relates to I / O communication between a host device (which can access and / or write to the non-volatile storage media) and a data storage device (which contains the non-volatile storage media). In this context, NVMe implements a mechanism of paired submission queues and completion queues, with host software on the host device placing commands in the submission queue. Completions are placed by the data storage device controller in the associated completion queue.

[0002] This document describes a technique for maintaining a responsive user interface while conserving the battery life of a user device by dynamically determining the interrupt rate / interrupt time. US 2017 / 0 010 992 A1. US 2016 / 0 0335 208 A1 concerns the representation of a direct-access memory in a logical drive model. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the invention and, together with the description, serve to explain its principles. Where appropriate, the same reference numerals are used throughout the drawings to refer to the same or similar elements. Fig. Figure 1A is a block diagram of an example non-volatile memory system. Fig. Figure 1B is a block diagram of a memory module containing multiple non-volatile data storage systems and a host. Fig. Figure 1C is a block diagram of a hierarchical storage system. Fig. 2A is a block diagram of exemplary components of a control unit of the non-volatile data storage system of Fig. 1A. Fig. 2B is a block diagram of exemplary components of a non-volatile memory assembly of the non-volatile data storage system of Fig. 1A. Fig. Figure 3 is a block diagram of the host device and the NVMe controller illustrating a sequence for a host device and a storage device to request and process an NVMe command. Fig. 4 is a block diagram of other exemplary components of a host system and a data storage device. Fig. Figure 5 is a block diagram illustrating the completion queue and interrupt merging. Fig. 6 is a flowchart of a first example method for merging interrupts. Fig. Figure 7 is a flowchart of a second example method for merging interrupts. Fig. Figure 8 is a flowchart of an example method for using a counter to aggregate interrupts. Fig. Figure 9 is a flowchart of an example method for analyzing queue depth for merging interrupts. Fig. 10 is a flowchart of an example method for estimating instruction completion time and host latency for merging interrupts. Detailed description of embodiments

[0004] According to the invention, a method and non-volatile data storage devices having the features of the independent claims are provided; dependent claims relate to preferred embodiments. Overview

[0005] A common bottleneck for high-speed data transfers is the large number of interrupts that the receiving system must process. These interrupts consume signaling resources on the receiving system's bus(es) and introduce significant CPU overhead if the receiving system constantly transitions between "productive" work and interrupt handling (which can occur thousands of times per second). To alleviate this burden, the NVMe standard includes two parameters for aggregating interrupts. In particular, the NVMe standard defines the TIME and THR parameters, which can be configured by the host device during the initialization phase, as shown below: Bit Beschreibung 31:16 Reserviert 15:08 Aggregationszeit (TIME) : Specifies the recommended maximum time, in 100-millisecond increments, that a controller can delay an interrupt due to interrupt merging. A value of 0h corresponds to no delay. The controller can apply this time per interrupt vector or across all interrupt vectors. The reset value of this setting is 0h. 07:00 Aggregationsschwellenwert (THR) : Specifies the recommended maximum number of completion queue entries to be aggregated per interrupt vector before an interrupt is signaled to the host. This is a 0-based value. The reset value of this setting is 0h.

[0006] The parameters listed above are global for all supported interrupt vectors. Thus, when the feature is enabled, the data storage device sends the interrupt in two scenarios: THR completion entries have been posted to the relevant completion queue; and TIME has expired since the aggregation of the very first interrupt.

[0007] Under these two parameters, if multiple instruction completions are received within a short time frame, the storage device controller merges the messages and interrupts the host device only once. Conversely, when implementing interrupt merging, the storage device that has completed an instruction does not immediately send an interrupt to the host device, but waits a short while if more instruction completions are posted. In practice, these two parameters result in a static interrupt merging methodology. As a result, using these two parameters can have a negative impact on latency, resulting in a trade-off between latency and load reduction.

[0008] In one implementation, the data storage device uses a dynamic and adaptive interrupt merging methodology that supports multiple platforms according to one or more parameters. The one or more parameters may include any one, any combination of, or all of the following: (i) one or more aspects of the completion queue (e.g., completion queue ID (which may indicate a priority, such as a relative priority, of a particular completion queue), the completion queue status (e.g., a measure of fullness, such as whether the completion queue is full, almost empty, or in between), etc.); (ii) one or more aspects of the instruction(s) (e.g., instruction classification, pending instructions in the data storage device (e.g., the stage of execution of the pending instructions), etc.); (iii) queue depth (number of instructions in the process, such as between the continuous queue bell and the completion queue post); (iv) Latency (e.g., host latency (e.g., the time elapsed between the data storage device posting the interrupt and the host device fetching entries from the completion queue in response to receiving the interrupt), feedback from past decisions (the logic may be adaptive based on past decisions and latency results), etc.); and (v) Firmware settings of the data storage device (e.g., internal thresholds of the data storage device, fill levels, etc.).

[0009] With respect to (i), special completion queues can modify interrupt scheduling. In particular, an admin completion queue (which can be considered the highest priority) and high-priority I / O completion queues (which can be considered the second highest priority) can modify interrupt scheduling, such as reducing the aggregation threshold to a lower level or even posting the interrupt immediately. The data storage device can use a counter that counts the number of entries the data storage device has posted to the completion queue to determine when to issue the interrupt.As discussed in more detail below, due to the host latency in responding to the interrupt and due to the data storage device posting additional entries to the completion queue during the host latency period, the data storage device may dynamically update the value of the counter to reflect that the additional posted entries have been processed by the host device.

[0010] With reference to (ii), one or more aspects of the instructions may alter the interrupt scheduling. For example, specific types of instructions may be considered urgent and may thus alter the interrupt scheduling, such as reducing the aggregation threshold to a lower level or even posting the interrupt immediately. In one implementation, the data storage device may determine a type of instruction and, based on the determined type, mark the interrupt as urgent. For example, the data storage device may treat read instructions as urgent because the host device is "waiting" for the read instructions to complete. As another example, the data storage device may treat a forced unit access (FUA) instruction as another type of instruction whose interrupt must be handled urgently (e.g.,Reducing the aggregation threshold to a lower level or even posting the interrupt immediately. In another implementation, the data storage device may analyze other aspects of the instructions, such as the LBA range, and revise the interrupt scheduling accordingly. In particular, the data storage device may detect a specific LBA range as an operating system log update and, in response, treat the interrupt as urgent. In yet another implementation, the data storage device may analyze the execution of the instruction if it interferes with interrupt scheduling. In particular, as discussed in more detail below, an instruction goes through various phases. The data storage device may analyze the phases of various instructions (e.g., deep queued, error correction, capture, or transfer from flash) and estimate a time to complete the various instructions.The data storage device may, in turn, use the estimated completion time to decide when to schedule interrupts for the host device and whether to merge the interrupts, as discussed in more detail below.

[0011] Regarding (iv), the data storage device may determine the host latency in one of several ways. In one way, the data storage device may determine the host latency based on previous communication transmissions (e.g., from the time of the data storage device interrupt until the time the host device reports that the completion queue entry has been checked). In another way, the data storage device may determine the host latency as a function of queue depth. The data storage device may use information about the host latency to post the interrupts before the data storage device updates the completion queue. For example, the data storage device may post an interrupt with the expectation that after factoring the host latency, the host device will check a specific number of new entries on the completion queue.

[0012] With reference to (v), the data storage device has various firmware settings, such as internal data storage device thresholds, fill levels, or the like, that may affect interrupt merging, as described in more detail below.

[0013] In this context, the interrupt merging methodology may use one or more parameters: based on an internal aspect of the data storage device; based on a dynamic aspect (e.g., after the initialization phase); based on the ongoing queue (e.g., based on the priority of the ongoing queue); and / or based on the completion queue (e.g., based on the priority of the completion queue). As discussed in more detail below, the interrupt merging methodology may be applied to various scenarios. For example, the interrupt merging methodology may adapt to different requirements for NVMe systems, such as low queue depth for a first NVMe system and high queue depth for a second NVMe system. Embodiments

[0014] The following embodiments describe non-volatile data storage devices and associated methods for processing instructions. Before turning to these and other embodiments, the following paragraphs provide a discussion of exemplary non-volatile data storage devices and memory modules that may be used with these embodiments. Of course, these are only examples, and other suitable types of non-volatile data storage devices and / or memory modules may be used.

[0015] Fig. 1A is a block diagram illustrating a non-volatile data storage device 100. The non-volatile data storage device 100 may include a control unit 102 and non-volatile data storage, which may consist of one or more non-volatile data storage assemblies 104. As used herein, the term assembly refers to a group of non-volatile data storage cells and associated circuitry for managing the physical operation of these non-volatile data storage cells formed on a single semiconductor substrate. The control unit 102 may interface with a host device or system and transmit command sequences for read, program, and erase operations to the non-volatile data storage assembly(s) 104. As discussed below, the commands may include logical and / or physical addresses.

[0016] The control unit 102 (which may be a flash memory control unit) may take the form of processing circuitry, a microprocessor or processor, and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by, for example, the (micro)processor, logic gates, switches, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. The control unit 102 may be configured with hardware and / or firmware to perform the various functions described below and shown in the flowcharts. In addition, some of the components shown as being internal to the control unit may also be stored external to the control unit, and other components may be used.Additionally, the phrase "operationally in communication with" could mean directly in communication with or indirectly (wired or wirelessly) in communication with through one or more components that may or may not be shown or described herein.

[0017] As used herein, a flash data storage controller is a device that manages data stored on the flash data storage and communicates with a host such as a computer or electronic device. A flash data storage controller may have various functionality in addition to the specific functionality described here. For example, the flash data storage controller may format the flash data storage to ensure that the data storage operates correctly, blank out defective flash data storage cells, and allocate spare cells to replace future failed cells. A portion of these spare cells may be used to hold firmware to operate the flash data storage controller and to implement other features. An example of firmware is a flash translation layer.In operation, when a host device needs to read data from or write data to the flash data storage, it will communicate with the flash data storage controller. In one embodiment, if the host device provides a logical address from / to which the data is to be read / written, the flash data storage controller can translate the logical address received from the host into a physical address in the flash data storage. The flash data storage controller can also perform various data storage management functions, such as wear leveling (spreading out write operations to avoid wear on specific blocks of the data storage that would otherwise be repeatedly written to) and garbage collection (after a block is full, moving only the valid data pages to a new block so that the full block can be erased and reused).

[0018] The interface between the control unit 102 and the non-volatile data storage assembly(s) 104 may be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, the data storage device 100 may be a card-based system, such as a secure digital (SD) card or a secure digital micro (micro SD) card. In an alternative embodiment, the non-volatile data storage device may be part of an embedded data storage device.

[0019] Although in the Fig. 1A, the non-volatile data storage device 100 may include a single channel between the control unit 102 and the non-volatile data storage assembly(s) 104, the subject matter described herein is not limited to having only a single data storage channel. For example, in some NAND data storage device architectures, 2, 4, 8, or more NAND channels may exist between the control unit and the NAND data storage assembly(s) 104, depending on the capabilities of the control unit. In any of the embodiments described herein, more than a single channel may exist between the control unit and the data storage assembly(s) 104, even if a single channel is shown in the drawings.

[0020] Fig. 1B illustrates a memory module 200 including a plurality of non-volatile data storage devices 100. As such, the memory module 200 may include a memory controller 202 that interfaces with a host 220 and with a memory system 204 including a plurality of non-volatile data storage devices 100. The interface between the memory controller 202 and the non-volatile data storage devices 100 may be a bus interface, such as an Advanced Serial Attached Storage (SATA) interface, an Express Peripheral Component (PCIe) interface, an Embedded Multimedia Card (eMMC) interface, an SD interface, or a Universal Serial Bus (USB) interface, as examples. The memory system 200, in one embodiment, may be a solid-state drive (SSD), such as those used in portable computing devices such as notebooks.laptop computers, tablet computers and mobile phones.

[0021] Fig. 1C is a block diagram illustrating a hierarchical storage system 250. The hierarchical storage system 250 may include multiple storage controllers 202, each controlling a respective storage system 204. Host systems 252 may access data storage within the hierarchical storage system 250 via a bus interface. Example bus interfaces may include a Non-Volatile Data Storage Express (NVMe) interface, a Fibre Channel over Ethernet (FCoE) interface, an SD interface, a USB interface, a SATA interface, a PCIe interface, or an eMMC interface, as examples. In one embodiment, the Fig. For example, the hierarchical storage system 250 illustrated in Figure 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as might be found in a data center or other location where mass storage is needed. In one embodiment, the host systems 252 may include the functionality described in the host 220.

[0022] Fig. 2A is a block diagram illustrating example components of the control unit 102 in greater detail. The control unit 102 may include a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with the non-volatile data storage assembly(s) 104, and various other modules that perform various functions of the non-volatile data storage device 100. In general, a module may be hardware or a combination of hardware and software. For example, each module may include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, and any other type of hardware, or a combination thereof.Additionally or alternatively, each module may include data storage hardware comprising instructions executable by a processor or processor circuitry to implement one or more of the features of the module. If any of the modules includes the portion of data storage comprising instructions executable by the processor, the module may or may not include the processor. In some examples, each module may be just the portion of data storage containing instructions executable by the processor to implement the features of the corresponding module, without the module including any other hardware. Because each module includes at least some hardware, even if the included hardware includes software, each module may be interchangeably referred to as a hardware module.

[0023] The control unit 102 may include a buffer manager / bus control module 114 that manages buffers in the random access memory (RAM) 116 and controls the internal bus arbitration for communication on an internal communication bus 117 of the control unit 102. A read-only memory (ROM) 118 may store and / or access system boot code. Although in Fig. 2A as being located separately from the control unit 102, in other embodiments, the RAM 116 and / or the ROM 118 may be located within the control unit 102. In still other embodiments, portions of the RAM 116 and the ROM 118 may be located both within the control unit 102 and external to the control unit 102. Further, in some implementations, the control unit 102, the RAM 116, and the ROM 118 may be located on separate semiconductor packages. As discussed below, in one implementation, the submission queues and the completion queues may be stored in the control unit data storage buffer, which may be located in the RAM 116.

[0024] Additionally, the front-end module 108 may include a host interface 120 and a physical layer (PHY) interface 122, which provide the electrical interface to the host or the next-level storage controller. The choice of host interface 120 type may depend on the type of data storage used. Example types of host interface 120 may include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 120 may typically support the transmission of data, control signals, and termination signals.

[0025] The backend module 110 may include an error correction control (ECC) engine 124 that encodes the data bytes received from the host and decodes and error corrects the data bytes read from the non-volatile data storage device(s). As discussed in more detail below, the ECC engine may be tunable, e.g., to generate different amounts of ECC data based on the operating mode (e.g., to generate normal-mode ECC data in normal programming mode and burst-mode ECC data in burst programming mode, where the burst-mode ECC data is larger than the normal-mode ECC data). The backend module 110 may also include an instruction sequencer 126 that executes instruction sequences, such as: B. generates programming, read and erase command sequences to be transferred to the non-volatile data storage module(s) 104.Additionally, the backend module 110 may include a RAID (Redundant Array of Independent Drives) module 128 that manages the generation of RAID parity and recovery of corrupted data. RAID parity may be used as an additional level of integrity protection for the data written to the non-volatile data storage device 100. In some cases, the RAID module 128 may be part of the ECC engine 124. A data storage interface 130 provides the command sequences to the non-volatile data storage module(s) 104 and receives status information from the non-volatile data storage module(s) 104. Along with the command sequences and status information, data to be programmed into or read from the non-volatile data storage module(s) 104 may be communicated via the data storage interface 130.In one embodiment, the data storage interface 130 may be a double data rate (DDR) interface, such as a switch mode 200, 400, or 800 interface. A flash control layer 132 may control the overall operation of the backend module 110.

[0026] Thus, the control unit 102 may include one or more management tables for managing the operation of the storage system 100. One type of management table includes a logical-to-physical address mapping table. The size of the logical-to-physical address mapping table may grow with the data storage size. In this context, for a high-capacity storage device (e.g., larger than 32G), the logical-to-physical address mapping table may be too large to be stored in SRAM and may be stored in the non-volatile data storage 104 along with user and host data. Therefore, accesses to the non-volatile data storage 104 may first require reading the logical-to-physical address mapping table from the non-volatile data storage 104.

[0027] Additional modules of the non-volatile data storage device 100, which are in Fig. 2A, may include a media management layer 138 that performs wear leveling of memory cells of the non-volatile data storage assembly 104. The non-volatile data storage device 100 may also include other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, and other components that may interface with the controller 102. In alternative embodiments, one or more of the RAID module 128, the media management layer 138, and the buffer management / bus controller 114 are optional components that may not be required in the controller 102.

[0028] Another module of the non-volatile data memory 100, which is in Fig. 2A, may include an interrupt aggregation module 112. As discussed in more detail below, the data storage device may determine whether to aggregate interrupts for the host device, wherein the data storage device uses the interrupt aggregation module 112 to make the determination.

[0029] Fig. 2B is a block diagram illustrating example components of a non-volatile data storage assembly 104 in more detail. The non-volatile data storage assembly 104 may include a non-volatile data storage array 142. The non-volatile data storage array 142 may include a plurality of non-volatile data storage elements or cells, each configured to store one or more bits of data. The non-volatile data storage elements or cells may be any suitable non-volatile data storage cells, including NAND flash data storage cells and / or NOR flash data storage cells in a two-dimensional and / or three-dimensional configuration. The memory cells may take the form of solid-state memory cells (e.g., flash memory cells) and may be programmable once, programmable a few times, or programmable many times.Additionally, the data storage elements or cells can be configured as single-level cells (SLCs) that store a single bit of data per cell, multi-level cells (MLCs) that store multiple bits of data per cell, or combinations thereof. For some example configurations, the multi-level cells (MLCs) can include tri-level cells (TLCs) that store three bits of data per cell.

[0030] Additionally, a flash data storage cell in array 142 may include a floating gate transistor (FGT) having a floating gate and a control gate. The floating gate is surrounded by an insulator or insulating material that helps retain charge in the floating gate. The presence or absence of charge within the floating gate may cause a shift in a threshold voltage of the FGT, which is used to distinguish logic levels. That is, the threshold voltage of each FGT may indicate the data stored in the data storage cell. Hereinafter, FGT, data storage element, and data storage cell may be used interchangeably to refer to the same physical entity.

[0031] The data storage cells may be arranged in the data storage array 142 according to a matrix-like structure of rows and columns of data storage cells. At the intersection of a row and a column is an FGT (or data storage cell). A column of FGTs may be referred to as a chain. FGTs in a chain or column may be electrically connected in series. A row of FGTs may be referred to as a page. Control gates of FGTs in a page or row may be electrically connected together.

[0032] The data storage array 142 may also include word lines and bit lines connected to the FGTs. Each page of FGTs is coupled to a word line. In particular, each word line may be coupled to the control gates of FGTs in a page. Additionally, each chain of FGTs may be coupled to a bit line. Further, a single chain may span multiple word lines, and the number of FGTs in a chain may be equal to the number of pages in a block.

[0033] The non-volatile data storage assembly 104 may further include a page buffer or data cache 144 that temporarily stores data to be acquired from the data storage array 142 and / or programmed into the data storage array 142. The non-volatile data storage assembly 104 may also include a row address decoder 146 and a column address decoder 148. The row address decoder 146 may decode a row address and select a specific word line in the data storage array 142 when data is read to or written from the data storage cells in the data storage array 142. The column address decoder 148 may decode a column address to select a specific group of bit lines in the data storage array 142 to be electrically coupled to the data cache 144.

[0034] Additionally, the non-volatile data storage assembly 104 may include peripheral circuitry 150. The peripheral circuitry 150 may include a state machine 151 that provides status information to the control unit 102. Other functionality of the state machine 151 is described in more detail below.

[0035] Fig. Figure 3 illustrates a sequence of steps for executing a command via the NVMe standard. As shown, host device 300 includes host data storage 302, and the data storage device includes a controller, such as an NVMe controller 310. In one implementation, host data storage 302 includes a submission queue 304 and a completion queue 306. Further, in one implementation, the submission queues and the completion queues may have a 1:1 correlation. Alternatively, the submission queues and the completion queues do not have a 1:1 correlation.

[0036] In practice, during the initialization phase, the host device 300 creates one or more submission queues and one or more corresponding completion queues. In particular, the host device 300 may notify the data storage device of the submission queue(s) and the completion queue(s) by sending information, such as the base address for each queue, to the data storage device. In this context, each submission queue has a corresponding completion queue. If the submission queue and the completion queue are resident on the host device, the host device sends information to the data storage device to allow the data storage device to determine the locations of the submission queue and the completion queue on the host device.In a specific implementation, the host device sends a command specifying the creation of the submission queue and the completion queue. The command may include a PRP1 pointer, which is a pointer to a list on the host device of the locations of the specific submission queue or the specific completion queue. In practice, the data storage device sends a TLP read request using the PRP1 to obtain the PRP list and stores the PRP list in the data storage device to determine the data storage locations within the host device for use in future commands to read from the specific submission queue or write to the specific completion queue.Alternatively, the host device 300 may instruct the data storage device to create the submission queue(s) and corresponding completion queue(s) in a data store resident in the data storage device, such as a controller data store buffer.

[0037] The submission queue 304 may be based on a circular buffer with a start pointer and an end pointer. After creating the submission queue(s) and notifying the data storage device of the created submission queue(s), the host device 300 may write a command (or multiple commands) to the submission queue. This is described in Fig. 3 as step 1, which is labeled “queue command”. In particular, Fig. 3 illustrates that four commands have been written to the submit queue. In one implementation, the data storage device 1 does not detect that the host device 300 has updated the submit queue 304 with four commands because the host device 300 has updated its own host data store 302. In another implementation (such as when the submit queue(s) and completion queue(s) are resident in the controller data store buffer), the data storage device may monitor a communication interface between the host device 300 and the data storage device for special communication, such as writing to the submit queue(s), that is resident on the data storage device.For example, the data storage device may monitor transport layer packets (TLPs) on the PCI Express bus to determine whether host device 300 has sent a TLP that results in an update to the submission queue resident in the controller's data storage buffer. In this context, the data storage device may identify one or more entries to be written to the submission queue(s).

[0038] In step 2, the host device 300 writes to a submit queue end ring register 312 in the data storage device. This write to the submit queue end ring register 312 notifies the data storage device that the host is posting one or more commands to this specific submit queue 304 (e.g., 4 commands, as in Fig. 3). Writing to the submit queue end ring register 312 can take one of several forms. In one way, the host device 300 indicates a new end for the submit queue 304 and thereby indicates the number of instructions that will be written to the submit queue 304. Thus, since the data storage device knows the base address for the submit queue 304, the data storage device only needs to know the end address to indicate the number of new instructions that will be written to the submit queue 304. After an instruction (or group of instructions) is processed, the data storage device sets the new beginning of the submit queue 304 accordingly. Thus, the end pointer may represent an "offset" from the beginning pointer.In another way, the data storage device 300 specifies a number of commands to be written to the submit queue 304. In practice, each submit queue 304 has a corresponding submit queue end ringing register in the data storage device, so that when the host device 300 updates a particular ringing register (correlated with a particular submit queue 304), the data storage device can determine which particular submit queue 304 has been updated based on the ringing register.

[0039] After step 2 (whereby the data storage device has been notified of command(s) on the commit queue 304) and before step 3 (whereby the data storage device fetches the command(s)), the data storage device knows that command(s) are waiting in the commit queue 304. In the general case, there may be multiple commit queues (with potentially waiting commands in the multiple commit queues). Thus, before executing step 3, the data storage device controller may arbitrate between different commit queues to select the specific commit queue from which the command(s) should be fetched.

[0040] In response to determining at step 3 which is the special submit queue 304 from which the instruction(s) are to be fetched, the data storage device fetches the instruction(s) from the special submit queue 304. In practice, the data storage device may access the base address of the special submit queue 304 plus the pointing to the current header implemented in the host device 300.

[0041] As discussed above, a memory location may be allocated to the submission queue or the completion queue (such as in the host device or in the controller data storage buffer in the data storage device). The submission queue and the completion queues may contain multiple entries, each associated with a specific command. The size of each entry may be a predetermined size, such as 64kB. In this context, entries within the submission queue may be determined using the base address for the submission queue and shifting the base address by the number of entries multiplied by the size of each entry (e.g., 64kB).

[0042] As discussed above, the storage device knows the end pointer because it was notified of step 2. Thus, the storage device can receive any new commands from the submission queue 304. In NVMe, the storage device can send a TLP request to receive the command(s) from the submission queue 304. In response to receiving the TLP request, the host device 300 sends a completion TLP message with the commands in the submission queue 304. In this context, at the end of step 3, the storage device receives the command(s) from the submission queue 304.

[0043] At step 4, the data storage device processes the command. In one implementation, the data storage device analyzes the commands and determines the steps to execute the commands (e.g., read / write / etc.). For example, the command may include a read command. In response to receiving the read command, the data storage device analyzes the read command, implements address translation, and accesses the flash to receive the data. After receiving the data, the data storage device causes the data to be stored on the host device based on information in the command (e.g., the PRP 1 discussed below). As another example, the command may include a write command.In response to receiving the write command, the data storage device analyzes the write command, determines the location of the data on the host device that is the subject of writing, reads the data from the location on the host device, and writes the data to the flash data storage.

[0044] In particular, the data storage device may receive a read command or write command with a PRP1 pointer. For example, a read command, in which the host device requests the data storage device to read data from the flash data memory, includes a PRP1 pointer pointing to a PRP list. The data storage device receives the PRP list to determine the data storage locations within the host device to write the data read from the flash data memory. As another example, a write command, in which the host device requests the data storage device to write data to the flash data memory, includes a PRP1 pointer pointing to a PRP list. The data storage device receives the PRP list to determine the data storage locations within the host device from which the data should be read (and then to store the read data to the flash data memory).

[0045] Each entry in the PRP list may be associated with a specific section in the host device's data memory and may be of a predetermined size, such as 4Kb. Thus, in a 1Mb transfer, there may be 250 references in the PRP list, each 4Kb in size. In practice, the data storage device may retrieve data out of order. This may occur because the data being retrieved is located on different flash devices, with the devices being available for data retrieval at different times. For example, the data storage device may retrieve the data corresponding to 100-200Kb of the 1Mb transfer before retrieving the data corresponding to 0-100Kb of the 1Mb transfer.Nevertheless, because the data storage device owns the PRP list (and therefore knows the data storage locations where the host device expects the data corresponding to 100-200Kb to be stored), the data storage device can transfer the data corresponding to 100-200Kb of the 1Mb transfer without first fetching the data corresponding to 0-100Kb of the 1Mb transfer.

[0046] In NVMe, multiple PCI Express TLPs may be present to transfer data from the data storage device to the host device 300. Typically, the transferred data is stored in the host data storage 302 of the host device 300 based on an indication in the command (e.g., the command includes an address to store the requested data).

[0047] After completing the data transfer, at step 5, the data storage device controller sends a completion message to the relevant completion queue 306. As mentioned above, during the initialization phase, the host device 300 maps submission queues to completion queues. Thus, the host device 300 knows which commands are completed in the submission queue based on which completion queue the data storage device is writing to. The completion message may contain information about the processing of the command(s), such as whether the command completed successfully or whether an error occurred during the execution of the command.

[0048] After step 5, the host device 300 is unaware that the data storage device has posted to the completion queue 306. This is because the data storage device is causing data to be written to the completion queue 306. In this regard, at step 6, the data storage device notifies the host device 300 that an update to the completion queue 306 has occurred. Specifically, the data storage device posts an interrupt to the host device 300 (e.g., in NVMe, the host device 300 may use an MSle interrupt). As described in more detail below, the data storage device may aggregate the interrupts based on one or more factors.

[0049] In response to receiving the interrupt, host device 300 determines that one or more completion entries for host device 300 are waiting in this completion queue 306. At step 7, host device 300 then processes the entries in completion queue 306.

[0050] After the host has processed the entries from the completion queue 306, at step 8, the host device 300 notifies the data storage device of the entries that the host device 300 has processed from the completion queue 306. This may be accomplished by updating a completion queue beginning ring register 314, which indicates to the data storage device that the host device 300 has processed one or more entries from the completion queue 306. When the host issues a completion queue ring write, the parameters of the relevant interrupt merge vector may be updated to reflect this change. For example, the status of the completion queue may change from a nearly full to a nearly empty status. As a result, an interrupt may be flushed to the host device.

[0051] In response to updating the completion queue beginning ring register 314, the data storage device updates the beginning of the completion queue 306. Given the new beginning, the data storage device identifies which entries in the completion queue 306 have already been processed by the host device 300 and can be overwritten.

[0052] Fig. 4 is a block diagram of other example components of a host system 400 and a data storage device 420. The host system 400 includes one or more processors 402 and the host data memory 404. The host data memory 404 may include physical region pages (RPRs) 406, data buffers 408, one or more submission queues 410, one or more completion queues 412, and other data storage 414.

[0053] Fig. 4 further illustrates a communication interface between the host device 400 and the data storage device 420. In a first implementation (in Fig. 4 not shown), the communication interface between the host device and the data storage device is single-directional, with communication to and from the data storage device on the same path. In a second implementation (in Fig. 4), the communication interface between host device 400 and data storage device 420 is provided on both sides with a separate input path and a separate output path. From the perspective of data storage device 420, the input path contains incoming requests from host device 400 to data storage device 420. Conversely, from the perspective of data storage device 420, the output path contains outgoing requests from data storage device 420 to host device 400.

[0054] The incoming requests (requests from host device 400 to data storage device 420) can be segmented in different ways, such as incoming read requests and incoming write requests. For example, host device 400 can send a read request to read a portion of the data storage in data storage device 420 or a write request to write to a portion of the data storage in data storage device 420 via the input path. Similarly, data storage device 420 can send a read request to a portion of the data storage in host device 400 or a write request to write to a portion of the data storage in host device 400 via the output path.

[0055] In practice, using NVMe, there may be a series of read requests (a request by the host device to read a data unit resident on the data storage device, and vice versa) and a series of write requests (a request by the host device to write data to a location resident on the data storage device, and vice versa). Specifically, in NVMe, the data storage device and the host device communicate with each other using Transaction Layer Packet (TLP) requests, such as TLP read requests to perform a read on the other device or TLP write requests to perform a write on the other device.In one example (where the submit queue and the completion queue are resident on the host device), in response to a TLP write request (sent over the input path) from the host device to the ring register on the data storage device (where the write to the ring register indicates that a command is on the submit queue), the data storage device uses a TLP read request (sent over the output path) to fetch the write command from the submit queue (resident on the host device). Thus, the write command is a request for the data storage device to write data to the non-volatile data storage. The data storage device analyzes the write command for information such as an indication of a PRP pointer (e.g., PRP1) to a PRP list. The PRP list is a set of information such asPointers or addresses that specify the location of the data in the host device. The data storage device then uses another TLP read request to read data from the pointers or address in the PRP list. Afterward, the data storage device performs the write by storing the data in non-volatile data storage (e.g., flash data storage) on the data storage device. After storing the data, the data storage device uses a TLP write request to write an entry to the completion queue (indicating that the write command has been completed). Finally, the data storage device uses a TLP write request to generate an interrupt to the host device, where the interrupt signals to the host device that an entry is present on the completion queue.In response to the interrupt, the host device reads the completion queue entry and then issues a TLP write request to the CQ ring write register indicating that the host device has verified the completion queue entry.

[0056] As another example (with the submission queue and completion queue again resident on the host device), in response to a TLP write request by the host to the ring register on the data storage device (where the write to the ring register indicates that a command is on the submission queue), the data storage device uses a TLP read request to fetch the read command from the submission queue (which is resident on the host device). Thus, the read command is a request for the data storage device to read data from the non-volatile data storage and send the read data to the host device. The data storage device then reads the non-volatile data storage (e.g., flash data storage) to read the data. The data storage device can perform a number of operations on the data, such as:Error correction, encryption / decryption, etc., with memory buffers inserted between each of the series of operations. The data storage device can then parse the read command for information such as an indication of a PRP pointer (e.g., PRP1) to a PRP list. The PRP list is a series of information such as pointers or addresses that specifies the location in the host device where the data read from the non-volatile data storage (and optionally error-corrected, encrypted, etc.) should be stored. The data storage device uses a TLP read request to read data from the pointers or address in the PRP list. The data storage device then uses a TLP write request to write the data read from the non-volatile data storage.After writing the data to the host device, the data storage device uses a TLP write request to write an entry to the completion queue (indicating that the read command has completed). Finally, the data storage device uses a TLP write request to generate an interrupt to the host device, where the interrupt signals to the host device that an entry is present on the completion queue. In response to the interrupt, the host device reads the entry from the completion queue and then issues a TLP write request to the CQ ring write register, indicating that the host device has verified the entry on the completion queue.

[0057] Optionally, the completion queue and the submission queue may reside in the data storage device, such as the control unit data buffer (CMB). In this case, the host device may send a TLP write request (sent via the input path) to the data storage device to write to the submission queue. Similarly, the data storage device may send a TLP write request (sent via the output path) to the host device to generate an interrupt.

[0058] The allocation of data storage to the submission queues and completion queues in the host data storage buffer may be physically contiguous or non-contiguous. In the case of a non-contiguous NVMe submission queue and / or completion queue, a PRP list is provided to the data storage device. The PRP list contains a list of pointers describing the location of each physical portion of the relevant queue, as described in more detail below. In practice, the PRP list is stored in the host device data storage and is not modified throughout the lifetime of the relevant queue. Additionally, a pointer to the PRP list may be used to point to at least a portion of the PRP list. Each of the PRP list and the pointer to the PRP list may be included in the RPRs 406.

[0059] The data storage device 420 includes the data storage device controller 422 and data storage arrays 450. The data storage array 450 may be segmented in various ways, such as into 10 sections, as shown in Fig. 4. The data storage device controller 422 may include one or more processors 424 and integrate one or all of a PCIe MAC and PHY interface 432.

[0060] The command fetch unit 434 is configured to retrieve commands from the submission queues 410 on the host system 400 and queue them internally in the data storage device 420. The command execution unit 436 is configured to dispatch and execute the commands fetched from the submission queues 410. The data transfer scheduling unit 444 is configured to schedule one or more types of data transfers. As an example, read data from different data storage arrays may arrive in parallel. The data transfer scheduling unit 444 may dispatch the different data transfers.

[0061] Direct memory access (DMA) is configured to perform the actual data transfer between the host system 400 and the data storage device 420. The flash interface module 438 is configured to control and access the data storage arrays 450. Fig. 4, the flash interface module 438 also includes the low-density parity check (LDPC) 440, which is a linear error correction code. Other error correction methods are contemplated.

[0062] The instruction collection unit 426 may analyze instructions currently being processed by the data storage device 420. In one implementation, the instruction collection unit 426 may determine the phase of the instructions currently being processed using the phase determination 428. Further, the instruction collection unit 426 may determine an estimated time to complete one or more of the instructions currently being processed by the data storage device 420 using the estimated completion time 430.

[0063] Counter 452 is configured to count the number of entries the data storage device has placed in the completion queue. As described in more detail below, the number reflected by counter 452 can be used to determine when to send an interrupt to the host device reporting the entries on the completion queue. Further, the number of counter 452 can be adjusted based on host latency in responding to the interrupt. For example, the data storage device can include a threshold of 5 entries before sending an interrupt to the host device. In practice, the data storage device uses counter 452 to count the number of entries placed on the completion queue.If the count of counter 452 is equal to 5: (i) the data storage device sends an interrupt to the host device notifying the host device of entries in the completion queue; and (ii) the data storage device sets counter 452 to zero so that the count of the counter is equal to 0. While the host device is servicing the interrupt, the data storage device may place additional entries on the completion queue (such as 2 additional entries) and increment the counter (so that the counter is equal to 2). After the host device notifies the data storage device that the entries on the completion queue have been serviced, the data storage device may determine that 7 entries on the completion queue have been checked by the host device.In this context, the data storage device may decrement the counter (from 2 to 0), reflecting the entries that the host device has processed during the host latency to service the interrupt.

[0064] The completion queue (CQ) and interrupt merging 446 are configured to perform one or more of the following: completion queue and interrupt posting; and interrupt merging. Interrupt merging feedback 448 is configured to monitor the issued interrupts and the responses of the host system 400. Based on the feedback, interrupt merging feedback 448 can adjust or fine-tune the interrupt merging thresholds and parameters, as described in more detail below.

[0065] The merging methodology may depend on a variety of factors. In one implementation, the merging methodology may strictly depend on the current state of the relevant completion queue. In particular, assuming a specific completion queue is empty or nearly empty, the data storage device may assume that the processor(s) 402 on the host system 400 are underutilized. In this case, the data storage device may post the interrupt immediately. On the other hand, if the completion queue is full or nearly full, the data storage device may assume that the processor(s) 402 are busy. In this case, to reduce the load on the processor(s) 402 in the host system 400, the data storage device 420 may merge the interrupts.If the completion queue is neither nearly empty nor nearly full, the processor(s) may not be overloaded and may not be in an idle state. In this case, the data storage device may partially merge the interrupts based on other parameters, as discussed in more detail below. Alternatively or additionally, CQ and interrupt merging 446 may use the estimated time to complete the instructions using the estimated time to complete 430 to determine whether and / or how to merge interrupts, as discussed in more detail below.

[0066] Fig. Figure 5 is a block diagram illustrating the completion queue and interrupt merging. In particular, Fig. 5 illustrates the relationship between a completion queue and the interrupt merging algorithm. For each completion queue, one or more fill levels may be defined. A fill level may include a number of instructions in a particular phase or processing, such as a number of instructions that have finished processing and / or for which an entry has been posted in the completion queue indicating that processing of the instruction has been completed. As discussed above, the data storage device may send an interrupt after an entry has been posted in the completion queue. In an implementation described in Fig. 5, two fill levels are defined to be different levels of fill. The low level may represent the nearly empty state (indicating that the processor on the host has additional capacity), while the high level represents the nearly full state (indicating that the processor on the host may be at or above capacity). In this context, the low level has a number that is smaller than the high level. Although two fill levels are illustrated, one fill level or three or more fill levels are contemplated.

[0067] One or more of the fill levels (such as one or both of the high level and the low level shown in Fig. 5) may be dynamically adjusted or changed based on one or more factors. As an example, the fill level(s) may be modified based on host latency. In particular, the high level and the low level may be modified based on previous interrupts posted to the host system 400 and responses of the host system 400 to the posting (e.g., how long it took the host system 400 to process the interrupt). As another example, one or more fill levels may be modified based on the priority of the instructions in the completion queue. As discussed above, the data storage device may immediately post an interrupt in response to determining a high-priority instruction in the completion queue. Alternatively, the data storage device may adjust the fill levels as in Fig. 5, based on the priority of the commands in the completion queue.

[0068] In practice, if the current level of the associated completion queue is below the low level, the interrupt can be posted immediately, assuming that the host system 400 is not busy. This methodology also solves the problem of shallow queue depth. When the queue depth is shallow, the completion queue level is below the low level, and therefore the interrupt is not merged. If the current level of the associated completion queue is above the high level, the interrupts can be fully merged based on one or more factors (e.g., the TIME and THR parameters configured in the host). Otherwise, the interrupts can be partially merged (e.g., based on currently pending instructions, interrupt merging may be present, but it may have lower TIME and THR values).Thus, interrupts can be partially merged, so that under certain circumstances interrupts are merged and under other circumstances interrupts are not merged.

[0069] Fig. 5 illustrates a single partial merge zone. In an alternative implementation, the partial merge zone in the completion queue may be divided into multiple zones, each with different rules. As an example, the partial merge zone may be segmented into three zones, where the first zone only merges the interrupt when an instruction is estimated to complete very soon (e.g., within a predetermined number of hardware cycles, such as when the read data has already been transferred from the flash data memory and is in the error correction phase). The second zone may merge the interrupt when there is a waiting instruction associated with the same completion queue, even if the data has not been fetched from the flash data memory but is scheduled to.The third zone can merge the interrupt if there is a waiting instruction associated with the same completion queue, even if it is deep queued, that is waiting for service in the data storage device. In one implementation, the partial merge algorithm is limited by the TIME and THR parameters configured in the host device. In an alternative implementation, the partial merge algorithm is not limited by the TIME and THR parameters configured in the host device.

[0070] Fig. 6 is a flowchart 600 of a first example method for merging interrupts. At 602, the data storage device determines whether to merge interrupts. If not, at 608, the interrupt is posted immediately. If yes, one or more aspects are analyzed, such as: one or more aspects of the completion queue (e.g., completion queue ID, completion queue status, etc.); one or more aspects of the instruction(s) (e.g., instruction classification, pending instructions in the data storage device, etc.); the queue depth; and the latency (e.g., host latency, feedback from past decisions, etc.). At 606, the data storage device determines whether to merge the interrupts based on the analysis. If yes, at 610, the interrupts are at least partially merged (e.g., partially or fully merging the interrupts).If not, the interrupt is posted immediately at 608.

[0071] Fig. 7 is a flowchart 700 of a second example method for merging interrupts. In particular, Fig. 7 the dynamic interrupt merging algorithm. At 702, the entry is posted to the completion queue and the interrupt is enabled. In one implementation, at 704, an interrupt may be merged under special circumstances, including: the merging feature is enabled; the relevant completion queue is not marked as a high-priority queue; the instruction is deemed non-urgent; and the instruction completes normally. If so, at 706, the interrupt is posted immediately. Alternatively, merging may be performed for entries in high-priority queues; however, the merging methodology (such as fill levels) may differ from the merging methodology for low-priority queues. As discussed above, the data storage device may determine whether a queue, such asA completion queue is considered a high-priority queue. Examples of high-priority queues include a queue designated as an admin queue and an I / O queue defined by the host as a high-priority queue. In one implementation, when an entry is assigned to a high-priority queue, the data storage device posts interrupts immediately, thus ignoring interrupt aggregation logic.

[0072] If no, at 708 the storage device determines whether the current level of the associated completion queue is below the low level. If yes, at 710 the storage device flushes, if already merged, and posts the interrupt immediately. Otherwise, at 712 the storage device determines whether the current level of the associated completion queue is above the high level. If yes, at 714 the storage device fully merges the interrupts based on the TIME and THR parameters configured in the host. If no, at 716 the interrupts are partially merged, such as based on the TIME and THR parameters and the current status of the storage device (e.g., interrupt merging with lower TIME and THR parameters may occur based on currently pending instructions).

[0073] Fig. 8 is a flowchart 800 of an example method using a counter to aggregate interrupts. At 802, the data storage device determines whether an entry has been posted to a completion queue. If so, at 804, the counter is incremented. Next, at 806, the counter value is compared to a predetermined amount. If the counter value is greater than the predetermined amount, at 808, the interrupt reporting the completion queue entries is sent to the host device, and at 810, the counter value is reset to zero.

[0074] Otherwise, at 812, the data storage device determines whether it has received an acknowledgment from the host device that entries on the completion queue have been verified (e.g., step 8 in Fig. 3). If no, the loop of flowchart 800 returns to 802. If yes, at 814, the data storage device determines the number of completion queue entries that have been checked by the host device. Further, at 816, the data storage device determines whether the number determined at 814 is greater than the predetermined amount + 1. If yes, this indicates that the host device has checked entries that were placed in the completion queue after the counter was reset at 810. To avoid prematurely sending an interrupt, the value of the counter is adjusted at 818 to reflect the number of entries currently in the completion queue that have not been checked by the host device.

[0075] Fig. 9 is a flowchart 900 of an example method for analyzing the queue depth for merging interrupts. As discussed above, instructions pass through multiple phases. The queue depth can be measured in one of several ways. In one way, the queue depth can be measured by the number of instructions currently in phases under the operational control of the data storage device. For example, the data storage device can Fig. 3 by performing various operations. Thus, the number of instructions that the data storage device has fetched but has not reported via an interrupt that they are placed on the completion queue is a measure of the queue depth. At 902, the data storage device determines the current queue depth (such as the current number of instructions in phases 3-6 of Fig. 3). At 904, the data storage device compares the current queue depth to the desired queue depth. In one implementation, the data storage device may have a desired queue depth. The desired queue depth may be predetermined and static, or it may be dynamic based on the current status of the data storage device and / or the host device. In one example, the desired queue depth is equal to 1, meaning the data storage device is processing a single command at a time (such as from phases 3-6).

[0076] At 906, the data storage device determines whether to merge the interrupts based on the comparison at 904. For example, the current queue depth may be less than the desired queue depth, resulting in the data storage device determining that the more instructions may be present in phases 3-6. Thus, at 901, the data storage device merges interrupts. Alternatively, the data storage device may determine that the current queue depth is greater than or equal to the desired queue depth, resulting in the data storage device immediately sending the interrupt to the host device at 908.

[0077] Fig. 10 is a flowchart 1000 of an example method for estimating instruction completion time and host latency for merging interrupts. In one implementation, the data storage device may estimate operations on the data storage device when determining when to send the interrupt to the host device. In another implementation, the data storage device may estimate operations on the host device when determining when to send the interrupt to the host device. For example, the data storage device may determine when to send the interrupt based on host latency so that the host device checks a predetermined number of completion queue entries (e.g., 10 completion queue entries).The data storage device may post the interrupt before all of the predetermined number of entries are written to the completion queue, such that by the time the host device services the interrupt, all of the predetermined number of entries are written to the completion queue (e.g., the interrupt is posted before the 10th entry is written to the completion queue, with sufficient time so that, due to host latency, the data storage device writes the 10th entry by the time the host device services the interrupt). In yet another implementation (illustrated in . Fig. 10), the data storage device may estimate operations on both the data storage device and the host device to determine when to send the interrupt to the host device. At 1002, the data storage device determines whether to factor in the scheduling when to send the interrupt. If no, at 1004, the data storage device sends the interrupt immediately. If yes, at 1006, the data storage device may estimate the time to complete operations on instruction(s) by the data storage device. For example, the data storage device may analyze instructions executed in step 4 of Fig. 3 are (processing the command) to determine whether the estimated time to complete step 4 is within a predetermined period of time.

[0078] At 1008, the data storage device may similarly estimate the host device latency in responding to the interrupt. As part of the estimation for operations on the host device, the data storage device may compile statistics and project / emulate the host's processing speed for the completion queue. In one implementation, the data storage device may use a hardware engine configured to estimate the host-side completion queue depth at any given time. In this context, the data storage device may factor the host-side completion queue depth into the interrupt scheduling methodology, in addition to the actual indications transmitted by the host device. The output of the hardware engine may be considered the "current level of CQ" and may be Fig. 10 or at 708 in Fig.7 may be used. At 1010, the data storage device may send the interrupt based on the estimated time to completion at 1006 and the estimated host device latency at 1008.

[0079] As an example, the storage device may estimate that at a predetermined time in the future (such as in a few hardware cycles of the storage device), the storage device will post another completion to the same completion queue. In this case, the storage device may post the interrupt after posting the second completion entry, thereby avoiding posting an interrupt message to the host. The storage device may also consider host device latency (including PCIe round trip time) and send the interrupt to the host device immediately before posting the second completion queue entry. Thus, the storage device may schedule the interrupt so that the second completion entry is on the completion queue when the host device fetches the entries.

[0080] Finally, as mentioned above, any type of data storage may be used. Semiconductor data storage devices include volatile data storage devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM"), non-volatile data storage devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of data storage device can have different configurations. For example, flash data storage devices can be configured in a NAND or NOR configuration.

[0081] The data storage devices may be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching memory element such as an anti-fuse, phase-change material, etc., and optionally a steering element such as a diode, etc. Further, as a non-limiting example, active semiconductor data storage elements include EEPROM and Flash data storage device elements, which in some embodiments include elements including a charge storage region such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0082] Multiple data storage elements may be configured to be connected in series or so that each element is individually accessible. As a non-limiting example, flash data storage devices in a NAND (NAND data storage) configuration typically include data storage elements connected in series. A NAND data storage array may be configured such that the array is composed of multiple chains of data storage, where a chain is composed of multiple data storage elements that share a single bit line and are accessed as a group. Alternatively, data storage elements may be configured so that each element is individually accessible, such as a NOR data storage array. NAND and NOR data storage configurations are exemplary, and data storage elements may be configured in other ways.

[0083] The semiconductor data storage elements located within and / or above a substrate may be arranged in two or three dimensions, such as a two-dimensional data storage structure or a three-dimensional data storage structure.

[0084] In a two-dimensional data storage structure, the semiconductor data storage elements are arranged in a single plane or a single data storage device plane. Typically, in a two-dimensional data storage structure, data storage elements are arranged in a plane (e.g., in a plane in the xz direction) that extends substantially parallel to a major surface of a substrate supporting the data storage elements. The substrate may be a wafer over or in which the layer of data storage elements is formed, or it may be a carrier substrate that is attached to the data storage elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0085] The data storage elements may be arranged in an ordered array, such as multiple rows and / or columns, within the single data storage device layer. However, the data storage elements may be arranged in non-regular or non-orthogonal configurations. The data storage elements may each have two or more electrodes or contact lines, such as bit lines and word lines.

[0086] A three-dimensional data storage array is arranged such that data storage elements occupy multiple levels or multiple data storage device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, with the y direction being substantially perpendicular and the x and z directions being substantially parallel to the main surface of the substrate).

[0087] As one non-limiting example, a three-dimensional data storage structure may be arranged vertically as a stack of multiple two-dimensional data storage device levels. As another non-limiting example, a three-dimensional data storage array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple data storage elements in each column. The columns may be arranged in a two-dimensional configuration, e.g., in an xz-plane, resulting in a three-dimensional array of data storage elements with elements on multiple vertically stacked data storage levels. Other configurations of data storage elements in three dimensions may also form a three-dimensional data storage array.

[0088] As a non-limiting example, in a three-dimensional NAND data storage array, the data storage elements may be coupled together to form a NAND chain within individual horizontal (e.g., xy) data storage device planes. Alternatively, the data storage elements may be coupled together to form a vertical NAND chain spanning multiple horizontal data storage device planes. Other three-dimensional configurations are conceivable, with some NAND chains including data storage elements in a single data storage plane, while other chains include data storage elements spanning multiple data storage planes. Three-dimensional data storage arrays may also be constructed in a NOR configuration and in a ReRAM configuration.

[0089] Typically, in a monolithic three-dimensional data storage array, one or more data storage device levels are formed above a single substrate. Optionally, the monolithic three-dimensional data storage array may further include one or more data storage layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers forming each data storage device level of the array are typically formed on top of the layers of the underlying data storage device levels of the array. However, layers of adjacent data storage device levels of a monolithic three-dimensional data storage array may be shared or may include intermediate layers between data storage device levels.

[0090] In turn, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic data storage device having multiple data storage layers. For example, non-monolithic stacked data storage devices can be constructed by forming data storage layers on separate substrates and then stacking the data storage layers on top of each other. The substrates can be thinned or removed from the data storage device layers before stacking, but because the data storage device layers are initially formed over separate substrates, the resulting data storage arrays are non-monolithic three-dimensional data storage arrays. Furthermore, multiple two-dimensional data storage arrays or three-dimensional data storage arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked-chip data storage device.

[0091] Dedicated circuitry is used to operate the data storage elements and to communicate with the data storage elements. As non-limiting examples, data storage devices may include circuitry used to control and drive data storage elements to achieve functions such as programming and reading. This dedicated circuitry may be on the same substrate as the data storage elements and / or on a separate substrate. For example, a controller for data storage read / write operations may be located on a separate controller chip and / or on the same substrate as the data storage elements.

[0092] It is intended that the foregoing detailed description be understood as an illustration of selected forms the invention may take, rather than as a definition of the invention. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it is to be understood that any aspect of any of the preferred embodiments described herein may be used alone or in combination with one another.

Claims

[1] Procedure that includes: Determine that the processing of one or more instructions on a data storage device (100) is complete; Analyzing one or more aspects of a completion queue (412) comprising analyzing the filling of the completion queue, wherein the analysis compares one level of filling of the completion queue with at least two levels; Determine, based on analysis, when to generate an interrupt for a host device (252, 400), wherein the interrupt for the host device indicates that the processing of one or more instructions on the completion queue is complete, wherein, in response to a determination that the fill level is below a first level (708), it is determined to immediately generate the interrupt for the host device (608, 710), wherein, in response to a determination (712) that the fill level is above a second level, it is determined to wait to generate the interrupt for the host device, and wherein, in response to a determination that the fill level is between the first and second levels, it is determined to partially merge the interrupt for the host device (610, 716); and Sending the interrupt to the host device (252, 400) in response to determining when to generate the interrupt for the host device. [2] Method according to claim 1, wherein determining when to generate the interrupt for the host device (252, 400) comprises: Determine whether the notification of completion of a first order should be merged with the notification of completion of a second order; and In response to the determination not to merge the interrupt, the interrupt is immediately sent to the host device (252, 400). [3] Method according to claim 1, wherein analyzing one or more aspects of the completion queue comprises analyzing an identification that is associated with the completion queue; where the identification assigned to the completion queue indicates a priority of the completion queue; and including determining, based on analysis, when to generate the interrupt for the host device (252, 400), and determining, based on the priority of the completion queue, when to generate the interrupt for the host device. [4] Method according to claim 3, wherein the identification associated with the completion queue comprises an associated identification with a transmission queue; where the priority of the completion queue includes a priority of the submission queue; and including determining when to generate the interrupt for the host device (252, 400), and determining, based on the priority of the transmission queue, when to generate the interrupt for the host device (252, 400). [5] Method according to claim 1, wherein the two levels are predetermined. [6] Method according to claim 1, wherein the two levels are determined dynamically. [7] Method according to claim 1, further comprising analyzing one or more aspects of the one or more instructions, including determining an instruction type; and wherein determining, based on the analysis, when the interrupt for the host device (252, 400) should be generated, includes determining, based on the instruction type, whether the interrupt should be merged with another interrupt or whether the interrupt should be sent immediately. [8] Method according to claim 1, further comprising analyzing one or more aspects of the one or more instructions, including determining pending instructions for execution in the data storage device (100); and wherein determining, based on the analysis, when to generate the interrupt for the host device (252, 400), includes determining, based on pending instructions for execution, whether to merge the interrupt with another interrupt or to send the interrupt immediately. [9] Non-volatile data storage device (100, 420) containing: a non-volatile data storage device (104, 450); a communication interface (120) configured to communicate with a host device (252, 400) so that the data storage device (100, 420) posts entries to a completion queue (412); and a control unit (102, 422) in communication with the non-volatile data storage (104, 450) and the communication interface (120), wherein the control unit (102, 422) is configured to: Determine that the processing of one or more instructions on the data storage device is complete; Analyzing one or more aspects of the completion queue, including analyzing the fill level of the completion queue, wherein the analysis compares one level of fill level of the completion queue with at least two levels; Determine, based on analysis, when to generate a host device interrupt, wherein the host device interrupt indicates that the processing of one or more instructions on the completion queue is complete; in response to a determination that the fill level is below a first level (708), determine to immediately generate the host device interrupt (608, 710); in response to a determination (712) that the fill level is above a second level, determine to wait to generate the host device interrupt; and in response to a determination that the fill level is between the first and second levels, determine to partially merge the host device interrupt (610, 716); and Sending the interrupt to the host device in response to determining when the interrupt should be generated for the host device. [10] Data storage device according to claim 9, wherein analyzing one or more aspects of the completion queue comprises analyzing an identification that is associated with the completion queue; where the identification assigned to the completion queue indicates a priority of the completion queue; and which includes determining, based on analysis, when to generate the interrupt for the host device, and determining, based on the priority of the completion queue, when to generate the interrupt for the host device. [11] Data storage device according to claim 10, wherein the identification associated with the completion queue comprises an associated identification with a transmission queue; where the priority of the completion queue includes a priority of the submission queue; and including determining when to generate the interrupt for the host device (252, 400), and determining, based on the priority of the transmission queue, when to generate the interrupt for the host device (252, 400). [12] Data storage device according to claim 9, wherein the two levels are predetermined. [13] Data storage device according to claim 9, wherein the two levels are dynamically determined. [14] Non-volatile data storage device (100, 420) containing: a non-volatile data storage device (104, 450: a communication interface (120) configured to communicate with a host device (252, 400) so that the data storage device (100, 420) posts entries to a completion queue (412); Means of determining that the processing of one or more instructions on the data storage device has been completed; Means for analyzing one or more aspects of the completion queue comprising analyzing the fill level of the completion queue, wherein the analysis compares one level of fill level of the completion queue with at least two levels; Means for determining, based on analysis, when to generate a host device interrupt (252, 400), wherein the host device interrupt indicates that the processing of one or more instructions on the completion queue is complete, wherein, in response to a determination that the fill level is below a first level (708), it is determined to immediately generate the host device interrupt (608, 710), wherein, in response to a determination (712) that the fill level is above a second level, it is determined to wait to generate the host device interrupt, and wherein, in response to a determination that the fill level is between the first and second levels, it is determined to partially merge the host device interrupt (610, 716); and Means of sending the interrupt to the host device in response to determining when the interrupt should be generated for the host device. [15] Data storage device according to claim 14, comprising means for dynamically determining the first level and / or the second level. [16] Data storage device according to claim 15, wherein the means for dynamically determining the first level and / or the second level are based on the host latency, wherein the host latency specifies a time period for the host device (252, 400) to respond to the interrupt. [17] Data storage device according to claim 15, wherein the means for dynamically determining the first level and / or the second level are based on the priority of instruction entries in the completion queue (412).

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