Method for manufacturing a semiconductor device with a channel stopper region

Abstract

Method for manufacturing a semiconductor device, comprising: Forming a channel stopper area (191) extending from a planar, horizontal first main surface (701) into a component layer (710) of a first conductivity type in an edge termination area (690) adjoining a saw track area (800) of a component area (600), wherein the formation of the channel stopper area (191) comprises forming a first dopant mask (410) on the first main surface (701) and introducing a first dopant (195) through a mask opening (415) of the first dopant mask (410), wherein the first dopant (195) is introduced through sections of the first main surface (701) exposed through the mask opening (415) of the first dopant mask (410); and Forming a doped area (120) extending from the first main surface (701) into the component layer (710) in the component area (600), wherein the channel stopper area (191) is formed by means of a photolithographic process which is carried out prior to a first photolithographic process for introducing dopants into a section of the component area (600) outside the channel stopper area (191), and where in the component area (600) a maximum vertical extent (v1) of the channel stopper area (191) perpendicular to the first main surface (701) is greater than a maximum lateral extent (w1) of the channel stopper area (191) in the component area (600) parallel to the first main surface (701).

Description

TECHNICAL FIELD

[0001] The present application relates to semiconductor devices with comparatively high blocking capability, e.g. power semiconductor diodes and power semiconductor switches. BACKGROUND

[0002] Vertical power semiconductor devices are based on a semiconductor body with the first load electrode on the front and the second load electrode on the back. In the blocking state, the electric field between the two load electrodes is reduced vertically in a central, active region of the semiconductor body. Along the side faces of the semiconductor body, the blocking capability is significantly lower than in the bulk and is also more difficult to control. Edge termination structures on the front face of the device aim to reduce the electric field laterally, so that the side face of the semiconductor body remains field-free. These edge termination structures can include, among other things, doped channel-stopper regions that typically extend from the front face into the semiconductor body near the outer edge of the semiconductor die.

[0003] German patent application DE 10 2015 105 016 A1 describes a vertical semiconductor device with a p-doped body region in an active region and a p-doped channel stop termination region that has a smaller vertical extent than the body region. German patent application DE 10 2015 212 464 A1 describes a vertical semiconductor device with a channel stop region that has the same vertical extent as a body region in the active edge region of the semiconductor device. A semiconductor device described in German patent application DE 10 2005 031 908 B3 has a channel stop zone formed in the edge region and spaced from the device edge. German patent application US 2017 / 0 323 958 A1 relates to an IGBT with a polycrystalline semiconductor layer as the back-side p+ emitter, which is doped after completion of doped regions on the front side of the device.

[0004] German patent application DE 10 2012 209 429 A1 describes a vertical power semiconductor device with an insulator trench circumferentially on the top surface. A vertical channel stop section is incorporated into the outer side wall of the insulator trench. A lateral channel stop section can extend from the insulator trench to the chip edge or to a second trench. Doped side walls of the second trench limit the lateral extent of the space charge region. A saw cut can intersect the second trench.

[0005] The present disclosure aims to increase the reliability of edge closure structures. SUMMARY

[0006] The present disclosure relates to a method for manufacturing a semiconductor device. A channel stopper region is formed which extends from a first main surface of a semiconductor substrate into a device layer of a first conductivity type in an edge termination region of a device area adjoining a saw-track region and is adjacent to or slightly spaced from the saw-track region.

[0007] The component area corresponds to a section of the semiconductor substrate that the semiconductor device encompasses at a minimum. The saw track area refers to the portion of the semiconductor substrate from which a process that removes the semiconductor devices from a semiconductor substrate composite can remove material without negatively affecting the component properties of the semiconductor device. For example, a sawing process removes material from a saw track within the saw track area, which extends beyond the actual saw track. Therefore, in addition to the actual component area, the semiconductor device may still exhibit residual sections of the original saw track area along its lateral sides.

[0008] Subsequently, a doped region of the first or a complementary second conductivity type is formed in the component area at a first distance from the channel stopper region. This region extends from the first main surface into the component layer. The channel stopper region is formed using a photolithographic process, which is performed prior to a first photolithographic process for introducing dopants into a section of the component area outside the channel stopper region.

[0009] In vertical devices with a load current flowing between a front and back face, the channel stopper region, in blocking mode, prevents the lateral propagation of a space charge zone towards the device edge. The channel stopper region can be the outermost area on the front face of the device, where the doping level is higher than the base doping level. The channel stopper region can completely enclose a central section of the device area.

[0010] Early formation of the channel stopper region, before any other laterally structured doped regions have formed in the component area (e.g., the anode region of a semiconductor diode or the source and body regions of transistor cells), allows for a higher temperature budget to be used for channel stopper region formation, as this temperature budget does not affect other doped regions. This free temperature budget can be used, for example, for deep diffusion of a suitable dopant or for the use of slow-diffusion dopants in the channel stopper region, thus making it possible to design the channel stopper region with a comparatively large vertical extent.

[0011] If the vertical extent of the channel stopper region exceeds that of the doped region by at least a factor of 2, for example by a factor of 4 or by more than a factor of 10, then, in the case of blocking, a space charge region propagating from the inner component area towards the outer edge of the semiconductor body encounters the channel stopper region in a section where areas of equal dopant concentration exhibit relatively low curvature. This reduces field peaks in the edge termination region, and the blocking capability of the semiconductor device is less affected by electrical charges that can accumulate at energetically favorable positions at interfaces in the region of an edge termination structure or in passivation layers above the edge termination structure, and which can negatively influence the electric field distribution. The robustness of the semiconductor device against external charges and moisture-induced corrosion is improved.During the manufacturing of the semiconductor device, deep channel stopper regions can reduce chipping effects when separating it from the wafer composite.

[0012] Forming the channel stopper region comprises forming a first dopant mask on the first main surface and introducing a first dopant through a mask opening in the first dopant mask, wherein the mask opening can expose at least one section of the saw track region adjacent to or slightly spaced from the component area, so that, with the same vertical extent, the lateral width of the channel stopper region can be reduced and the area efficiency of the semiconductor device can be improved.

[0013] The first dopant is introduced through sections of the first main surface exposed by the mask opening of the first dopant mask. According to one embodiment, after the introduction of the first dopant, a process sequence can be carried out at least once more, comprising removing the first dopant mask, applying another component layer, forming another first dopant mask with a mask opening that exposes at least one section of the saw track area adjacent to the component area, and introducing the first dopant through the mask opening.

[0014] By using such a procedure, in which epitaxy and implantation alternate several times (“Multi-Epi / Multi-Implant”), the ratio of the vertical extent to the lateral extent of the canal stopper area can be further improved.

[0015] If a trench extending from the first main surface into the component layer is formed before the introduction of the first dopant, the first dopant can be introduced into the component layer through an inner surface of the trench. Such a trench further improves the ratio of vertical to lateral extent of the channel stopper region without increasing the required temperature budget. The trench can be formed partially or completely within the saw track region and filled with doped semiconductor material, which can serve as the source of the first dopant. The trench can be designed as an annular trench that completely encloses an active region laterally and can shield the active region against cracking and chipping effects when individual semiconductor bodies are separated from the semiconductor substrate along a saw track within the saw track region.

[0016] The channel stopper region can be formed, at least partially, by thermomigration. For this purpose, an n- or p-doping dopant source is applied to the semiconductor surface to be doped, and then the dopant is driven into the disk by creating a targeted vertical temperature gradient.

[0017] According to one embodiment, the first dopant contains phosphorus and / or selenium and / or sulfur. If, for example, the introduction of phosphorus and / or selenium and / or sulfur is followed by a high-temperature treatment at a temperature above 1000°C, which is carried out before the formation of the doped region in the inner component area, the first dopant can distribute itself over a comparatively deep diffusion region, with sections of the diffusion region in the component areas forming the channel stopper regions.

[0018] The high-temperature treatment of the semiconductor substrate can, for example, be carried out in an oxygen-containing environment at a temperature above 1000°C, whereby an oxide layer forms on the first main surface. The formation of channel-stopper regions can therefore be effectively combined, for example, with the elimination of near-surface crystal defects by growing an oxide layer or with the formation of a scattering oxide, so that deep channel-stopper regions can be provided with comparatively little additional effort. According to one embodiment, the diffusion, which occurs directly after the introduction of the dopant required for the channel-stopper region, e.g., by ion implantation, takes place at least temporarily in a moist-oxidizing atmosphere, since under these conditions a very high concentration of interstitial silicon is present, leading to a greatly accelerated diffusion of the phosphorus or selenium atoms.

[0019] According to one embodiment, the formation of channel stopper regions includes plasma deposition of phosphorus, which involves comparatively high implantation doses of greater than 1 × 10 17 cm -2 This enables the resulting high density of implanted phosphorus to support the diffusion of phosphorus at comparatively strong doping gradients, thus enabling deep channel stopper regions with a comparatively low temperature / time budget during the furnace process.

[0020] Forming the channel stopper region can involve the formation of hydrogen-correlated donors within the channel stopper region. Hydrogen-correlated donors can be generated by implanting protons with a comparatively long range in the semiconductor substrate, thus further increasing the net doping of the channel stopper region at a distance from the first main surface.

[0021] The channel stopper region can completely enclose an inner central area of ​​the device area. Within the device area, the vertical extent of the channel stopper region can decrease strictly monotonically with increasing distance from the saw track area. The maximum vertical extent of the channel stopper region perpendicular to the first principal surface is greater than the lateral extent parallel to the first principal surface, so that the gain in depth of the channel stopper region hardly reduces the area efficiency of a semiconductor device.

[0022] The first dopant is introduced into the edge termination region through the first main surface. According to a further embodiment, a method for manufacturing a semiconductor device comprises introducing a first dopant into at least one section of a saw-track region of a semiconductor substrate adjacent to or spaced apart from a device region, wherein a channel stopper region extending laterally from the saw-track region into the device region is formed. A doped region is formed in the device region and at a distance from the channel stopper region, which forms a pn junction with a drift layer in the semiconductor substrate. The vertical extent of the channel stopper region in the device region is greater than its lateral extent. In the device region, the dopant concentration in the channel stopper region can decrease strictly monotonically with increasing distance from the saw-track region.

[0023] Forming a channel stopper region by introducing a dopant at least partially into a section of the saw track area adjacent to or separated from the component area enables a comparatively deep and narrow channel stopper region in the component area, so that the robustness of the edge termination structure against charges above the semiconductor surface can be increased without loss of active area.

[0024] The first dopant can comprise at least one of the dopants phosphorus, selenium, or sulfur. A high-temperature treatment can diffuse out the first dopant, wherein the high-temperature treatment can be carried out in an oxidizing atmosphere, and according to one embodiment, in a moist oxidizing atmosphere, so that during the high-temperature treatment an oxide layer is formed on the first main surface and the formation of deep channel-stopper regions can be effectively linked to the elimination of crystal defects, for example, so-called crystal-originated particles (COPs).

[0025] If a trench extending from the first main surface into the component layer is formed before the introduction of the first dopant, the first dopant can be introduced into the component layer through an inner surface of the trench. Such a trench improves the ratio of vertical to lateral extent of the channel stopper area between the introduction of the first dopant and the formation of doped regions in the component area, even without high-temperature treatment.

[0026] Further features and advantages of the disclosed item will become apparent to the person skilled in the art from the following detailed description and from the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings provide a deeper understanding of the invention, are incorporated into the disclosure, and form part of it. The drawings illustrate embodiments of the present invention and, together with the description, explain the principles of the invention. Further embodiments of the invention and intended advantages will become apparent from understanding the detailed description below. Fig. Figure 1 is a simplified flowchart for a process for manufacturing a semiconductor device with a deep channel stopper region according to one embodiment. Fig. Figure 2A is a schematic vertical cross-section through a section of a semiconductor substrate to illustrate a method for manufacturing a semiconductor device according to one embodiment, after forming a channel stopper region. Fig. 2B is a schematic vertical cross-section through the semiconductor substrate section according to Fig. 2A, after forming a doped area at a distance from the channel stopper area. Fig. Figure 3A is a schematic vertical cross-section through a semiconductor device with a deep channel stopper region to illustrate the embodiments. Fig. Figure 3B is a schematic diagram illustrating the dependence of a breakdown voltage on an external negative charge and on a vertical extent of the deep channel stopper region according to the Fig. 3A for an explanation of the embodiments. Fig. Figure 4A shows a first vertical doping profile for a channel stopper area based on the implantation of phosphorus and subsequent high-temperature treatment to illustrate the embodiments. Fig. Figure 4B shows a second vertical doping profile for a channel stopper area based on the implantation of phosphorus and subsequent high-temperature treatment to illustrate the embodiments. Fig. Figure 4C shows a third vertical doping profile for a channel stopper region based on the implantation of phosphorus and subsequent high-temperature treatment to illustrate the embodiments. Fig. Figure 4D shows a fourth vertical doping profile for a channel stopper area based on the implantation of phosphorus and subsequent high-temperature treatment to illustrate the embodiments. Fig. Figure 5A is a schematic vertical cross-section through a section of a semiconductor substrate to illustrate a method for producing deep, n-doped channel stopper regions according to an embodiment comprising high-dose phosphorus implantation following the implantation of phosphorus. Fig. 5B is a schematic vertical cross-section through the semiconductor substrate section according to Fig. 5A after high-temperature treatment. Fig. 5C is a schematic vertical cross-section through the semiconductor substrate section according to Fig. 5B after formation of p-doped regions at a distance from the channel stopper regions. Fig. 5D is a schematic vertical cross-section through a section of the semiconductor substrate according to Fig. 5C Semiconductor body of a semiconductor device separated by sawing. Fig. 6A is a schematic vertical cross-section through a section of a semiconductor substrate with a first dopant mask having a mask opening spaced away from the sawing area. Fig. 6B is a schematic vertical cross-section through a section of a semiconductor substrate with a first dopant mask with a mask opening adjacent to the sawing area. Fig. 6C is a schematic vertical cross-section through a section of a semiconductor substrate with a first dopant mask according to an embodiment with a mask opening overlapping the saw area. Fig. Figure 6D is a schematic vertical cross-section through a section of a semiconductor substrate with a first dopant mask according to an embodiment with a mask opening formed exclusively in the sawing area. Fig. 7A is a schematic vertical cross-section through a section of a semiconductor substrate with a saw track at a distance from a channel stopper region. Fig. 7B is a schematic vertical cross-section through a section of a semiconductor substrate according to an embodiment with a saw track adjacent to a channel stopper area. Fig. 7C is a schematic vertical cross-section through a section of another semiconductor substrate according to an embodiment with a saw track adjacent to a channel stopper region. Fig. 7D is a schematic vertical cross-section through a section of a semiconductor substrate according to another embodiment with a saw track adjacent to a channel stopper area. Fig. 7E is a schematic vertical cross-section through a section of a semiconductor substrate with a channel stopper region spaced apart from the saw track region. Fig. Figure 8A is a schematic vertical cross-section through a section of a semiconductor substrate to illustrate a method for producing deep n-doped channel stopper regions comprising the formation of trenches, after the trenches have been formed. Fig. 8B is a schematic vertical cross-section through the semiconductor substrate section according to Fig. 8A after high-temperature treatment. Fig. 8C is a schematic vertical cross-section through the semiconductor substrate section according to Fig. 8B after forming p-doped regions at a distance from the channel stopper regions. Fig. 8D is a schematic vertical cross-section through a section of the semiconductor substrate according to Fig. 8C Semiconductor body of a semiconductor device separated by sawing. Fig. Figure 9 is a simplified flowchart for a method for manufacturing a semiconductor device with a deep channel stopper region according to a further embodiment. Fig. Figure 10A is a schematic vertical cross-section through a section of a semiconductor substrate to illustrate a method for forming deep channel stopper regions comprising the formation of trenches, after forming the trenches. Fig. 10B is a schematic vertical cross-section through the semiconductor substrate section according to Fig. 10B after forming doped areas at a distance from the channel stopper areas. Fig. 10C is a schematic vertical cross-section through a section of the semiconductor substrate according to Fig. 10B Semiconductor body of a semiconductor device separated by sawing. DETAILED DESCRIPTION

[0028] The following detailed description refers to the accompanying drawings, which form part of the disclosure and show specific embodiments for illustrative purposes. In particular, elements of the embodiments described below can be combined with elements of other described embodiments, unless otherwise indicated by the context.

[0029] The terms "have," "contain," "comprise," "exhibit," and the like are, in the following, open terms that indicate the presence of the aforementioned elements or characteristics, but do not exclude the presence of further elements or characteristics. The indefinite and definite articles include both the plural and the singular, unless the context clearly indicates otherwise.

[0030] Some figures represent relative dopant concentrations by indicating "-" or "+" next to the dopant type. For example, "n-" means a dopant concentration that is lower than the dopant concentration of an "n"-doped region, while an "n+"-doped region has a higher dopant concentration than the "n"-doped region. The indication of a relative dopant concentration does not mean that doped regions with the same relative dopant concentration must have the same absolute dopant concentration unless otherwise stated. For example, two different "n"-doped regions may have the same or different absolute dopant concentrations.

[0031] The Fig. 1 refers to a method for manufacturing a semiconductor device, for example a vertical power semiconductor device, such as a semiconductor diode, an IGBT (insulated gate bipolar transistor) or an HVMOS-FET (high voltage metal oxide semiconductor field effect transistor).

[0032] A channel-stopper region extending from a first main surface into a component layer of a first conductivity type is formed in a component area adjoining a saw-track region, the channel-stopper region being able to border the saw-track region (902). Subsequently, a doped region extending from the first main surface into the component layer within the component area, of the first or of a complementary second conductivity type, is formed at a first distance from the channel-stopper region (904). The channel-stopper region is formed by means of a photolithographic process, which is carried out prior to a first photolithographic process for introducing dopants into a section of the component area outside the channel-stopper region.

[0033] The Fig. 2A and Fig. 2B illustrate the procedure of Fig. 1 based on cross-sections through a semiconductor substrate 700.

[0034] The semiconductor substrate 700 is based on single-crystal semiconductor material, for example silicon, germanium, a silicon-germanium mixed crystal, silicon carbide or an A III B V Compound semiconductors, for example GaN or GaAs.

[0035] On the front side, the semiconductor substrate 700 has a largely planar first main surface 701, and on the back side, a second main surface 702 that is essentially parallel to the first main surface 701. A direction perpendicular to the first main surface 701 defines a vertical direction. Directions parallel to the first main surface 701 are lateral or horizontal directions.

[0036] The semiconductor substrate 700 comprises at least one component layer 710 adjoining the first main surface 701, which is unstructured over its entire vertical and lateral extent in the lateral direction, is uniformly doped at least in the lateral direction, and has no laterally separated doped regions. The component layer 710 is of a first conductivity type, for example, n-doped.

[0037] In the vertical direction, the dopant concentration in the component layer 710 can be constant or vary depending on the distance to the first main surface 701.

[0038] The semiconductor substrate 700 can also include a substrate section 780, which may have a different conductivity type than the component layer 710. For example, the substrate section 780 is a starting substrate sawn from a semiconductor crystal, on which the component layer 710 has grown as an epitaxial layer.

[0039] The semiconductor substrate 700 has component areas 600 arranged in a regular pattern in columns and rows. A grid-like saw-track area 800 separates adjacent component areas 600 from one another. Each component area 600 comprises a central active area 610 and a laterally enclosing edge termination area 690 that separates the active area 610 from the saw-track area 800.

[0040] The actual saw mark lies within saw mark area 800 and does not necessarily coincide with a boundary line between component area 600 and saw mark area 800. This boundary line can be defined such that a deviation of the saw mark beyond the boundary line into component area 600 leads to a reduction in the breakdown voltage. In saw mark area 800 below a channel stopper region, the maximum field strength occurring when the breakdown voltage is applied is < 100 V / cm.

[0041] In the active region 610, semiconductor elements are subsequently formed that determine the nominal functionality of a semiconductor device, for example, an anode region of a semiconductor diode, switchable transistor cells of a MOSFET, a MGD (MOS-gated diode), an IGBT, or a thyristor, or a charge collection zone of a radiation detector. Such semiconductor elements are absent in the edge region 690. The edge region may have an edge termination structure that ensures a minimum blocking capability of the edge region, e.g., field rings, a JTE (junction termination extension) region, or a VLD (variation of lateral doping) region.

[0042] A first mask layer is applied to the first main surface 701 and structured by a photolithographic process. Subsequently, a first dopant 195 is introduced into predefined sections of the component layer 710 through mask openings 415 of a first dopant mask 410 resulting from the first mask layer, wherein the first dopant is of the conductivity type of the component layer 710.

[0043] The first dopant 195 can contain phosphorus, selenium, and / or sulfur as well as hydrogen-correlated donors generated by implantation of protons for a silicon semiconductor substrate 700 with n-doped component layer 710, and, for example, aluminium or boron for a semiconductor substrate 700 with p-doped component layer 710.

[0044] Fig. Figure 2A shows the first dopant mask 410 resulting from the first mask layer, with a mask opening 415 that can completely enclose the active area 610 laterally and is formed at a distance from the active area 610. The mask opening 415 can be formed completely within the edge termination area 690 and at a distance from the saw mark area 800, can be adjacent to the saw mark area 800, can be formed exclusively within the saw mark area 800, or can overlap both the edge termination area 690 and the saw mark area 800. The first dopant 195 is introduced into the sections of the component layer 710 exposed by the mask opening 415.

[0045] During a subsequent high-temperature treatment, the first dopant 195 diffuses laterally and vertically. The first dopant mask 410 is removed. A second mask layer is applied and structured using a photolithographic process. Through mask openings 425 of a second dopant mask 420 formed from the first, a second dopant is introduced into predefined sections of the component layer 710.

[0046] Fig. Figure 2B shows the second dopant mask 420 with a mask opening 425 in the active region 610, as well as a doped region 120 containing the second dopant in a section of the component layer 710 exposed by the mask opening 425. The doped region 120 forms a first pn junction pn1 with a section of the component layer 710 that remains unaffected by the two implantations and forms a drift layer 731. The doped region 120 forms, for example, the anode region of a power semiconductor diode or a dopant well for forming body regions of transistor cells of MOSFETs or IGBTs. For simplicity, only one contiguous body region is shown here. In reality, a multitude of body regions are typically created.

[0047] The doped region 120 is formed at a lateral distance from a channel stopper region 191, which is formed from the vertical and lateral diffusion of the first dopant 195 of the Fig. 2A emerges. The channel stopper region 191 is of the same conductivity type as the component layer 710 and forms a unipolar transition jn with the drift layer 731, for example an n- / n+ transition or a p- / p+ transition, wherein the position of the unipolar transition jn is determined by the locations of maximum dopant concentration change on lines that intersect the unipolar transition jn.

[0048] Since no other doped regions have yet formed in component layer 710 at the time of the formation of the channel stopper region 191, a large temperature budget is available for the formation of the channel stopper region 191. This budget can be used to provide the channel stopper region 191 with a comparatively large maximum vertical extent v1 compared to the maximum vertical extent v2 of the doped region 120. For example, the maximum vertical extent v1 or depth of the channel stopper region 191 is at least twice, for example at least five times, or at least ten times the maximum vertical extent v2 of the doped region 120.

[0049] If the mask opening 415 of the first doping mask 410 overlaps at least partially the saw track area 800, then the lateral area requirement of the channel stopper area 191 within the component area 600 can be further reduced. According to one embodiment, the maximum vertical extent v1 of the channel stopper area 191 is at least as large as the maximum lateral extent w1, for example, at least twice or at least five times.

[0050] As a consequence, the unipolar transition jn between the drift layer 731 and the channel stopper region 191 at a distance from the first main surface 701, corresponding to the maximum vertical extent v2 of the doped region 120, exhibits only a comparatively small curvature, so that in the case of obstruction, a "run-up" of the space charge zone onto the channel stopper region 191 does not generate any field peaks, or only field peaks that are greatly reduced compared to field peaks when "running up" onto a section of the channel stopper region with strong curvature.

[0051] The Fig. Sections 3A to 3B refer to semiconductor diodes 500 produced using the described method, with a doped region 120 forming the anode region on the front face of the component. A JTE region 125 adjoins the doped region 120 in the edge termination region 690. An n+ doped channel stopper region 191 extends from a first surface 101 into the semiconductor body 100 along a side surface 103. The channel stopper region 191 forms an n- / n+ junction with an n- doped drift zone 131 that separates the p-doped regions 120, 125 on the front face from a more heavily doped cathode layer on the back face of the component, and in which the electric field decays in the vertical direction when the device is reverse-biased.

[0052] The maximum doping concentration in channel stopper area 191 is approximately 5 × 10 18 cm -3. The maximum vertical extent v1 of the channel stopper area 191 is approximately twice the maximum lateral extent w1 and approximately five times the maximum vertical extent v2 of the doped areas 120, 125.

[0053] A first load electrode 310 contacts the doped area 120 on the front face of the component in the active region 610. A passivation layer 400 lies on the semiconductor body 100 in the edge termination region 690, laterally surrounds the first load electrode 310, and can cover a portion of the first load electrode 310. Negative electrical charges 250 are schematically indicated in the passivation layer 400, for example OH. - -ions, fluorine ions or lithium ions, which can accumulate at energetically favorable locations in the passivation layer 400.

[0054] In Fig. 3B gives a first line 921 the dependence of the breakdown voltage V PTof the edge termination region 690 as a function of an externally integrated charge density Q F in the volume of the passivation layer 400 for a maximum vertical extent v1 of the channel stopper area 191 of the Fig. Line 3A is 4 µm long, a second line 922 is 4 µm long, a third line 923 is 4 µm long, a fourth line 924 is 100 µm long, and a fifth line 925 is 200 µm long. The deeper the channel stopper region 191 extends, the less influence the negative electrical charge present in the passivation layer 400 has on the breakdown voltage. From a vertical extent or depth of 200 µm, no reduction in the blocking capacity due to the negative charge on the breakdown voltage is discernible.

[0055] The Fig. Sections 4A to 4D describe the deep diffusion of phosphorus to form a channel stopper region 191 in a silicon-based semiconductor substrate, whereby the diffusion of phosphorus can be combined with the diffusion of selenium and / or sulfur. To keep the maximum lateral extent w1 of the channel stopper region 191 low, phosphorus can be introduced at least partially or exclusively in the area of ​​the saw track, so that the majority of the diffusion region formed by the diffusion of phosphorus is removed from the semiconductor substrate during sawing to separate the individual devices, and only a relatively narrow region of lateral diffusion remains in the final semiconductor device.

[0056] The Fig. Figure 4A shows a first vertical dopant distribution 931 for a channel stopper region that is directed to a phosphorus implantation dose of 5 × 10 15 cm -2at an implantation energy of 100 keV, the depth of the channel stopper area 191 decreases. After a 20-hour high-temperature treatment at 1150°C, the depth is approximately 20 µm. If the high-temperature treatment takes place in an oxidizing atmosphere, a 20 nm thick oxide layer grows in the same period.

[0057] According to one embodiment, phosphorus is implanted by means of plasma deposition with an implantation dose greater than 10 17 cm -2 .

[0058] For example, it shows Fig. 4B a second vertical dopant distribution 932 of the channel stopper region for a phosphorus implantation dose of a plasma deposition of 2 × 10 17 cm -2 at an implantation energy of 100 keV after a 20-hour high-temperature treatment at 1150°C. The depth of the canal stopper area is approximately 30 µm.

[0059] For example, in silicon semiconductor devices with a nominal blocking voltage of 1.2 kV and a vertical drift zone extent of approximately 90 µm, a channel stopper region with a vertical extent of about 30 µm significantly reduces the dependence of the breakdown voltage on negative charges in the passivation layer.

[0060] The Fig. 4C and Fig. Figures 4D show a third and a fourth vertical dopant distribution 933, 934 with the implantation parameters of the Fig. 4A and Fig. 4B after a 30-hour high-temperature treatment at 1106°C. The penetration depths achieved are approximately 16 µm and just under 30 µm, respectively.

[0061] A first dopant mask 410 is formed on a first main surface 701 of a semiconductor substrate 700 made of single-crystal silicon with a component layer 710 adjoining the first main surface 701. Phosphorus is deposited through a lattice-shaped mask opening 415 or a plurality of frame-like mask openings 415 in the first dopant mask 410 at a dose of at least 10 15 cm -2 , for example with a dose of at least 10 16 cm -2 or at least 10 17 cm -2 The phosphorus is implanted into layer 710. Phosphorus implantation can involve plasma deposition. The implantation energy can range from 50 keV to 200 keV, for example, around 100 keV.

[0062] The Fig. Figure 5A shows the introduced phosphorus atoms of the first dopant 195 in the vertical projection of the mask opening 415 in the first dopant mask 410. In the illustrated embodiment, the first dopant mask 410 completely covers the component area 600 of the semiconductor substrate 700, and the mask opening 415 exposes at least a portion of the saw track area 800. According to other embodiments, the mask opening 415 can laterally overlap the component areas 600 or be formed only in a central area of ​​the saw track area 800. In another embodiment, each component area is assigned a frame-like mask opening, which is formed either exclusively within the component area 600, exclusively within the saw track area 800, or overlapping both the component area 600 and the saw track area 800.

[0063] Following the implantation of phosphorus and the removal of the first dopant mask 410, a high-temperature step is performed at a temperature above 1000°C, or, according to one embodiment, at a temperature above 1100°C. The high-temperature step can serve solely for the diffusion of phosphorus or, in addition to phosphorus diffusion, serve another purpose, for example, the formation of an oxide layer on the first main surface 701. For example, in the high-temperature step, the semiconductor substrate 700 is held in an oxidizing atmosphere at a temperature of at least 1000°C or at least 1100°C for a period of at least one hour, for example, at least three hours, whereby an oxide layer 210 is formed on the first main surface 701. According to one embodiment, the oxidation is carried out in a humid atmosphere.

[0064] Fig. Figure 5B shows the oxide layer 210 on the first main surface 701 and the diffusion regions 190 formed by lateral and vertical diffusion of the implanted phosphorus atoms. The diffusion regions 190 comprise first sections that form channel stopper regions 191 in component areas 600, and second sections 192 in the saw-track area 800. The thickness of the oxide layer 210 is several nanometers, e.g., at least 5 nm or at least 10 nm, or even more than 100 nm, or, when using wet oxidation, even more than 1000 nm. The oxide layer 210 can be a sacrificial oxide, the formation and subsequent removal of which eliminates near-surface crystal defects. The oxide layer 210 can also function as a scattering oxide layer for subsequent implantation.

[0065] A second dopant mask 420 is formed on the oxide layer 210 or, after removal of the oxide layer 210, directly on the first main surface 701. This mask covers at least an outer section of the edge termination areas 690 of the component areas 600 and can also completely cover the saw track area 800. Mask openings 425 in the second dopant mask 420 expose at least the central active areas 610 of the component areas 600. A second p-type dopant is implanted through the mask openings 425.

[0066] Fig. Figure 5C shows second doped regions 120 formed by the implantation of the second dopant. These regions form a first pn junction pn1 near the substrate face with a drift layer 731, which includes a section of the component layer 710 outside the doped regions 120 and outside the diffusion regions 190. The doped regions 120 are formed at a distance from the diffusion regions 190. One or more further implantations can form additional p-doped regions 125 or n-doped regions of an edge termination structure, such as field rings, JTE regions, or VLD regions, in the area between the doped regions 120 and the diffusion regions 190. A section of the drift layer 731 adjacent to the first main surface 701 can separate the outermost doped region of such an edge termination structure, e.g., the p-doped region 125 of a JTE, from the diffusion regions 190.

[0067] Following further process steps, individual semiconductor bodies 100 are obtained from the semiconductor substrate 700, for example, by a sawing process. During the sawing process, sections of the semiconductor substrate 700 are partially or completely consumed along with the second sections 192 of the diffusion regions 190.

[0068] Fig. 5D shows a section of a semiconductor substrate 700 cut by a sawing process. Fig. 5C separated semiconductor body 100.

[0069] A p-doped region 120 in the active area 610 forms a first pn transition pn1 with a section of the drift layer 731 of the Fig. The drift zone 131 formed by 5C. The p-doped region 120 forms, for example, the anode region of a semiconductor diode or a p-well for the body regions of transistor cells of a MOSFET. In the edge termination region, another p-doped region 125 is formed, which can adjoin the p-doped region 120.

[0070] A channel-stopper region 191 forms an n- / n+ junction jn with the drift zone 131, wherein a section of the drift zone 131 bordering the first surface 101 of the semiconductor body 100 separates the channel-stopper region 191 from the nearest doped region of the complementary conductivity type. The position of the n- / n+ junction jn is determined by the locations of maximum dopant concentration change along lines intersecting the n- / n+ junction. The channel-stopper region 191 is located laterally at a distance d1 from the nearest p-doped region 120, 125, wherein the lateral distance d1 between the first surface 101 and a second surface opposite the first surface 101 is at least D / 20 and at most 2 x D for a thickness D of the semiconductor body 100.

[0071] The maximum vertical extent v1 of the channel stopper region 191 exceeds the maximum vertical extent v2 of the p-doped region 120 by at least double, for example, by at least five times or at least ten times. The maximum vertical extent v1 of the channel stopper region 191 can be less than, equal to, or greater than the distance of a lower edge of the drift zone 131 to the first surface 101. For example, the maximum vertical extent v1 of the channel stopper region 191 is at least 20% and at most 100% of the distance d3.

[0072] Within the channel stopper region 191, the dopant concentration can decrease monotonically, e.g., strictly monotonically, with increasing distance from the side surface 103. The maximum vertical extent v1 of the channel stopper region 191 can be found at the side surface 103. The vertical extent can decrease monotonically, e.g., strictly monotonically, with increasing distance from the side surface 103.

[0073] The Fig. Figures 6A to 6D show different configurations of the first dopant mask 410 for implanting the first dopant.

[0074] In Fig. 6A the first doping mask 410 has a plurality of frame-like mask openings 415, each of which laterally frames an active area 610 of a component area 600 and is spaced apart from both the saw track area 800 and the active areas 610.

[0075] Fig. Figure 6B shows frame-like mask openings 415, which are directly adjacent to the saw track area 800. Fig. Figure 6C shows frame-like mask openings 415, each partially overlapping with an outermost section of an edge termination area 690 of a component area 600 and with sections of the saw track area 800 adjacent to the component areas 600.

[0076] In Fig. In 6D, the mask openings 415 are formed completely within the saw track area 800. Instead of a plurality of frame-like mask openings 415, the doping mask 410 can have a single, grid-like mask opening 415 that exposes at least a central section of the saw track area 800 and can expose outermost sections of the edge termination areas 690 of the component areas 600.

[0077] The Fig. Figures 7A to 7E show different positions of a saw track 810 relative to a component area 690. A separation process, e.g., sawing, laser dicing, or etching, which divides the semiconductor substrate 710 into individual semiconductor bodies, removes a section 795 of the semiconductor substrate 710 in the saw track 810. The lateral width of the saw track 810 can be several tens of micrometers. The saw track area 800 corresponds to a tolerance window for a permissible lateral positional deviation of the saw track 810.

[0078] A boundary line 681 between the saw track area 800 and the component area 600 can be defined by the fact that a lateral deviation of the saw track 810 into the component area 600 causes the breakdown stress of the component to drop below a predetermined threshold.

[0079] In the embodiments of the Fig. From 7A to 7C, the boundary line 681 runs through the lateral center of the channel stopper area 191 prior to the separation process.

[0080] In Fig. 7A, the saw track 810 runs at a distance d2 from the channel stopper region 191. A semiconductor device obtained from the semiconductor substrate 700 comprises, in addition to the component region 600, a residual section 699 of the saw track region 800. The distance d2 between the saw track 810 and the channel stopper region 191 can be in the range of 0 µm to 200 µm, for example in a range of 10 µm to 100 µm or from 20 µm to 50 µm.

[0081] In Fig. 7B borders saw lane 810 on canal stop area 191. In Fig. 7C, saw track 810, borders directly on boundary line 681.

[0082] In the Fig. In 7D, the boundary line 681 is shifted from the lateral center of the channel stopper area 191 prior to the separation process further towards the component area 600, such that the channel stopper area 191 formed in component area 600 comprises less than 50% of the channel stopper area prior to the separation process. If the saw track 810 just reaches the boundary line 681, a narrow channel stopper area 191 results, the vertical extent of which decreases from the component edge from the outset.

[0083] In the Fig. 7E, the channel stopper area 191 is formed at a distance from the saw track area 810 and is maintained during the separation process. The distance d2 between the saw track 810 and the channel stopper area 191 can be in the range of 0 µm to 200 µm, for example in a range of 10 µm to 100 µm or from 20 µm to 50 µm.

[0084] The Fig. 8A to 8D refer to the formation of channel stopper areas 191 by introducing the first dosing material through inner surfaces of trenches 790.

[0085] On the first main surface 701, a trench etching mask 430 is formed, wherein mask openings 435 in the trench etching mask 430 are aligned with the component areas 600 and the saw track area 800. In the drawn example, the trench etching mask 430 has a plurality of frame-like mask openings, each formed along a dividing line between component area 600 and saw track area, and overlapping component area 600, saw track area 800, or both.

[0086] By directed etching, for example by an ion beam etching process, 435 grooves 790 are introduced into the component layer 710 of the semiconductor substrate 700 in the vertical projection of the mask openings. A first dopant, for example phosphorus, selenium or sulfur, is introduced through the inner surfaces of the grooves 790.

[0087] The introduction of the first dopant can be achieved by masked implantation or masked diffusion using a first dopant mask, where the first dopant mask can, for example, be the trench etching mask 430. According to another embodiment, the trenches 790 can be filled with doped material, for example, doped semiconductor material, so that the introduction of the first dopant involves diffusion out of the doped material.

[0088] Fig. Figure 8A shows the first dopant 195 introduced into the trenches 790, assuming the first dopant 195 is introduced by implantation or diffusion from a gas phase. The dopant mask is removed, and the trenches 790 are filled. A high-temperature treatment, such as a high-temperature step to form an oxide layer 210, causes the first dopant atoms to diffuse vertically and laterally. To ensure sufficient doping of the trench walls, oblique implantation or plasma deposition can be used, resulting in an almost homogeneous coverage of the sidewall / trench floor with dopant.

[0089] Fig. Figure 8B shows the oxide layer 210 on the first main surface 701 as well as diffusion areas 190 with an almost vertical n- / n+ transition jn over a long distance.

[0090] Fig. 8C and Fig. 8D refers to a processing method similar to that already used for Fig. 5C and Fig. 5D described. According to Fig. 8D exhibit channel-stopper regions 191, defined by a trench-etching process, with nearly vertical n- / n+ transitions jn over long distances. The area where, in the case of blocking, the space charge zone meets the channel-stopper region 191 shows hardly any curvature. The blocking capability of the component is therefore comparatively insensitive to charges in a passivation layer above the first surface.

[0091] Fig. Reference 9 relates to a further method for fabricating a semiconductor device. A first dopant is introduced into at least one section of a saw-track region of a semiconductor substrate adjacent to a device region (912), forming a channel-stopper region extending laterally from the saw-track region into a device region. At a lateral distance from the channel-stopper region, doped regions are formed in the semiconductor substrate, forming pn junctions with a drift layer (914), wherein a maximum vertical extent of the channel-stopper region perpendicular to a first principal surface is at least twice as large as a maximum vertical extent of the doped regions.

[0092] For a silicon carbide semiconductor substrate 700, the introduction of the first dopant can include one or more implantations with a higher implantation energy than is subsequently used to form a doped region in the active area, each implantation being able to be carried out by means of an energy diffuser arranged in the beam path which causes a more uniform vertical distribution of the first dopant 195.

[0093] The Fig. 10A to 10C refer to a further method for the formation of channel stopper areas 191 by introducing the first doping material through inner surfaces of trenches 790.

[0094] In the vertical projection of mask openings 435 of a trench etching mask 730, trenches 790 are introduced into a component layer 710 of a semiconductor substrate 700. A first dopant, for example phosphorus, selenium, sulfur, arsenic, is introduced into the component layer 710 through the inner surfaces of the trenches 790.

[0095] Fig. Figure 10A shows the diffusion zones 190 formed by the introduction of the first dopant in the area of ​​the trenches 790. The formation of the diffusion zones 190 can include a high-temperature step. According to one method, the formation of the diffusion zones 190 occurs without a high-temperature step.

[0096] Fig. Figure 10B shows p-doped regions 120, 125, which are formed further along or even before the diffusion regions 190 in component area 600 and at a distance from the diffusion regions 190.

[0097] The Fig. Figure 10C shows a section of a diffusion area 190 from the first part of the Fig. 10B formed channel stopper region 191, which has hardly any curvature over a large area of ​​its vertical extent and whose blocking capability is thus largely insensitive to charges in a passivation layer of a semiconductor device above a first surface 101 of a semiconductor body 100.

Claims

[1] Method for manufacturing a semiconductor device comprising: Forming a channel stopper area (191) extending from a planar, horizontal first main surface (701) into a component layer (710) of a first conductivity type in an edge termination area (690) adjoining a saw track area (800) of a component area (600), wherein the formation of the channel stopper area (191) comprises forming a first dopant mask (410) on the first main surface (701) and introducing a first dopant (195) through a mask opening (415) of the first dopant mask (410), wherein the first dopant (195) is introduced through sections of the first main surface (701) exposed through the mask opening (415) of the first dopant mask (410); and Forming a doped area (120) extending from the first main surface (701) into the component layer (710) in the component area (600), wherein the channel stopper area (191) is formed by means of a photolithographic process which is carried out prior to a first photolithographic process for introducing dopants into a section of the component area (600) outside the channel stopper area (191), and where in the component area (600) a maximum vertical extent (v1) of the channel stopper area (191) perpendicular to the first main surface (701) is greater than a maximum lateral extent (w1) of the channel stopper area (191) in the component area (600) parallel to the first main surface (701). [2] Method according to claim 1, wherein the channel stopper area (191) borders the saw track area (800) or extends into the saw track area (800). [3] Method according to claim 1, wherein the channel stopper area (191) is spaced apart from the saw track area (800). [4] Method according to one of claims 1 to 2, wherein the mask opening (415) exposes at least a section of the saw track area (800). [5] Method according to claim 4, wherein after the introduction of the first dopant (195) a process sequence is carried out at least once more, comprising removing the first dopant mask (410), applying a further component layer to the first main surface (701), forming a further first dopant mask (410) with a mask opening (415) that exposes at least a section of the saw track area (800), and introducing the first dopant (195) through the mask opening (415). [6] Method according to any one of claims 1 to 5, wherein the channel stopper area (191) is formed at least partially by thermomigration. [7] Method according to claim one of claims 1 to 6, wherein the first dopant (195) contains at least selenium, sulfur or phosphorus. [8] Method according to any one of claims 1 to 7, wherein the formation of the channel stopper region (191) comprises a high-temperature treatment at a temperature of at least 1000°C, the high-temperature treatment is carried out after the introduction of the first dopant (195) and before the formation of the doped region (120), and the high-temperature treatment causes the first dopant (195) to be distributed over a diffusion region (190), wherein a first section of the diffusion region (190) in the component area (600) forms the channel stopper region (191). [9] Method according to claim 8, wherein the high-temperature treatment is carried out at a temperature above 1000°C and in an oxygen-containing environment, wherein an oxide layer (210) is formed on the first main surface (701). [10] Method according to any one of claims 1 to 9, wherein the formation of the channel stopper region (191) comprises plasma deposition of phosphorus. [11] Method according to any one of claims 1 to 10, wherein forming the channel stopper region (191) comprises forming hydrogen-correlated donors in the channel stopper region (191). [12] Method according to any one of claims 1 to 11, wherein the channel stopper area (191) completely encloses an active area (610). [13] Method according to any one of claims 1 to 12, wherein a maximum vertical extent (v1) of the channel stopper area (191) perpendicular to the first main area (701) is at least twice as large as a maximum vertical extent (v2) of the doped area (120). [14] Method according to any one of claims 1 to 13, wherein in the component area (600) the vertical extent of the channel stopper area (191) decreases strictly monotonically with increasing distance to the saw track area (800). [15] Method for manufacturing a semiconductor device, comprising: Introducing a first dopant (195) at least into a section of a saw track region (800) of a semiconductor substrate (700) adjacent to a component region (600) through a mask opening (415) of a dopant mask (410) exposing at least a section of the saw track region (800), wherein a channel stopper region (191) extending laterally from the saw track region (800) into the component region (600) is formed; and Formation of endowed areas (120, 125) at a distance from the canal stopper area (191), wherein a drift layer (731) borders a planar, horizontal first principal surface (701) of the semiconductor substrate (700) between the doped regions (120, 125) and the channel stopper region (191), and wherein the doped regions (120, 125) in the semiconductor substrate (700) form pn junctions with the drift layer (731) and wherein a maximum vertical extent (v1) of the channel stopper region (191) perpendicular to the first principal surface (701) is at least twice as large as a maximum vertical extent (v2) of the doped regions (120, 125). [16] Method according to claim 15, wherein the first dopant (195) contains at least one of the dopant materials selenium, sulfur or phosphorus, diffusing the first dopant (195) comprises a high-temperature treatment in an oxidizing atmosphere and wherein an oxide layer (210) is formed on the first main surface (701) during the high-temperature treatment. [17] Method according to one of claims 15 to 16, wherein the drift layer (731) and the channel stopper region (191) form a unipolar transition (jn).

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