Self-adjusting / resetting latch and memory cell with such a latch

Abstract

Latch circuit, which includes: a first inverter coupled to a supply voltage and a cancel terminal (CANCEL terminal), wherein the first inverter has a first resistive load (R0); and a second inverter which is cross-coupled with the first inverter and coupled to the supply voltage terminal (VPOS) and an adjustment terminal (SET), wherein the second inverter includes a second resistive load (R3), wherein the first and second resistive loads cause the latch circuit to automatically set or reset in response to a change in the supply voltage, and wherein at least one of the first or second resistive loads is set up to set a threshold voltage at which the latch circuit is automatically set or reset.

Description

[0001] The subject of this revelation relates generally to latch circuits.

[0002] A latch circuit has two stable states and can be used to store state information. The circuit can be designed to change its state by signals applied to one or more control inputs and will have one or two outputs. One of the inputs is called the setting input; the other is called the reset or cancel input. Latch circuits can be either active-high or active-low. The difference is determined by whether the latch circuit's operation is triggered by high or low signals at the inputs. For an active-high configuration, both inputs are connected to ground, and the latch circuit is triggered by a momentary high signal at either input. For an active-low configuration, both inputs are high, and the latch circuit is triggered by a momentary low signal at either input.Some latch circuits have a second output that is the inverted version of the first. Some applications, such as those using power-on reset (POR), have undefined low-voltage states where, below a certain threshold voltage, proper latch operation is impossible. For critical applications using POR, an undefined low-voltage state may be unacceptable.

[0003] Corresponding latch circuits are known, for example, from US 4 047 194 A, US 5 325 325 A and DE 33 36 640 A1.

[0004] A self-adjusting / resetting latch circuit with the features of claim 1 and a memory cell with a corresponding latch circuit with the features of claim 5 are disclosed.

[0005] In one embodiment, a latch circuit comprises: a first transistor (M1) having gate, source, and drain terminals, wherein the source terminal is coupled to a negative power supply terminal (VNEG) and the drain terminal is coupled to an output terminal (OUT) of the latch circuit; a first resistor (R3) having two terminals, wherein a first terminal is coupled to the gate terminal of M1 and a second terminal is coupled to VNEG; a second transistor (M3) having gate, source, and drain terminals, wherein the drain terminal is coupled to the gate terminal of M1 and the first terminal of R3, and the source terminal is coupled to a positive power supply terminal (VPOS); a second resistor (R0) having two terminals, wherein a first terminal is coupled to the gate of M3 and a second terminal is coupled to VPOS;a third transistor (M4) comprising gate, source and drain terminals, wherein the gate terminal is coupled to a lift terminal of the latch circuit, the drain terminal is coupled to OUT and the first terminal of R0 and the source terminal is coupled to VNEG; and a fourth transistor (M2) comprising gate, source and drain terminals, wherein the gate terminal is coupled to a setting terminal of the latch circuit, the drain terminal is coupled to the drain terminal of M3, the gate terminal of M1 and the first terminal of R3, and the source terminal is coupled to VNEG. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A is a circuit diagram of an exemplary self-adjusting latch circuit according to one embodiment. Fig. 1B is a circuit diagram of the exemplary self-adjusting latch circuit of Fig. 1 with optional components removed. Fig. Figure 2 shows exemplary waveforms representing an operation of the self-adjusting latch circuit of Fig. Figure 1A shows one embodiment. DETAILED DESCRIPTION Example circuit

[0006] Fig. Figure 1A is a diagram of a self-adjusting latch circuit 100 according to one embodiment. Latch circuit 100 comprises transistors 101-106 (M0-M6) and resistors 107-110 (R0-R3). Latch circuit 100 can be incorporated into another circuit to process critical signals, such as in a memory (e.g., a serial EEPROM, SRAM) used in critical applications or as a memory cell in a microcontroller's cache memory. The memory cell can be one of a plurality of memory cells in a memory cell array coupled to an interface that includes a row and column selection circuit (e.g., a multiplexer, a demultiplexer) and a signal conditioning circuit. A memory controller can be coupled to or included in the interface to read and write data to the memory cells in the memory cell array.

[0007] The Latch Circuit 100 comprises two cross-coupled inverters. The first inverter includes transistor M1 and resistors R0 and R1. The second inverter includes transistor M3 and resistors R2 and R3. Transistor M4 implements a cancel function, and transistor M2 implements a set function for the Latch Circuit 100. The Latch Circuit 100 includes a positive and a negative supply voltage terminal (VPOS, VNEG), an output terminal (OUT), a set terminal (SET), and a cancel terminal (AUFHEBEN).

[0008] The ratio of R3 to R2 (a voltage divider) can be adjusted to set a threshold voltage at which Latch Circuit 100 is automatically set. When the voltage at the gate of transistor M1 becomes insufficient (greater than a threshold voltage plus the drain-source voltage at saturation (vdsat) of transistor M1), the output OUT goes high. When OUT goes high, transistor M3 is turned off, and the positive feedback of Latch Circuit 100 maintains the ON state. The operation is similar for R0 and R1, which are connected to the gate of transistor M3. Transistor M4 is connected to the output terminal OUT but could instead be connected to node 111, which is shared by resistors R0 and R1 (a voltage divider). This alternating connection would ensure cancellation at a lower supply voltage.

[0009] In one embodiment, transistors M1, M2, M4, and M5 are n-channel metal-oxide-semiconductor (NMOS) transistors, and transistors M0 and M3 are p-channel metal-oxide-semiconductor (PMOS) transistors. Resistors R1 and R2 are optional and are used with R0 and R3 to set a voltage threshold below which latch circuit 100 will self-adjust. Transistors M0 and M5 are also optional and are used to add the gate-source capacitance (cgs) to that of transistors M3 and M1, respectively. In the Fig. In the embodiment shown in Figure 1A, latch circuit 100 is self-adjusting. To make latch circuit 100 self-resetting or self-canceling, the CANCEL and SEND connections can be reversed and the OUT connection can be connected to the drain of transistor M3.

[0010] Fig. 1B is a circuit diagram of the exemplary self-adjusting latch from Fig. 1, where optional transistors M0, M5, and optional resistors R1 and R2 are removed. The first inverter includes transistor M1 and resistor R0, and the second inverter includes transistor M3 and resistor R3. One source terminal of transistor M1 is coupled to a negative power supply terminal (VNEG), and one drain terminal of M1 is coupled to an output terminal (OUT) of the latch circuit. One terminal of resistor R3 is coupled to the gate terminal of M1, and a second terminal of R3 is coupled to VNEG. One drain terminal of transistor M3 is coupled to the gate terminal of M1 and the first terminal of R3. One source terminal of M3 is coupled to a positive power supply terminal (VPOS). One terminal of resistor R0 is coupled to a gate terminal of M3, and a second terminal of R0 is coupled to VPOS.A gate terminal of transistor M4 is coupled to a lift terminal of the latch circuit, a drain terminal of M4 is coupled to OUT and the first terminal of R0, and a source terminal of M4 is coupled to VNEG. A gate terminal of transistor M2 is coupled to a set terminal of the latch circuit, a drain terminal of M2 is coupled to the drain terminal of M3, the gate terminal of M1, and the first terminal of R3, and a source terminal of M2 is coupled to VNEG.

[0011] Fig. Figure 2 shows exemplary waveforms representing an operation of the self-adjusting latch circuit of Fig. Figure 1A shows one embodiment. Three waveforms are displayed for VPOS, OUT, and CANCEL. Time increases from left to right. Each point in time under discussion is represented by a letter.

[0012] At time 0, VPOS rises and OUT follows VPOS. At time A, CANCEL goes high, causing the latch circuit to "latch" into a CLEAR state with OUT=0 volts. At time B, VPOS begins to fall. At time C, OUT drops below 2 volts. Assuming R1=R0 and that the threshold of M3 is approximately 1 volt, M3 turns off, which turns M1 on, thus setting the latch circuit. At time D, CANCEL is high again and OUT is cleared. At time E, CANCEL is low and the latch circuit is self-setting because the voltage divider formed by R1 and R0 (or R2 and R3) cannot keep M3 (or M1) in an ON state to maintain the latch circuit in a CANCEL state.

[0013] While this document contains many specific implementation details, these should not be interpreted as limitations on the scope of the claimed invention, but rather as descriptions of features that may be specific to certain embodiments. Certain features described in this document in connection with separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in connection with a single embodiment may also be implemented separately in several embodiments or in any suitable subcombination.Although features that can be described above are described in certain combinations and are even initially claimed as such, in some cases one or more features from a claimed combination may be extracted from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Claims

[1] Latch circuit comprising: a first inverter coupled to a supply voltage and a cancel terminal (CANCEL terminal), wherein the first inverter has a first resistive load (R0); and a second inverter which is cross-coupled with the first inverter and coupled to the supply voltage terminal (VPOS) and an adjustment terminal (SET), wherein the second inverter includes a second resistive load (R3), wherein the first and second resistive loads cause the latch circuit to automatically set or reset in response to a change in the supply voltage, and wherein at least one of the first or second resistive loads is set up to set a threshold voltage at which the latch circuit is automatically set or reset. [2] Latch circuit according to claim 1, wherein the latch circuit automatically adjusts or resets in response to the supply voltage falling below the threshold voltage. [3] Latch circuit according to claim 1, wherein the first inverter comprises a first transistor (M1) and a first resistor (R0), wherein the first resistor (R0) is coupled to a first drain terminal of the first transistor (M1), and the second inverter comprises a second transistor (M3) and a second resistor (R3), wherein the second resistor (R3) is coupled to a second drain terminal of the second transistor (M3). [4] Latch circuit according to claim 3, wherein the first transistor (M1) is an n-channel metal oxide semiconductor (NMOS) transistor and the second transistor (M3) is a p-channel metal oxide semiconductor (PMOS) transistor. [5] Memory cell comprising: an interface; a latch circuit (100) coupled to the interface, wherein the latch circuit (100) comprises: a first inverter coupled to a supply voltage and a cancel terminal (CANCEL terminal), wherein the first inverter has a first resistive load (R0); and a second inverter which is cross-coupled with the first inverter and is coupled to the supply voltage terminal (VPOS) and an adjustment terminal (SETTING), wherein the second inverter includes a second resistive load (R3), wherein the first and the second resistive load cause the latch circuit (100) to be automatically set or reset in response to a change in the supply voltage, and wherein at least one of the first or second resistive load is configured to set a threshold voltage at which the latch circuit (100) is set or reset. [6] Memory cell according to claim 5, wherein the latch circuit (100) automatically adjusts or resets in response to the supply voltage falling below the threshold voltage. [7] Memory cell according to claim 5, wherein the first inverter comprises a first transistor (M1) and a first resistor (R0), wherein the first resistor (R0) is coupled to a first drain terminal of the first transistor (M1), and the second inverter comprises a second transistor (M3) and a second resistor (R3), wherein the second resistor (R3) is coupled to a second drain terminal of the second transistor (M3). [8] Memory cell according to claim 7, wherein the first transistor (M1) is an n-channel metal oxide semiconductor (NMOS) transistor and the second transistor (M3) is a p-channel metal oxide semiconductor (PMOS) transistor.

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