High-side control for multi-stage step-down converter

Abstract

Multi-stage step-down converter (600, 800) featuring the following: a plurality of four switching transistors with four switching states with respect to an inductor (L1), wherein the plurality of four switching transistors comprises a first switching transistor (A) with a drain connected to an input voltage node (VIN), a second switching transistor (B) with a source connected to an input node for the inductor (L1) and with a drain connected to a source for the first switching transistor (A), a third switching transistor (C) with a drain connected to the source of the second switching transistor (B), and a fourth switching transistor (D) with a drain connected to a source for the third switching transistor (C) and with a source connected to ground; a flying capacitor (CF) with a positive terminal (CP) connected to the source of the first switching transistor (A) and a negative terminal (CM) connected to the source of the third switching transistor (C); a first gate driver (805) to drive a gate for the first switching transistor (A); a second gate driver (810) for driving a gate of the second switching transistor (B); a third gate driver (815) for driving a gate of the third switching transistor (C), wherein the positive terminal (CP) of the flying capacitor (CF) is connected to a power supply node for the third gate driver (815); a control device (615) configured to regulate the voltage of the flying capacitor (CF) using a reference voltage (Vcapref) derived from the input voltage (VIN), clamping the voltage of the flying capacitor (CF) when it falls below a minimum voltage or rises above a maximum voltage; a first boot capacitor (CB1) connected between the source of the first switching transistor (A) and a power supply node for the first gate driver (805); and a second boot capacitor (CB2) connected between the source of the second switching transistor (B) and a power supply node for the second gate driver (810).

Description

Technical field

[0001] The present invention relates to a multi-stage buck converter and in particular to the control of the switching transistors in a multi-stage buck converter. background

[0002] Compared to a conventional buck converter, a multi-stage buck converter offers several advantages, such as higher efficiency under high load conditions. Additionally, the extra switches in multi-stage buck converters, combined with the fact that the flying capacitor voltage is half the input voltage, reduce switching loads compared to conventional buck converters. Furthermore, ripple is reduced because the four switches in multi-stage buck converters generate twice the ripple frequency compared to the ripple frequency at the same switching speed for a conventional (single-phase) buck converter, effectively doubling the switching frequency. This increase in output ripple frequency advantageously allows a multi-stage buck converter to use a smaller inductor than a conventional buck converter.

[0003] Although multi-stage buck converters offer advantages over conventional buck converters, controlling the multiple switches in a multi-stage buck converter is problematic. Generally, there are four switching states for a multi-stage buck converter with four switches, as in Fig. Figure 1 shows that in each switching state, only two switching transistors from a set of four switching transistors are turned on: switching transistor A, switching transistor B, switching transistor C, and switching transistor D. In switching state D1, switching transistors A and C are turned on, so the voltage across the flying capacitor V CF is charged by the input voltage and the switching node voltage V SW at the input of the inductor. The resulting inductor current I SW charges an output capacitor with the output voltage V OUTIn switching state DV, switching transistors C and D are switched on such that the inductor is free-running and discharges into the output capacitor. The floating capacitor is suspended during switching state DV. In switching state D2, switching transistors D and B are switched on such that the floating capacitor discharges into the switching node. Finally, in switching state DP, switching transistors A and B are switched on such that the switching node is connected to the input voltage V. IN is being charged. The flying capacitor floats during the DP switching state.

[0004] In comparison to a conventional buck converter, the root mean square (RMS) switching node voltage V is SW The voltage at the input node to the inductor is reduced by 50%. In particular, it can be shown that V SW between the input voltage V INand switches at half the input voltage if the output voltage is greater than half the input voltage. Conversely, V switches SW between V IN / 2 and mass, if V IN / 2 greater than V OUT This reduction in switching node voltage oscillation also reduces the switching voltage loads on the switching transistors. Due to the reduced voltage load, the breakdown voltage ratings for the switching transistors can be lowered compared to conventional buck converter switching transistors. Multi-stage buck converters thus offer reduced conduction losses for their switching transistors.

[0005] However, these advantages come at the cost of higher control complexity, as shown by the four switching states mentioned above with reference to Fig.1. This will be discussed. Despite this increased complexity, prior art multi-stage buck converters have typically employed conventional buck converter control techniques, such as valley-mode or peak-mode (peak current) control. However, the transition between valley-mode and peak-mode control in a multi-stage buck converter introduces a number of control stability problems not present in standard buck converters. In particular, it should be noted that a transition from peak-mode to valley-mode control is typically not required in a conventional buck converter over a wide range of operating conditions.However, conventional multi-stage buck converters that use current-mode control to maintain an amp-second balance on the flying capacitor switch from valley-mode to peak current control when the duty cycle ranges from less than 50% to more than 50% (where the duty cycle is defined as the ratio of the output voltage to the input voltage). It is therefore common practice to restrict the control of the multi-stage buck converter to only one of the valley-mode or peak current control modes. Such control limitation, in turn, restricts the duty cycle range. There is thus a need in the engineering for an improved multi-stage buck converter with control over a wide input voltage range.

[0006] The limitation of the operating range is not the only problem that conventional multi-stage buck converters have. Furthermore, multi-stage buck converters suffer from non-ideal voltage levels of the flying capacitor. Due to their topology, the voltage of the flying capacitor is ideally Vf. IN / 2 averaged. Similarly, the switching node voltage is set to V IN / 2 averaged for switching states D1 and D2. In contrast, the switching node voltage in switching state DV is connected to ground and corresponds to V IN in the switching state DP. With these three possible voltage values, a multi-stage step-down converter, as in Fig. Figure 1, also known as a three-stage buck converter. The sum of the switching state periods D1 and D2 multiplied by the (ideal) voltage of the floating capacitor V. IN / 2 corresponds to the output voltage. As mentioned above, the ratio of the output voltage to the input voltage for a multi-stage buck converter can be considered defining a duty cycle ratio D such that D = V OUT / V IN Assuming that the voltage V CF Since the voltage of the flying capacitor is half the input voltage, the duty cycle D thus corresponds to half the sum of the switching periods D1 and D2. Under ideal conditions, the voltage of the flying capacitor settles to V. IN / 2, but imbalances due to differences in parasitic elements, such as switching capacitance, cause the voltage of the flying capacitor to move towards ground or towards V INThis tends to lead to a significant impairment in the regulation of the output voltage by the multi-stage buck converter. Furthermore, existing schemes for regulating the voltage of the flying capacitor complicate the regulation of the output voltage. Accordingly, there is a need in engineering for improved multi-stage buck converters that operate over a wide V IN -to-V OUT The duty cycle ratio (a wide duty cycle range) can be regulated, while the voltage of the flying capacitor is also regulated.

[0007] Compared to a conventional buck converter, driving the switching transistors in a multi-stage buck converter presents an additional challenge due to the difficulty of supplying the gate drive voltage to turn on the three floating switching transistors. In contrast, a conventional buck converter has only one floating switching transistor. In both types of buck converters, one switching transistor is connected to ground. It is common to implement a multi-stage buck converter using NMOS switching transistors because of their advantageously low on-resistance. However, generating sufficient gate drive voltages to turn on the floating NMOS switching transistors in a multi-stage buck converter is problematic.

[0008] There is therefore a need in engineering for improved gate drivers for the switching transistors in a multi-stage buck converter.

[0009] Furthermore, US 2009 / 0 195 068 A1 describes a power conversion device which includes a single drive unit that does not require its own dedicated power supply and includes gate drivers connected to switches and interface circuits, as well as a gate driver circuit of the power converter which is configured with a common power supply to supply the gate driver unit.

[0010] US 2014 / 0300413A1 describes a gate driver for a power transistor that includes a first charging path, which is operationally connected between a first voltage supply and a gate terminal of the power transistor. A second charging path is switchable between the gate terminal of the power transistor and a second voltage supply to charge the gate terminal from the first gate voltage to a second gate voltage.

[0011] US 2016 / 0065072A1 describes a power converter with a bootstrap circuit, wherein the power converter has a high-side switch, a low-side switch, a bootstrap circuit and a bootstrap capacitor to provide a bootstrap voltage to supply a high-side driver of the high-side switch.

[0012] US 2015 / 0244302A1 describes an electric power steering system that drives and controls a motor through an inverter consisting of a FET bridge based on phased PWM duty cycle setpoints, and performs support control of a steering system, including a charge pump circuit and a bootstrap circuit that generates an amplified supply voltage to drive the upper FETs of the FET bridge.

[0013] US Patent 2014 / 0217959A1 describes a synchronous switching converter that converts a DC input voltage to a DC output voltage. This synchronous switching converter includes a high-side switching MOSFET connected between an input node and a first node. The converter further includes a low-side switching MOSFET connected between the first node and a ground node, in series with the high-side switching MOSFET.

[0014] US 2016 / 0315539A1 describes a DC / DC converter comprising a plurality of power switches connected in series between an input node and a ground node, a first capacitor connected in parallel to at least two power switches in the series chain, an inductor connected between an intermediate node of the series chain and an output node, a second capacitor connected between the output node and the ground node, and a plurality of drivers, each generating a switching control signal for each of the power switches. Summary

[0015] The present invention is defined by the appended claims. In the following, parts of the description and the drawings relating to earlier embodiments and not necessarily including all features for implementing embodiments of the claimed invention are to be understood as not representing embodiments of the invention, but serving as examples to facilitate understanding of the embodiments of the invention.

[0016] A multi-stage buck converter uses a regulated voltage from a flying capacitor to drive a first, second, and third switching transistor. The first switching transistor has a drain connected to an input voltage node for the multi-stage buck converter and a source connected to a positive terminal of the flying capacitor and also to a drain for the second switching transistor. A source of the second switching transistor is connected to the input node of an inductor for the multi-stage buck converter. The drain of the third switching transistor is connected to the input node of the inductor and also to the source of the second switching transistor.One drain of the third switching transistor is connected to a negative terminal for the floating capacitor and also to a drain of the fourth switching transistor. The source of the fourth switching transistor is connected to ground and is therefore not floating with respect to ground. In contrast, the first, second, and third switching transistors are all floating with respect to such a direct ground connection.

[0017] Each of the switching transistors has its own gate driven by a corresponding gate driver. Thus, there is a first gate driver for the first switching transistor, a second gate driver for the second switching transistor, and a third gate driver for the third switching transistor. Each gate driver has its own power supply node for receiving a power supply voltage. The following discussion concerns an advantageous application of the regulated voltage from the flying capacitor to directly or indirectly power the gate driver power supply nodes. Specifically, the power supply node for the third gate driver is connected to the positive terminal of the flying capacitor such that the regulated voltage from the flying capacitor can directly power the third gate driver. The application of the flying capacitor voltage to the first and second gate drivers is somewhat more subtle.Specifically, the power supply node for the first gate driver is connected to a first capacitor, which is also connected to the source for the first floating switching transistor. Similarly, the power supply node for the second gate driver is connected to a second capacitor, which is also connected to the source for the second floating switching transistor.

[0018] The floating capacitor charges the first and second capacitors either directly or indirectly as follows. Specifically, the four switching states are used for a four-switch multi-stage buck converter to facilitate this energy exchange. In the first switching state (here designated D1), only the first and third floating switching transistors are turned on. In switching state D1, the floating capacitor is connected in parallel with the second capacitor, allowing it to charge the second capacitor. This same parallel configuration of the floating capacitor and the second capacitor occurs in a second switching state (here designated DV), in which only the third and fourth switching transistors are turned on.

[0019] The charged second capacitor can then be used to power the gate driver of the second switching transistor in a third and a fourth switching state. In the third switching state (here designated D2), only the second and fourth switching transistors are turned on. Switching state D2 is used to charge a first capacitor connected between a power supply node for the first gate driver and the source of the first switching transistor, since the first and second capacitors are then coupled in parallel. Similarly, the first and second capacitors are coupled in parallel in the fourth switching state (here designated DP), with only the first and second switching transistors being turned on. The flying capacitor thus indirectly powers the first capacitor by charging the second capacitor in switching states D1 and DV.The charged second capacitor then charges the first capacitor in switching states D2 and DP. Accordingly, the regulated voltage of the flying capacitor is advantageously used to supply the gate drivers for the first switching transistor, the second switching transistor, and the third switching transistor. The gate driver for the fourth switching transistor can be supplied conventionally by an internal power supply voltage VDD for a control device for the multi-stage buck converter.

[0020] These and other advantageous features of the disclosed multi-stage step-down converters can be better assessed by considering the following detailed description. Brief description of the drawings Fig. Figure 1 shows the four switching states for a conventional multi-stage step-down converter with four switches. Fig.Figure 2 is a diagram of a multi-stage downward converter according to one aspect of the Revelation. Fig. Figure 3 shows additional details for the timing circuit in the multi-stage step-down converter of Fig. 2. Fig. Figure 4 shows the ramp signal waveforms and resulting switching states for the multi-stage step-down converter of Fig. 2 in response to the fact that the error signal is smaller than an average level for the ramp signals. Fig. Figure 5 shows the ramp signal waveforms and resulting switching states for the multi-stage step-down converter of Fig. 2 in response to the fact that the error signal is greater than an average level for the ramp signals. Fig. Figure 6 shows a multi-stage step-down converter configured to regulate its output voltage and its flying capacitor voltage according to an aspect of the revelation. Fig.Figure 7 shows further details for the control device in the multi-stage step-down converter of Fig. 6. Fig. Figure 8 shows a multi-stage step-down converter in which the voltage of the flying capacitor is used to supply the floating switching transistors, according to one aspect of the Revelation. Fig. Figure 9 shows how the four switching states for the multi-stage step-down converter in Fig. 8 is used to distribute a charge from the flying capacitor to supply the gate drivers for the floating switching transistors. Fig. Figure 10 shows a waveform for the regulated voltage of the flying capacitor in the multi-stage step-down converter of Fig. 8. Detailed description

[0021] A regulated voltage from a flying capacitor is used to supply the gate driver for the floating switching transistors in a multi-stage buck converter. The following discussion concerns a particularly advantageous regulation of the flying capacitor voltage, which is seamlessly integrated into regulation of the output voltage over a wide duty cycle range. However, it is evident that the floating switching transistor driver circuits and methods disclosed here can be implemented with alternative regulation techniques for the flying capacitor voltage.

[0022] The advantageous regulation of the output voltage over a wide range of duty cycles is discussed first, followed by a discussion of the regulation of the floating capacitor voltage. The gate drive of the floating switching transistor is then discussed in the context of the disclosed regulation of the floating capacitor voltage. An exemplary multi-stage buck converter 200 is presented in Fig.Figure 2 shows switching transistors A, B, C, and D in a conventional arrangement. Specifically, switching transistor A has a first terminal connected to a node for the input voltage V_IN and a second terminal connected to a first terminal for a flying capacitor CF. Additionally, the second terminal of switching transistor A is connected to a first terminal for switching transistor B. As used here, a transistor "terminal" denotes, for example, a drain or source terminal for a MOS field-effect transistor. A second terminal for switching transistor B is connected to a switching terminal (SW) for an inductor L1, which is connected to an output capacitor C1 to smooth the output voltage V_OUT.The switching transistor C has a first terminal connected to the SW node (input node for inductor L1) and a second terminal connected to a remaining terminal for the flying capacitor CF. Additionally, the second terminal of switching transistor C is connected to the first terminal of switching transistor D, whose second terminal is connected to ground.

[0023] An error amplifier 205 generates an error voltage (ER V_OUT) in response to a difference between the output voltage and a reference voltage (REF V_OUTThe fault voltage is compared to two ramp signals that are 180° out of phase with each other (it should be noted that other phase relationships can be used in alternative embodiments). A first ramp generator 210 generates a first ramp signal in response to a clock signal from a clock source 215. A second ramp generator 220 generates a second ramp signal in response to an inverted clock signal from the clock source 215. The second ramp signal is thus 180° out of phase with the first ramp signal. A first comparator 225 compares the first ramp signal with the fault signal to generate a first control signal 230. Similarly, a second comparator 235 compares the second ramp signal with the fault signal to generate a second control signal 240. A timing logic circuit 245 determines the times or timings for the switching states D1, D2, DV and DP (as in relation to Fig.(1 discussed) in response to the first control signal 230 and the second control signal 240, as described below. A switching control and driver circuit 250 controls the gates of switching transistors A, B, C, and D to effect the switching state selected by the timing logic circuit 245. For example, when the timing logic circuit 245 indicates that switching state D1 should be activated, the switching control and driver circuit 250 turns on switching transistors A and C by driving their gates with the appropriate voltages. If switching transistors A and C are NMOS transistors, the switching control and driver circuit 250 charges their gates to turn these transistors on. Simultaneously, the gates of switching transistors B and D are discharged. The charging and discharging is reversed in an embodiment of a PMOS switching transistor.

[0024] An example of the 245 time control logic circuit is given in Fig. 3 shown in more detail. A first flip-flop 300 sets (activates) a first signal, designated D1_pulse, in response to a rising edge for the clock signal (designated CLK) from the clock source 215 ( Fig. 2) The flip-flop 300 resets the D1_pulse signal in response to the activation of the first control signal 230 from the first comparator 225 ( Fig. 2) The signal D1_pulse is thus activated at the beginning of the ramp period for the first ramp signal and deactivated when the first ramp signal is larger than the error signal from the differential amplifier 205 ( Fig. 2) A second flip-flop 305 sets a second signal, designated D2_pulse, in response to a rising edge of the inverted clock signal (designated CLK_B) from clock source 215. Flip-flop 305 resets the D2_pulse signal in response to the activation of the second control signal 240 from the second comparator 235 ( Fig.2) The signal D2_pulse is thus activated at the beginning of each period for the second ramp signal and deactivated if the second ramp signal is greater than the error signal.

[0025] As used herein, a signal, such as the signals D1_pulse and D2_pulse, is considered enabled or set when it has a logically true value, regardless of whether the logic convention is logically high or logically low. Similarly, a signal is considered disabled or reset when it has a logically false value. As used herein, a signal that is "on" is considered enabled, while a signal that is "off" is considered disabled. There are thus four possible on and off combinations for the logical states of the signals D1_pulse and D2_pulse. These four logical states can be mapped to the switching states D1, D2, DP, and DV in a lookup table (LUT) 310 as follows. When the signal D1_pulse is on and the signal D2_pulse is off, LUT 310 activates a command to select the switching state D1.Conversely, if signal D2_pulse is on while signal D1_pulse is off, LUT 310 activates a command to select switching state D2. If both signals are off, LUT 310 activates a command to select switching state DV. Finally, if both signals are on, LUT 310 activates a command to select switching state DP. The resulting operating rules encoded in LUT 310 are summarized in the following table. Switching state D1_ pulse D2_ pulse D1 A OUT OF D2 OUT OF A DV OUT OF OUT OF DP A A

[0026] The resulting control depends on the duty cycle, which in turn determines whether the fault signal is less than 50% or greater than 50% of the midpoint of the peak voltage for the two ramp signals (half the peak voltage). An example of the ramp waveforms for a fault signal that is less than 50% of the midpoint voltages of the ramp signal is shown in Fig.Figure 4 shows that the first ramp signal begins a period at time t0, at which point the first ramp signal continues to rise until it is larger than the error signal at time t1. The second ramp signal begins its period only at time t2. This is in relation to Fig.The discussed signal D1_pulse is therefore on from time t0 to time t1, while the signal D2_pulse is off. Switching state D1 is thus activated from time t0 to t1. Between times t1 and t2, both signals D1_pulse and D2_pulse are off, so the DV switching state is activated from time t1 to time t2. At time t2, the signal D2_pulse is activated until it is deactivated when the second ramp signal is larger than the error signal at time t3. The first ramp signal does not begin for another period until after time t4. Thus, the signal D2_pulse is on and the signal D1_pulse is off from times t2 to t3, so switching state D2 is activated during this period. It is therefore evident that the switching states in this pattern continue from D1 to DV to D2 as long as the error signal is below the midpoint of the two ramp signals.Another such cycle begins at time t4 with switching state D1. The current in switching node I(SW) increases during switching state D1 because the input voltage charges the floating capacitor. During switching state DV, the current I(SW) decreases because the inductor is free-running. During switching state D2, the current I(SW) increases again because the floating capacitor discharges in switching node SW.

[0027] If the error signal rises above the midpoint for the ramp signals, the control system disclosed here generates the following: Fig.The waveforms shown in Figure 5 illustrate this. Because the ramp waveforms are 180° out of phase with each other and the fault signal is above their midpoints, a ramp signal starting from the beginning of a ramp period cannot rise above the fault signal before the remaining ramp signal begins another period. For example, the first ramp signal begins a period at time t0. Due to the phase relationship with the second ramp signal, the first ramp signal reaches its midpoint at time t1, when the second ramp signal begins its period. However, the fault signal is above the midpoint, so from time t1 until time t2, when the first ramp signal passes the fault signal, both the D1_pulse and D2_pulse signals are active. From time t0 until time t1, only the D1_pulse signal is active, so the switching period D1 is activated between times t0 and t1.From time t1 to time t2, the DP switching state is activated. Since the signal D1_pulse is off from time t2 until the start of its next period at time t3, switching state D2 is activated from time t2 to time t3. From time t3 to time t4, both the D1 and D2 phases are on, so the DP switching state is selected. The cycle from D1 to DP to D2 to DP would then repeat, so switching state D1 is activated at time t4. Due to the increase in the error signal, both switching states D1 and D2 demagnetize, so the switching current I(SW) decreases during these switching states. In contrast, the DP switching state is a magnetizing state such that the switching current I(SW) increases during the DP switching state.

[0028] When the fault signal exceeds the midpoint, it can be seen that switching states D1 and D2 essentially have a 50% duty cycle. When the fault signal falls slightly below the midpoint of the ramp signals, small periods of the DV switching state occur, while small periods of the DP switching states occur when the fault signal rises slightly above the midpoint. Thus, accurate regulation of the output voltage is advantageously provided over the range of fault signal amplitudes and also over a wide duty cycle range for the disclosed multi-stage buck converter.

[0029] The resulting control of the switching states for regulating the output power is advantageously modified to also regulate the voltage of the flying capacitor to the desired level of V_IN / 2. An exemplary multi-stage buck converter 600 is described in Fig.Figure 6 shows the switching transistors A, B, C, and D, the flying capacitor CF, the inductor L1, and the output capacitor C1 arranged as discussed in relation to the multi-stage buck converter 200. Additionally, the load is represented by a resistor RL. The output voltage is sampled by a voltage divider formed by resistors R1 and R2, so that the sampled output voltage can be compared to the reference voltage Vref in the error amplifier 205. The error signal voltage (Vea) from the error amplifier 205 is compensated by a loop filter formed by capacitors C2 and C3 and resistor RC. It is evident that an analog loop filter can be used to compensate for the error signal in the multi-stage buck converter 200. Fig.2 to compensate. The error signal voltage is compared at comparators 225 and 235 to generate the control signals 230 and 240 respectively, as well as in relation to Fig. 2. The first ramp signal generator 210 comprises a current source IR2 that drives a capacitor CR2. The voltage of the first ramp signal thus increases as the current source IR2 charges the capacitor CR2. Each ramp signal period for the first ramp signal begins by resetting the voltage across the capacitor CR2 via a switch S2. Similarly, the second ramp signal generator 220 comprises a current source IR1 that drives a capacitor CR1, which is reset by a switch S1.

[0030] An amplifier 605 monitors the voltage V CFof the flying capacitor, so that it can be compared with a reference voltage (Vcapref) of the flying capacitor at a transconductance amplifier 610. The output of the transconductance amplifier 610 is thus an error current Ierr, which represents the error (difference) between the voltage of the flying capacitor and the reference voltage of the flying capacitor. It is obvious that such an error signal can be a voltage error signal in alternative embodiments. With regard again to the Fig. 4 and Fig. It should be noted that the switching states D1 and D2 are either both magnetizing or both demagnetizing, depending on the error signal amplitude. If the sum of D1 and D2 is kept constant, the desired output power control is achieved. Fig.As can be seen in Figure 1, switching state D1 increases the voltage of the flying capacitor, while switching state D2 decreases it. If the voltage of the flying capacitor is too high, the control of the flying capacitor disclosed here increases the duration of switching state D2. However, switching state D1 must then be decreased so that the sum of D1 and D2 remains constant. To control the voltage of the flying capacitor, the multi-stage buck converter 600 therefore includes a switching control circuit 615 that modifies the periods for switching states D1 and D2 in response to the fault current Ierr, while the sum of the switching state periods D1 and D2 remains unchanged. To achieve this control, opposite edges of the signals D1_pulse and D2_pulse can be either delayed or introduced, depending on the sign of the fault current Ierr, as explained below.

[0031] Instead of adjusting the D1_pulse and D2_pulse signals in the switching control circuit 615, the ramp signal generation itself can be adjusted, as shown in Fig. Figure 6 shows that, for example, the two current sources IR1 and IR2 in the ramp signal generators 210 and 215 can be configured to respond to the fault current Ierr in a complementary manner. The ramp slope for the two ramp signals is adjusted such that the rate of increase for one ramp signal is increased, while the remaining rate of increase for the other ramp signal is decreased.

[0032] The following discussion concerns the adaptation of the signals D1_pulse and D2_pulse in the switching control circuit 615, since it can be shown that the resulting regulation of the voltage of the flying capacitor is advantageously decoupled from the output power control. An exemplary embodiment of the switching control circuit 615 is given in Fig.Figure 7 shows that the signal D1_pulse is delayed by a fixed delay circuit 715 (for example, by a delay of 1 / 4 of the period for the initial ramp signal) to form a delayed output signal that clocks a flip-flop 720. A Q output of the flip-flop 720 (designated RisingEdgeD1) is thus driven high after the 1 / 4 period delay from the rising edge of the signal D1_pulse. The Q output of the flip-flop 720 sets an RS latch 740. The Q output of the latch 740 is the delayed version of the signal D1_pulse, designated D1_pulse_delay. The fault current Ierr (marked with a + / - sign, as it can be positive or negative depending on the voltage error of the flying capacitor) drives a current-controlled delay circuit 700, which has the same nominal delay as the fixed delay circuit 715.If, for example, the fixed delay is 1 / 4 of the ramp period, then the nominal delay for the current-controlled delay circuit 700 is 1 / 4 of the ramp period. However, this nominal delay is either increased or decreased by a factor (denoted as Delta T) in response to the error current Ierr to produce an output signal whose falling edge clocks a flip-flop 725. Like the flip-flop 720, the data input D of the flip-flop 725 is bound to the supply voltage VDD such that the Q output of the flip-flop 725 goes high when the flip-flop 725 is clocked. The Q output of the flip-flop 725 (denoted FallingEdgeD1) resets the latch 740, which is reset dominantly to resolve conflicts between its set and reset instructions.The falling edge of the signal D1_pulse_delay is thus either advanced or delayed relative to its nominal delay of 1 / 4 period by the adjustment in the current-controlled delay circuit 700. The on-time for the signal D1_pulse_delay can therefore be either lengthened or shortened with respect to its rising edge to provide the desired adjustment of the switching state D1. Upon reset, the latch 740 activates a Q-bar signal (Q-complement) received by a one-shot circuit 745 triggered by a rising edge. The resulting one-shot pulse from the one-shot circuit 745 is received at the Clear (CLR) terminal for flip-flops 720 and 725 to reset them.

[0033] The signal D2_pulse is modified to form a delayed version (referred to as the D2_pulse_delay signal) in a complementary manner. Since the falling edge for the signal D1_pulse_delay has been modified, it is the rising edge for the signal D2_pulse_delay that is either advanced or delayed with respect to its nominal delay value. The signal D2_pulse is thus received by both a fixed delay circuit 710 and a current-controlled delay circuit 705, which has a corresponding nominal delay of 1 / 4 of the ramp period. Depending on the error current sign and amplitude, the current-controlled delay circuit 705 adjusts the nominal delay by a factor of ΔT, as described with respect to the current-controlled delay circuit 700.It is evident that in alternative embodiments, the fixed delay of 1 / 4 of the ramp period and the corresponding nominal delay of 1 / 4 of the ramp period can either be increased or decreased. The output signal of the current-controlled delay circuit 705 is received at the clock input of a flip-flop 730, which activates a Q output signal (designated RisingEdgeD2) in response to the rising edge of the output signal from the current-controlled delay circuit 705. The RisingEdgeD2 signal sets an SR latch 750 to activate the D2_plus_delay signal. The falling edge of the output signal from the fixed delay circuit 710 clocks a flip-flop 735 to activate a FallingEdgeD2 output signal, which resets the latch 750.In response to the reset, the Q-complement output of the latch 750 is pulled high to trigger a one-shot pulse from a rising-edge-triggered one-shot circuit 755, which resets the flip-flops 730 and 735 via their clear inputs. The control and gate driver circuit 760 includes a logic circuit similar to the LUT 310 in [reference missing]. Fig. 3. The resulting control of the switching states D1, D2, DV, and DP is as discussed in the table above, with the signals D1_pulse and D2_pulse being replaced by the signals D1_pulse_delay and D2_pulse_delay, respectively. The gate drive for the switching transistors A, B, and C is discussed below.

[0034] With reference to Fig.Figure 8 comprises a multi-stage buck converter 800, comprising a plurality of gate drivers for the switching transistors, which are powered by the regulated voltage of the flying capacitor. In particular, the switching transistors A, B, C, and D are arranged as discussed with reference to the multi-stage buck converter 600 ( Fig. 6) Similarly, inductor L1 and flying capacitor CF are arranged as discussed in relation to the multi-stage buck converter 600. For clarity, the components for regulating the output voltage and the voltage of the flying capacitor, such as the switching control circuit 615, the ramp generators 210 and 220, the transconductance amplifier 610, the error amplifier 205, etc., are shown in Fig.Components 8 and 8 are not shown but are assumed to be present to regulate the output voltage and the voltage of the flying capacitor. It should be noted that these components are powered by an internal power supply voltage VDD. This internal power supply voltage can be used to supply a gate driver 820 for switching transistor D, since the source for switching transistor D is connected to ground. The remaining switching transistors are floating with respect to such a direct ground connection, so the power supply voltage VDD is unsuitable for supplying their gate drivers. In particular, switching transistor A is switched on and off by a gate driver 805. Similarly, a gate driver 810 controls the gate voltage for switching transistor B, while a gate driver 815 controls the gate voltage for switching transistor C.The supply of energy to the gate drivers 805, 810 and 815 using the regulated voltage of the flying capacitor is carried out as follows.

[0035] Regarding the 815 gate driver, the source of switching transistor C is connected to a capacitor negative (CN) terminal for the flying capacitor. A capacitor positive (CP) terminal for the flying capacitor is connected to the power supply node for the 815 gate driver, allowing the voltage from the flying capacitor to directly power it. However, the sources of switching transistors A and B are not connected to the CN terminal for the flying capacitor, so their gate drivers cannot be directly connected to the CP terminal of the flying capacitor. Instead, a first boot capacitor CB1 is connected from the source of switching transistor A to the power supply node for the 805 gate driver to power the 805 gate driver.Likewise, a second boot capacitor CB2 is connected from the source of the switching transistor B to the power supply node for the gate driver 810 in order to supply power to the gate driver 810.

[0036] Charging the boot capacitors CB1 and CB2 by the flying capacitor is in relation to the in Fig. to better understand the 9 shown switching states. In particular, it shows Fig. 9 the switching states D1, D2, DV and DP, which are discussed in relation to figure. As in Fig.As shown in Figure 9, the boot capacitor CB2 is coupled in parallel with the flying capacitor in both the D1 and DV switching states. The flying capacitor CF thus charges the boot capacitor CB2 in these switching states. The switching transistor B is only switched on in the D2 and DP switching states, such that the charged boot capacitor CB2 can then provide the required gate voltage. To prevent the charged boot capacitor CB2 from discharging into the flying capacitor, the CP terminal for the flying capacitor is connected to the boot capacitor CB2 via a rectifier device, such as diode D2.

[0037] In switching states D2 and DP, the boot capacitors CB1 and CB2 are coupled in parallel such that charging boot capacitor CB2 in switching states D1 and DV provides the energy to charge boot capacitor CB1 in switching states D2 and DP. Thus, in switching states D1 and DP, the gate driver 805 is supplied with energy by the charged boot capacitor CB1, enabling it to switch on the switching transistor A. To prevent boot capacitor CB1 from discharging into boot capacitor CB2 in switching states D1 and DV, the power supply node for the gate driver 810 is connected to the power supply node for the driver 805 via a rectifier device, such as diode D1.Additionally, it should be noted that the internal power supply voltage VDD can support charging the power supply nodes for the gate drivers 805 and 810 by connecting the power supply rail for VDD to the power supply nodes via a rectifier device, such as diode D3. It is evident that diodes D1, D2, and D3 can be replaced by alternative rectifier devices, such as rectifier switches.

[0038] The voltage of the flying capacitor can be locked in such a way that the voltage of the flying capacitor neither falls below a minimum voltage nor rises above a maximum voltage, as in Fig. Figure 10 shows that in this exemplary embodiment, the minimum voltage is 3.5V and the maximum voltage is 5.5V, but it is obvious that other clamped voltages can be used in alternative embodiments. Referring again to Fig. 6. The reference voltage Vcapref, which is used in the control of the flying capacitor, can be determined from the input voltage V. IN The voltage can be derived by a voltage divider (not shown) formed by a series pair of resistors with equal resistances. However, the voltage resulting from the voltage divider can become stuck if it falls below the minimum voltage or rises above the maximum voltage. Preventing the flying capacitor voltage from falling below the minimum voltage, such as 3.5 V, ensures that sufficient voltage is available to supply the gate drivers. Similarly, preventing the flying capacitor voltage from exceeding the maximum voltage, such as 5.5 V, ensures that the gate drivers are not overloaded by excessive power supply voltages.

[0039] As is obvious to those skilled in the art, and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of this disclosure without altering their scope. Therefore, the scope of this disclosure should not be limited to the specific embodiments presented and described herein, as they are merely exemplary, but should correspond in full to the claims appended below and their functional equivalents.

Claims

[1] Multi-stage step-down converter (600, 800) which has the following features: a plurality of four switching transistors with four switching states with respect to an inductor (L1), wherein the plurality of four switching transistors comprises a first switching transistor (A) with a drain connected to an input voltage node (VIN), a second switching transistor (B) with a source connected to an input node for the inductor (L1) and with a drain connected to a source for the first switching transistor (A), a third switching transistor (C) with a drain connected to the source of the second switching transistor (B), and a fourth switching transistor (D) with a drain connected to a source for the third switching transistor (C) and with a source connected to ground; a flying capacitor (CF) with a positive terminal (CP) connected to the source of the first switching transistor (A) and a negative terminal (CM) connected to the source of the third switching transistor (C); a first gate driver (805) to drive a gate for the first switching transistor (A); a second gate driver (810) for driving a gate of the second switching transistor (B); a third gate driver (815) for driving a gate of the third switching transistor (C), wherein the positive terminal (CP) of the flying capacitor (CF) is connected to a power supply node for the third gate driver (815); a control device (615) configured to regulate the voltage of the flying capacitor (CF) using a reference voltage (Vcapref) derived from the input voltage (VIN), clamping the voltage of the flying capacitor (CF) when it falls below a minimum voltage or rises above a maximum voltage; a first boot capacitor (CB1) connected between the source of the first switching transistor (A) and a power supply node for the first gate driver (805); and a second boot capacitor (CB2) connected between the source of the second switching transistor (B) and a power supply node for the second gate driver (810). [2] Multi-stage step-down converter (600, 800) according to claim 1, further comprising: a first rectifier device (D1) connecting the power supply node for the second gate driver (810) to the power supply node for the first gate driver (805). [3] Multi-stage step-down converter (600, 800) according to claim 2, further comprising a second rectifier device (D2) which connects the positive terminal (CP) for the flying capacitor (CF) to the power supply node for the second gate driver (810). [4] Multi-stage step-down converter (600, 800) according to claim 3, wherein the first rectifier device (D1) has a first diode and the second rectifier device (D2) has a second diode. [5] Multi-stage step-down converter (600, 800) according to claim 3 or 4, further comprising: a first error amplifier (205) configured to generate a first error signal in response to a difference between an output voltage and a first reference voltage; and a second error amplifier (610) configured to generate a second error signal in response to a difference between a voltage across the flying capacitor and a second reference voltage; wherein the control device (615) is further configured to generate a first control signal which is activated at the beginning of each period for a first ramp signal and is reset when the first ramp signal exceeds the first error signal, and which is configured to generate a second control signal which is activated at the beginning of each period for a second ramp signal and is reset when the second ramp signal exceeds the first error signal, wherein the control device (615) is further configured to adapt the activation of the first control signal and the second control signal in response to the second error signal in order to generate an adapted first control signal and an adapted second control signal, and wherein the control device (615) comprises a logic circuit,which is configured to select each of the four switching states in response to a binary value for the adapted first control signal and for the adapted second control signal, in order to maintain control for the output voltage and for the voltage across the flying capacitor (CF). [6] Multi-stage step-down converter (600, 800) according to one of claims 1 or 2, further comprising: a first ramp generator (210) for generating the first ramp signal in response to a first clock signal; and a second ramp generator (220) for generating the second ramp signal in response to a second clock signal, wherein the first ramp signal is phase-shifted by 180° to the second ramp signal. [7] Multi-stage step-down converter (600, 800) according to claim 5 or 6, further comprising: a first latch (305) configured to be set in response to the start of each period for the first ramp signal and to be reset in response to the first ramp signal exceeding the first error signal, the first latch (305) further configured to generate the first control signal at a Q output; and a second latch (300) which is configured to be set in response to the start of each period for the second ramp signal and to be reset in response to the second ramp signal exceeding the first error signal, wherein the second latch (300) is further configured to generate the second control signal at a Q output. [8] Multi-stage step-down converter (600, 800) according to any one of claims 5 to 7, wherein the control device (615) is configured to be powered by a power supply voltage VDD, wherein the multi-stage step-down converter (600, 800) further comprises: a fourth gate driver (820) for the fourth switching transistor (D), wherein a power supply voltage node for the power supply voltage VDD is connected to a power supply node for the fourth gate driver (820). [9] Multi-stage step-down converter (600, 800) according to claim 8, further comprising: a third rectifier device (D3) that connects the power supply voltage node for the power supply voltage VDD to the power supply node for the second gate driver (810). [10] Method which features: Controlling a voltage of the flying capacitor for a flying capacitor (CF) in a multi-stage buck converter (600, 800) with four switching transistors, including a first switching transistor (A) with a source connected to an input voltage node (VIN), including a second switching transistor (B) with a drain connected to the source of the first switching transistor (A) and a source connected to an input node for an inductor (L1) for the multi-stage buck converter, a third switching transistor (C) with a drain connected to the source for the second switching transistor (B) and with a source connected to a negative terminal (CM) for the flying capacitor (CF); in a first switching state (D1) for the multi-stage buck converter, connecting a second boot capacitor (CB2) in parallel to the flying capacitor (CF) so that the voltage of the flying capacitor (CF) charges the second boot capacitor (CB2), wherein the first switching state (D1) further comprises connecting a power supply node for a third gate driver (815) to a positive terminal (CP) for the flying capacitor (CF) to supply energy to the third gate driver (815) to turn on the third switching transistor (C); in a second switching state (D2) for the multi-stage buck converter, switching on the second switching transistor (B) via a second gate driver (810), which is supplied with energy by the charged second boot capacitor (CB2); In the second switching state (D2) of the multi-stage buck converter, the charged second boot capacitor (CB2) is connected in parallel with a first boot capacitor (CB1) to charge the first boot capacitor (CB1), wherein the first switching state (D1) further features turning on a first switching transistor (A) by a first gate driver (805) which is powered by the charged first boot capacitor (CB1); and selecting from a plurality of four switching configurations, including the first switching state and the second switching state, to regulate the voltage of the flying capacitor using a reference voltage (Vcapref) derived from the input voltage (VIN), wherein the regulation of the voltage of the flying capacitor features clamping the voltage of the flying capacitor (CF) when the voltage of the flying capacitor (CF) falls below a minimum value or exceeds a maximum value. [11] Method according to claim 10, wherein the charging of the first boot capacitor (CB1) comprises charging the first boot capacitor by a first rectifier device (D1). [12] Method according to one of claims 10 or 11, wherein the charging of the second boot capacitor (CB2) comprises charging the second boot capacitor by a second rectifier device (D2). [13] Method according to any one of claims 10 to 12, further comprising: Generating an initial error signal in response to a difference between an output voltage for the multi-stage buck converter and an initial reference voltage; Generating a second error signal in response to a difference between the voltage of the flying capacitor and a second reference voltage; Activating an initial control signal at the beginning of each period for an initial ramp signal and resetting the initial control signal in response to the initial ramp signal exceeding the initial error signal, with the initial control signal having an on-time when activated; Activating a second control signal at the beginning of each period for a second ramp signal and resetting the second control signal in response to the second ramp signal exceeding the first error signal, wherein the second control signal has an on-time when activated, and wherein a total on-time is equal to a sum of the on-time for the first control signal and the on-time for the second control signal; In response to the second fault signal, adjust the on-time for the first control signal to generate a modified first control signal that is periodically activated for a first on-time and then reset, and adjust the on-time for the second control signal to generate a modified second control signal that is periodically activated for a second on-time and then reset, such that the sum of the first on-time and the second on-time equals the total on-time; and the selection from the multitude of four switching configurations, including the first switching state and the second switching state, further includes regulating the output voltage in response to whether the adapted first control signal and the adapted second control signal are activated or reset. [14] Method according to claim 13, wherein the regulation of the flying capacitor voltage maintains an average value for the flying capacitor voltage equal to half an input voltage for the multi-stage buck converter.

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