Radio receiver as part of a battery-powered, long-term energy-autonomous sensor arrangement

Abstract

Radio receiver (10) of the SDR type for narrowband radio transmission as part of a long-term energy-autonomous, battery-operated sensor arrangement, wherein the radio receiver (10) comprises a receiving device (1) which receives data (2) in the form of a data stream at a specific data rate and makes it available for further data processing, characterized in that Data (2) from the data stream are tapped at the receiving device (1) in an operating mode A selectable via a switching device (9) and fed to a microcontroller (3) with a definable sampling rate, the microcontroller (3) or the receiving device (1) reduces the diverted data by selecting a portion from the sample set, and the microcontroller (3) temporarily stores the decimated data in a memory (4, 18) and makes it available for further processing.

Description

[0001] The present invention relates to a radio receiver according to the preamble of claim 1 and a communication system for transmitting data. Technological background

[0002] The radio receivers of interest here, of the Software Defined Radio (SDR) type, typically contain a receiving unit, such as a radio chip, and are primarily used in battery-powered stationary sensor arrays with unidirectional or bidirectional data transmission. The data to be received includes, for example, data for operating the sensor array, such as update data, program data, control data, or the like, which is sent from a concentrator to the radio receiver. For reasons including minimizing energy consumption at the radio front end, the data or data telegrams are not transmitted by the concentrator in one piece, but rather in fragments as individual data packets or parts thereof (e.g., partial data packets), and are received by the radio receiver in this form.

[0003] Conventional radio chips are typically low-cost components with functions already integrated into the chip, which can only be modified to a very limited extent. Especially in narrowband radio transmissions, for example, the sampling rate must be precisely controlled, which cannot be set accurately on the radio chips themselves. If the sampling rate cannot be precisely controlled, complex computing power is required for resampling, which consumes a significant amount of electrical energy and is undesirable or impossible due to the need for a self-sufficient energy supply.

[0004] Furthermore, the analog-to-digital converter (ADC) contained in the radio chip is usually clocked by a clock generator, meaning that the sampling rate of the radio chip can only be set very imprecisely. On the other hand, efforts are being made, especially for the aforementioned applications, to provide radio receivers with the greatest possible range. Nearest state of the art

[0005] WO 2006 / 126166 A2 describes a special demodulator for a multi-mode receiver of a mobile phone, enabling it to operate in the GSM and UMTS bands, for example, with different baseband demodulation and bit rates depending on the mode. The demodulator receives samples of a data-modulated signal whose sampling rate is not an integer multiple of the data rate of the current mode, demodulates these samples, and outputs them at a sampling rate that is a fraction of the sampling rate of the received samples but an integer factor of the required data rate of the current mode. For this purpose, samples with an increased sampling rate compared to all modes are generated from the received samples in an analog-to-digital converter. The samples are then fed to a demodulator and from there to a fractional decimator.The latter reduces the output samples to a symbol rate suitable for the mode in question.

[0006] From EP 3 002 560 B1, a battery-powered stationary terminal device (or sensor arrangement) for performing wireless unidirectional transmission is known. The terminal device comprises a sensor for acquiring sensor data and for providing a sensor data packet based on the sensor data. By means of a data packet generation device, the sensor data packet is divided into at least three data packets, each of which is shorter than the sensor data packet itself. The sensor arrangement also includes a data packet transmission device designed to send the data packets at a data rate of less than 50 kbit / s and at intervals over a communication channel.

[0007] Due to the lower data rate compared to conventional data rates of 100 kbit / s, the signal-to-noise ratio at a data receiver (concentrator) can be reduced. Furthermore, the data packets are channel-coded by the data packet generation device in such a way that only a portion of the data packets is required to decode the sensor data packet. Thus, the use of such a terminal increases the transmission range from the terminal to the concentrator. However, the use of such a terminal does not improve the data transmission quality during transmission from the concentrator to the terminal. Object of the present invention

[0008] The object of the present invention is therefore to provide a radio receiver, in particular for a generic terminal device, with improved data transmission quality while simultaneously optimizing power consumption. Solution to the task

[0009] The foregoing problem is solved by a radio receiver according to claim 1 and by the dependent claims. Advantageous embodiments of the invention are described in the further claims.

[0010] A radio receiver according to the invention can be a radio receiver of the SDR type. For the purposes of this invention, SDR type encompasses concepts for high-frequency transmitters and receivers in which smaller or larger portions of the signal processing are implemented using software. The radio receiver comprises a receiving device (e.g., a radio chip) that receives the data in the form of at least one data packet or a part thereof (partial data packet) or a data stream at a specific data rate and makes it available for further data processing. In particular, the data stream can be continuous or semi-continuous (i.e., with interruptions).

[0011] By diverting the data within the receiving device in operating mode A and feeding it to a microcontroller, the microcontroller or the receiving device then reduces the data by selecting only a portion from the sample set, and the microcontroller temporarily stores the reduced data in memory for further processing, data can be processed without requiring significant computing power from the microcontroller and without resampling. This requires comparatively little electrical energy, thus placing only a minimal load on the self-contained power source. As a result, data transmission quality is improved while simultaneously reducing or optimizing power consumption.

[0012] The receiving device advantageously includes a filter that filters the data before it is fed to the microcontroller, thus reducing unnecessary calculations by the microcontroller. As a result, data transmission quality is further improved and energy consumption is reduced.

[0013] Furthermore, the microcontroller can decimate the data by discarding individual samples from the sample set and selecting samples based on an integer decimation factor. This reduces the transmitted sample size, which in turn reduces the bandwidth required for data transmission between the receiving device and the microcontroller. The sampling rate thus represents the maximum possible unfiltered bandwidth between the receiving device and the microcontroller and preferably corresponds to an integer factor of the (filtered) bandwidth used after the filter.

[0014] It has proven particularly advantageous if the bandwidth of the data supplied to the microcontroller or the bandwidth used after the filter is preferably less than 200 kHz, preferably less than 100 kHz and particularly preferably less than 50 kHz.

[0015] Because different sampling rates can be set on the microcontroller for different bandwidths, data transmission can be adapted to varying or abruptly changing transmission conditions. The wireless system can support different data rates to, for example, adapt to abruptly changing transmission conditions. Different data rates thus require different sampling rates and therefore different bandwidths. This further improves data transmission quality.

[0016] Preferably, a clock generator is provided, preferably a crystal oscillator or an oscillator with an RF crystal or crystal oscillator. The sampling rate is preferably determined by the clock frequency (or crystal frequency) of the clock generator. The clock generator can also serve as the clock generator for the analog-to-digital converter, so that the latter is clocked differently by changing the clock frequency or by selecting a clock generator with a specific clock frequency. The clock frequency is set or selected taking the decimation factor into account such that the desired sampling rate is achieved. This prevents costly resampling by the microcontroller.

[0017] It has proven particularly advantageous if the clock frequency of the clock generator is between 20 MHz and 50 MHz, preferably between 23 MHz and 25 MHz, 38 MHz and 40 MHz or 47 MHz and 49 MHz, and especially preferably at 24 MHz, 39 MHz or 48 MHz.

[0018] Advantageously, the sampling error that occurs during sampling can be modified by selecting the clock frequency of the clock generator. Preferably, the clock frequency is reduced.

[0019] It is particularly advantageous if the error of the clock generator or the quartz crystal after the change in clock frequency is less than 10 ppm, preferably less than 5 ppm, and especially preferably less than 3 ppm.

[0020] The operating mode A can be conveniently switched on and off via the radio receiver. This offers the advantage that receiving, forwarding, and further processing of data can be selectively carried out via operating mode A and can also be switched on and / or off during operation, allowing for flexible responses to changes in the transmission or processing sequence. This significantly improves data transmission quality and processing reliability.

[0021] According to a preferred embodiment, in addition to operating mode A, an operating mode C can be provided, in which the data is processed by a microprocessor or a logic or digital receiving circuit, which is connected downstream of and / or part of the receiving device. It is particularly advantageous if the radio receiver is designed to switch between operating mode A and operating mode C. In particular, this can be achieved by means of a switching device, which is, for example, an integral part of the receiving device.

[0022] Preferably, the data is transferred between the receiving device and the microcontroller in increments, i.e. step by step, with time intervals provided between the data transfer steps in which no transfer takes place.

[0023] According to a preferred embodiment, the microcontroller can enter a standby or sleep mode during periods when no data transmission is taking place, in order to reduce energy consumption during these periods. This allows for significant energy savings and thus, for example, increases the operating time or lifespan of a battery-powered, energy-autonomous device.

[0024] The microcontroller can also be conveniently configured to decode the data. This eliminates the need for an additional decoder.

[0025] Alternatively or additionally, the microcontroller can also be designed to process higher layers (especially of the OSI model). For example, the microcontroller can also take over program and / or process functions of the end device, such as sensor control or the evaluation of sensor readings. This eliminates the need for a separate microcontroller for sensor control, thereby significantly reducing energy consumption and manufacturing costs.

[0026] Advantageously, the receiver, microcontroller, and / or decoder can be designed as a single structural unit. It has proven particularly advantageous if the receiver, microcontroller, and / or decoder are implemented as an integrated circuit (IC). This offers the advantage of simple and cost-effective installation in / on the radio receiver.

[0027] The data is preferably processed after input to the receiving device using the I / Q (in-phase / quadrature) method; that is, the data is digital I / Q data. This can be achieved, for example, by splitting the analog input signal into two signal parts, one with the original phase (I-data) and the other with a reference frequency shifted by 90° (Q-data).

[0028] The SDR-type radio receiver is designed for use in an energy-autonomous, preferably long-term energy-autonomous, environment. Energy-autonomous or long-term energy-autonomous, as defined in the invention, refers in particular to an operating mode in which the radio receiver or the terminal device comprising the radio receiver operates without an external energy supply and can perform or maintain operation independently. The energy required for operation is preferably obtained from an energy storage device or energy source. Preferably, a battery is provided as the energy source, which is installed within the radio receiver or the terminal device and optionally encapsulated in a dustproof and waterproof manner. In particular, the battery capacity is less than 20 Ah.Furthermore, means for generating electrical energy (energy harvesting) can also be provided, whereby the electrical energy required for operation is obtained in particular from airflow, ambient lighting, ambient temperature, or vibrations (e.g., through piezoelectric effects). Advantageously, a combination of battery and energy harvesting can also be provided, which allows for further optimization of power consumption, especially in the present SDR concept.

[0029] Furthermore, the present invention claims a radio receiver of the SDR type for use in an energy-autonomous, preferably in a long-term energy-autonomous environment, with a receiving device that receives the data in the form of at least one data packet or a part thereof, or in a data stream at a specific data rate (and / or at a specific sampling rate) and makes it available for further data processing. In an operating mode B, the data is fed to a microprocessor or a digital receiving circuit (logic), respectively, in the receiving device. The data is then filtered by the microprocessor or the digital receiving circuit and subsequently decimated by selecting a portion from the sample set. In a practical manner, the decimation can be performed, for example, by the microprocessor and the algorithms or signal processing (e.g.,...)Decoding, demodulation, and / or similar tasks are performed by the microcontroller. Alternatively or additionally, the microprocessor can also handle the algorithms or signal processing.

[0030] Advantageously, operating mode B can be switched on and off by the radio receiver. In addition to operating mode B, operating mode C can also be provided, whereby the radio receiver can switch between operating mode B and operating mode C using the switching device.

[0031] Furthermore, the present invention claims a communication system for transmitting data between at least one concentrator and several, in particular a plurality, energy-autonomous terminal devices. Each terminal device comprises a radio receiver with a receiving unit that receives the data from the concentrator, in the form of at least one data packet, preferably a plurality of individual data packets, at a specific data rate (and / or at a specific sampling rate), and makes it available for further data processing. Furthermore, a radio receiver according to the invention is provided as the radio receiver, which, in an operating mode A within the receiving unit, diverts the data and feeds it to a microcontroller at a preferably definable sampling rate. The microcontroller or the receiving unit reduces the data by selecting a portion from the sample set.The microcontroller then temporarily stores the decimated data in memory and makes it available, for example, for further processing. Alternatively or additionally, the radio receiver can also supply the data in operating mode B to a microprocessor or a digital receiving circuit, respectively, and filter and then decimate the data by selecting a portion from the sample. Description of the invention using exemplary embodiments

[0032] Advantageous embodiments of the present invention are explained in more detail below with reference to the drawing figures. These show: Fig. 1 a simplified schematic representation of a communication system consisting of several terminal devices and a concentrator; Fig. 2 a simplified schematic representation of data sent in the form of multiple data packets; Fig. 3 a simplified schematic representation of a radio receiver according to the state of the art; Fig. 4 a simplified schematic representation of a first embodiment of the radio receiver according to the invention; Fig. 5 a simplified schematic representation of a further embodiment of the radio receiver according to the invention; Fig. 6 a simplified schematic representation of a further embodiment of the radio receiver according to the invention; Fig. 7 a simplified schematic representation of a further embodiment of the radio receiver according to the invention; Fig. 8 a simplified schematic representation of a further embodiment of the radio receiver according to the invention; Fig. 9 a simplified schematic representation of different operating modes; Fig. 10 a simplified schematic representation of an embodiment of a hardware-implemented radio receiver not belonging to the invention, as well as Fig. 11 a simplified schematic representation of a further embodiment of a radio receiver realized by hardware, which does not belong to the invention.

[0033] Fig. Figure 1 shows a communication system according to the invention in which several terminal devices 11, each with an integrated radio receiver 10 of the SDR (Software Defined Radio) type, communicate wirelessly with a transmitting and receiving unit 13 of a data collector 12. The terminal devices 11 can be, for example, consumption meters such as gas, water, heat meters, or energy meters, sensor units such as level sensors or temperature measuring devices, or other sensor nodes, e.g., of an IoT (Internet of Things) application. The receiving unit 1 can be configured as a radio chip, SoC (System-on-Chip), SoS (System-on-Silicon), SIP (System-in-Package), or the like. The terminal device 11 and the receiving unit 1 are expressly not gateways. The data collector 12 is configured in such a way that it can transmit the data 2 to the terminal devices 11 via the transmitting and receiving unit 13 and / or receive it from them.

[0034] The data 2 can be, for example, operational data, program update data, or firmware update data, which is transmitted, in particular, from the data collector 12 to the terminal devices 11. The data collector 12 can receive the data 2, for example, from a higher-level central unit (not shown in the figures), store it in a data memory 14, and then send it to the terminal devices 11. The data 2 is processed as shown in Fig. 2 represented, in the form of at least one data packet, preferably a plurality of data packets 2a transmitted.

[0035] In Fig. Figure 3 shows a radio receiver 110 of a type known from the prior art. The data 2 or data packets 2a are received and demodulated as an analog input signal by a receiving unit 101 of the radio receiver 110 in an operating mode C. An analog-to-digital converter (not shown in the figures) is provided to convert the analog input signal into a digital data stream. A microprocessor 115, either associated with or connected downstream of the receiving unit 101, serves for further processing and / or forwarding of the data 2. Furthermore, the radio receiver 110 has an oscillator or clock generator, which serves to determine the frequency used.

[0036] In Fig. Figure 4 shows an embodiment of the radio receiver 10 according to the invention. The radio receiver 10 comprises a receiving unit 1 and a microcontroller 3 and is preferably designed as a single structural unit, such as an integrated circuit (IC). According to the invention, the data 2 or data packets 2a, which are received as an analog signal, are tapped within the receiving unit 1 and fed to the microcontroller 3 via an interface 1a. The receiving unit 1 prepares the data in such a way that complex calculations by the microcontroller 3 are reduced or even prevented, and no significant degradation, e.g., due to aliasing, occurs. This is achieved by first digitizing the data 2 using the analog-to-digital converter (not shown in the figures), which is preferably arranged within the receiving unit 1, and then filtering it via a filter 6 of the receiving unit 1.The digitized data is provided to microcontroller 3 with a bandwidth equal to or smaller than the sampling rate, e.g., less than 50 kHz. Filter 6 then pre-filters the data 2 so that microcontroller 3 no longer needs to perform any filtering. The sampling rate describes the frequency with which the analog signal (a continuous-time signal) is sampled in one second, i.e., measured and converted into a discrete-time signal. For example, a value of 2 kHz or 4 kHz indicates that 2000 or 4000 samples are taken per second, respectively. The sampling rate to microcontroller 3 defines the bandwidth; that is, the sampling rate represents the maximum adjustable unfiltered bandwidth between receiver 1 and microcontroller 3.For example, with a sampling rate of 20 kHz, a maximum bandwidth of 20 kHz is theoretically possible, however, due to the filtering of filter 6 with a bandwidth of only 10 kHz, 3 is transmitted to the microcontroller (factor = 2).

[0037] The bandwidth during the transmission of data 2 from the receiving device 1 to the microcontroller 3 is therefore equal to or less than the sampling rate. This can be achieved, in particular, by the microcontroller 3 decimating the data 2 within a decimation unit 7 with a definable decimation factor N, i.e., the microcontroller 3 selects a portion from the sample set supplied by the receiving device 1. The decimation factor N is preferably an integer, such as 2, 3, or 4. For example, with a decimation factor N = 2, the microcontroller 3 omits every second sample, so that the bandwidth is reduced by a factor of 2 compared to the sampling rate.

[0038] Alternatively or in addition to filter 6, the microcontroller 3 can also have a filter 8, as shown in Fig. Figure 5 illustrates this. The microcontroller 3 can then store or temporarily buffer the decimated data in a memory 4, for example, in blocks, to make it available for further processing. The crystal oscillator 5 serves as the clock source for frequency generation and the carrier frequency, as well as for clocking the analog-to-digital converter. The clock source can be either an external unit or a structure functionally associated with the receiver 1. The sampling rate is determined primarily by changing the clock frequency of the crystal oscillator 5 accordingly, or by selecting the crystal oscillator 5 based on its clock frequency to clock the analog-to-digital converter differently. The clock frequency is set such that the crystal oscillator 5, together with the divider or decimation factor N, specifies the desired sampling rate.Therefore, additional filtering on the microcontroller 3 side or energy-intensive resamples are not necessary.

[0039] The data 2 are preferably processed after input to the receiving device 1 using the I / Q method (in-phase quadrature method), i.e., converted into I / Q data (digital data). This is done by splitting the analog input signal into two signal parts, one signal part being demodulated with the original phase (I-data) and the other signal part with a reference frequency shifted by 90° (Q-data). The I / Q data are then passed from the receiving device 1 to the microcontroller 3. The microcontroller 3 can then further process the data within an algorithm or use it for signal processing.

[0040] The operating method, as in Fig. 4 and Fig. Figure 5, for example, represents the first operating mode A, which can be selectively switched on and off in the radio receiver 10, even during operation. In addition to operating mode A, operating mode C may also be provided, which is shown in Fig. 4 and Fig. 5 is shown by the dashed arrow. In this configuration of the radio receiver 10, operating mode A and operating mode C can be selected or switched between by means of a selection or switching device 9.

[0041] The design of the radio receiver according to Fig. 6 is operated by means of an operating mode C. For this purpose, the receiving device 1 includes a microprocessor 15, which can alternatively also be designed as a digital receiving circuit. The microprocessor 15 is part of an RF front end with an A / D converter (not shown in the figures for clarity). In addition, the microprocessor 15 can include the filter 6 and its own memory, in particular a RAM memory 16. Alternatively or additionally, as in Fig. Figure 7 shows a shared (RAM) memory 18, which the microcontroller 3 and the microprocessor 15 can access, e.g., via a bus system. Furthermore, an additional operating mode can also be provided, which is described in Fig. 6 and Fig. Figure 7 illustrates this with the dashed lines and arrows. Switching between operating mode B and the additional operating mode can optionally also be performed during operation via the switching device 9.

[0042] Fig. Figure 8 shows a further alternative embodiment of the present invention, in which the microprocessor 15 of the receiving device 1 comprises the filter 6 and additionally has a decimation unit 17. This means that the microprocessor 15 filters and decimates the data before providing it to the microcontroller 3 for signal processing and / or storing it in memory 18. Equipping the microcontroller 3 with a filter 8 and a decimation unit 7 is optional. Preferably, the microcontroller 3 has greater efficiency for the required processing steps and is more performant than the microprocessor 15. However, the algorithmic processing and signal processing can also be performed by the microprocessor 15, provided it already possesses the necessary processing efficiency.

[0043] Furthermore, in Fig. Nine different operating modes I, II, and III of the radio receiver 10 are shown. The receiving unit 1 or the microprocessor 15 first performs filtering using the filter 6. The filter 6 can be, in particular, a high-pass, low-pass, or band-pass filter. If the filtering for decimation has been carried out sufficiently, the data can be transmitted to the microcontroller 3 according to operating mode I. The microcontroller 3 decimates the data by the decimation factor N (e.g., 2 or 4) using the decimation unit 7, by processing only every Nth sample and discarding the remaining samples. Subsequently, the microcontroller 3 can perform the algorithmic or signal processing.In the event that the filtering for decimation could not be performed sufficiently effectively, the data are first filtered in microcontroller 3 using filter 8, according to operating mode II, to achieve at least adequate filtering, and then decimated by decimation unit 7. Alternatively, the data can also be filtered by microprocessor 15 or a digital receiver circuit of receiver 1 using filter 6, according to operating mode III, and then decimated by the decimation unit 17 of microprocessor 15. The decimated data is then transferred to microcontroller 3 for algorithmic or signal processing, or the algorithmic or signal processing can be performed directly by microprocessor 15. In particular, operating modes I and II can be implemented, for example, via operating mode A, and operating mode III, for example, via operating mode B.

[0044] In Fig. Figure 10 shows a radio receiver 210, which is a type of radio receiver in which the signal processing is implemented exclusively in hardware. The radio receiver 210 is designed entirely as an application-specific integrated circuit (ASIC). Furthermore, a clock generator, in particular a crystal oscillator 5, is provided. The sampling error is modified, in particular reduced, by selecting the clock generator based on its clock frequency. Preferably, the selection of the clock generator can be made during the manufacturing process. Furthermore, the radio receiver 210 can also be designed according to Fig.11 shall be designed such that it can perform operating mode A as well as operating mode C (dashed arrow). As an alternative to the externally connected crystal oscillator 5, the radio receiver 210 can also include an internal clock generator, such as an integrated oscillator circuit, as a clock source. In practical terms, this design also includes embodiments of the radio receiver 210 not shown, which are configured to perform operating modes A, B and / or C and / or operating modes I, II and / or III, in particular in the manner described above.

[0045] The disclosure explicitly includes combinations of individual features (sub-combinations) as well as possible combinations of individual features of different forms not shown in the drawings. REFERENCE MARK LIST 1 Receiving device 1a interface 2 Data 2a Data package 3 microcontrollers 4 storage 5 quartz crystals 6 filters 7 Decimation Unit 8 filters 9 Switching device 10 radio receivers 11 End device 12 Concentrator 13 Transmitting and receiving unit 14 Data storage 15 microprocessor 16 GB RAM 17 Decimation 18 shared storage 101 Reception facility 105 quartz crystal 110 radio receivers 115 microprocessor 210 Receiving equipment

Claims

[1] Radio receiver (10) of the SDR type for narrowband radio transmission as a component of a long-term energy-autonomous, battery-operated sensor arrangement, wherein the radio receiver (10) comprises a receiving device (1) which receives data (2) in the form of a data stream at a specific data rate and makes it available for further data processing, characterized by , that Data (2) are branched off from the data stream in an operating mode A selectable via a switching device (9) at the receiving device (1) and fed to a microcontroller (3) with a definable sampling rate, the microcontroller (3) or the receiving device (1) decimates the branched data by selecting a part from the sample set, and the microcontroller (3) temporarily stores the decimated data in a memory (4, 18) and makes it available for further processing. [2] Radio receiver (10) of the SDR type for a narrowband radio transmission as a component of a long-term energy-autonomous, battery-operated sensor arrangement, wherein the radio receiver (10) comprises a receiving device (1) which receives data (2) in the form of a data stream with a specific data rate and makes it available for further data processing, in particular according to claim 1, characterized by , that the data (2) of the data stream are fed to a microprocessor (15) or a digital receiving circuit of the receiving device (1) in an operating mode B selectable via the switching device (9), the data (2) are filtered by the microprocessor (15) or the digital receiving circuit and subsequently decimated in a microcontroller (3) different from the microprocessor (15) by selecting a part from the sample set. [3] Radio receiver according to one of the preceding claims, characterized bythat the receiving device (1) comprises a filter (6) which filters the data (2) before it is fed to the microcontroller (3). [4] Radio receiver according to one of the preceding claims, characterized by that the microcontroller (3) comprises a filter (8) which filters the data (2) before decimation. [5] Radio receiver according to one of the preceding claims, characterized by that the decimation of the data (2) is carried out by the microcontroller (3) in that the microcontroller (3) disregards individual samples of the sample set supplied by the receiving device (1) and the selection of the samples is carried out on the basis of an integer decimation factor. [6] Radio receiver according to one of the preceding claims, characterized by that the sampling rate of the sample quantity supplied by the receiving device (1) represents an integer factor of the bandwidth between the receiving device (1) and the microcontroller (3). [7] Radio receiver according to claims 3 and 6, characterized by that the bandwidth with which the data (2) are fed to the microcontroller (3) after the filter (6) is less than 200 kHz, preferably less than 100 kHz and particularly preferably less than 50 kHz. [8] Radio receiver according to one of the preceding claims, characterized by that different sampling rates can be set on the microcontroller (3) for different bandwidths. [9] Radio receiver according to one of the preceding claims, characterized by that a quartz crystal (5) is provided as the clock generator. [10] Radio receiver according to claim 9, characterized by that the sampling rate is determined based on the clock frequency of the clock generator. [11] Radio receiver according to claim 9 or 10, characterized bythat the clock frequency of the clock generator is between 20 MHz and 50 MHz, preferably between 23 MHz and 25 MHz, 38 MHz and 40 MHz or 47 MHz and 49 MHz, particularly preferably 24 MHz, 39 MHz or 48 MHz. [12] Radio receiver according to one of claims 9-11, characterized by that the error of the clock frequency of the clock generator is less than 10 ppm, preferably less than 5 ppm, particularly preferably less than 3 ppm. [13] Radio receiver according to one of the preceding claims, characterized by that the sampling error is reduced by selecting the clock generator with regard to its clock frequency. [14] Radio receiver according to one of the preceding claims, characterized by that operating mode A and / or operating mode B can be switched on and off. [15] Radio receiver according to one of the preceding claims, characterized bythat in addition to the operating mode A or the operating mode B, an operating mode C is provided, in which the data (2) are processed by a microprocessor (15) or a digital receiving circuit of the receiving device (1) before being transmitted to the microcontroller (3), and it is possible to switch between the operating mode A or operating mode B and the operating mode C. [16] Radio receiver according to one of the preceding claims, characterized by that the transmission of the data (2) between the receiving device (1) and the microcontroller (3) takes place step by step and time intervals are provided between the transmission of the data in which no transmission takes place. [17] Radio receiver according to claim 16, characterized by that the microcontroller (3) goes into sleep mode in the time intervals in which no transmission of the data (2) takes place. [18] Radio receiver according to one of the preceding claims, characterized bythat the microcontroller (3) is designed to decode the data (2). [19] Radio receiver according to one of the preceding claims, characterized by that the microcontroller (3) is designed to process higher layers in addition to processing and storing the data (2). [20] Radio receiver according to one of the preceding claims, characterized by that the receiving device (1) and the microcontroller (3) are designed as an integrated circuit. [21] Radio receiver according to one of the preceding claims, characterized by that the data (2) are I / Q data. [22] Radio receiver according to one of the preceding claims, characterized by that the radio receiver (10, 210) comprises a battery with a capacity of less than 20 Ah. [23] Communication system for transmitting data (2) between at least one concentrator (12) and several, preferably a plurality of, energy-autonomous terminals (11), wherein a terminal (12) comprises a radio receiver (10, 210) with a receiving device (1), the receiving device (1) receives the data (2) of the concentrator (12) in the form of at least one data packet or a part thereof or a data stream with a specific data rate and preferably makes it available for further data processing, characterized by , that a radio receiver (10, 210) according to the preceding claims is provided as the radio receiver.

Images