Epitactic source or drain structures for advanced integrated circuit fabrication

Abstract

An integrated circuit structure (700), comprising: a first fin (702) which contains silicon; a second fin (702) which contains silicon; an insulating structure (704) between the first fin and the second fin; a first epitaxial source or drain structure (910) on the first fin, wherein the first epitaxial source or drain structure and the first fin meet at a first interface; a second epitaxial source or drain structure (910) on the second fin, wherein the second epitaxial source or drain structure and the second fin meet at a second interface; a dielectric material layer (714) extending continuously from above the first interface but below a top surface of the first epitaxial source or drain structure, along a section of a side wall of the first fin, on the insulating structure, along a section of a side wall of the second fin, to above the second interface but below a top surface of the second epitaxial source or drain structure.

Description

TECHNICAL AREA

[0001] Embodiments of the disclosure lie in the field of advanced integrated circuit structure fabrication and in particular 10-nanometer node and smaller integrated circuit structure fabrication and the resulting structures. BACKGROUND

[0002] In recent decades, the scaling of features in integrated circuits has been a driving force behind the ever-expanding semiconductor industry. Scaling down to ever smaller features enables increased densities of functional units on the limited usable area of ​​semiconductor chips. For example, shrinking the transistor size allows for the inclusion of a greater number of memory or logic devices on a single chip, which is advantageous for manufacturing products with increased capacity. However, the drive for ever greater capacities also presents some challenges. The need to optimize the performance of each device is becoming increasingly critical.

[0003] Variables in conventional and currently known manufacturing processes may limit the possibility of further extending them into the 10-nanometer node or sub-10-nanometer node range. Consequently, the fabrication of functional components required for future technology nodes may necessitate the introduction of new methodologies or the integration of new technologies into, or replacement with, current manufacturing processes.

[0004] The publications describe well-known US 9911824 B2 and US 9847224 B2 semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A illustrates a cross-sectional view of an initial structure following deposition but prior to structuring a hard mask material layer formed on an interlayer dielectric (ILD) layer. Fig. Figure 1B illustrates a cross-sectional view of the structure. Fig. 1 A following the structuring of the hard mask layer by halving the grid dimension. Fig. Figure 2A is a diagram of a grid-dimensioning approach used for manufacturing semiconductor fins, according to an embodiment of the present disclosure. Fig. Figure 2B illustrates a cross-sectional view of semiconductor fins manufactured using a grid-dimensioned quartering approach, according to an embodiment of the present disclosure. Fig. Figure 3A is a diagram of a union fin grid quartering approach used for manufacturing semiconductor fins, according to an embodiment of the present disclosure. Fig. Figure 3B illustrates a cross-sectional view of semiconductor fins manufactured using a union fin grid quartering approach, according to an embodiment of the present disclosure. Fig. 4A-4C Cross-sectional views representing different operations in a method for manufacturing multiple semiconductor fins according to an embodiment of the present disclosure. Fig. Figure 5A illustrates a cross-sectional view of a pair of semiconductor fins separated by a three-layer trench insulation structure according to an embodiment of the present disclosure. Fig. Figure 5B illustrates a cross-sectional view of another pair of semiconductor fins separated by a different three-layer trench insulation structure, according to another embodiment of the present disclosure. Fig. Figures 6A-6D illustrate a cross-sectional view of various processes in the manufacture of a three-layer trench insulation structure according to an embodiment of the present disclosure. Fig. Figures 7A-7E illustrate inclined three-dimensional cross-sectional views of various processes in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure. Fig. Figures 8A-8F illustrate slightly projected cross-sectional views along the a-a' axis. Fig. 7E for various operations in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure. Fig. Figure 9A illustrates a slightly projected cross-sectional view along the a-a' axis. Fig. 7E for an integrated circuit structure including permanent gate stacks and epitaxial source or drain regions according to an embodiment of the present disclosure. Fig. Figure 9B illustrates a cross-sectional view along the b-b' axis. Fig. 7E for an integrated circuit structure including epitaxial source or drain regions and a multilayer trench insulation structure according to an embodiment of the present disclosure. Fig. Figure 10 illustrates a cross-sectional view of an integrated circuit structure at a source or drain position according to an embodiment of the present disclosure. Fig. Figure 11 illustrates a cross-sectional view of another integrated circuit structure at a source or drain position according to an embodiment of the present disclosure. Fig. Figures 12A-12D illustrate cross-sectional views at a source or drain position and represent various processes in the fabrication of an integrated circuit structure according to an embodiment of the present disclosure. Fig. 13A and Fig. Figure 13B illustrates top views representing various processes in a method for structuring fins with multiple gate spacing to form a local isolation structure, according to an embodiment of the present disclosure. Fig. Figures 14A-14D illustrate top views representing various processes in a method for structuring fins with single-gate spacing to form a local isolation structure, according to another embodiment of the present disclosure. Fig. Figure 15 illustrates a cross-sectional view of an integrated circuit structure with a fin having multiple gate spacing for local isolation according to an embodiment of the present disclosure. Fig. Figure 16A illustrates a cross-sectional view of an integrated circuit structure with a fin having single-gate spacing for local isolation according to another embodiment of the present disclosure. Fig. Figure 16B illustrates a cross-sectional view showing positions where a fin insulation structure can be formed instead of a gate electrode, according to an embodiment of the present disclosure. Fig. Figures 17A-17C illustrate various depth profiles for a fin cut produced using a fin trimming isolation approach, according to an embodiment of the preset disclosure. Fig. Figure 18 illustrates a top view and a corresponding cross-sectional view along the a-a' axis, showing possible options for the depth of local versus wider positions of fin cuts within a fin, according to an embodiment of the present disclosure. Fig. 19A and Fig. Figure 19B illustrates cross-sectional views of various processes in a method for selecting fin end stressor positions at the ends of a fin having a wide cut, according to an embodiment of the present disclosure. Fig. 20A and Fig. Figure 20B illustrates cross-sectional views of various processes in a method for selecting fin end stressor positions at the ends of a fin having a local cut, according to an embodiment of the present disclosure. Fig. Figures 21A-21M illustrate cross-sectional views of various processes in a method for manufacturing an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure. Fig. Figures 22A-22D illustrate cross-sectional views of exemplary structures of a PMOS fin end stressor dielectric plug according to an embodiment of the present disclosure. Fig. 23A illustrates a cross-sectional view of another semiconductor structure with mechanical stress-inducing fin end features according to another embodiment of the present disclosure. Fig. Figure 23B illustrates a cross-sectional view of another semiconductor structure with mechanical stress-inducing fin end features according to another embodiment of the present disclosure. Fig. Figure 24A illustrates an inclined view of a fin with uniaxial tensile stress according to an embodiment of the present disclosure. Fig. Figure 24B illustrates an inclined view of a fin with uniaxial compressive stress according to an embodiment of the present disclosure. Fig. 25A and Fig. Figure 25B illustrates top views representing various processes in a method for structuring fins with single-gate spacing to form a local isolation structure in select-gate line section positions, according to an embodiment of the present disclosure. Fig. Figures 26A-26C illustrate cross-sectional views of various dielectric plug options for polycut and fin trim insulation (FTI) local fin cut positions and polycut-only positions for different areas of the structure. Fig. 25B according to one embodiment of the present disclosure. Fig. Figure 27A illustrates a top view and corresponding cross-sectional view of an integrated circuit structure with a gate-line section having a dielectric plug extending into dielectric spacers of the gate line, according to an embodiment of the present disclosure. Fig. Figure 27B illustrates a top view and corresponding cross-sectional view of an integrated circuit structure with a gate-line section having a dielectric plug extending beyond dielectric spacers of the gate line, according to another embodiment of the present disclosure. Fig. Figures 28A-28F illustrate cross-sectional views of various processes in a method for manufacturing an integrated circuit structure having a gate-line section, with a dielectric plug having an upper part extending beyond dielectric spacers of the gate line and a lower part extending into the dielectric spacers of the gate line, according to another embodiment of the present disclosure. Fig. Figures 29A-29C illustrate a top view and corresponding cross-sectional views of an integrated circuit structure with residual dummy gate material at parts of the bottom of a permanent gate stack according to an embodiment of the present disclosure. Fig. Figures 30A-30D illustrate cross-sectional views of various processes in a method for fabricating an integrated circuit structure with residual dummy gate material at parts of the underside of a permanent gate stack according to another embodiment of the present disclosure. Fig. Figure 31A illustrates a cross-sectional view of a semiconductor device with a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure. Fig. Figure 31B illustrates a cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present disclosure. Fig. Figure 32A illustrates a top view of several gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure. Fig. Figure 32B illustrates a cross-sectional view along the a-a' axis. Fig. 32A according to an embodiment of the present disclosure. Fig. Figure 33A illustrates cross-sectional views of a pair of NMOS devices with a differentiated voltage threshold based on modulated doping and a pair of PMOS devices with a differentiated voltage threshold based on modulated doping according to an embodiment of the present disclosure. Fig. Figure 33B illustrates cross-sectional views of a pair of NMOS devices with a differentiated voltage threshold based on a differentiated gate-electrode structure and a pair of PMOS devices with a differentiated voltage threshold based on a differentiated gate-electrode structure according to another embodiment of the present disclosure. Fig. Figure 34A illustrates cross-sectional views of a group of three NMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure and on a modulated doping, and a group of three PMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure and on a modulated doping according to an embodiment of the present disclosure. Fig. Figure 34B illustrates cross-sectional views of a group of three NMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure and on modulated doping, and a group of three PMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure and on modulated doping according to another embodiment of the present disclosure. Fig. Figures 35A-35D illustrate cross-sectional views of various processes in a method for manufacturing NMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure according to another embodiment of the present disclosure. Fig. Figures 36A-36D illustrate cross-sectional views of various processes in a method for manufacturing PMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure according to another embodiment of the present disclosure. Fig. Figure 37 illustrates a cross-sectional view of an integrated circuit structure with a p / n junction according to an embodiment of the present disclosure. Fig. Figures 38A-38H illustrate cross-sectional views of various processes in a method for manufacturing an integrated circuit structure using a double-metal-gate-replacement-gate process flow according to an embodiment of the present disclosure. Fig. Figures 39A-39H illustrate cross-sectional views representing various operations in a method for manufacturing a double silicide-based integrated circuit according to an embodiment of the present disclosure. Fig. Figure 40A illustrates a cross-sectional view of an integrated circuit structure with trench contacts for an NMOS device according to an embodiment of the present disclosure. Fig. Figure 40B illustrates a cross-sectional view of an integrated circuit structure with trench contacts for a PMOS device according to another embodiment of the present disclosure. Fig. Figure 41A illustrates a cross-sectional view of a semiconductor device with a conductive contact on a source or drain region according to an embodiment of the present disclosure. Fig. Figure 41B illustrates a cross-sectional view of another semiconductor device having a conductive element on a raised source or drain area according to an embodiment of the present disclosure. Fig. Figure 42 illustrates a top view of several gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure. Fig. Figures 43A-43C illustrate cross-sectional views along the a-a' axis. Fig. 42 for various operations in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure. Fig. Figure 44 illustrates a cross-sectional view along the b-b' axis. Fig. 42 for an integrated circuit structure according to an embodiment of the present disclosure. Fig. 45A and Fig. Figure 45B illustrates a top view or corresponding cross-sectional view of an integrated circuit structure including trench contact plugs with a hard mask material thereon according to an embodiment of the present disclosure. Fig. Figures 46A-46D illustrate cross-sectional views representing various operations in a method for manufacturing an integrated circuit structure including trench contact plugs with a hard mask material thereon, according to an embodiment of the present disclosure. Fig. Figure 47A illustrates a top view of a semiconductor device with a gate contact positioned over a non-active part of a gate electrode. Fig. Figure 47B illustrates a cross-sectional view of a non-planar semiconductor device with a gate contact positioned over a non-active part of a gate electrode. Fig. Figure 48A illustrates a top view of a semiconductor device with a gate contact via arranged over an active part of a gate electrode, according to an embodiment of the present disclosure. Fig. Figure 48B illustrates a cross-sectional view of a non-planar semiconductor device with a gate contact via arranged over an active part of a gate electrode, according to an embodiment of the present disclosure. Fig. Figures 49A-49D illustrate cross-sectional views representing various operations in a method for manufacturing a semiconductor structure with a gate-contact structure arranged over an active part of a gate, according to an embodiment of the present disclosure. Fig. Figure 50 illustrates a top view and corresponding cross-sectional views of an integrated circuit structure with trench contacts including an overlying insulating cap layer according to an embodiment of the present disclosure. Fig. Figures 51A-51F illustrate cross-sectional views of various integrated circuit structures, each with trench contacts including an overlying insulation cap layer and with gate stacks including an overlying insulation cap layer, according to an embodiment of the present disclosure. Fig. Figure 52A illustrates a top view of another semiconductor device having a gate contact via arranged over an active part of a gate, according to another embodiment of the present disclosure. Fig. Figure 52B illustrates a top view of another semiconductor device having a trench contact via coupling a pair of trench contacts, according to another embodiment of the present disclosure. Fig. Figures 53A-53E illustrate cross-sectional views representing various operations in a method for manufacturing an integrated circuit structure with a gate stack having an overlying insulation cap structure, according to an embodiment of the present disclosure. Fig. Figure 54 is a diagram of a grid-division quartering approach used to produce trenches for intermediate connection structures, according to an embodiment of the present disclosure. Fig. Figure 55A illustrates a cross-sectional view of a metallization layer produced using a grid-dimensioned quarter scheme, according to an embodiment of the present disclosure. Fig. Figure 55B illustrates a cross-sectional view of a metallization layer produced using a grid-dimensioning scheme above a metallization layer produced using a grid-dimensioning scheme, according to an embodiment of the present disclosure. Fig. Figure 56A illustrates a cross-sectional view of an integrated circuit structure comprising a metallization layer with a metal conductor composition above a metallization layer with a different metal conductor composition, according to an embodiment of the present disclosure. Fig. Figure 56B illustrates a cross-sectional view of an integrated circuit structure comprising a metallization layer with a metal conductor composition coupled with a metallization layer with a different metal conductor composition, according to an embodiment of the present disclosure. Fig. Figures 57A-57C illustrate cross-sectional views of individual intermediate connecting lines with various lining and conductive covering structure arrangements according to an embodiment of the present disclosure. Fig. Figure 58 illustrates a cross-sectional view of an integrated circuit structure comprising four metallization layers with a metal conductor composition and a grid dimension above two metallization layers with a different metal conductor composition and smaller grid dimension, according to an embodiment of the present disclosure. Fig. Figures 59A-59D illustrate cross-sectional views of various intermediate conductor and via arrangements with a lower conductive layer according to an embodiment of the present disclosure. Fig. Figures 60A-60D illustrate cross-sectional views of structural arrangements for a recessed conductor topography of a BEOL metallization layer according to an embodiment of the present disclosure. Fig. Figures 61A-61D illustrate cross-sectional views of structural arrangements for a stepped conduction topography of a BEOL metallization layer according to an embodiment of the present disclosure. Fig. Figure 62A illustrates a top view and corresponding cross-sectional view along the a-a' axis of the top view of a metallization layer according to an embodiment of the present disclosure. Fig. Figure 62B illustrates a cross-sectional view of a conduit end or plug according to an embodiment of the present disclosure. Fig. Figure 62C illustrates another cross-sectional view of a conduit end or plug according to an embodiment of the present disclosure. Fig. Figures 63A-63F illustrate top views and corresponding cross-sectional views representing various operations in a scheme of processing a plug as the last step, according to an embodiment of the present disclosure. Fig. Figure 64A illustrates a cross-sectional view of a conductive conduit plug with a seam therein according to an embodiment of the present disclosure. Fig. Figure 64B illustrates a cross-sectional view of a stack of metallization layers including a conductive conduit plug at a lower metal conduit position according to an embodiment of the present disclosure. Fig. Figure 65 illustrates a first view of a cell layout for a memory cell. Fig. Figure 66 illustrates a first view of a cell layout for a memory cell with an internal node jumper according to an embodiment of the present disclosure. Fig. Figure 67 illustrates a second view of a cell layout for a memory cell. Fig. Figure 68 illustrates a second view of a cell layout for a memory cell with an internal node jumper according to an embodiment of the present disclosure. Fig. Figure 69 illustrates a third view of a cell layout for a memory cell. Fig. Figure 70 illustrates a third view of a cell layout for a memory cell with an internal node jumper according to an embodiment of the present disclosure. Fig. 71A and Fig. Figure 71B illustrates a bit cell layout or a schematic diagram for a six-transistor (6T) static random access memory (SRAM) according to an embodiment of the present disclosure. Fig. Figure 72 illustrates cross-sectional views of two different layouts for an identical standard cell according to one embodiment of the present disclosure. Fig. Figure 73 illustrates top views of four different cell arrangements indicating the even (E) or odd (O) designation, according to one embodiment of the present disclosure. Fig. Figure 74 illustrates a top view of a block plane polylattice according to an embodiment of the present disclosure. Fig. Figure 75 illustrates an exemplary acceptable (existing) layout based on standard cells with different versions according to an embodiment of the present disclosure. Fig. Figure 76 illustrates an exemplary unacceptable (failure) layout based on standard cells with different versions according to an embodiment of the present disclosure. Fig. Figure 77 illustrates another exemplary acceptable (existing) layout based on standard cells with different versions according to an embodiment of the present disclosure. Fig. Figure 78 illustrates a partial sectional plan view and a corresponding cross-sectional view of a fin-based thin-film resistance structure, wherein the cross-sectional view is shown along the a-a' axis of the partial sectional plan view, according to an embodiment of the present disclosure. Fig. Figures 79-83 illustrate top views and corresponding cross-sectional views representing various processes in a method for manufacturing a fin-based thin-film resistance structure according to an embodiment of the present disclosure. Fig. Figure 84 illustrates a top view of a fin-based thin-film resistor structure with a plurality of exemplary positions for anode or cathode electrode contacts according to an embodiment of the present disclosure. Fig. Figures 85A-85D illustrate top views of various fin geometries for manufacturing a fin-based precision resistor according to an embodiment of the present disclosure. Fig. Figure 86 illustrates a cross-sectional view of a lithography mask structure according to an embodiment of the present disclosure. Fig. 87 illustrates a computing device according to an implementation of the disclosure. Fig. Figure 88 illustrates an interposer that includes one or more embodiments of the disclosure. Fig. Figure 89 is an isometric view of a mobile computing platform employing an IC manufactured according to one or more of the processes described herein or incorporating one or more of the features described herein, according to an embodiment of the present disclosure. Fig. Figure 90 illustrates a cross-sectional view of a flip-chip mounted die according to an embodiment of the present disclosure. DESCRIPTION OF THE EXECUTION FORMS

[0005] An advanced integrated circuit structure fabrication process is described. Numerous specific details, such as particular integration and material conditions, are presented in the following description to provide a comprehensive understanding of the embodiments of this disclosure. It will be obvious to a person skilled in the art that embodiments of this disclosure can be implemented without these specific details. In other cases, generally known features, such as design layouts of integrated circuits, are not described in detail in order to avoid unnecessarily obscuring the embodiments of this disclosure. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0006] The following detailed description is merely exemplary and is not intended to limit the embodiments of the subject matter or the applications and uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be considered preferred or advantageous over other implementations. Furthermore, there is no intention to be limited by any theory, expressed or implied, presented in the preceding technical field, background, summary, or the following detailed description.

[0007] This description includes references to "an embodiment" or "a form of embodiment". The appearance of the phrase "in an embodiment" does not necessarily refer to the same embodiment. Certain features, structures, or properties may be combined in any suitable manner consistent with this disclosure.

[0008] Terminology. The following paragraphs provide definitions or context for terms that appear in this disclosure (including the attached claims):

[0009] "Comprehensive." This expression is open-ended. As used in the attached claims, this expression does not exclude additional structures or processes.

[0010] "Configured to." Various units or components may be described or claimed to be "configured to perform a task or tasks." In such contexts, "configured to perform" is used to imply a structure by indicating that the units or components contain a structure that performs that task or tasks during operation. Therefore, it can be said that the unit or component is configured to perform the task even if the specified unit or component is not currently operational (for example, not powered on or active). Describing that a unit, circuit, or component is "configured to perform one or more tasks" is expressly not intended to invoke 35 USC §112, sixth paragraph, for that unit or component.

[0011] “First”, “Second”, etc. As four is used, these terms are used as labels for nouns they precede and do not imply any kind of order (e.g. spatial, temporal, logical, etc.).

[0012] "Coupled" - The following description refers to elements, nodes, or features that are "coupled" to one another. As used here, unless explicitly stated otherwise, "coupled" means that an element, node, or feature is directly or indirectly joined to (or communicates with) another element, node, or feature, and not necessarily mechanically.

[0013] Furthermore, certain terminology used in the following description may be for reference only and is therefore not intended to be restrictive. For example, terms such as "top," "bottom," "above," and "below" refer to directions in the referenced drawings. Terms such as "front," "back," "rear," "side," "outside of the board," and "inside the board" describe the orientation or position, or both, of parts of the component within a consistent but arbitrary frame of reference, clarified by reference to the text and associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0014] "Hiding" - As used here, "hindering" is used to describe a reduction or minimization effect. When a component or feature is described as hindering an action, movement, or condition, it may completely prevent the outcome, result, or future state. Furthermore, "hindering" can also refer to a reduction or decrease in the outcome, performance, or effect that might otherwise occur. Accordingly, when a component, element, or feature is described as hindering an outcome or state, it need not completely prevent or eliminate the outcome or state.

[0015] The embodiments described here can be applied to FEOL semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, in which the individual devices (e.g., transistors, capacitors, resistors, etc.) are structured within the semiconductor substrate or semiconductor layer. FEOL generally covers everything up to (but not including) the deposition of metal interlayers. Following the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0016] The embodiments described here can be applied to BEOL semiconductor processing (BEOL: Back-End-Of-Line) and structures. BEOL is the second part of IC manufacturing, where the individual components (e.g., transistors, capacitors, resistors, etc.) are interconnected via wiring on the wafer, such as the metallization layer(s). BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-package connections. In the BEOL part of the manufacturing process, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in the BEOL.

[0017] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both. In particular, although an exemplary processing scheme may be illustrated using an FEOL processing scenario, such approaches can also be applied to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches can also be applied to FEOL processing.

[0018] Grid spacing processing and structuring scenarios can be implemented to enable, or may be included as part of, the embodiments described herein. Grid spacing structuring typically refers to grid spacing halving, grid spacing quartering, etc. Grid spacing schemes may be applicable to FEOL processing, BEOL processing, or both FEOL (fixture) and BEOL (metallization) processing. According to one or more of the embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., either strictly unidirectional or mostly unidirectional) at a predefined grid spacing. Grid spacing processing is then implemented as a technique to increase line density.

[0019] In one embodiment, the term "grid structure" is used here to refer to fins, gate leads, metal leads, ILD leads, or hard mask leads, specifically to a grid structure with a narrow pitch. In such an embodiment, the narrow pitch is not directly achievable through a selected lithography. For example, a structure based on a selected lithography can first be formed, but the pitch can be halved by using spacer mask structuring, as is known in the art. Furthermore, the original pitch can be quartered by a second pass of spacer mask structuring. Accordingly, the grid-like structures described here can feature metal leads, ILD leads, or hard mask leads with a substantially uniform pitch and width.For example, in some embodiments the grid dimension variation would be within ten percent and the width variation would be within ten percent, and in other embodiments the grid dimension variation would be within five percent and the width variation would be within five percent. The structuring can be achieved by a grid dimension halving, grid dimension quartering, or another grid dimension division approach. In one embodiment, the grid does not necessarily have a single grid dimension.

[0020] In a first example, a grid dimension halving can be implemented to double the line density of a manufactured grid structure. Fig. Figure 1A illustrates a cross-sectional view of an initial structure following deposition but prior to structuring a hard mask material layer formed on an interlayer dielectric (ILD) layer. Fig. Figure 1B illustrates a cross-sectional view of the structure. Fig. 1A following the structuring of the hard mask layer by halving the grid dimension.

[0021] With reference to Fig. 1A has an initial structure 100 comprising a hard mask material layer 104 formed on an interlayer dielectric (ILD) layer 102. A structured mask 106 is arranged above the hard mask material layer 104. The structured mask 106 has spacers 108 formed along the sidewalls of features (conductors) on the hard mask material layer 104.

[0022] With reference to Fig. In step 1B, the hard mask material layer 104 is structured using a half-grid approach. Specifically, the structured mask 106 is removed first. The resulting structure of the spacers 108 has twice the density, or half the grid spacing, or the features of the mask 106. The structure of the spacers 108 is transferred, for example, by an etching process to the hard mask material layer 104 to form a structured hard mask 110, as shown in Fig. Figure 1B illustrates this. In such an embodiment, the structured hard mask 110 is formed with a grid structure having unidirectional conductors. The grid structure of the structured hard mask 110 can be a grid structure with a narrow pitch. For example, the narrow pitch may not be directly achievable by selected lithography techniques. Although not shown, the original pitch can also be quartered by a second pass of a spacer mask structure. Accordingly, the grid-like structure of the structured hard mask 110 can be formed from Fig. 1B hard mask lines are spaced at a constant grid spacing and have a constant width relative to each other. The achieved dimensions can be much smaller than the critical dimension of the lithographic technique used.

[0023] Accordingly, for either front-end-of-line (FEOL) or back-end-of-line (BEOL) integration schemes, or for both, a cover film can be patterned using lithography and etching processes, which may include, for example, spacer-based double patterning (SBDP) or screen division splitting, or spacer-based quadruple patterning (SBQP) or screen division quartering. It is understood that other screen division approaches can also be implemented. In any embodiment, a grid-like layout can be produced by a selected lithography approach, such as 193 nm immersion lithography (193i). Screen division can be implemented to increase the density of lines in the grid-like layout by a factor of n.A grid-like layout created using 193i lithography plus a screen ruling of a factor of "n" can be referred to as 193i+P / n screen ruling. With such an embodiment, the 193 nm immersion scaling can be extended for many generations with a cost-effective screen ruling.

[0024] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more common with the ongoing downward scaling of device dimensions. Tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yield bulk silicon substrate infrastructure.

[0025] However, scaling up multi-gate transistors is not without consequences. As the dimensions of these fundamental building blocks of a microelectronic circuit arrangement are reduced, and as the sheer number of these fundamental building blocks manufactured in a given area increases, the limitations on the semiconductor processes used to fabricate these building blocks have become overwhelming.

[0026] According to one or more embodiments of the present disclosure, a grid-division quartering approach is implemented for structuring a semiconductor layer to form semiconductor fins. In one or more embodiments, a union fin grid-division quartering approach is implemented.

[0027] Fig. 2A is a diagram of a grid quartering approach 200 used for manufacturing semiconductor fins, according to an embodiment of the present disclosure. Fig. Figure 2B illustrates a cross-sectional view of semiconductor fins manufactured using a grid-dimensioned quartering approach, according to an embodiment of the present disclosure.

[0028] With reference to Fig. In step (a), a photoresist layer (PR) is patterned to form photoresist features 202. The photoresist features 202 can be patterned using standard lithographic processing techniques, such as immersion lithography. In step (b), the photoresist features 202 are used to pattern a material layer, such as an insulating or dielectric hard mask layer, to form first backbone (BB1) features 204. First spacer (SP1) features 206 are then formed adjacent to the sidewalls of the first backbone features 204. In step (c), the first backbone features 204 are removed to leave only the first spacer features 206. Before or during the removal of the first backbone features 204, the first spacer features 206 can be thinned to form thinned first spacer features 206', as shown in Fig. Figure 2A illustrates this. This thinning can be performed before (as shown) or after the removal of BB1 (feature 204), depending on the required spacing and sizing necessary for BB2 features (208, described below). In operation (d), the first spacer features 206 or the thinned first spacer features 206' are used to structure a material layer, such as an insulating or dielectric hard mask layer, to form second backbone (BB2) features 208. Second spacer (SP2) features 210 are then formed adjacent to the sidewalls of the second backbone features 208. In operation (e), the second backbone features 208 are removed, leaving only the second spacer features 210.The remaining second spacer features 210 can then be used to structure a semiconductor layer such that multiple semiconductor fins with a quarter-sized grid dimension relative to the initial structured photoresist features 202 are provided. As an example, with reference to . Fig. 2B Several semiconductor fins 250, such as silicon fins formed from a bulk silicon layer, are formed using the second spacer features 210 as a mask for structuring, e.g., dry or plasma etching. In the example from Fig. 2B, the multiple semiconductor fins 250 have essentially the same grid dimension and spacing throughout.

[0029] It is understood that the spacing between initially structured photoresist features can be modified to vary the structural result of the screen-division quartering process. In one example, Fig. 3A a diagram of a union fin grid quartering approach 300 used for manufacturing semiconductor fins, according to an embodiment of the present disclosure. Fig. Figure 3B illustrates a cross-sectional view of semiconductor fins manufactured using a union fin grid quartering approach, according to an embodiment of the present disclosure.

[0030] With reference to Fig. In step (a), a photoresist layer (PR) is structured to form photoresist features 302. The photoresist features 302 can be structured using standard lithographic processing techniques, such as 193 immersion lithography, but with a spacing that may ultimately conflict with the design rules necessary to produce a uniform screen-multiplied structure (e.g., a spacing referred to as a sub-design rule space). In step (b), the photoresist features 302 are used to structure a material layer, such as an insulating or dielectric hard mask layer, to form first backbone (BB1) features 304. First spacer (SP1) features 306 are then formed adjacent to the sidewalls of the first backbone features 304. However, unlike in step (b), the first spacer (SP1) features 306 are not used to structure the photoresist features 302. Fig. Figure 2A illustrates that some of the adjacent first spacer features 306 merged spacer features as a result of the closer photoresist features 302. In process (c), the first backbone features 304 are removed to leave only the first spacer features 306. Before or after the removal of the first backbone features 304, some of the first spacer features 306 can be thinned to form thinned first spacer features 306', as shown in Fig. Figure 3A illustrates this. In process (d), the first spacer features 306 and the thinned first spacer features 306' are used to structure a material layer, such as an insulating or dielectric hard mask layer, to form second backbone (BB2) features 308. Second spacer (SP2) features 310 are then formed adjacent to the side walls of the second backbone features 308. However, the second spacers are formed at positions where BB2 features 308 are combined features, such as the central BB2 features 308. Fig. 3A, not formed. In process (e), the second backbone features 308 are removed to leave only the second spacer features 310. The remaining second spacer features 310 can then be used to structure a semiconductor layer such that multiple semiconductor fins with a quarter-spaced dimension relative to the initial structured photoresist features 302 are provided.

[0031] As an example, with reference to Fig. 3B several semiconductor fins 350, such as silicon fins formed from a bulk silicon layer, are formed using the second spacer features 310 as a mask for structuring, e.g., dry or plasma etching. In the example from Fig. However, in 3B, the multiple semiconductor fins 350 exhibit varying grid dimensions and spacing. Such a union fin spacer structuring approach can be implemented to essentially eliminate the presence of a fin at certain locations within a multi-fin structuring. Accordingly, unioning the first spacer features 306 at certain locations enables the fabrication of six or four fins based on two first backbone features 304, typically generating eight fins, as in association with Fig. 2A and Fig. 2B is described. In one example, in-board fins have a narrower grid spacing than would normally be permitted by producing the fins with a uniform grid spacing and then cutting off the unneeded fins, although the latter approach can still be implemented according to the embodiments described here.

[0032] In one embodiment, referring to Fig. In an integrated circuit structure 3B, the first set of semiconductor fins 352 has a longest dimension along a first direction (y, into the side). Adjacent individual semiconductor fins 353 of the first set of semiconductor fins 352 are spaced apart from each other by a first amount (S11) in a second direction (x) orthogonal to the first direction y. The second set of semiconductor fins 354 has a longest dimension along the first direction y. Adjacent individual semiconductor fins 355 of the second set of semiconductor fins 354 are spaced apart from each other by a first amount (S1) in the second direction. The next semiconductor fins 356 and 357 of the first set of semiconductor fins 352 and the second set of semiconductor fins 354, respectively, are spaced apart from each other by a second amount (S2) in the second direction x. In one embodiment, the second amount S2 is greater than the first amount S1, but less than twice the first amount S1.In another embodiment, the second amount S2 is more than twice the first amount S1.

[0033] In one embodiment, the first multiple semiconductor fins 352 and the second multiple semiconductor fins 354 comprise silicon. In another embodiment, the first multiple semiconductor fins 352 and the second multiple semiconductor fins 354 are continuous with an underlying monocrystalline silicon substrate. In another embodiment, individual fins 352 and the second multiple semiconductor fins 354 have outwardly tapered sidewalls along the second direction x from a top to a bottom surface. In another embodiment, the first multiple semiconductor fins 352 and the second multiple semiconductor fins 354 each have exactly five semiconductor fins.

[0034] In another embodiment, with reference to Fig. 3A and Fig. 3B A method for fabricating an integrated circuit structure. Forming a first primary backbone structure 304 (left BB1) and a second primary backbone structure 304 (right BB1). Primary spacer structures 306 are formed adjacent to the side walls of the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1). Primary spacer structures 306 between the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) are joined. The first primary backbone structure (left BB1) and the second primary backbone structure (right BB1) are removed, and a first, second, third, and fourth secondary backbone structure 308 are provided. The second and third secondary backbone structures (e.g., the central pair of secondary backbone structures 308) are joined.Secondary spacer structures 310 are formed adjacent to the side walls of the first, second, third, and fourth secondary backbone structures 308. The first, second, third, and fourth secondary backbone structures 308 are then removed. A semiconductor material is then structured with the secondary spacer structures 310 to form semiconductor fins 350 in the semiconductor material.

[0035] In one embodiment, the first primary backbone structure 304 (left BB1) and the second primary backbone structure 304 (right BB1) are structured with a sub-design rule spacing between the first primary backbone structure and the second primary backbone structure. In one embodiment, the semiconductor material comprises silicon. In one embodiment, individual semiconductor fins 350 have outwardly tapered sidewalls along the second direction x from a top to a bottom surface. In one embodiment, the semiconductor fins 350 are continuously bonded to an underlying monocrystalline silicon substrate.In one embodiment, structuring the semiconductor material with the secondary spacer structures 310 involves forming a first set of semiconductor fins 352 with a longest dimension along a first direction y, wherein adjacent individual semiconductor fins of the first set of semiconductor fins 352 are spaced apart from each other by a first amount S1 in a second direction x orthogonal to the first direction y. A second set of semiconductor fins 354 is formed with a longest dimension along the first direction y, wherein adjacent individual semiconductor fins of the second set of semiconductor fins 354 are spaced apart from each other by a first amount S1 in the second direction x. The next semiconductor fins 356 and 357 of the first set of semiconductor fins 352 and the second set of semiconductor fins 354, respectively, are spaced apart from each other by a second amount S2 in the second direction x.In one embodiment, the second amount S2 is greater than the first amount S1. In such an embodiment, the second amount S2 is less than twice the first amount S1. In another such embodiment, the second amount S2 is more than twice, but less than three times, greater than the first amount S1. In one embodiment, the first multiple semiconductor fins 352 have exactly five semiconductor fins, and the second multiple semiconductor fins 254 have exactly five semiconductor fins, as shown in [reference]. Fig. 3B illustrates this.

[0036] Another aspect is that in a fin trimming process, where fin removal is performed as an alternative to a union fin approach, fins can be trimmed (removed) during hard mask structuring or by physically removing the fin. As an example of the latter approach... Fig. 4A-4C Cross-sectional views representing different operations in a method for manufacturing multiple semiconductor fins according to an embodiment of the present disclosure.

[0037] With reference to Fig. 4A A structured hard mask layer 402 is formed above a semiconductor layer 404, such as a bulk single-crystal silicon layer. With reference to Fig. 4B The fins 406 are then formed in the semiconductor layer 404, e.g. by a dry or plasma etching process. With reference to Fig. 4C Selected fins 406 are removed, for example, using a masking and etching process. In the example shown, one of the fins 406 is removed and may leave a residual fin stub 408, as shown in Fig. 4C is shown. In this "fin trimming last" approach, the hard mask 402 is structured as a whole to provide a lattice structure without removing or modifying individual features. The fin population is not modified until after the fins have been manufactured.

[0038] In another aspect, a multi-layer trench isolation region, which can be described as a shallow trench isolation (STI) structure, can be implemented between semiconductor fins. In one embodiment, a multi-layer STI structure is formed between silicon fins embedded in a bulk silicon substrate to define under-finning regions of the silicon fins.

[0039] It may be desirable to use bulk silicon for fin- or tri-gate-based transistors. However, there are concerns that regions (underfins) below the active silicon fin portion of the device (e.g., the gate-controlled region or HSi) may have reduced or no gate control. Therefore, if source or drain regions are located at or below the HSi point, leakage paths through the underfin region may exist. It may be necessary to control these leakage paths in the underfin region for proper device operation.

[0040] One approach to addressing the above problems involves the use of tub implantation procedures, where the underfining area is heavily doped (e.g., much more than 2E18 / cm²). 3), which blocks bottom fin leakage but also leads to significant fin doping. Adding halo implants further increases fin doping, so end-of-line fins are doped to a high level (e.g., more than approximately 1E18 / cm²). 3 ).

[0041] Another approach involves doping provided by underfin doping without necessarily supplying the same doping level to the HSi portions of the fins. Processes can involve selective doping of underfin regions of Tri-Gate or FinFET transistors fabricated on bulk silicon wafers, for example, by Tri-Gate-doped glass underfin diffusion out. For instance, selectively doping an underfin region of Tri-Gate or FinFET transistors can mitigate underfin leakage losses while keeping fin doping low. Incorporating solid-state doping sources (e.g., p-type and n-type doped oxides, nitrides, or carbides) into the transistor process flow, which, after being reset by the fin sidewalls, provides well doping into the underfin region while keeping the fin body relatively undoped.

[0042] Accordingly, process schemes may involve the use of a solid-source doping layer (e.g., boron-doped oxide) which is subsequently deposited onto fins following fin etching. Later, after trench filling and polishing, the doping layer is reset along with the trench filler material to define the fin height (HSi) for the device. This process removes the doping layer from the fin sidewalls above HSi. Therefore, the doping layer is present only along the fin sidewalls in the underfin region, ensuring precise control of doping placement. After drive-in annealing, high doping is confined to the underfin region, rapidly transitioning to low doping in the adjacent fin region above HSi (forming the transistor channel region).Generally, borosilicate glass (BSG) is implemented for NMOS fin doping, while a phosphosilicate glass (PSG) or arsenic glass (AsSG) layer is implemented for PMOS fin doping. In one example, such a p-type solid doping source layer is a BSG layer with a boron concentration approximately in the range of 0.1–10 wt%. In another example, such an n-type solid doping source layer is a PSG layer or an AsSG layer with a phosphorus or arsenic concentration, respectively, approximately in the range of 0.1–10 wt%. A silicon nitride cover layer may be included on the doping layer, and a silicon dioxide or silicon oxide filler material may then be included on the silicon nitride cover layer.

[0043] According to another embodiment of the present disclosure, underfin leakage loss is sufficiently low for relatively thinner fins (e.g., fins with a width of less than approximately 20 nanometers) in which an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to a fin, a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film, and a silicon dioxide or silicon oxide filler material is contained on the silicon nitride top layer. It is understood that doping, such as halo doping, of the underfin regions can also be implemented with such a structure.

[0044] Fig. Figure 5A illustrates a cross-sectional view of a pair of semiconductor fins separated by a three-layer trench insulation structure according to an embodiment of the present disclosure.

[0045] With reference to Fig. 5A includes an integrated circuit structure and a fin 502, such as a silicon fin. The fin 502 has a lower fin part (lower fin) 502A and an upper fin part 502B (H). Si ) on. A first insulating layer 504 is located directly on the side walls of the lower fin section 502A of the fin 502. A second insulating layer 506 is located directly on the first insulating layer 504, directly on the side walls of the lower fin section 502A of the fin 502. A dielectric filling material 508 is located directly laterally adjacent to the second insulating layer 506, directly on the first insulating layer 504, directly on the side walls of the lower fin section 502A of the fin 502.

[0046] In one embodiment, the first insulating layer 504 is an undoped insulating layer including silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In another embodiment, the first insulating layer 504 contains silicon and oxygen and does not contain any other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter. In another embodiment, the first insulating layer 504 has a thickness in the range of 0.5–2 nanometers.

[0047] In one embodiment, the second insulating layer 506 comprises silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In one embodiment, the second insulating layer 506 has a thickness in the range of 2–5 nanometers.

[0048] In one embodiment, the dielectric filling material 508 comprises silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. Finally, in one embodiment, a gate electrode is formed above a top surface of and laterally adjacent to the side walls of the upper fin part 502B of the fin 502.

[0049] It is understood that during processing, the upper fin portions of semiconductor fins can be eroded or consumed. Furthermore, trench insulation structures between fins can also be eroded, resulting in a non-planar topography, or they can be formed during manufacturing with a non-planar topography. As an example, the following illustrates... Fig. 5B a cross-sectional view of another pair of semiconductor fins separated by another three-layer trench insulation structure, according to another embodiment of the present disclosure.

[0050] With reference to Fig. 5B includes an integrated circuit structure and a first fin 552, such as a silicon fin. The first fin 552 has a lower fin part 552A and an upper fin part 552B, and a shoulder feature 554 in an area between the lower fin part 552A and the upper fin part 552B. A second fin 562, such as a second silicon fin, has a lower fin part 562A and an upper fin part 562B, and a shoulder feature 564 in an area between the lower fin part 562A and the upper fin part 562B. A first insulating layer 574 is located directly on the side walls of the lower fin part 552A of the first fin 552 and directly on the side walls of the lower fin part 562A of the second fin 562.The first insulation layer 574 has a first end part 574A that is essentially coplanar with the shoulder feature 554 of the first fin 552, and the first insulation layer 574 further has a second end part 574B that is essentially coplanar with the shoulder feature 564 of the second fin 562. A second insulation layer 576 is located directly on the first insulation layer 574, directly on the side walls of the lower fin part 552A of the first fin 552 and directly on the side walls of the lower fin part 562A of the second fin 562.

[0051] A dielectric filler material 578 is located directly laterally adjacent to the second insulating layer 576, directly on the first insulating layer 574, directly on the side walls of the lower fin part 552A of the first fin 552, and directly on the side walls of the lower fin part 562A of the second fin 562. In one embodiment, the dielectric filler material 578 has an upper surface 578A, wherein a portion of the upper surface 578A of the dielectric filler material 578 lies below at least one of the shoulder features 554 of the first fin 552 and below at least one of the shoulder features 564 of the second fin 562, as shown in Fig. 5B is illustrated.

[0052] In one embodiment, the first insulating layer 574 is an undoped insulating layer including silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In another embodiment, the first insulating layer 574 contains silicon and oxygen and does not contain any other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter. In another embodiment, the first insulating layer 574 has a thickness in the range of 0.5–2 nanometers.

[0053] In one embodiment, the second insulating layer 576 comprises silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. In one embodiment, the second insulating layer 576 has a thickness in the range of 2–5 nanometers.

[0054] In one embodiment, the dielectric filling material 578 comprises silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In another embodiment, a gate electrode is formed above and laterally adjacent to the side walls of the upper fin part 552B of the first fin 552, and above and laterally adjacent to the side walls of the upper fin part 562B of the second fin 562. The gate electrode is further located above the dielectric filling material 578 between the first fin 552 and the second fin 562.

[0055] Fig. Figures 6A-6D illustrate a cross-sectional view of various processes in the manufacture of a three-layer trench insulation structure according to an embodiment of the present disclosure.

[0056] With reference to Fig. 6A includes a method for fabricating an integrated circuit structure by forming a fin 602, such as a silicon fin. A first insulating layer 604 is formed directly on and conformed to the fin 602, as shown in Fig. Figure 6B illustrates this. In one embodiment, the first insulating layer 604 comprises silicon and oxygen and contains no other atomic species with an atomic concentration greater than 1E15 atoms per cubic centimeter.

[0057] With reference to Fig. In 6C, a second insulating layer 606 is formed directly on and conformed to the first insulating layer 604. In one embodiment, the second insulating layer 606 comprises silicon and nitrogen. A dielectric filler material 608 is formed directly on the second insulating layer 606, as shown in Fig. 6D is illustrated.

[0058] In one embodiment, the method further involves resetting the dielectric filler material 608, the first insulating layer 604 and the second insulating layer 606 to expose the fin 602 with an exposed upper fin part 602A (e.g., such as the upper fin parts 502B, 552B or 562B). Fig. 5A and Fig. 5B). The resulting structure can be associated with Fig. 5A or Fig. 5B. In one embodiment, resetting the dielectric material to fill 608, the first insulating layer 604, and the second insulating layer 606 involves using a wet etching process. In another embodiment, resetting the dielectric material to fill 608, the first insulating layer 604, and the second insulating layer 606 involves using a plasma etching or dry etching process.

[0059] In one embodiment, the first insulating layer 604 is formed using a chemical vapor deposition (CVD) process. In another embodiment, the second insulating layer 606 is formed using a CVD process. In another embodiment, the dielectric filler material 608 is formed using a spin-on process. In such an embodiment, the dielectric filler material 608 is a spin-on material and is subjected to a vapor treatment, e.g., either before or after a reset etching process, to provide a cured material including silicon and oxygen. Finally, in another embodiment, a gate electrode is formed above the top surface of and laterally adjacent to the side walls of an upper fin portion of the fin 602.

[0060] In another aspect, gate sidewall spacer material can be retained over certain trench isolation areas as protection against erosion of the trench isolation areas during subsequent processing operations. For example, illustrate Fig. 7A-7E inclined three-dimensional cross-sectional views of various processes in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure.

[0061] With reference to Fig. 7A includes a method for fabricating an integrated circuit structure forming a fin 702, such as a silicon fin. The fin 702 has a lower fin part 702A and an upper fin part 702B. An insulating structure 704 is formed directly adjacent to the side walls of the lower fin part 702A of the fin 702. A gate structure 706 is formed over the upper fin part 702B and over the insulating structure 704. In one embodiment, the gate structure is a placeholder or dummy gate structure including a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C. A dielectric material 708 is formed conformally with the upper fin part 702B of the fin 702, conformally with the gate structure 706 and conformally with the insulation structure 704.

[0062] With reference to Fig. In 7B, a hard mask material 710 is formed over the dielectric material 708. In one embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-on process.

[0063] With reference to Fig. In step 7C, the hard mask material 710 is reset to form a reset hard mask material 712 and to expose a portion of the dielectric material 708 conforming to the upper fin portion 702B of the fin 702 and conforming to the gate structure 706. The reset hard mask material 712 covers a portion of the dielectric material 708 conforming to the insulation structure 704. In one embodiment, the hard mask material 710 is reset using a wet etching process. In another embodiment, the hard mask material 710 is reset using an ashing, dry etching, or plasma etching process.

[0064] With reference to Fig. 7D the dielectric material 708 is anisotropically etched to form a structured dielectric material 714 along side walls of the gate structure 706 (as dielectric spacers 714A), along parts of the side walls of the upper fin part 702B of the fin 702 and over the insulation structure 704.

[0065] With reference to Fig. 7E will remove the reset hard mask material 712 from the structure. Fig. 7D removed. In one embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing involves replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In another embodiment, further processing involves forming embedded source or drain structures on opposite sides of the gate structure 706, as described in more detail below.

[0066] Again with reference to Fig. 7E includes an integrated circuit structure 700, in one embodiment comprising a first fin (702 left), such as a first silicon fin, wherein the first fin has a lower fin part 702A and an upper fin part 702B. The integrated circuit structure further comprises a second fin (702 right), such as a second silicon fin, wherein the second fin has a lower fin part 702A and an upper fin part 702B. An insulating structure 704 is located directly adjacent to the side walls of the lower fin part 702A of the first fin and directly adjacent to the side walls of the lower fin part 702A of the second fin. A gate electrode 706 is located above the upper fin part 702B of the first fin (702 left), above the upper fin part 702B of the second fin (702 right) and above a first part 704A of the insulation structure 704.A first dielectric spacer 714A is located along a side wall of the upper fin section 702B of the first fin (702 left), and a second dielectric spacer 702C is located along a side wall of the upper fin section 702B of the second fin (702 right). The second dielectric spacer 714C is continuous with the first dielectric spacer 714B over a second section 704B of the insulating structure 704 between the first fin (702 left) and the second fin (702 right).

[0067] In one embodiment, the first and second dielectric spacers 714B and 714C comprise silicon and nitrogen, such as a stoichiometric Si3N4 silicon nitride material, a silicon-rich silicon nitride material, or a silicon-poor silicon nitride material.

[0068] In one embodiment, the integrated circuit structure 700 further comprises embedded source or drain structures on opposite sides of the gate electrode 706, the embedded source or drain structures having a lower surface below an upper surface of the first and second dielectric spacers 714B and 714C along the side walls of the upper fin parts 702B of the first and second fin 702, and the source or drain structures having an upper surface above an upper surface of the first and second dielectric spacers 714B and 714C along the side walls of the upper fin parts 702B of the first and second fin 702, as in association with Fig. 9B is described. In one embodiment, the insulation structure 704 comprises a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric filler material directly laterally on the second insulating layer, as also described below in association with Fig. 9B is described.

[0069] Fig. Figures 8A-8F illustrate slightly projected cross-sectional views along the a-a' axis. Fig. 7E for various operations in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure.

[0070] With reference to Fig. 8A includes a method for fabricating an integrated circuit structure forming a fin 702, such as a silicon fin. The fin 702 has a lower fin part (in Fig. 8A not visible) and an upper fin part 702B. An insulation structure 704 is formed directly adjacent to the side walls of the lower fin part 702A of the fin 702. A pair of gate structures 706 is formed above the upper fin part 702B and above the insulation structure 704. It is understood that the in Fig. The perspective shown in Figures 8A-8F is slightly projected to show portions of the gate structures 706 and the insulation structure in front of (outside the side) the upper fin portion 702B, with the upper fin portion slightly inward. In one embodiment, the gate structures 706 are placeholder or dummy gate structures including a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

[0071] With reference to Fig. 8B, which is associated with Fig. In accordance with the process described in 7A, a dielectric material 708 is formed conforming to the upper fin part 702B of the fin 702, conforming to the gate structures 706 and conforming to the exposed parts of the insulation structure 704.

[0072] With reference to Fig. 8C, which is associated with Fig. In accordance with the process described in 7B, a hard mask material 710 is formed over the dielectric material 708. In one embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin-on process.

[0073] With reference to Fig. 8D, which is associated with Fig. In accordance with the process described in 7C, the hard mask material 710 is reset to form a reset hard mask material 712 and expose a portion of the dielectric material 708 conforming to the upper fin portion 702B of the fin 702 and conforming to the gate structures 706. The reset hard mask material 712 covers a portion of the dielectric material 708 conforming to the insulation structure 704. In one embodiment, the hard mask material 710 is reset using a wet etching process. In another embodiment, the hard mask material 710 is reset using an ashing, dry etching, or plasma etching process.

[0074] With reference to Fig. 8E, which is associated with Fig. In accordance with the process described in 7D, the dielectric material 708 is anisotropically etched to form a structured dielectric material 714 along side walls of the gate structure 706 (as parts 714A), along parts of the side walls of the upper fin part 702B of the fin 702 and over the insulation structure 704.

[0075] With reference to Fig. 8F, which is associated with Fig. As described in 7E, the reset hard mask material 712 is removed from the structure. Fig. 8E removed. In one embodiment, the gate structures 706 are dummy gate structures, and subsequent processing involves replacing the gate structures 706 with permanent gate dielectric and gate electrode stacks. In another embodiment, further processing involves forming embedded source or drain structures on opposite sides of the gate structure 706, as described in more detail below.

[0076] Again with reference to Fig. 8F includes an integrated circuit structure 700, in one embodiment a fin 702, such as a silicon fin, wherein the fin 702 has a lower fin part (in Fig. 8F not visible) and has an upper fin part 702B. An insulation structure 704 is located directly adjacent to the side walls of the lower fin part of the fin 702. A first gate electrode (706 left) is located above the upper fin part 702B and above a first part 704A of the insulation structure 704. A second gate electrode (706 right) is located above the upper fin part 702B and above a second part 704A' of the insulation structure 704.A first dielectric spacer (714A right or 706 left) is located along a side wall of the first gate electrode (706 left) and a second dielectric spacer (714A to the left of 706 right) is located along a side wall of the second gate electrode (706 right), wherein the second dielectric spacer is continuous with the first dielectric spacer over a third part 704A** of the insulation structure 704 between the first gate electrode (706 left) and the second gate electrode (706 right).

[0077] Fig. Figure 9A illustrates a slightly projected cross-sectional view along the a-a' axis. Fig. 7E for an integrated circuit structure including permanent gate stacks and epitaxial source or drain regions according to an embodiment of the present disclosure. Fig. Figure 9B illustrates a cross-sectional view along the b-b' axis. Fig. 7E for an integrated circuit structure including epitaxial source or drain regions and a multilayer trench insulation structure according to an embodiment of the present disclosure.

[0078] With reference to Fig. 9A and Fig. In one embodiment, the integrated circuit structure 9B includes embedded source or drain structures 910 on opposite sides of the gate electrodes 706. The embedded source or drain structures 910 have a lower surface 910A below an upper surface 990 of the first and second dielectric spacers 714B and 714C along the side walls of the upper fin parts 702B of the first and second fins 702. The embedded source or drain structures 910 have an upper surface 910B above an upper surface of the first and second dielectric spacers 714B and 714C along the side walls of the upper fin parts 702B of the first and second fins 702.

[0079] In one embodiment, the gate stacks 706 are permanent gate stacks 920. In such an embodiment, the permanent gate stacks 920 comprise a gate dielectric layer 922, a first gate layer 924, such as a work function gate layer, and a gate filler material 926, as described in Fig. Figure 9A illustrates this. In one embodiment, wherein the permanent gate structures 920 are located above the insulation structure 704, the permanent gate structures 920 are formed on remaining polycrystalline silicon parts 930, which are remnants of a replacement gate process involving polycrystalline sacrificial silicon gate electrodes.

[0080] In one embodiment, the insulating structure 704 comprises a first insulating layer 902, a second insulating layer 904 directly on top of the first insulating layer 902, and a dielectric filler material 906 directly laterally on the second insulating layer 904. In one embodiment, the first insulating layer 902 is an undoped insulating layer including silicon and oxygen. In one embodiment, the second insulating layer 904 includes silicon and nitrogen. In one embodiment, the dielectric filler material 906 includes silicon and oxygen.

[0081] In another aspect, epitaxial embedded source or drain regions are implemented as source or drain structures for semiconductor fins. An example illustrates this. Fig. 10 a cross-sectional view of an integrated circuit structure at a source or drain position according to an embodiment of the present disclosure.

[0082] With reference to Fig. 10 includes an integrated circuit structure 1000, a p-type device, such as a p-type metal-oxide-semiconductor (PMOS) device. The integrated circuit structure 1000 also includes an n-type device, such as an n-type metal-oxide-semiconductor (PMOS) device.

[0083] The PMOS device from Fig. The first component comprises several semiconductor fins 1002, such as silicon fins, formed from a bulk silicon substrate 1001. At the source or drain position, the upper portions of the fins 1002 have been removed, and an identical or different semiconductor material is grown to form source or drain structures 1004. It is understood that the source or drain structures 1004 will appear the same in a cross-sectional view along one side of a gate electrode; for example, they will look essentially the same on a source side as on a drain side. In one embodiment, the source or drain structures 1004, as shown, have a portion below and a portion above an upper surface of an insulating structure 1006. In another embodiment, the source or drain structures 1004 are highly faceted, as shown.In one embodiment, a conductive contact 1008 is formed over the source or drain structures 1004. However, in such an embodiment, the strong faceting and the relatively wide growth of the source or drain structures 1004 hinder good coverage by the conductive contact 1008, at least to some extent.

[0084] The NMOS device from Fig. The second component comprises several semiconductor fins 1052, such as silicon fins, formed from the bulk silicon substrate 1001. At the source or drain position, the upper portions of the fins 1052 have been removed, and an identical or different semiconductor material is grown to form source or drain structures 1054. It is understood that the source or drain structures 1054 will appear the same in a cross-sectional view along one side of a gate electrode; for example, they will look essentially the same on a source side as on a drain side. In one embodiment, the source or drain structures 1054, as shown, have a portion below and a portion above an upper surface of the insulating structure 1006. In another embodiment, the source or drain structures 1054, as shown, are weakly faceted relative to the source or drain structures 1004.In one embodiment, a conductive contact 1058 is formed over the source or drain structures 1054. In such an embodiment, the relatively weak faceting and the resulting relatively narrower growth of the source or drain structures 1054 (compared to the source or drain structures 1004) improve the coverage by the conductive contacts 1058.

[0085] The shape of the source or drain structures of a PMOS device can be varied to improve the contact surface with a contact above it. For example, this illustrates... Fig. 11 a cross-sectional view of another integrated circuit structure at a source or drain position according to an embodiment of the present disclosure.

[0086] With reference to Fig. Figure 11 includes an integrated circuit structure 1100 comprising a p-type semiconductor (e.g., PMOS) device. The PMOS device includes a first fin 1102, such as a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102. In one embodiment, although not shown, the first epitaxial source or drain structure 1104 is located at a first side of a first gate electrode (which may be formed above an upper fin portion, such as a channel portion of the fin 1102), and a second epitaxial source or drain structure is arranged in the first fin 1102 at a second side of such a first gate electrode opposite the first side. In one embodiment, the first 1104 and second epitaxial source or drain structures comprise silicon and germanium and have a profile 1105. In one embodiment, the profile is a matchstick profile, as in Fig. Figure 11 shows a first conductive electrode 1108 located above the first epitaxial source or drain structure 1104.

[0087] Again with reference to Fig. In one embodiment, the integrated circuit structure 1100 includes an n-type semiconductor (e.g., NMOS) device. The NMOS device includes a second fin 1152, such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152. In another embodiment, although not shown, the third epitaxial source or drain structure 1154 is located at a first side of a second gate electrode (which may be formed above an upper fin portion, such as a channel portion of the fin 1152), and a fourth epitaxial source or drain structure is arranged in the second fin 1152 at a second side of such a second gate electrode opposite the first side.In one embodiment, the third 1154 and fourth epitaxial source or drain structures contain silicon and have essentially the same profile as the profile 1105 of the first and second epitaxial source or drain structures 1004. A second conductive electrode 1158 is located above the third epitaxial source or drain structure 1154.

[0088] In one embodiment, the first epitaxial source or drain structure 1104 is weakly faceted. In another embodiment, the first epitaxial source or drain structure 1104 has a height of approximately 50 nanometers and a width in the range of 30–35 nanometers. In such an embodiment, the third epitaxial source or drain structure 1154 has a height of approximately 50 nanometers and a width in the range of 30–35 nanometers.

[0089] In one embodiment, the first epitaxial source or drain structure 1104 is graded from a germanium concentration of approximately 20% at a lower surface 1104A of the first epitaxial source or drain structure 1104 to a germanium concentration of approximately 45% at a top surface 1104B of the first epitaxial source or drain structure 1104. In another embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In such an embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus or arsenic atoms.

[0090] Fig. Figures 12A-12D illustrate cross-sectional views at a source or drain position and represent various processes in the fabrication of an integrated circuit structure according to an embodiment of the present disclosure.

[0091] With reference to Fig. 12A includes a method for fabricating an integrated circuit structure forming a fin, such as a silicon fin, formed from a silicon substrate 1201. The fin 1202 has a lower fin part 1202A and an upper fin part 1202B. In one embodiment, although not shown, a gate electrode is formed over a portion of the upper fin part 1202B of the fin 1202 at a position inward along the side. Such a gate electrode has a first side opposite a second side and defines source and drain positions on the first and second sides. For example, for the purpose of illustration, the cross-sectional positions for the views from Fig. 12A-12D along one of the source or drain positions at one of the sides of a gate electrode.

[0092] With reference to Fig. 12B is a source offset from a drain position of fin 1202 to form a recessed fin portion 1206. The recessed source or drain position of fin 1202 can be located at one side of a gate electrode and at the other side of the gate electrode. Referring to both Fig. In one embodiment, dielectric spacers 1204 (12A and 12B) are formed along side walls of a portion of the fin 1202, for example, on one side of a gate structure. In such an embodiment, resetting the fin 1202 involves resetting the fin 1202 below an upper surface 1204A of the dielectric spacers 1204.

[0093] With reference to Fig. In 12C, an epitaxial source or drain structure 1208 is formed on, for example, the recessed fin 1206 and can accordingly be formed on one side of a gate electrode. In such an embodiment, a second epitaxial source or drain structure is formed on a second part of the recessed fin 1206 on a second side of such a gate electrode. In one embodiment, the epitaxial source or drain structure 1208 comprises silicon and germanium and has a matchstick profile, as shown in Fig. Figure 12C is shown. In one embodiment, dielectric spacers 1204 are included and are located, as shown, along a lower part 1208A of side walls of the epitaxial source or drain structure 1208.

[0094] With reference to Fig. 12D is a conductive electrode 1210 formed on the epitaxial source or drain structure 1208. In one embodiment, the conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive filler material 1201B. In one embodiment, the conductive electrode 1210 follows the profile of the epitaxial source or drain structure 1208, as shown. In other embodiments, upper parts of the epitaxial source or drain structure 1208 are eroded during the fabrication of the conductive electrode 1210.

[0095] Another aspect described is fin trim isolation (FTI) and single-gate spacing for insulated fins. Non-planar transistors that utilize a fin of semiconductor material projecting from a substrate surface employ a gate electrode that encloses two, three, or even all sides of the fin (i.e., dual-gate, tri-gate, nanowire transistors). Source and drain regions are then typically formed within the fin, or as regrown portions of the fin, on one side of the gate electrode. To isolate a source or drain region of a first non-planar transistor from a source or drain region of an adjacent second non-planar transistor, a gap or space can be formed between two adjacent fins. Such an isolation gap generally requires some form of masked etching.Once isolated, a gate stack is structured across the individual fins, typically using some kind of masked etching (e.g., line etching or aperture etching depending on the specific implementation).

[0096] A potential problem with the fin isolation techniques described above is that the gates are not self-aligned with the fin ends, and alignment of the gate stack pattern with the semiconductor fin pattern relies on a superposition of these two patterns. Therefore, lithographic superposition tolerances are added to the dimensioning of the semiconductor fin and the isolation gap, requiring fins to be longer and isolation gaps to be larger than would otherwise be necessary for a given level of transistor functionality. Device architectures and fabrication techniques that reduce such oversizing thus offer highly beneficial improvements in transistor density.

[0097] Another potential problem with the fin isolation techniques described above is that mechanical stress in the semiconductor fin, which is desirable for improving charge carrier mobility, can be lost from the transistor's channel region if too many fin surfaces are left exposed during fabrication, allowing mechanical fin stress to dissipate. Device architectures and fabrication techniques that maintain higher levels of desirable mechanical fin stress therefore offer advantageous improvements in the performance of non-planar transistors.

[0098] According to one embodiment of the present disclosure, through-gate fin isolation architectures and techniques are described herein. In the illustrated exemplary embodiments, non-planar transistors in a microelectronic device, such as an integrated circuit (IC), are isolated from one another in a manner that is self-aligned with the gate electrodes of the transistors. Although embodiments of the present disclosure are applicable to virtually any IC that uses non-planar transistors, exemplary ICs include, among others, microprocessor cores including logic and memory (SRAM) sections, RFICs (e.g., wireless ICs including digital baseband and analog front-end modules), and power ICs.

[0099] In embodiments, two ends of adjacent semiconductor fins are electrically isolated from each other by an isolation region positioned relative to gate electrodes using only one structuring mask plane. In one embodiment, a single mask is used to form multiple sacrificial placeholder strips with a fixed grid dimension, wherein a first subset of the placeholder strips defines a position or dimension of isolation regions, while a second subset of the placeholder strips defines a position or dimension of a gate electrode. In certain embodiments, the first subset of placeholder strips is removed, and isolation cuts are made in the semiconductor fins at the openings resulting from the removal of the first subset, while the second subset of placeholder strips is ultimately replaced with non-sacrificial gate electrode stacks.Because a subset of placeholders used for gate electrode replacement is employed to form the isolation regions, the method and the resulting architecture are referred to here as "through-gate" isolation. One or more through-gate isolation implementations described here can, for example, enable higher transistor densities and higher levels of advantageous mechanical transistor channel voltage.

[0100] By defining the isolation after the placement or definition of the gate electrode, a higher transistor density can be achieved because fin isolation dimensioning and placement can be perfectly aligned with the grid spacing of the gate electrodes, such that both gate electrodes and isolation regions are integer multiples of a minimum feature grid spacing of a single masking plane. In further embodiments where the semiconductor fin has a grid mismatch with a substrate on which the fin is mounted, greater degrees of mechanical stress are maintained by defining the isolation after the placement or definition of the gate electrode.For such embodiments, other features of the transistor (such as the gate electrode and added source or drain materials) that are formed before fin ends are defined help to mechanically maintain fin loading after an insulation cut has been made into the fin.

[0101] To provide further connectivity, transistor scaling can benefit from a denser packing of cells within the chip. Currently, most cells are separated from their neighbors by two or more dummy gates, which have buried fins. The cells are isolated by etching the fins beneath these two or more dummy gates, which connect one cell to another. Scaling can be significantly beneficial if the number of dummy gates separating adjacent cells can be reduced from two or more to just one. As explained above, a solution requires two or more dummy gates. The fins beneath the two or more dummy gates are etched during fin structuring. A potential problem with such an approach is that dummy gates consume space on the chip that could be used for cells.In one embodiment, the approaches described here allow the use of only a single dummy gate to separate adjacent cells.

[0102] In one embodiment, a fin-trimming isolation approach is implemented as a self-aligning structuring scheme. Here, the fins are etched out below a single gate. Accordingly, adjacent cells can be separated by a single dummy gate. Advantages of such an approach can include saving space on the chip and enabling more computing power for a given area. The approach can also allow fin trimming to be performed at a sub-fin grid spacing.

[0103] Fig. 13A and Fig. Figure 13B illustrates top views representing various processes in a method for structuring fins with multiple gate spacing to form a local isolation structure, according to an embodiment of the present disclosure.

[0104] With reference to Fig. Figure 13A shows several fins 1302 with a length along a first direction 1304. A grid 1306 with spacings 1307 between them, defining positions for the final formation of several gate lines, is shown along a second direction 1308 orthogonal to the first direction 1304.

[0105] With reference to Fig. In step 13B, a portion of the multiple fins 1302 is cut (e.g., removed by an etching process), leaving fins 1310 with a cut 1312 within them. An isolation structure ultimately formed in cut 1312 therefore has a dimension of more than a single gate line, e.g., a dimension of three gate lines 1306. Accordingly, gate structures ultimately formed along the positions of the gate lines 1306 are formed, at least partially, over an isolation structure formed in cut 1312. Therefore, cut 1312 is a relatively wide fin cut.

[0106] Fig. Figures 14A-14D illustrate top views representing various processes in a method for structuring fins with single-gate spacing to form a local isolation structure, according to another embodiment of the present disclosure.

[0107] With reference to Fig. Document 14A includes a method for fabricating an integrated circuit structure forming multiple fins 1402, wherein individual fins 1402 have a longest dimension along a first direction 1404. Multiple gate structures 1406 are located above the multiple fins 1402, wherein individual gate structures 1406 have a longest dimension along a second direction 1408 orthogonal to the first direction 1404. In one embodiment, the gate structures 1406 are sacrificial or dummy gate lines, e.g., made of polycrystalline silicon. In another embodiment, the multiple fins 1402 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0108] With reference to Fig. 14B a dielectric material structure 1410 is formed between adjacent of the several gate structures 1406.

[0109] With reference to Fig. In 14C, a part 1412 is removed from one of the multiple gate structures 1406 to expose a part 1414 from each of the multiple fins 1402. In one embodiment, removing a part 1412 from one of the multiple gate structures 1406 involves using a lithographic window 1416 that is wider than a width 1418 of the part 1412 of one of the multiple gate structures 1406.

[0110] With reference to Fig. In 14D, the exposed portion 1414 is removed from each of the multiple fins 1402 to form a cut area 1420. In one embodiment, the exposed portion 1414 is removed from each of the multiple fins 1402 using a dry or plasma etching process. In another embodiment, removing the exposed portion 1414 from each of the multiple fins 1402 involves etching to a depth less than the height of the multiple fins 1402. In such an embodiment, the depth is greater than the depth of source or drain regions in the multiple fins 1402. In yet another embodiment, the depth is greater than the depth of an active portion of the multiple fins 1402 to provide an isolation boundary. In one embodiment, the exposed part 1414 is removed from each of the multiple fins 1402 without etching or substantially without etching source or drain regions (such as epitaxial source or drain regions) of the multiple fins 1402.In such an embodiment, the exposed part 1414 is removed from each of the multiple fins 1402 without lateral etching or substantially without lateral etching of source or drain regions (such as epitaxial source or drain regions) of the multiple fins 1402.

[0111] In one embodiment, the cut area 1420 is ultimately filled with an insulating layer, e.g., at positions of the removed portion 1414 of each of the multiple fins 1402. Exemplary insulating layers or a "polycut" or "plug" structure are described below. In other embodiments, however, the cut area 1420 is only partially filled with an insulating layer, in which a conductive structure is then formed. The conductive structure can be used as a local interconnect. In one embodiment, dopants can be implanted or supplied through the cut area 1420 via a solid source dopant layer into the local cut portion of the fin or fins before the cut area 1420 is filled with an insulating layer or with an insulating layer that contains a local interconnect structure.

[0112] Fig. Figure 15 illustrates a cross-sectional view of an integrated circuit structure with a fin having a multi-gate spacing for local isolation according to an embodiment of the present disclosure.

[0113] With reference to Fig. Figure 15 shows a silicon fin 1502 with a first part 1504 laterally adjacent to a second fin part 1506. The first fin part 1504 is separated from the second fin part 1506 by a relatively wide cut 1508, as in association with Fig. 13A and Fig. As described in Figure 13B, the relatively wide section 1508 has a width X. A dielectric filler material 1510 is formed in the relatively wide section 1508 and electrically insulates the first fin part 1504 from the second fin part 1506. Several gate lines 1512 are located above the silicon fin 1502, each of which may include a gate dielectric and gate electrode stack 1514, a dielectric cap layer 1516, and sidewall spacers 1518. Two gate lines (the left two gate lines 1512) occupy the relatively wide section 1508, and therefore the first fin part 1504 is effectively separated from the second fin part 1506 by two dummy or inactive gates.

[0114] In contrast, fin sections can be separated by a single gate gap. An example illustrates this. Fig. 16A a cross-sectional view of an integrated circuit structure with a fin having single-gate spacing for local isolation according to another embodiment of the present disclosure.

[0115] With reference to Fig. 16A has a silicon fin 1602 with a first fin part 1604 laterally adjacent to a second fin part 1606. The first fin part 1604 is separated from the second fin part 1606 by a relatively narrow cut 1608, as in association with Fig. 14A-14D is described, where the relatively narrow section 1608 has a width Y, where Y is less than X. Fig. 15. A dielectric filler material 1610 is formed in the relatively narrow cut 1608 and electrically insulates the first fin part 1604 from the second fin part 1606. Several gate lines 1612 are located above the silicon fin 1602, each of which may include a gate dielectric and gate electrode stack 1614, a dielectric cap layer 1616, and sidewall spacers 1618. The dielectric filler material 1610 occupies the position where a single gate line was previously located, and therefore the first fin part 1604 is separated from the second fin part 1606 by a single "stuffed" gate line. In one embodiment, residual spacer material 1620 remains on the sidewalls at the position of the removed gate line part, as described.It is understood that other areas of fin 1602 may be isolated from each other by two or even more inactive gate lines (area 1622 with three inactive gate lines) produced by an earlier wider fin cutting process, as described below.

[0116] Again with reference to Fig. 16A an integrated circuit structure 1600 a fin 1602, such as a silicon fin. The fin 1602 has a longest dimension along a first direction 1650. An isolation structure 1610 separates a first upper part 1604 of the fin 1602 from a second upper part 1606 of the fin 1602 along the first direction 1650. The isolation structure 1610 has a center 1611 along the first direction 1650.

[0117] A first gate structure 1612A is located above the first upper part 1604 of the fin 1602. The first gate structure 1612A has a longest dimension along a second direction 1652 (e.g., laterally) orthogonal to the first direction 1650. A center 1613A of the first gate structure 1612A is spaced from the center 1611 of the isolation structure 1610 by one grid unit along the first direction 1650. A second gate structure 1612B is located above the first upper part 1604 of the fin, with the second gate structure 1612B having a longest dimension along the second direction 1652. A center 1613B of the second gate structure 1612B is spaced from the center 1613A of the first gate structure 1612A by the grid dimension along the first direction 1650. A third gate structure 1612C is located above the second upper part 1606 of the fin 1602, with the third gate structure 1612C having a longest dimension along the second direction 1652.A center 1613C of the third gate structure 1612C is spaced from the center 1611 of the isolation structure 1610 by the grid dimension along the first direction 1650. In one embodiment, the isolation structure 1610 has a top surface substantially coplanar with a top surface of the first gate structure 1612A, with a top surface of the second gate structure 1612B, and with a top surface of the third gate structure 1612C, as shown.

[0118] In one embodiment, the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C each include a gate electrode 1660 on and between side walls of a high-k-gate dielectric layer 1662, as illustrated, for example, in the third gate structure 1612C. In such an embodiment, the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C each further include an insulating cap 1616 on the gate electrode 1660 and on and between the side walls of the high-k-gate dielectric layer 1662.

[0119] In one embodiment, the integrated circuit structure 1600 further comprises a first epitaxial semiconductor region 1664A on the first upper part 1604 of the fin 1602 between the first gate structure 1612A and the isolation structure 1610. A second epitaxial semiconductor region 1664B is located on the upper part 1604 of the fin 1602 between the first gate structure 1612A and the second gate structure 1612B. A third epitaxial semiconductor region 1664C is located on the upper part 1606 of the fin 1602 between the third gate structure 1612C and the isolation structure 1610. In one embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions comprise silicon and germanium. In another embodiment, the first 1664A, second 1664B and third 1664C include epitaxial semiconductor silicon.

[0120] In one embodiment, the insulating structure 1610 induces a mechanical stress on the first upper part 1604 of the fin 1602 and on the second upper part 1606 of the fin 1602. In one embodiment, the mechanical stress is a compressive stress. In another embodiment, the mechanical stress is a tensile stress. In other embodiments, the insulating structure 1610 is a partially filling insulating layer in which a conductive structure is then formed. The conductive structure can be used as a local interconnect. In one embodiment, dopants are implanted or supplied through a solid source dopant layer into a local cut portion of the fin or fins before the formation of the insulating structure 1610 with an insulating layer or with an insulating layer that accommodates a local interconnect structure.

[0121] Another aspect is that isolation structures, such as the isolation structure 1610 described above, can be formed at local or broader positions of a fin cut, instead of an active gate electrode. Furthermore, the depth of such a local or broader fin cut can be varied relative to each other within the fin. A first example illustrates this. Fig. Figure 16B shows a cross-sectional view showing positions where a fin insulation structure can be formed instead of a gate electrode, according to an embodiment of the present disclosure.

[0122] With reference to Fig. In 16B, a fin 1680, such as a silicon fin, is formed above a substrate 1682 and may be continuous with it. The fin 1680 has fin ends or broad fin cuts 1684, which may be formed, for example, during fin structuring, such as in a fin trimming approach described above as the final step. The fin 1680 also has a local cut 1686, where part of the fin 1680 is removed, for example, using a fin trimming isolation approach, replacing dummy gates with dielectric plugs as described above. Active gate electrodes 1688 are formed above the fin and are shown, for illustrative purposes, slightly in front of the fin 1680, with the fin 1680 in the background, where the dashed lines represent areas covered by the front view.Dielectric plugs 1690 can be formed at the fin ends or wide fin cuts 1684 instead of using active gates at such positions. Furthermore, or alternatively, a dielectric plug 1692 can be formed at the local cut 1686 instead of using an active gate at such a position. It is understood that epitaxial source and drain regions 1694 are also shown for fin positions 1680 between the active gate electrodes 1688 and the plugs 1690 or 1692. In one embodiment, the surface roughness of the fin ends at the local cut 1686 is rougher than that of the fin ends at a wider cut position, as shown in [reference missing]. Fig. 16B illustrates this.

[0123] Fig. Figures 17A-17C illustrate various depth profiles for a fin cut produced using a fin trimming isolation approach, according to an embodiment of the present disclosure.

[0124] With reference to Fig. In 17A, a semiconductor fin 1700, such as a silicon fin, is formed above an underlying substrate 1702 and can be continuous with it. The fin 1700 has a lower fin part 1700A and an upper fin part 1700B, as defined by the height of an insulating structure 1704 relative to the fin 1700. A local fin insulating cut 1706A separates the fin 1700 into a first fin part 1710 from a second fin part 1712. In the example from Fig. 17A, as shown along the a-a' axis, is the depth of the local fin isolation cut 1706A the total length of the fin 1700 to the substrate 1702.

[0125] With reference to Fig. In a second example, as shown along the a-a' axis, the depth of a local fin isolation cut 1706B is deeper than the entire length of the fin 1700 to the substrate 1702. That is, the cut 1706B extends into the underlying substrate 1702.

[0126] With reference to Fig. In a third example, as shown along the a-a' axis, the depth of a local fin insulation cut 1706C is less than the total length of the fin 1700, but deeper than an upper surface of the insulation structure 1704. Again, with reference to Fig. In a fourth example, as shown along the a-a' axis, 17C, the depth of a local fin insulation cut 1706D is less than the total length of the fin 1700 and is approximately coplanar with an upper surface of the insulation structure 1704 in a plane.

[0127] Fig. Figure 18 illustrates a top view and a corresponding cross-sectional view along the a-a' axis, showing possible options for the depth of local versus wider positions of fin cuts within a fin, according to an embodiment of the present disclosure.

[0128] With reference to Fig. 18 feature first and second semiconductor fins 1800 and 1802, such as silicon fins, upper fin portions 1800B and 1802B, extending above an insulating structure 1804. Both fins 1800 and 1802 have fin ends or broad fin cuts 1806, which may be formed, for example, during fin structuring, such as in a fin trimming approach described above as the final step. Both fins 1800 and 1802 also feature a local cut 1808, where a portion of fin 1800 or 1802 is removed, for example, using a fin trimming isolation approach, with dummy gates being replaced with dielectric plugs as described above. In one embodiment, the surface roughness of the ends of the fins 1800 and 1802 at local cut 1808 is rougher than the ends of the fins at position 1806 as shown in Fig. 18 is illustrated.

[0129] Referring to the cross-sectional view fromFig. 18. Lower fin portions 1800A and 1802A can be seen below the height of the insulation structure 1804. Also visible in the cross-sectional view is a remaining portion 1810 of a fin, which was removed last in a fin-trimming process before the formation of the insulation structure 1804, as described above. The remaining portion 1810, although shown to protrude above a substrate, could also be at the level of or within the substrate, as illustrated by the additional exemplary wide-section depths 1820. It is understood that the wide sections 1806 for fins 1800 and 1802 may be at the levels described for a deep section 1820, for which examples are shown. The local section 1808 may have exemplary depths that correspond to the levels described for Fig. The depths described in sections 17A-17C correspond to those shown.

[0130] With joint reference to Fig. Figures 16A, 16B, 17A-17C, and 18 comprise an integrated circuit structure according to an embodiment of the present disclosure, comprising a fin including silicon, wherein the fin has a top surface and side walls, the top surface having a longest dimension along a first direction. A first insulation structure separates a first end of a first part of the fin from a first end of a second part of the fin along the first direction. The first insulation structure has a width along the first direction. The first end of the first part of the fin has a surface roughness. A gate structure comprises a gate electrode above the top surface of and laterally adjacent to the side walls of a region of the first part of the fin.The gate structure has a width along the first direction, and a center of the gate structure is spaced from a center of the first isolation structure by a grid unit along the first direction. A second isolation structure is located over the second end of a first fin segment, with the second end opposite the first end. The second isolation structure has a width along the first direction, and the second end of the first fin segment has a surface roughness lower than the surface roughness of the first end of the first fin segment. A center of the second isolation structure is spaced from the center of the gate structure by a grid unit along the first direction.

[0131] In one embodiment, the first end of the first part of the fin has a grooved topography, as shown in Fig. Figure 16B illustrates this. In one embodiment, a first epitaxial semiconductor region is located on the first part of the fin between the first gate structure and the first isolation structure. A second epitaxial semiconductor region is located on the first part of the fin between the gate structure and the second isolation structure. In another embodiment, the first and second epitaxial semiconductor regions have a width along a second direction orthogonal to the first direction, wherein the width along the second direction is wider than the width of the first part of the fin along the second direction below the gate structure, e.g., as in conjunction with Fig. 11 and Fig. 12D described epitaxial features that have a width wider than the fin parts on which they are located in the Fig. 11 and Fig. The perspective shown in 12D has grown up. In one embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the first part of the fin and along the side walls of the gate electrode.

[0132] With joint reference to Fig. Figures 16A, 16B, 17A-17C, and 18 comprise an integrated circuit structure according to another embodiment of the present disclosure, comprising a fin including silicon, wherein the fin has a top surface and side walls, the top surface having a longest dimension along a direction. A first insulation structure separates a first end of a first part of the fin from a first end of a second part of the fin along the direction. The first end of the first part of the fin has a depth. A gate structure comprises a gate electrode above the top surface and laterally adjacent to the side walls of a region of the first part of the fin. A second insulation structure is located above a second end of a first part of the fin, the second end being opposite the first end. The second end of the first part of the fin has a depth different from the depth of the first end of the first part of the fin.

[0133] In one embodiment, the depth of the second end of the first part of the fin is less than the depth of the first end of the first part of the fin. In another embodiment, the depth of the second end of the first part of the fin is greater than the depth of the first end of the first part of the fin. In one embodiment, the first isolation structure has a width along the direction, and the gate structure has a width along the direction. The second isolation structure has a width along the direction. In one embodiment, the center of the gate structure is spaced from the center of the first isolation structure by a grid unit along the direction, and the center of the second isolation structure is spaced from the center of the gate structure by the grid unit along the direction.

[0134] With joint reference to Fig. Figures 16A, 16B, 17A-17C, and 18 comprise an integrated circuit structure according to another embodiment of the present disclosure, comprising a first fin including silicon, wherein the first fin has a top surface and side walls, the top surface having a longest dimension along a direction, and a discontinuity separating a first end of a first part of the first fin from a first end of a second part of the fin along the direction. The first part of the first fin has a second end opposite the first end, and the first end of the first part of the fin has a depth. The integrated circuit structures also comprise a second fin including silicon, wherein the second fin has a top surface and side walls, the top surface having a longest dimension along the direction.The integrated circuit structure also includes a residual or remaining fin portion between the first fin and the second fin. This remaining fin portion has a top surface and side walls, with the top surface having a longest dimension along the direction, and the top surface is not coplanar with the depth of the first end of the first fin portion.

[0135] In one embodiment, the depth of the first end of the first part of the fin is below the top surface of the remaining fin section. In another embodiment, the second end of the first part of the fin has a depth coplanar with the depth of the first end of the first part of the fin. In yet another embodiment, the second end of the first part of the fin has a depth below the depth of the first end of the first part of the fin. In yet another embodiment, the second end of the first part of the fin has a depth above the depth of the first end of the first part of the fin. In yet another embodiment, the depth of the first end of the first part of the fin is above the top surface of the remaining fin section. In yet another embodiment, the second end of the first part of the fin has a depth coplanar with the depth of the first end of the first part of the fin.In one embodiment, the second end of the first part of the fin has a depth below the depth of the first end of the first part of the fin. In another embodiment, the second end of the first part of the fin has a depth above the depth of the first end of the first part of the fin. In another embodiment, the second end of the first part of the fin has a depth coplanar with the upper surface of the remaining fin part. In another embodiment, the second end of the first part of the fin has a depth below the upper surface of the remaining fin part. In yet another embodiment, the second end of the first part of the fin has a depth above the upper surface of the remaining fin part.

[0136] In another aspect, dielectric plugs formed at local or wide fin cuts can be custom-designed to provide a specific mechanical stress to the fin or fin segment. In such implementations, the dielectric plugs can be referred to as fin end stressors.

[0137] One or more embodiments relate to the fabrication of fin-based semiconductor devices. Performance improvements for such devices can be achieved via mechanical channel stress induced by a polyplug filling process. Embodiments may involve exploiting material properties in a polyplug filling process to induce mechanical stress in a metal-oxide-semiconductor field-effect transistor (MOSFET) channel. Consequently, induced mechanical stress can improve the transistor's mobility and drive current. Furthermore, a plug filling method described herein can enable the elimination of any seam or gap formation during deposition.

[0138] To provide a coherent effect, manipulating the unique material properties of a plug filling that abuts fins can induce mechanical stress within the channel. According to one or more embodiments, by tuning the composition, deposition, and post-treatment conditions of the plug filling material, mechanical stress in the channel is modulated to benefit both NMOS and PMOS transistors. Furthermore, such plugs can be positioned deeper within the fin substrate compared to other common stressor techniques, such as epitaxial sources or drains. The nature of the plug filling to achieve such an effect also eliminates seams or gaps during deposition and attenuates defect modes during processing.

[0139] To provide further reinforcement, there is no intended technical design for a mechanical stress on gate (poly) plugs. The improvement in mechanical stress compared to conventional stressors, such as epitaxial sources or drains, dummy poly gate removal, mechanical stress linings, etc., unfortunately tends to diminish with a reduction in device grid dimensions. Addressing one or more of the above problems according to one or more embodiments of the present invention incorporates an additional source of mechanical stress into the transistor structure. Another potential advantage of such a process may be the elimination of seams or gaps within the plug, which can be common with other chemical vapor deposition processes.

[0140] Fig. 19A and Fig. Figure 19B illustrates cross-sectional views of various processes in a method for selecting fin end stressor positions at the ends of a fin that has a wide cut, e.g. as part of a fin trimming process as the last step, as described above, according to an embodiment of the present disclosure.

[0141] With reference to Fig. In 19A, a fin 1900, such as a silicon fin, is formed above a substrate 1902 and may be continuous with it. The fin 1900 exhibits fin ends or broad fin cuts 1904, which may be formed, for example, at the time of fin structuring, as in a fin trimming approach described above. An active gate electrode site 1906 and dummy gate electrode sites 1908 are formed above the fin 1900 and are shown for illustrative purposes slightly in front of the fin 1900, with the fin 1900 in the background, the dashed lines representing areas obscured by the front view. It is understood that epitaxial source and drain regions 1910 are also shown for fin 1900 positions between gate positions 1906 and 1908. Furthermore, an interlayer dielectric material 1912 is included at fin positions 1900 between gate positions 1906 and 1908.

[0142] With reference to Fig. In 19B, the gate placeholder structures or dummy gate sites 1908 are removed, exposing the fin ends or wide fin cuts 1904. This removal creates openings 1920, ultimately forming dielectric plugs, e.g., dielectric fin end stressor plugs.

[0143] Fig. 20A and Fig. Figure 20B illustrates cross-sectional views of various processes in a method for selecting fin end stressor positions at the ends of a fin that has a local cut, e.g. as part of a fin trimming isolation process as described above, according to an embodiment of the present disclosure.

[0144] With reference to Fig. In step 20A, a fin 2000, such as a silicon fin, is formed above a substrate 2002 and may be continuous with it. The fin 2000 has a local cut 2004, in which part of the fin 2000 is removed, for example, using a fin trimming isolation approach, removing a dummy gate, and etching the fin at a local position as described above. Active gate electrode sites 2006 and a dummy gate electrode site 2008 are formed above the fin 2000 and are shown for illustrative purposes slightly in front of the fin 2000, with the fin 2000 in the background, the dashed lines representing areas covered by the front view. It is understood that epitaxial source and drain areas are also shown for positions of the fin 2000 between the gate positions 2006 and 2008.Furthermore, an interlayer dielectric material 2012 is included at fin positions 2000 between gate positions 2006 and 2008.

[0145] With reference to Fig. In step 20B, the gate placeholder structure or dummy gate electrode location 2008 is removed, exposing the fin ends with local cut 2004. The removal creates an opening 2020, ultimately forming a dielectric plug, e.g., a dielectric fin end stressor plug.

[0146] Fig. Figures 21A-21M illustrate cross-sectional views of various processes in a method for manufacturing an integrated circuit structure with differentiated fin end dielectric plugs according to an embodiment of the present disclosure.

[0147] With reference to Fig. 21A includes an initial structure 2100, an NMOS region, and a PMOS region. The NMOS region of the initial structure 2100 includes a first fin 2102, such as a first silicon fin, which is formed above a substrate 2104 and may be continuous with it. The first fin 2102 has fin ends 2106, which may be formed from local or broad cuts. A first active gate electrode site 2108 and first dummy gate electrode sites 2110 are formed above the first fin 2102 and are shown for illustrative purposes slightly in front of the first fin 2102, with the first fin 2102 in the background, and the dashed lines representing areas covered by the front view. Epitaxial n-type source or drain regions 2112, such as epitaxial silicon source of drain structures, are also shown at positions of the first fin 2102 between the gate positions 2108 and 2110.Furthermore, an interlayer dielectric material 2114 is included at the positions of the first fin 2102 between the gate positions 2108 and 2110.

[0148] The PMOS region of the initial structure 2100 includes a second fin 2122, such as a second silicon fin, which is formed above the substrate 2104 and may be continuous with it. The second fin 2122 has fin ends 2126, which may be formed from local or broad cuts. A second active gate electrode site 2128 and second dummy gate electrode sites 2130 are formed above the second fin 2122 and are shown for illustrative purposes slightly in front of the second fin 2122, with the second fin 2122 in the background, where the dashed lines represent areas covered by the front view. Epitaxial p-type source or drain regions 2132, such as epitaxial silicon germanium source of drain structures, are also shown at positions of the second fin 2122 between the gate positions 2128 and 2130.Furthermore, an interlayer dielectric material 2134 is included at the positions of the second fin 2122 between the gate positions 2128 and 2130.

[0149] With reference to Fig. In step 21B, the first and second dummy gate electrodes are removed at positions 2110 and 2130, respectively. This removal exposes the fin ends 2106 of the first fin 2102 and the fin ends 2126 of the second fin 2122. The removal also creates openings 2116 and 2136, ultimately forming dielectric plugs, such as dielectric fin end stressor plugs.

[0150] With reference to Fig. 21C will have a material lining 2140 conforming to the structure made of Fig. 21B. In one embodiment, the material lining includes silicon and nitrogen, such as a silicon nitride material lining.

[0151] With reference to Fig. 21D a protective crown layer 2142, such as a metal nitride layer, is applied to the structure made of Fig. 21C formed.

[0152] With reference to Fig. 21E a hard mask material 2144, such as a carbon-based hard mask material, is applied over the structure made of Fig. 21D is formed. A lithographic mask or mask stack 2146 is formed over the hard mask material 2144.

[0153] With reference to Fig. 21F parts of the hard mask material 2144 and parts of the protective crown layer 2142 in the PMOS area are removed from the structure. Fig. 21E removed. The lithographic mask or mask stack 2146 is also removed.

[0154] With reference to Fig. 21G will have a second material lining 2148 conforming to the structure made of Fig. 21F formed. In one embodiment, the second material lining comprises silicon and nitrogen, such as a second silicon nitride material lining. In another embodiment, the second material lining 2148 has a different mechanical stress state to adapt to mechanical stress in exposed plugs.

[0155] With reference to Fig. 21H will deposit a second hard mask material 2150, such as a second carbon-based hard mask material, over the structure made of Fig. 21G is formed and is then reset within the openings 2136 of the PMOS region of the structure.

[0156] With reference to Fig. 21I will form the second lining 2148 of the structure. Fig. 2H etched to remove the second material lining 2148 from the NMOS region and to reset the second material lining 2148 in the PMOS region of the structure.

[0157] With reference to Fig. 2J the hard mask material 2144, the protective crown layer 2142 and the second hard mask material 2150 are removed from the structure. Fig. 2I removed. The removal leaves two different filling structures for 2116 compared to the openings 2136.

[0158] With reference to Fig. 2K will be an insulating filler material 2152 in the openings 2116 and 2136 of the structure made of Fig. 2J formed and planarized. In one embodiment, the insulating filler material 2152 is a flowable oxygen material, such as a flowable silicon oxide or silicon dioxide material.

[0159] With reference to Fig. 2L will be the insulating filler material 2152 within the openings 2116 and 2136 of the structure made of Fig. 2K is reset to form a reset insulating filler material 2154. In one embodiment, a vapor oxidation process is carried out as part of or following the reset process to cure the reset insulating filler material 2154. In such an embodiment, the reset insulating filler material 2154 shrinks, thereby inducing tensile stress in the fins 2102 and 2122. However, there is relatively less tensile stress-inducing material in the PMOS region than in the NMOS region.

[0160] With reference to Fig. 21M there is a third material lining 2156 above the structure made of Fig. 21L. In one embodiment, the third material lining 2156 comprises silicon and nitrogen, such as a third silicon nitride material lining. In one embodiment, the third material lining 2156 prevents the recessed insulating filler material 2154 from being etched out during a subsequent source or drain contact etching.

[0161] Fig. Figures 22A-22D illustrate cross-sectional views of exemplary structures of a PMOS fin end stressor dielectric plug according to an embodiment of the present disclosure.

[0162] With reference to Fig. 22A includes an opening 2136 on the PMOS region of the structure 2100 and a material lining 2140 along the sidewalls of the opening 2136. A second material lining 2148 conforms to a lower part of the material lining 2140 but is recessed relative to an upper part of the material lining 2140. A recessed insulating filler material 2154 is located within the second material lining 2148 and has an upper surface coplanar with an upper surface of the second material lining 2148. A third material lining 2156 lies within the upper part of the material lining 2140 and is located on the upper surface of the insulating filler material 2154 and on the upper surface of the second material lining 2148. The third material lining 2156 has a seam 2157, e.g. B. as an artifact of a deposition process used to form the third material lining 2156

[0163] With reference to Fig. 22B includes an opening 2136 on the PMOS region of the structure 2100 and a material lining 2140 along the sidewalls of the opening 2136. A second material lining 2148 conforms to a lower part of the material lining 2140 but is recessed relative to an upper part of the material lining 2140. A recessed insulating filler material 2154 is located within the second material lining 2148 and has an upper surface coplanar with an upper surface of the second material lining 2148. A third material lining 2156 lies within the upper part of the material lining 2140 and is located on the upper surface of the insulating filler material 2154 and on the upper surface of the second material lining 2148. The third material lining 2156 has no seam.

[0164] With reference to Fig. 22C includes an opening 2136 on the PMOS region of the structure 2100 and a material lining 2140 along the side walls of the opening 2136. A second material lining 2148 conforms to a lower part of the material lining 2140 but is recessed relative to an upper part of the material lining 2140. A recessed insulating filler material 2154 is located within and above the second material lining 2148 and has an upper surface above an upper surface of the second material lining 2148. A third material lining 2156 lies within the upper part of the material lining 2140 and is located on the upper surface of the insulating filler material 2154. The third material lining 2156 is shown without a seam, but in other embodiments, the third material lining 2156 has a seam.

[0165] With reference to Fig. 22D includes an opening 2136 on the PMOS region of the structure 2100 and a material lining 2140 along the side walls of the opening 2136. A second material lining 2148 conforms to a lower part of the material lining 2140 but is recessed relative to an upper part of the material lining 2140. A recessed insulating filler material 2154 is located within the second material lining 2148 and has an upper surface recessed from an upper surface of the second material lining 2148. A third material lining 2156 lies within the upper part of the material lining 2140 and is located on the upper surface of the insulating filler material 2154 and on the upper surface of the second material lining 2148. The third material lining 2156 is shown without a seam, but in other embodiments, the third material lining 2156 has a seam.

[0166] With joint reference to Fig. 19A, 19B, 20A, 20B, 21A-21M and 22A-22D comprise an integrated circuit structure according to an embodiment of the present disclosure, comprising a fin, such as a silicon fin, wherein the fin has a top surface and side walls. The top surface has a longest dimension along a direction. A first insulating structure is located over a first end of the fin. A gate structure comprises a gate electrode located over the top surface and laterally adjacent to the side walls of a region of the fin. The gate structure is spaced apart from the first insulating structure along the direction. A second insulating structure is located over a second end of the fin, the second end being opposite the first end. The second insulating structure is spaced apart from the gate structure along the direction. The first insulating structure and the second insulating structure both comprise a first dielectric material (e.g., silicon).the material lining 2140), which laterally surrounds a recessed second dielectric material (e.g., the second material lining 2148) that is different from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material (e.g., the recessed insulating fill material 2154) that is different from the first and second dielectric materials.

[0167] In one embodiment, the first insulating structure and the second insulating structure both further include a fourth dielectric material (e.g., the third material lining 2156), which is laterally surrounded by an upper part of the first dielectric material, the fourth dielectric material being located on an upper surface of the third dielectric material. In such an embodiment, the fourth dielectric material is also located on an upper surface of the second dielectric material. In another such embodiment, the fourth dielectric material has an approximately vertical central seam. In yet another such embodiment, the fourth dielectric material has no seam.

[0168] In one embodiment, the third dielectric material has an upper surface coplanar with an upper surface of the second dielectric material. In another embodiment, the third dielectric material has an upper surface below an upper surface of the second dielectric material. In yet another embodiment, the third dielectric material has an upper surface above an upper surface of the second dielectric material, and the third dielectric material is further located above the upper surface of the second dielectric material. In one embodiment, the first and second insulation structures induce a compressive stress on the fin. In such an embodiment, the gate electrode is a p-type gate electrode.

[0169] In one embodiment, the first insulation structure has a width along the direction, the gate structure has a width along the direction, and the second insulation structure has a width along the direction. In such an embodiment, the center of the gate structure is spaced from the center of the first insulation structure by a grid dimension along the direction, and the center of the second insulation structure is spaced from the center of the gate structure by the grid dimension along the direction. In one embodiment, the first and second insulation structures are both located in a corresponding trench in an interlayer dielectric.

[0170] In such an embodiment, a first source or drain region is located between the gate structure and the first insulation structure. A second source or drain region is located between the gate structure and the second insulation structure. In such an embodiment, the first and second source or drain regions are embedded source or drain regions including silicon and germanium. In such an embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the fin and along the sidewalls of the gate electrode.

[0171] Another aspect is that the depth of individual dielectric plugs within a semiconductor structure or within an architecture formed on a common substrate can vary. As an example, Fig. 23A a cross-sectional view of another semiconductor structure with mechanical stress-inducing fin end features according to another embodiment of the present disclosure. With reference to Fig. 23A comprises a flat dielectric plug 2308A together with a pair of deep dielectric plugs 2308B and 2308C. In such an embodiment, as shown, the flat dielectric plug 2308C is located within a substrate 2304 at a depth approximately equal to the depth of a semiconductor fin 2302, while the pair of deep dielectric plugs 2308B and 2308C are located within the substrate 2304 at a depth below the depth of the semiconductor fin 2302.

[0172] Again with reference to Fig. 23A Such an arrangement can enable an increase in mechanical stress on fin-trim-insulation (FTI) devices in a trench that etches deeper into the substrate 2304 to provide insulation between adjacent fins 2302. Such an approach can be implemented to increase the density of transistors on a chip. In one embodiment, the mechanical stress effect induced by the plug filling in FTI transistors is amplified because the transfer of mechanical stress occurs both in the fin and in a substrate or well beneath the transistor.

[0173] Another aspect is that the width or amount of a tensile stress-inducing oxide layer contained in a dielectric plug can be varied within a semiconductor structure or within an architecture formed on a common substrate, e.g., depending on whether the device is a PMOS device or an NMOS device. As an example, this is illustrated... Fig. 23B a cross-sectional view of another semiconductor structure with mechanical stress-inducing fin end features according to another embodiment of the present disclosure. With reference to Fig. 23B NMOS devices in a certain embodiment include a relatively more tensile stress-inducing oxide layer 2350 than corresponding PMOS devices.

[0174] Again with reference to Fig. In one embodiment, 23B implements a different plug filling to induce appropriate mechanical stress in NMOS and PMOS. For example, NMOS plugs 2308D and 2308E have a larger volume and width of the tensile stress-inducing oxide layer 2350 than PMOS plugs 2308F and 2308G. The plug filling can be structured to induce different mechanical stress in NMOS and PMOS devices. For example, lithographic structuring can be used to open up PMOS devices (e.g., widening the dielectric plug grooves for PMOS devices), and different filling options can be implemented at this point to differentiate the plug filling in NMOS versus PMOS devices. In one embodiment, reducing the volume of a flowable oxide in the plug on PMOS devices can reduce the induced tensile stress.In such an embodiment, compressive stress can dominate, e.g., from applying compressive stress to the source and drain regions. In other embodiments, the use of different plug linings or different filling materials provides adjustable control of mechanical stress.

[0175] As described above, it is understood that the effects of mechanical polyplug stress can benefit both NMOS transistors (e.g., channel pull stress) and PMOS transistors (e.g., channel push stress). According to one embodiment of the present disclosure, a semiconductor fin is a semiconductor fin subjected to uniaxial mechanical stress. The semiconductor fin subjected to uniaxial mechanical stress can be subjected to uniaxial tensile or compressive stress. For example, illustrated according to one or more embodiments of the present disclosure Fig. 24A an inclined view of a fin with a uniaxial tensile stress, while Fig. Figure 24B illustrates an inclined view of a fin under uniaxial compressive stress.

[0176] With reference to Fig. In 24A, a semiconductor fin 2400 has a discrete channel region (C) arranged within it. A source region (S) and a drain region (D) are arranged in the semiconductor fin 2400 on both sides of the channel region (C). The discrete channel region of the semiconductor fin 2400 has a current flow direction along the direction of a uniaxial tensile stress (arrows pointing away from each other and towards ends 2402 and 2404) from the source region (S) to the drain region (D).

[0177] With reference to Fig. In 24B, a semiconductor fin 2450 has a discrete channel region (C) arranged therein. A source region (S) and a drain region (D) are arranged in the semiconductor fin 2450 on both sides of the channel region (C). The discrete channel region of the semiconductor fin 2450 has a current flow direction along the direction of a uniaxial pressure stress (arrows pointing towards each other and from the ends 2452 and 2454) from the source region (S) to the drain region (D). Accordingly, embodiments described here can be implemented to improve transistor mobility and driver current, thereby enabling faster-operating circuits and chips.

[0178] Another aspect involves a relationship between positions where gate-line cuts (polycuts) are performed and local fin trim insulation (FTI) fin cuts are performed. In one embodiment, local FTI fin cuts are performed only at positions where polycuts are performed. However, in such an embodiment, an FTI cut is not necessarily performed at every position where a polycut is performed.

[0179] Fig. 25A and Fig. Figure 25B illustrates top views representing various processes in a method for structuring fins with single-gate spacing to form a local isolation structure in select-gate line section positions, according to an embodiment of the present disclosure.

[0180] With reference to Fig. Document 25A includes a method for fabricating an integrated circuit structure forming multiple fins 2502, wherein individual fins 2502 have a longest dimension along a first direction 2504. Multiple gate structures 2506 are located above the multiple fins 2502, wherein individual gate structures 2506 have a longest dimension along a second direction 2508 orthogonal to the first direction 2504. In one embodiment, the gate structures 2506 are sacrificial or dummy gate lines, e.g., made of polycrystalline silicon. In another embodiment, the multiple fins 2502 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0181] Again with reference to Fig. 25A A dielectric material structure 2510 is formed between adjacent multiple gate structures 2506. Portions 2512 and 2513 of two of the multiple gate structures 2506 are removed to expose portions of each of the multiple fins 2502. In one embodiment, removing portions 2512 and 2513 of the two of the multiple gate structures 2506 involves using a lithographic window wider than the width of each of portions 2512 and 2513 of the gate structures 2506. The exposed portion of each of the multiple fins 2502 at position 2512 is removed to form a section region 2520. In one embodiment, the exposed portion of each of the multiple fins 2502 is removed using a dry or plasma etching process. However, the exposed part of each of the multiple fins 2502 at position 2513 is masked before removal.In one embodiment, area 2512 / 2520 represents both a polycut and a local FIT cut. However, position 2513 represents only a polycut.

[0182] With reference to Fig. 25B, positions 2512 / 2520 of the polycut and the local FTI fin cut, and position 2513 of the polycut are filled with insulating structures 2530, such as dielectric plugs. Exemplary structures or a “polycut” or “plug” structure are described below.

[0183] Fig. Figures 26A-26C illustrate cross-sectional views of various dielectric plug options for polycut and FTI local fin cut positions and polycut-only positions for different areas of the structure. Fig. 25B according to one embodiment of the present disclosure.

[0184] With reference to Fig. 26A is a cross-sectional view of part 2600A of the dielectric plug 2530 at position 2513 along the a-a' axis of the structure. Fig. 25B shown. Part 2600A of the dielectric plug 2530 is shown on an uncut fin 2502 and between dielectric material structures 2510.

[0185] With reference to Fig. 26B is a cross-sectional view of part 2600B of the dielectric plug 2530 at position 2512 along the b-b' axis of the structure. Fig. 25B shown. Part 2600B of the dielectric plug 2530 is shown on a cut fin position 2520 and between dielectric material structures 2510.

[0186] With reference to Fig. 26C is a cross-sectional view of part 2600C of the dielectric plug 2530 at position 2512 along the c-c' axis of the structure. Fig. Figure 25B shows the part 2600C of the dielectric plug 2530 on a trench insulation structure 2602 between the fins 2502 and between dielectric material structures 2510. In an embodiment, examples of which are described above, the trench insulation structure 2602 includes a first insulation layer 2602A, a second insulation layer 2602B, and an insulating filler material 2602C on the second insulation layer 2602B.

[0187] With joint reference to Fig. Documents 25A, 25B, and 26A-26C comprise a method for fabricating an integrated circuit structure according to an embodiment of the present disclosure. Several fins are formed, wherein individual fins are located along a first direction. Several gate structures are formed over the multiple fins, with individual gate structures located along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent multiple gate structures. A portion of a first multiple gate structure is removed to expose a first portion of each multiple fin. A portion of a second multiple gate structure is removed to expose a second portion of each multiple fin. The exposed first portion of each multiple fin is removed, but the exposed second portion of each multiple fin is not removed.A first isolation structure is formed at the position of the remote first part of the multiple fins. A second isolation structure is formed at the position of the remote part of the second of the multiple gate structures.

[0188] In one embodiment, removing portions of the first and second of the multiple gate structures involves using a lithographic window wider than the width of each portion of the first and second of the multiple gate structures. In another embodiment, removing the exposed first portion of each of the multiple fins involves etching to a depth less than the height of the multiple fins. In such an embodiment, the depth is greater than the depth of source or drain regions in the multiple fins. In one embodiment, the multiple fins include silicon and are continuous with a portion of a silicon substrate.

[0189] With joint reference to Fig. 16A, 25A, 25B and 26A-26C comprise an integrated circuit structure according to another embodiment of the present disclosure, comprising a fin including silicon, wherein the fin has a longest dimension along a first direction. An insulation structure is located over an upper part of the fin, the insulation structure having a center along the first direction. A first gate structure is located over the upper part of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. A center of the first gate structure is spaced from the center of the insulation structure by a grid unit along the first direction. A second gate structure is located over the upper part of the fin, the second gate structure having a longest dimension along the second direction.The center of the second gate structure is spaced from the center of the first gate structure by the grid dimension along the first direction. A third gate structure is located above the upper part of the fin opposite one side of the isolation structure from the first and second gate structures, with the third gate structure having its longest dimension along the second direction. The center of the third gate structure is spaced from the center of the isolation structure by the grid dimension along the first direction.

[0190] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between sidewalls of a high-k-gate dielectric layer. In such an embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on and between the sidewalls of a high-k-gate dielectric layer.

[0191] In one embodiment, a first epitaxial semiconductor region is located on the upper part of the fin between the first gate structure and the isolation structure. A second epitaxial semiconductor region is located on the upper part of the fin between the first and second gate structures. A third epitaxial semiconductor region is located on the upper part of the fin between the third gate structure and the isolation structure. In this embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon and germanium. In another such embodiment, the first, second, and third epitaxial semiconductor regions comprise silicon.

[0192] With joint reference to Fig. 16A, 25A, 25B, and 26A-26C comprise an integrated circuit structure according to another embodiment of the present disclosure, comprising a shallow trench insulation (STI) structure between a pair of semiconductor fins, wherein the STI structure has a longest dimension along a first direction. An insulation structure is located on the STI structure, the insulation structure having a center along the first direction. A first gate structure is located on the STI structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. A center of the first gate structure is spaced from the center of the insulation structure by one grid unit along the first direction. A second gate structure is located on the STI structure, the second gate structure having a longest dimension along the second direction.The center of the second gate structure is spaced from the center of the first gate structure by the grid dimension along the first direction. A third gate structure is located on the STI structure opposite one side of the isolation structure from the first and second gate structures, with the third gate structure having its longest dimension along the second direction. The center of the third gate structure is spaced from the center of the isolation structure by the grid dimension along the first direction.

[0193] In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode on and between sidewalls of a high-k-gate dielectric layer. In such an embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on and between the sidewalls of a high-k-gate dielectric layer. In one embodiment, the pair of semiconductor fins is a pair of silicon fins.

[0194] In another aspect, either a polycut and a local FIT cut together or just a polycut, the insulating structures or dielectric plugs used to fill the cut positions may extend laterally into dielectric spacers of the corresponding cut gate line or even beyond the dielectric spacers of the corresponding cut gate line.

[0195] In a first example, where a trench contact shape is not affected by a dielectric poly-cut plug, the following is illustrated Fig. 27A a top view and corresponding cross-sectional view of an integrated circuit structure with a gate line section having a dielectric plug extending into dielectric spacers of the gate line, according to an embodiment of the present disclosure.

[0196] With reference to Fig. 27A includes an integrated circuit structure 2700A comprising a first silicon fin 2702 with a longest dimension along a first direction 2703. A second silicon fin 2704 has a longest dimension along the first direction 2703. An insulating material 2706 is located between the first silicon fin 2702 and the second silicon fin 2704. A gate line 2708 is located above the first silicon fin 2702 and above the second silicon fin 2704 along a second direction 2709, the second direction 2709 being orthogonal to the first direction 2703. The gate line 2708 has a first side 2708A and a second side 2708B, and has a first end 2708C and a second end 2708D. The gate line 2708 has a discontinuity 2710 above the insulator material 2706 between the first end 2708C and the second end 2708D of the gate line 2708. The discontinuity 2710 is filled by a dielectric plug 2712.

[0197] A trench contact 2714 is located above the first silicon fin 2702 and above the second silicon fin 2704 along the second direction 2709 on the first side 2708A of the gate line 2708. The trench contact 2714 is continuous above the insulator material 2706 at a position 2715 laterally adjacent to the dielectric plug 2712. A dielectric spacer 2716 is located laterally between the trench contact 2714 and the first side 2708A of the gate line 2708. The dielectric spacer 2716 is continuous along the first side 2708A of the gate line 2708 and the dielectric plug 2712. The dielectric spacer 2716 has a width (W2) laterally adjacent to the dielectric plug 2712 that is thinner than a width (W1) laterally adjacent to the first side 2708A of the gate line 2708.

[0198] In one embodiment, a trench contact 2718 is located above the first silicon fin 2702 and above the second silicon fin 2704 along the second direction 2709 on the second side 2708B of the gate line 2708. The second trench contact 2718 is continuous above the insulator material 2706 at a position 2719 laterally adjacent to the dielectric plug 2712. In such an embodiment, a second dielectric spacer 2720 is located laterally between the second trench contact 2718 and the second side 2708B of the gate line 2708. The second dielectric spacer 2720 is continuous along the second side 2708B of the gate line 2708 and the dielectric plug 2712. The second dielectric spacer has a width laterally adjacent to the dielectric plug 2712 that is thinner than a width laterally adjacent to the second side 2708B of the gate line 2708.

[0199] In one embodiment, the gate conductor 2708 includes a high-k-gate dielectric layer 2722, a gate electrode 2724, and a dielectric cap layer 2726. In one embodiment, the dielectric plug 2712 includes the same material as the dielectric spacer 2714 but is separate from the dielectric spacer 2714. In another embodiment, the dielectric plug 2712 includes a different material than the dielectric spacer 2714.

[0200] A second example, in which a trench contact shape is influenced by a dielectric poly-cut plug, illustrates Fig. 27B a top view and corresponding cross-sectional view of an integrated circuit structure with a gate-line section having a dielectric plug extending beyond dielectric spacers of the gate line, according to another embodiment of the present disclosure.

[0201] With reference to Fig. 27B includes an integrated circuit structure 2700B, a first silicon fin 2752 with a longest dimension along a first direction 2753, and a second silicon fin 2754 with a longest dimension along the first direction 2753. An insulating material 2756 is located between the first silicon fin 2752 and the second silicon fin 2754. A gate line 2758 is located above the first silicon fin 2752 and above the second silicon fin 2754 along a second direction 2759, the second direction 2759 being orthogonal to the first direction 2753. The gate line 2758 has a first side 2758A and a second side 2758B, and a first end 2758C and a second end 2758D. The gate line 2758 has a discontinuity 2760 above the insulator material 2756 between the first end 2758C and the second end 2758D of the gate line 2758. The discontinuity 2760 is filled by a dielectric plug 2762.

[0202] A trench contact 2764 is located above the first silicon fin 2752 and above the second silicon fin 2754 along the second direction 2759 on the first side 2758A of the gate line 2758. The trench contact 2764 is continuous above the insulator material 2756 at a position 2765 laterally adjacent to the dielectric plug 2762. A dielectric spacer 2766 is located laterally between the trench contact 2764 and the first side 2758A of the gate line 2758. The dielectric spacer 2766 is located along the first side 2758A of the gate line 2758, but is not located along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2766. The trench contact 2764 has a width (W1) laterally adjacent to the dielectric plug 2762 that is thinner than a width (W2) laterally adjacent to the dielectric spacer 2766.

[0203] In one embodiment, a second trench contact 2768 is located above the first silicon fin 2752 and above the second silicon fin 2754 along the second direction 2759 on the second side 2758B of the gate line 2758. The second trench contact 2768 is continuous above the insulator material 2756 at a position 2769 laterally adjacent to the dielectric plug 2762. In such an embodiment, a second dielectric spacer 2770 is located laterally between the second trench contact 2768 and the second side 2758B of the gate line 2758. The second dielectric spacer 2770 is located along the second side 2758B of the gate line 2758, but is not located along the dielectric plug 2762, resulting in a discontinuous dielectric spacer 2770. leads.The second trench contact 2768 has a width laterally adjacent to the dielectric plug 2762 that is thinner than a width laterally adjacent to the dielectric spacer 2770.

[0204] In one embodiment, the gate conductor 2758 comprises a high-k-gate dielectric layer 2772, a gate electrode 2774, and a dielectric cap layer 2776. In one embodiment, the dielectric plug 2762 comprises the same material as the dielectric spacer 2764 but is separate from the dielectric spacer 2764. In another embodiment, the dielectric plug 2762 comprises a different material than the dielectric spacer 2764.

[0205] In a third example, where a dielectric plug tapers from the top of the plug to the bottom of the plug for a poly-section position, we illustrate Fig. 28A-28F Cross-sectional views of various operations in a method for manufacturing an integrated circuit structure having a gate-line section, with a dielectric plug having an upper part extending beyond dielectric spacers of the gate line and a lower part extending into the dielectric spacers of the gate line, according to another embodiment of the present disclosure.

[0206] With reference to Fig. In embodiment 28A, several gate lines 2802 are formed over a structure 2804, such as a trench insulation structure between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line, e.g., with a dummy gate electrode 2806 and a dielectric cap 2808. Portions of such sacrificial or dummy gate lines can be replaced later in a replacement gate process, e.g., following the formation of a dielectric plug as described below. Dielectric spacers 2810 are located along the side walls of the gate lines 2802. A dielectric material 2812, such as an interdielectric layer, is located between the gate lines 2802. A mask 2814 is formed and lithographically structured to expose part of one of the gate lines 2802.

[0207] With reference to Fig. In embodiment 28B, the central gate line 2802 is removed by an etching process, with the mask 2814 replacing it. The mask 2814 is then removed. In one embodiment, the etching process erodes portions of the dielectric spacers 2810 of the removed gate line 2802, forming reduced dielectric spacers 2816. Additionally, upper portions of the dielectric material 2812 exposed by the mask 2814 are eroded in the etching process, forming eroded dielectric material portions 2818. In a particular embodiment, residual dummy gate material 2820, such as residual polycrystalline silicon, remains in the structure as an artifact of an incomplete etching process.

[0208] With reference to Fig. 28C will have a hard mask 2822 applied over the structure made of Fig. 28B formed. The hard mask 2822 can be conformed to the upper part of the structure made of Fig. 2B and in particular with the eroded dielectric material parts 2818.

[0209] With reference to Fig. In 28D, the remaining dummy gate material 2820 is removed, for example, by an etching process that may be chemically similar to the etching process used to remove the central part of the gate lines 2802. In one embodiment, the hard mask 2822 protects the eroded dielectric material parts 2818 from further erosion during the removal of the remaining dummy gate material 2820.

[0210] With reference to Fig. 28E The hard mask 2822 is removed. In one embodiment, the hard mask 2822 is removed without or substantially without further erosion of the eroded dielectric material parts 2818.

[0211] With reference to Fig. 28F will be a dielectric plug 2830 in the opening of the structure made of Fig. 28E formed. The upper part of the dielectric plug 2830 is located above the eroded dielectric material portions 2818, e.g., effectively beyond the original spacers 2810. The lower part of the dielectric plug 2830 is located adjacent to the reduced dielectric spacers 2816, e.g., effectively within, but not beyond, the original spacers 2810. Consequently, a dielectric plug 2830 has a tapered profile, as shown in Fig. 28F is shown. It is understood that the dielectric plug 2830 can be manufactured from materials and a process described above for other polycut or FTI plugs or fin end stressors.

[0212] In another aspect, parts of a placeholder gate structure or a dummy gate structure can be retained over trench isolation areas below a permanent gate structure as protection against erosion of the trench isolation areas during a replacement gate process. For example, illustrate Fig. 29A-29C a top view and corresponding cross-sectional views of an integrated circuit structure with residual dummy gate material at parts of the bottom of a permanent gate stack according to an embodiment of the present disclosure.

[0213] With reference to Fig. 29A-29C includes an integrated circuit structure and a fin 2902, such as a silicon fin, projecting from a semiconductor substrate 2904. The fin 2902 has a lower fin part 2902B and an upper fin part 2902A. The upper fin part 2902A has a top surface 2902C and side walls 2902D. An insulating structure 2906 surrounds the lower fin part 2902B. The insulating structure 2906 includes an insulating material 2906C with an upper surface 2907. A semiconductor material 2908 is located on a portion of the upper surface 2907 of the insulating material 2906C. The semiconductor material 2908 is separated from the fin 2902.

[0214] A gate dielectric layer 2910 is located above the top surface 2902C of the upper fin part 2902A and laterally adjacent to the side walls 2902D of the upper fin part 2902A. The gate dielectric layer 2910 is also located on the semiconductor material 2908 on part of the upper surface 2907 of the insulating material 2906C. An intervening additional gate dielectric layer 2911, such as an oxidized part of the fin 2902, may be located between the gate dielectric layer 2910 above the top surface 2902C of the upper fin part 2902A and laterally adjacent to the side walls 2902D of the upper fin part 2902A. A gate electrode 2912 is located above the gate dielectric layer 2910 above the top surface 2902C of the upper fin part 2902A and laterally adjacent to the side walls 2902D of the upper fin part 2902A.The gate electrode 2912 is further located above the gate dielectric layer 2910 on the semiconductor material 2908 on the portion of the upper surface 2907 of the insulating material 2906C. A first source or drain region 2916 is located adjacent to a first side of the gate electrode 2912, and a second source or drain region 2918 is located adjacent to a second side of the gate electrode 2912, the second side being opposite the first side. In an embodiment, examples of which are described above, the insulating structure 2906 comprises a first insulating layer 2906A, a second insulating layer 2906B, and the insulating material 2906C.

[0215] In one embodiment, the semiconductor material 2908 on the portion of the upper surface 2907 of the insulating material 2906C is or comprises polycrystalline silicon. In this embodiment, the upper surface 2907 of the insulating material 2906C has a concave depression, as shown, and the semiconductor material 2908 is located in the concave depression. In another embodiment, the insulating structure 2906 comprises a second insulating material (2906A or 2906B or both 2906A / 2906B) along a bottom and side walls of the insulating material 2906C. In such an embodiment, the portion of the second insulating material (2906A or 2906B or both 2906A / 2906B) along the side walls of the insulating material 2906C has an upper surface above a top surface of the insulating material 2906C, as shown.In one embodiment, the upper surface of the second insulating material (2906A or 2906B or both 2906A12906B) is located above or coplanar with a top surface of the semiconductor material 2908.

[0216] In one embodiment, the semiconductor material 2908 extends on the portion of the upper surface 2907 of the insulating material 2906C not beyond the gate dielectric layer 2910. That is, from a top-down perspective, the position of the semiconductor material 2908 is limited to the area covered by the gate stack 2912 / 2910. In one embodiment, a first dielectric spacer 2920 is located along the first side of the gate electrode 2912. A second dielectric spacer 2922 is located along the second side of the gate electrode 2912. In such an embodiment, the gate dielectric layer 2910 further extends along the side walls of the first dielectric spacer 2920 and the second dielectric spacer 2922, as shown in Fig. 29B is shown.

[0217] In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (e.g., an exit working layer). In such an embodiment, the exit working layer 2912A includes titanium and nitrogen. In another embodiment, the exit working layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 further includes a conductive filler metal layer 2912B over the exit working layer 2912A. In such an embodiment, the conductive filler metal layer 2912B includes tungsten. In a particular embodiment, the conductive filler metal layer 2912B includes 95 or more atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, an insulating cap 2924 is located on the gate electrode 2912 and may extend over the gate dielectric layer 2910, as shown in Fig. 29B is shown.

[0218] Fig. Figures 30A-30D illustrate cross-sectional views of various processes in a method for fabricating an integrated circuit structure with residual dummy gate material at portions of the bottom of a permanent gate stack according to another embodiment of the present disclosure. The perspective shown is along a portion of the a-a' axis of the structure. Fig. 29C.

[0219] With reference to Fig. Document 30A comprises a method for fabricating an integrated circuit structure forming a fin 3000 from a semiconductor substrate 3002. The fin 3000 has a lower fin part 3000A and an upper fin part 3000B. The upper fin part 3000B has a top surface 3000C and side walls 3000D. An insulating structure 3004 surrounds the lower fin part 3000A. The insulating structure 3004 includes an insulating material 3004C with a top surface 3005. A placeholder gate electrode 3006 is located above the top surface 3000C of the upper fin part 3000B and laterally adjacent to the side walls 3000D of the upper fin part 3000B. The placeholder gate electrode 3006 includes a semiconductor material.

[0220] Although this is from the perspective of Fig. 30A is not shown (but positions for it are in Fig. (29C) a first source or drain region can be formed adjacent to a first side of the placeholder gate electrode 3006, and a second source or drain region can be formed adjacent to a second side of the placeholder gate electrode 3006, the second side being opposite the first side. Furthermore, dielectric gate spacers can be formed along the side walls of the placeholder gate electrode 3006, and an interlayer dielectric (ILD) layer can be formed laterally adjacent to the placeholder gate electrode 3006.

[0221] In one embodiment, the placeholder gate electrode 3006 is or includes polycrystalline silicon. In one embodiment, the upper surface 3005 of the insulating material 3004C of the insulating structure 3004 has a concave depression, as shown. Part of the placeholder gate electrode 3006 is located in the concave depression. In one embodiment, the insulating structure 3004 includes a second insulating material (3004A or 3004B or both 3004A and 3004B) that extends along a bottom and side walls of the insulating material 3004C, as shown. In such an embodiment, the part of the second insulating material (3004A or 3004B or both 3004A and 3004B) along the side walls of the insulating material 3004C has an upper surface above at least a part of the upper surface 3005 of the insulating material 3004C.In one embodiment, the upper surface of the second insulating material (3004A or 3004B or both 3004A and 3004B) is located above a lowermost surface of a part of the placeholder gate electrode 3006.

[0222] With reference to Fig. 30B will be the placeholder gate electrode 3006 from above the top 3000C and side walls 3000D of the upper fin part 3000B, e.g. along the direction 3008. Fig. 30A, etched. The etching process can be described as a substitute gate process. In one embodiment, the etching or substitute gate process is incomplete and leaves a part 3012 of the placeholder gate electrode 3006 on at least a part of the upper surface 3005 of the insulating material 3004C of the insulating structure 3004.

[0223] Referring to both Fig. In both 30A and 30B, an oxidized portion 3010 of the upper fin portion 3000B, which is formed before the formation of the placeholder gate electrode 3006, is retained during the etching process, as shown. In another embodiment, however, a placeholder gate dielectric layer is formed before the formation of the placeholder gate electrode 3006 and the placeholder gate dielectric layer is subsequently removed after etching the placeholder gate electrode.

[0224] With reference to Fig. In one embodiment, a gate dielectric layer 3014 is formed over the top surface 3000C of the upper fin part 3000B and laterally adjacent to the side walls 3000D of the upper fin part 3000B. In another embodiment, the gate dielectric layer 3014 is formed on the oxidized part 3010 of the upper fin part 3000B, over the top surface 3000C of the upper fin part 3000B and laterally adjacent to the side walls 3000D of the upper fin part 3000B, as shown. In another embodiment, the gate dielectric layer 3014 is formed directly on the upper fin part 3000B above the top surface of 3000C of the upper fin part 3000B and laterally adjacent to the side walls 3000D of the upper fin part 3000B if the oxidized part 3010 of the upper fin part 3000B is subsequently removed after etching the placeholder gate electrode.In both cases, in one embodiment, the gate dielectric layer 3014 is further formed on the part 3012 of the placeholder gate electrode 3006 on the part of the upper surface 3005 of the insulating material 3004C of the insulating structure 3004.

[0225] With reference to Fig. A permanent gate electrode 3016 is formed above the gate dielectric layer 3014 on the top surface 3000C of the upper fin part 3000B and laterally adjacent to the side walls 3000D of the upper fin part 3000B. The permanent gate electrode 3016 is further located above the gate dielectric layer 3014 on part 3012 of the placeholder gate electrode 3006 on part of the upper surface 3005 of the insulating material 3004C.

[0226] In one embodiment, the formation of the permanent gate electrode 3016 includes the formation of an exit working layer 3016A. In such an embodiment, the exit working layer 3016A comprises titanium and nitrogen. In another such embodiment, the exit working layer 3016A comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, the formation of the permanent gate electrode 3016 further includes the formation of a conductive filler metal layer 3016B, which is formed over the exit working layer 3016A. In such an embodiment, the formation of the conductive filler metal layer 3016B includes the formation of a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In one embodiment, an insulating gate cap layer 3018 is formed on the permanent gate electrode 3016.

[0227] In another aspect, some embodiments of the present disclosure include an amorphous high-k layer in a gate dielectric structure for a gate electrode. In other embodiments, a partially or fully crystalline high-k layer is included in a gate dielectric structure for a gate electrode. In one embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment including a partially or fully crystalline high-k layer, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

[0228] In one embodiment, approaches are described here for increasing the charge in a device channel and improving subthreshold behavior by using ferroelectric or antiferroelectric gate oxides. A ferroelectric or antiferroelectric gate oxide can increase the channel charge for a higher current and can also result in a steeper turn-on behavior.

[0229] To provide context, hafnium- or zirconium-based (Hf or Zr) ferroelectric and antiferroelectric (FE or AFE) materials are typically much thinner than ferroelectric materials such as lead zirconium titanate (PZT) and can therefore be compatible with highly scaled logic technology. Two features of FE or AFE materials can improve the performance of logic transistors: (1) the higher charge in the channel achieved through FE or AFE polarization, and (2) a steeper turn-on behavior due to a sharp FE or AFE transition. Such properties can improve transistor performance by increasing current and reducing subthreshold swing (SS).

[0230] Fig. Figure 31A illustrates a cross-sectional view of a semiconductor device with a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure.

[0231] With reference to Fig. 31A comprises an integrated circuit structure 3100 and a gate structure 3102 above a substrate 3104. In one embodiment, the gate structure 3102 is located above or over a semiconductor channel structure 3106, including a monocrystalline material such as monocrystalline silicon. The gate structure 3102 includes a gate dielectric above the semiconductor channel structure 3106 and a gate electrode above the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3102A. The gate electrode has a conductive layer 3102B on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. The conductive layer 3102B contains a metal and can be a barrier layer, an exit working layer, or a template layer that enhances crystallization of FE or AFE layers.A gate filler layer or layers 3102C is located on or above the conductive layer 3102B. A source region 3108 and a drain region 3110 are located on opposite sides of the gate structure 3102. Source or drain contacts 3112 are electrically connected to the source region 3108 and the drain region 3110 at positions 3149 and are spaced from the gate structure 3102 by an interlayer dielectric layer 3114 and / or gate-dielectric spacers 3116. In the example from... Fig. 31A are the source region 3108 and the drain region 3110 regions of the substrate 3104. In one embodiment, the source or drain contacts 3112 include a barrier layer 3112A and a conductive trench filler material 3112B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3102A extends along the dielectric spacers 3116, as shown in Fig. 31A is shown.

[0232] In one embodiment, and as is true throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide including Zr and Hf with a Zr:Hf ratio of 50:50 or more in Zr. The ferroelectric effect can increase with increasing orthorhombic crystallinity. In one embodiment, the ferroelectric polycrystalline material layer has an orthorhombic crystallinity of at least 80%.

[0233] In one embodiment, and as is true throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide including Zr and Hf with a Zr:Hf ratio of 80:20 or more in Zr and even up to 100% Zr, ZrO2. In one embodiment, the antiferroelectric polycrystalline material layer has a tetragonal crystallinity of at least 80%.

[0234] In one embodiment, and as is true throughout the disclosure, the gate dielectric of the gate stack 3102 further comprises an amorphous dielectric layer 3103, such as a native silicon oxide layer, a high-k dielectric (HfOx, Al₂O₃, etc.), or combinations of oxide and high-k materials, between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106. In one embodiment, and as is true throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness in the range of 1 nanometer to 8 nanometers. In one embodiment, and as is true throughout the disclosure, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a crystal grain size approximately in the range of 20 nanometers or more.

[0235] In one embodiment, following the deposition of the ferroelectric or antiferroelectric polycrystalline material layer 3102A, e.g., by atomic layer deposition (ALD), a layer including a metal (e.g., layer 3102B, such as a 5-10 nanometer titanium nitride or tantalum nitride or tungsten) is formed on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. Annealing is then carried out. In one embodiment, the annealing is performed for a duration in the range of 1 millisecond to 30 milliseconds. In another embodiment, the annealing is performed at a temperature in the range of 500-1100 degrees Celsius.

[0236] Fig. Figure 31B illustrates a cross-sectional view of another semiconductor device having a ferroelectric or antiferroelectric gate dielectric structure according to an embodiment of the present disclosure.

[0237] With reference to Fig. 31B comprises an integrated circuit structure 3150 and a gate structure 3152 above a substrate 3154. In one embodiment, the gate structure 3152 is located above or over a semiconductor channel structure 3156, including a monocrystalline material such as monocrystalline silicon. The gate structure 3152 includes a gate dielectric above the semiconductor channel structure 3156 and a gate electrode above the gate dielectric structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer 3152A and may further include an amorphous oxide layer 3153. The gate electrode has a conductive layer 3152B on the ferroelectric or antiferroelectric polycrystalline material layer 3152A. The conductive layer 3152B includes a metal and may be a barrier layer or an exit layer.A gate filler layer or layers 3152C is located on or above the conductive layer 3152B. A raised source region 3158 and a raised drain region 3160, such as regions of a semiconductor material different from the semiconductor channel structure 3156, are located on opposite sides of the gate structure 3152. Source or drain contacts 3162 are electrically connected to the source region 3158 and the drain region 3160 at positions 3199 and are spaced from the gate structure 3152 by an interlayer dielectric layer 3164 and / or gate-dielectric spacers 3166. In one embodiment, the source or drain contacts 3162 include a barrier layer 3162A and a conductive trench filler 3162B. In one embodiment, the ferroelectric or antiferroelectric polycrystalline material layer 3152A extends along the dielectric spacers 3166, as shown in . Fig. 31B is shown.

[0238] Fig. Figure 32A illustrates a top view of several gate lines over a pair of semiconductor fins according to another embodiment of the present disclosure.

[0239] With reference to Fig. In 32A, several active gate lines 3204 are formed over several semiconductor fins 3200. Dummy gate lines 3206 are located at the ends of the several semiconductor fins 3200. Spacers 3208 between the gate lines 3204 / 3206 are positions where trench contacts can be located to provide conductive contacts to source or drain regions, such as source or drain regions 3251, 3252, 3253, and 3254. In one embodiment, the structuring of the several gate lines 3204 / 3206 or the structuring of the several semiconductor fins 3200 is described as a lattice structure. In one embodiment, the grid-like structuring includes the multiple gate lines 3204 / 3206 or the structuring of the multiple semiconductor fins 3200, which are spaced apart at a constant grid spacing and / or have a constant width.

[0240] Fig. Figure 32B illustrates a cross-sectional view along the a-a' axis. Fig. 32A according to an embodiment of the present disclosure.

[0241] With reference to Fig. In 32B, several active gate lines 3264 are formed over a semiconductor fin 3262, which is formed over a substrate 3260. Dummy gate lines 3266 are located at the ends of the semiconductor fin 3262. A dielectric layer 3270 is located outside the dummy gate lines 3266. A trench contact material 3297 is located between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264. Embedded source or drain structures 3268 are located in the semiconductor fin 3262 between the active gate lines 3264 and between the dummy gate lines 3266 and the active gate lines 3264.

[0242] The active gate lines 3264 comprise a gate dielectric structure 3272, a work-function gate electrode portion 3274, a fill gate electrode portion 3276, and a dielectric cover layer 3278. Dielectric spacers 3280 line the side walls of the active gate lines 3264 and the dummy gate lines 3266. In one embodiment, the gate dielectric structure 3272 comprises a ferroelectric or antiferroelectric polycrystalline material layer 3298. In another embodiment, the gate dielectric structure 3272 further comprises an amorphous oxide layer 3299.

[0243] In another aspect, devices of the same conductivity type, e.g., n-type or p-type, may have differentiated gate electrode stacks for the same conductivity type. However, for comparison purposes, devices of the same conductivity type may have a differentiated voltage threshold (VT) based on modulated doping.

[0244] Fig. Figure 33A illustrates cross-sectional views of a pair of NMOS devices with a differentiated voltage threshold based on modulated doping and a pair of PMOS devices with a differentiated voltage threshold based on modulated doping according to an embodiment of the present disclosure.

[0245] With reference to Fig. In embodiment 33A, a first NMOS device 3302 is located adjacent to a second NMOS device 3304 above an active semiconductor region 3300, such as a silicon fin or a silicon substrate. Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306, a first conductive gate electrode layer 3308, such as a work function layer, and a conductive gate electrode filling 3310. In one embodiment, the first conductive gate electrode layer 3308 of the first NMOS device 3302 and the second NMOS device 3304 are made of the same material and have the same thickness, and therefore exhibit the same work function. However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304.In such an embodiment, the first NMOS device 3302 is referred to as a "standard VT" device and the second NMOS device 3304 is referred to as a "high VT" device. In one embodiment, differentiated VT is achieved by using a modulated or differentiated implantation doping in areas 3312 of the first NMOS device 3302 and the second NMOS device 3304.

[0246] Again with reference to Fig. In embodiment 33A, a first PMOS device 3322 is located adjacent to a second PMOS device 3324 above an active semiconductor region 3320, such as a silicon fin or a silicon substrate. Both the first PMOS device 3322 and the second PMOS device 3324 comprise a gate dielectric layer 3326, a first conductive gate electrode layer 3328, such as a work function layer, and a conductive gate electrode filling 3330. In one embodiment, the first conductive gate electrode layer 3328 of the first PMOS device 3322 and the second PMOS device 3324 are made of the same material and have the same thickness, and therefore exhibit the same work function. However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324.In such an embodiment, the first PMOS device 3322 is referred to as a "standard VT" device and the second PMOS device 3324 is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved by using a modulated or differentiated implantation doping in areas 3332 of the first PMOS device 3322 and the second PMOS device 3324.

[0247] As opposed to Fig. 33A illustrates Fig. 33B Cross-sectional views of a pair of NMOS devices with a differentiated voltage threshold based on a differentiated gate-electrode structure and a pair of PMOS devices with a differentiated voltage threshold based on a differentiated gate-electrode structure according to another embodiment of the present disclosure.

[0248] With reference to Fig. In 33B, a first NMOS device 3352 is located adjacent to a second NMOS device 3354 above an active semiconductor region 3350, such as a silicon fin or a silicon substrate. Both the first NMOS device 3352 and the second NMOS device 3354 contain a gate dielectric layer 3356. However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. In particular, the first NMOS device 3352 includes a first conductive gate electrode layer 3358, such as a first output working layer, and a conductive gate electrode filling 3360. The second NMOS device 3354 includes a second conductive gate electrode layer 3359, such as a second output working layer, the first conductive gate electrode layer 3358, and the conductive gate electrode filling 3360.The first NMOS device 3352 has a lower VT than the second NMOS device 3354. In such an embodiment, the first NMOS device 3352 is referred to as a "standard VT" device, and the second NMOS device 3354 is referred to as a "high VT" device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices with the same conductivity type.

[0249] Again with reference to Fig. In 33B, a first PMOS device 3372 is located adjacent to a second PMOS device 3374 above an active semiconductor region 3370, such as a silicon fin or a silicon substrate. Both the first PMOS device 3372 and the second PMOS device 3374 contain a gate dielectric layer 3376. However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. In particular, the first PMOS device 3372 includes a conductive gate electrode layer 3378A with a first thickness, such as an exit working layer, and a conductive gate electrode filling 3380. The second PMOS device 3374 includes a conductive gate electrode layer 3378B with a second thickness and the conductive gate electrode filling 3380.In one embodiment, the conductive gate electrode layer 3378A and the conductive gate electrode layer 3378B have the same composition, but the thickness of the conductive gate electrode layer 3378B (second thickness) is greater than the thickness of the conductive gate electrode layer 3378A (first thickness). The first PMOS device 3372 has a higher conductivity (VT) than the second PMOS device 3374. In such an embodiment, the first PMOS device 3372 is referred to as a "standard VT" device, and the second PMOS device 3374 is referred to as a "low VT" device. In another embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices with the same conductivity type.

[0250] Again with reference to Fig. 33B comprises an integrated circuit structure according to an embodiment of the present disclosure, including a fin (e.g., a silicon fin, such as 3350). The fin is understood to have a top surface (as shown) and side walls (extending into and out of the side). A gate dielectric layer 3356 is located above the top surface of the fin and laterally adjacent to the side walls of the fin. An n-type gate electrode 3354 is located above the gate dielectric layer 3356 above the top surface of the fin and laterally adjacent to the side walls of the fin. The n-type gate electrode comprises a p-type metal layer 3359 on the gate dielectric layer 3356 and an n-type metal layer 3358 on the p-type metal layer 3359. It is understood that a first n-type source or drain region is connected to a first side of the gate electrode (e.g.,a second n-type source or drain region can be adjacent to a second side of the gate electrode (e.g., from the side), with the second side opposite the first side.

[0251] In one embodiment, the p-type metal layer 3359 comprises titanium and nitrogen, and the n-type metal layer 3358 comprises titanium, aluminum, carbon, and nitrogen. In one embodiment, the p-type metal layer 3359 has a thickness in the range of 2–12 angstroms, and in a particular embodiment, the p-type metal layer 3359 has a thickness in the range of 2–4 angstroms. In one embodiment, the n-type gate electrode further comprises a conductive filler metal layer 3360 on the n-type metal layer 3358. In such an embodiment, the conductive filler metal layer 3360 comprises tungsten. In a particular embodiment, the conductive filler metal layer 3360 comprises 95 or more atomic percent tungsten and 0.1 to 2 atomic percent fluorine.

[0252] Again with reference to Fig. 33B comprises an integrated circuit structure according to another embodiment of the present disclosure, comprising a first n-type device 3352 with a voltage threshold (VT), wherein the first n-type device 3352 has a first gate dielectric layer 3356, and a first n-type metal layer 3358 on the first gate dielectric layer 3356. Also included is a second n-type device 3354 with a voltage threshold (VT), wherein the second n-type device 3354 has a second gate dielectric layer 3356, a p-type metal layer 3359 on the second gate dielectric layer 3356, and a second n-type metal layer 3358 on the p-type metal layer 3359.

[0253] In one embodiment, the VT of the second n-type device 3354 is higher than the VT of the first n-type device 3352. In one embodiment, the first n-type metal layer 3358 and the second n-type metal layer 3358 have the same composition. In one embodiment, the first n-type metal layer 3358 and the second n-type metal layer 3358 have the same thickness. In one embodiment, the n-type metal layer 3358 comprises titanium, aluminum, carbon, and nitrogen, and the p-type metal layer 3359 comprises titanium and nitrogen.

[0254] Again with reference to Fig. 33B comprises an integrated circuit structure according to another embodiment of the present disclosure, comprising a first p-type device 3372 with a voltage threshold (VT), wherein the first p-type device 3372 has a first gate dielectric layer 3376 and a first p-type metal layer 3378A on the first gate dielectric layer 3376. The first p-type metal layer 3378A has a thickness of . A second p-type device 3374 is also included and has a voltage threshold (VT). The second p-type device 3374 has a second gate dielectric layer 3376 and a second p-type metal layer 3378B on the second gate dielectric layer 3376. The second p-type metal layer 3378B has a thickness greater than the thickness of the first p-type metal layer 3378A.

[0255] In one embodiment, the VT of the second p-type device 3374 is lower than the VT of the first p-type device 3372. In one embodiment, the first p-type metal layer 3378A and the second p-type metal layer 3378B have the same composition. In one embodiment, the first p-type metal layer 3378A and the second p-type metal layer 3378B both contain titanium and nitrogen. In one embodiment, the thickness of the first p-type metal layer 3378A is less than an exit work saturation thickness of a material of the first p-type metal layer 3378A. In one embodiment, although not shown, the second p-type metal layer 3378B includes a first metal film (e.g., from a second deposition) on a second metal film (e.g., from a first deposition), and there is a seam between the first metal film and the second metal film.

[0256] Again with reference to Fig. 33B comprises an integrated circuit structure according to another embodiment of the present disclosure, comprising a first n-type device 3352 having a first gate dielectric layer 3356 and a first n-type metal layer 3358 on the first gate dielectric layer 3356. A second n-type device 3354 has a second gate dielectric layer 3356, a first p-type metal layer 3359 on the second gate dielectric layer 3356, and a second n-type metal layer 3358 on the first p-type metal layer 3359. A first p-type device 3372 has a third gate dielectric layer 3376 and a second p-type metal layer 3378A on the third gate dielectric layer 3376. The second p-type metal layer 3378A has a thickness. A second p-type device 3374 has a fourth gate dielectric layer 3376 and a third p-type metal layer 3378B on the fourth gate dielectric layer 3376.The third p-type metal layer 3378B has a greater thickness than the thickness of the second p-type metal layer 3378A.

[0257] In one embodiment, the first n-type device 3352 has a stress threshold (VT), wherein the second n-type device 3354 has a stress threshold (VT), and the VT of the second n-type device 3354 is lower than the VT of the first n-type device 3352. In one embodiment, the first p-type device 3372 has a stress threshold (VT), wherein the second p-type device 3374 has a stress threshold (VT), and the VT of the second p-type device 3374 is lower than the VT of the first p-type device 3372. In one embodiment, the third p-type metal layer 3378B comprises a first metal film on a second metal film and a seam between the first metal film and the second metal film.

[0258] It is also understood that more than two types of VT devices for the same conductivity type can be contained in the same structure, such as on the same die. A first example illustrates this. Fig. 34A Cross-sectional views of a group of three NMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure and on a modulated doping and a group of three PMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure and on a modulated doping according to an embodiment of the present disclosure.

[0259] With reference to Fig. In 34A, a first NMOS device 3402 is located adjacent to a second NMOS device 3404 and a third NMOS device 3403 above an active semiconductor region 3400, such as a silicon fin or a silicon substrate. The first NMOS device 3402, the second NMOS device 3404, and the third NMOS device 3403 each contain a gate dielectric layer 3406. The first NMOS device 3402 and the third NMOS device 3403 have structurally identical or similar gate electrode stacks. However, the second NMOS device 3404 has a structurally different gate electrode stack than the first NMOS device 3402 and the third NMOS device 3403. In particular, the first NMOS device 3402 and the third NMOS device 3403 include a first conductive gate electrode layer 3408, such as a first exit working layer, and a conductive gate electrode filling 3410.The second NMOS device 3404 includes a second conductive gate electrode layer 3409, such as a second output work function, the first conductive gate electrode layer 3408, and the conductive gate electrode filling 3410. The first NMOS device 3402 has a lower conductivity (VT) than the second NMOS device 3404. In such an embodiment, the first NMOS device 3402 is referred to as a "standard VT" device, and the second NMOS device 3404 is referred to as a "high VT" device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices with the same conductivity type.In one embodiment, the third NMOS device 3403 has a VT different from the VT of the first NMOS device 3402 and the second NMOS device 3404, although the gate electrode structure of the third NMOS device 3403 is the same as the gate electrode structure of the first NMOS device 3402. In another embodiment, the VT of the third NMOS device 3403 lies between the VT of the first NMOS device 3402 and the second NMOS device 3404. In yet another embodiment, the differentiated VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved by using a modulated or differentiated implantation doping at a region 3412 of the third NMOS device 3403. In such an embodiment, the third n-type device 3403 has a channel area with a dopant concentration different from a dopant concentration of a channel area of ​​the first n-type device 3402.

[0260] Again with reference to Fig. In 34A, a first PMOS device 3422 is located adjacent to a second PMOS device 3424 and a third PMOS device 3423 above an active semiconductor region 3420, such as a silicon fin or a silicon substrate. The first PMOS device 3422, the second PMOS device 3424, and the third PMOS device 3423 each contain a gate dielectric layer 3426. The first PMOS device 3422 and the third PMOS device 3423 have structurally identical or similar gate electrode stacks. However, the second PMOS device 3424 has a structurally different gate electrode stack than the first PMOS device 3422 and the third PMOS device 3423. In particular, the first PMOS device 3422 and the third PMOS device 3423 include a conductive gate electrode layer 3428A with a first thickness, such as an exit working layer, and a conductive gate electrode filling 3430.The second PMOS device 3424 comprises a conductive gate electrode layer 3428B with a second thickness and the conductive gate electrode filling 3430. In one embodiment, the conductive gate electrode layer 3428A and the conductive gate electrode layer 3428B have the same composition, but the thickness of the conductive gate electrode layer 3428B (second thickness) is greater than the thickness of the conductive gate electrode layer 3428A (first thickness). In another embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424. In such an embodiment, the first PMOS device 3422 is referred to as a "standard-VT" device, and the second PMOS device 3424 is referred to as a "low-VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices with the same conductivity type.In one embodiment, the third PMOS device 3423 has a VT different from the VT of the first PMOS device 3422 and the second PMOS device 3424, although the gate electrode structure of the third PMOS device 3423 is the same as the gate electrode structure of the first PMOS device 3422. In another embodiment, the VT of the third PMOS device 3423 lies between the VT of the first PMOS device 3422 and the second PMOS device 3424. In yet another embodiment, the differentiated VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved by using a modulated or differentiated implantation doping at a region 3432 of the third PMOS device 3423. In such an embodiment, the third p-type device 3423 has a channel region with a dopant concentration different from a dopant concentration of a channel region of the first p-type device 3422.

[0261] A second example illustrates Fig. 34B Cross-sectional views of a group of three NMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure and on a modulated doping and a group of three PMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure and on a modulated doping according to another embodiment of the present disclosure.

[0262] With reference to Fig. In 34B, a first NMOS device 3452 is located adjacent to a second NMOS device 3454 and a third NMOS device 3453 above an active semiconductor region 3450, such as a silicon fin or a silicon substrate. The first NMOS device 3452, the second NMOS device 3454, and the third NMOS device 3453 each contain a gate dielectric layer 3456. The second NMOS device 3454 and the third NMOS device 3453 have structurally identical or similar gate electrode stacks. However, the first NMOS device 3452 has a structurally different gate electrode stack than the second NMOS device 3454 and the third NMOS device 3453. In particular, the first NMOS device 3452 includes a first conductive gate electrode layer 3458, such as a first exit working layer, and a conductive gate electrode filling 3460.The second NMOS device 3454 and the third NMOS device 3453 include a second conductive gate electrode layer 3459, such as a second work function, the first conductive gate electrode layer 3458, and the conductive gate electrode filling 3460. The first NMOS device 3452 has a lower conductivity (VT) than the second NMOS device 3454. In such an embodiment, the first NMOS device 3452 is referred to as a "standard VT" device, and the second NMOS device 3454 is referred to as a "high VT" device. In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices with the same conductivity type.In one embodiment, the third NMOS device 3453 has a VT different from the VT of the first NMOS device 3452 and the second NMOS device 3454, although the gate electrode structure of the third NMOS device 3453 is the same as the gate electrode structure of the second NMOS device 3454. In another embodiment, the VT of the third NMOS device 3453 lies between the VT of the first NMOS device 3452 and the second NMOS device 3454. In yet another embodiment, the differentiated VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved by using a modulated or differentiated implantation doping at a region 3462 of the third NMOS device 3453.In such an embodiment, the third n-type device 3453 has a channel area with a dopant concentration different from a dopant concentration of a channel area of ​​the second n-type device 3454.

[0263] Again with reference to Fig. In 34B, a first PMOS device 3472 is located adjacent to a second PMOS device 3474 and a third PMOS device 3473 above an active semiconductor region 3470, such as a silicon fin or a silicon substrate. The first PMOS device 3472, the second PMOS device 3474, and the third PMOS device 3473 each contain a gate dielectric layer 3476. The second PMOS device 3474 and the third PMOS device 3473 have structurally identical or similar gate electrode stacks. However, the first PMOS device 3472 has a structurally different gate electrode stack than the second PMOS device 3474 and the third PMOS device 3473. In particular, the first PMOS device 3472 includes a conductive gate electrode layer 3478A with a first thickness, such as an exit working layer, and a conductive gate electrode filling 3480.The second PMOS device 3474 and the third PMOS device 3473 comprise a conductive gate electrode layer 3478B with a second thickness and the conductive gate electrode filling 3480. In one embodiment, the conductive gate electrode layer 3478A and the conductive gate electrode layer 3478B have the same composition, but the thickness of the conductive gate electrode layer 3478B (second thickness) is greater than the thickness of the conductive gate electrode layer 3478A (first thickness). In another embodiment, the first PMOS device 3472 has a higher VT than the second PMOS device 3474. In such an embodiment, the first PMOS device 3472 is referred to as a "standard VT" device and the second PMOS device 3474 is referred to as a "low VT" device.In one embodiment, the differentiated VT is achieved by using differentiated gate stacks for devices with the same conductivity type. In one embodiment, the third PMOS device 3473 has a VT different from the VT of the first PMOS device 3472 and the second PMOS device 3474, although the gate electrode structure of the third PMOS device 3473 is the same as the gate electrode structure of the second PMOS device 3474. In one embodiment, the VT of the third PMOS device 3473 lies between the VT of the first PMOS device 3472 and the second PMOS device 3474. In another embodiment, the differentiated VT between the third PMOS device 3473 and the first PMOS device 3472 is achieved by using a modulated or differentiated implantation doping at a region 3482 of the third PMOS device 3473.In such an embodiment, the third p-type device 3473 has a channel region with a dopant concentration different from a dopant concentration of a channel region of the second p-type device 3474.

[0264] Fig. Figures 35A-35D illustrate cross-sectional views of various processes in a method for manufacturing NMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure according to another embodiment of the present disclosure.

[0265] With reference to Fig. Figure 35A, in which a "Standard-VT-NMOS" region (STD-VT-NMOS) and a "High-VT-NMOS" region (HOHE-VT-NMOS) are shown branched on a common substrate, includes a method for fabricating an integrated circuit structure by forming a gate dielectric layer 3506 over a first semiconductor fin 3502 and over a second semiconductor fin 3504, such as over a first and second silicon fin. A p-type metal layer 3508 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and over the second semiconductor fin 3504.

[0266] With reference to Fig. 35B a part of the p-type metal layer 3508 is removed from the gate dielectric layer 3506 above the first semiconductor fin 3502, but a part 3509 of the p-type metal layer 3508 is retained on the gate dielectric layer 3506 above the second semiconductor fin 3504.

[0267] With reference to Fig. In 35C, an n-type metal layer 3510 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and on part 3509 of the p-type metal layer on the gate dielectric layer 3506 over the second semiconductor fin 3504. In one embodiment, subsequent processing includes forming a first n-type device with a voltage threshold (VT) over the first semiconductor fin 3502 and forming a second n-type device with a voltage threshold (VT) over the second semiconductor fin 3504, wherein the VT of the second n-type device is higher than the VT of the first n-type device.

[0268] With reference to Fig. In one embodiment of 35D, a conductive filler metal layer 3512 is formed on the n-type metal layer 3510. In such an embodiment, the formation of the conductive filler metal layer 3512 involves forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor.

[0269] Fig. Figures 36A-36D illustrate cross-sectional views of various processes in a method for manufacturing PMOS devices with a differentiated voltage threshold based on a differentiated gate electrode structure according to another embodiment of the present disclosure.

[0270] With reference to Fig. Figure 36A, in which a "standard-VT-PMOS" region (STD-VT-PMOS) and a "low-VT-PMOS" region (LOW-VT-PMOS) are shown branched on a common substrate, includes a method for fabricating an integrated circuit structure by forming a gate dielectric layer 3606 over a first semiconductor fin 3602 and over a second semiconductor fin 3604, such as over a first and second silicon fin. A first p-type metal layer 3608 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 and over the second semiconductor fin 3604.

[0271] With reference to Fig. 36B a part of the first p-type metal layer 3608 is removed from the gate dielectric layer 3606 above the first semiconductor fin 3602, but a part 3609 of the first p-type metal layer 3608 is retained on the gate dielectric layer 3606 above the second semiconductor fin 3604.

[0272] With reference to Fig. In 36C, a second p-type metal layer 3610 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 and on part 3609 of the first p-type metal layer on the gate dielectric layer 3606 over the second semiconductor fin 3604. In one embodiment, subsequent processing includes forming a first p-type device with a voltage threshold (VT) over the first semiconductor fin 3602 and forming a second p-type device with a voltage threshold (VT) over the second semiconductor fin 3604, wherein the VT of the second p-type device is lower than the VT of the first p-type device.

[0273] In one embodiment, the first p-type metal layer 3608 and the second p-type metal layer 3610 have the same composition. In another embodiment, the first p-type metal layer 3608 and the second p-type metal layer 3610 have the same thickness. In another embodiment, the first p-type metal layer 3608 and the second p-type metal layer 3610 have the same thickness and the same composition. In another embodiment, a seam 3611 is located between the first p-type metal layer 3608 and the second p-type metal layer 3610, as shown.

[0274] With reference to Fig. In one embodiment, a conductive filler metal layer 3612 is formed over the p-type metal layer 3610. In such an embodiment, the formation of the conductive filler metal layer 3612 involves forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor. In another embodiment, an n-type metal layer 3614 is formed on the p-type metal layer 3610 prior to the formation of the conductive filler metal layer 3612, as shown. In such an embodiment, the n-type metal layer 3614 is an artifact of a double-metal-gate replacement processing scheme.

[0275] Another aspect describes metal-gate structures for CMOS semiconductor devices (CMOS: Complementary Metal Oxide Semiconductor). An example illustrates this. Fig. 37 a cross-sectional view of an integrated circuit structure with a p / n junction according to an embodiment of the present disclosure.

[0276] With reference to Fig. 37 comprises an integrated circuit structure 3700 and a semiconductor substrate 3702, which has an n-well region 3704 with a first semiconductor fin 3706 extending from it and a p-well region 3708 with a second semiconductor fin 3710 extending from it. The first semiconductor fin 3706 is spaced apart from the second semiconductor fin 3710. The n-well region 3704 is directly adjacent to the p-well region 3708 in the semiconductor substrate 3702. A trench isolation structure 3712 is located on the semiconductor substrate 3702 outside of and between the first 3706 and second 3710 semiconductor fins. The first 3706 and second 3710 semiconductor fins extend above the trench isolation structure 3712.

[0277] A gate dielectric layer 3714 is located on the first 3706 and second 3710 semiconductor fins and on the trench insulation structure 3712. The gate dielectric layer 3714 is continuous between the first 3706 and second 3710 semiconductor fins. A conductive layer 3716 is located above the gate dielectric layer 3714 over the first semiconductor fin 3706, but not over the second semiconductor fin 3710. In one embodiment, the conductive layer 3716 includes titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is located above the conductive layer 3716 above the first semiconductor fin 3706, but not above the second semiconductor fin 3710. The p-type metal gate layer 3718 is further located on part of, but not all of, the trench insulation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710.An n-type metal gate layer 3720 is located above the second semiconductor fin 3710, above the trench insulation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and above the p-type metal gate layer 3718.

[0278] In one embodiment, an interlayer dielectric (ILD) layer 3722 is located above the trench insulation structure 3712 on the outer surfaces of the first semiconductor fin 3706 and the second semiconductor fin 3710. The ILD layer 3722 has an opening 3724, the opening 3724 exposing the first 3706 and second 3710 semiconductor fins. In such an embodiment, the conductive layer 3716, the p-type metal gate layer 3718, and the n-type metal gate layer 3720 are further formed along a side wall 3726 of the opening 3724, as shown. In a particular embodiment, the conductive layer 3716 has an upper surface 3717 along the side wall 3726 of the opening 3724 below an upper surface 3719 of the p-type metal gate layer 3718 and an upper surface 3721 of the n-type metal gate layer 3720 along the side wall 3726 of the opening 3724, as shown.

[0279] In one embodiment, the p-type metal gate layer 3718 comprises titanium and nitrogen. In another embodiment, the n-type metal gate layer 3720 comprises titanium and aluminum. In another embodiment, a conductive filler metal layer 3730 is located above the n-type metal gate layer 3720, as shown. In such an embodiment, the conductive filler metal layer 3730 comprises tungsten. In a particular embodiment, the conductive filler metal layer 3730 comprises 95 or more atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 has a layer including hafnium and oxygen. In another embodiment, a thermal or chemical oxide layer 3732 is located between the upper portions of the first 3706 and second 3710 semiconductor fins, as shown. In another embodiment, the semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

[0280] Now, referring only to the right side... Fig. 37 comprises an integrated circuit structure according to one embodiment of the present disclosure, comprising a semiconductor substrate 3702 including an n-well region 3704 with a semiconductor fin 3706 projecting from it. A trench insulation structure 3712 is located on the semiconductor substrate 3702 around the semiconductor fin 3706. The semiconductor fin 3706 extends above the trench insulation structure 3712. A gate dielectric layer 3714 is located above the semiconductor fin 3706. A conductive layer 3716 is located above the gate dielectric layer 3714 above the semiconductor fin 3706. In one embodiment, the conductive layer 3716 comprises titanium, nitrogen, and oxygen. A p-type metal gate layer 3718 is located above the conductive layer 3716 above the semiconductor fin 3706.

[0281] In one embodiment, an interlayer dielectric (ILD) layer 3722 is located above the trench insulation structure 3712. The ILD layer has an opening, the opening exposing the semiconductor fin 3706. The conductive layer 3716 and the p-type metal gate layer 3718 are further formed along a side wall of the opening. In such an embodiment, the conductive layer 3716 has an upper surface along the side wall of the opening below an upper surface of the p-type metal gate layer 3718 along the side wall of the opening. In one embodiment, the p-type metal gate layer 3718 is located on top of the conductive layer 3716. In one embodiment, the p-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, a conductive filler metal layer 3730 is located above the p-type metal gate layer 3718.In one such embodiment, the conductive filler metal layer 3730 comprises tungsten. In a particular embodiment, the conductive filler metal layer 3730 consists of 95 or more atomic percent tungsten and 0.1 to 2 atomic percent fluorine. In one embodiment, the gate dielectric layer 3714 comprises a layer containing hafnium and oxygen.

[0282] Fig. Figures 38A-38H illustrate cross-sectional views of various processes in a method for manufacturing an integrated circuit structure using a double-metal-gate-replacement-gate process flow according to an embodiment of the present disclosure.

[0283] With reference to Fig. Figure 38A, which shows an NMOS (n-type) region and a PMOS (p-type) region, includes a method for fabricating an integrated circuit structure by forming an interlayer dielectric (ILD) layer 3802 above a first 3804 and second 3806 semiconductor fin above a substrate 3800. An opening 3808 is formed in the ILD layer 3802, the opening 3808 exposing the first 3804 and second 3806 semiconductor fin. In one embodiment, the opening 3808 is initially formed in place of the first 3804 and second 3806 semiconductor fin by removing a gate placeholder or dummy gate structure.

[0284] A gate dielectric layer 3810 is formed in the opening 3808 and over the first 3804 and second 3806 semiconductor fins, and on part of a trench insulation structure 3812 between the first 3804 and second 3806 semiconductor fins. In one embodiment, the gate dielectric layer 3810 is formed on a thermal or chemical oxide layer 3811, such as a silicon oxide or silicon dioxide layer, formed on the first 3804 and second 3806 semiconductor fins, as shown. In another embodiment, the gate dielectric layer 3810 is formed directly on the first 3804 and second 3806 semiconductor fins.

[0285] A conductive layer 3814 is formed over the gate dielectric layer 3810, which is formed over the first 3804 and second 3806 semiconductor fins. In one embodiment, the conductive layer 3814 comprises titanium, nitrogen, and oxygen. A p-type metal gate layer 3816 is formed over the conductive layer 3814, which is formed over the first 3804 and second 3806 semiconductor fins.

[0286] With reference to Fig. In 38B, a dielectric etch stop layer 3818 is formed on the p-type metal gate layer 3816. In one embodiment, the dielectric etch stop layer 3818 comprises a first layer of silicon oxide (e.g., SiO2), a layer of aluminum oxide (e.g., Al2O3) on the first silicon oxide layer, and a second silicon oxide layer (e.g., SiO2) on the aluminum oxide layer.

[0287] With reference to Fig. 38C will have a mask 3820 over the structure made of Fig. 38B was formed. Mask 3820 covers the PMOS region and exposes the NMOS region.

[0288] With reference to Fig. In embodiment 38D, the dielectric etch stop layer 3818, the p-type metal gate layer 3816, and the conductive layer 3814 are structured to provide a structured dielectric etch stop layer 3819, a structured p-type metal gate layer 3817 over a structured conductive layer 3815 over the first semiconductor fin 3804, but not over the second semiconductor fin 3806. In one embodiment, the conductive layer 3814 protects the second semiconductor fin 3806 during structuring.

[0289] With reference to Fig. 38E will be the mask 3820 from the structure Fig. 38D removed. With reference to Fig. 3F will be the dielectric etch stop layer 3819 from the structure Fig. 3E away.

[0290] With reference to Fig. In 38G, an n-type metal gate layer 3822 is formed over the second semiconductor fin 3806, over the portion of the trench insulation structure 3812 between the first 3804 and second semiconductor fin 3806, and over the structured p-type metal gate layer 3817. In one embodiment, the structured conductive layer 3815, the structured p-type metal gate layer 3817, and the n-type metal gate layer 3822 are further formed along a side wall 3824 of the opening 3808. In such an embodiment, the structured conductive layer 3815 has an upper surface along the side wall 3824 of the opening 3808 below an upper surface of the structured p-type metal gate layer 3817 and an upper surface of the n-type metal gate layer 3822 along the side wall 3824 of the opening 3808.

[0291] With reference to Fig. In 38H, a conductive filler metal layer 3826 is formed over the n-type metal gate layer 3822. In one embodiment, the conductive filler metal layer 3826 is formed by depositing a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF6) precursor.

[0292] Another aspect describes double silicide structures for complementary metal-oxide-semiconductor (CMOS) semiconductor devices. An exemplary process flow is illustrated. Fig. 39A-39H Cross-sectional views representing various operations in a method for manufacturing a double silicide-based integrated circuit according to an embodiment of the present disclosure.

[0293] With reference to Fig. Figure 39A, in which an NMOS region and a PMOS region are shown branched on a common substrate, includes a method for fabricating an integrated circuit structure by forming a first gate structure 3902, which may include dielectric sidewall spacers 3903, over a first fin 3904, such as a first silicon fin. A second gate structure 3952, which may include dielectric sidewall spacers 3953, is formed over a second fin 3954, such as a second silicon fin. An insulating material 3906 is formed adjacent to the first gate structure 3902 over the first fin 3904 and adjacent to the second gate structure 3952 over the second fin 3954. In one embodiment, the insulating material 3906 is a sacrificial material and is used as a mask in a double silicide process.

[0294] With reference to Fig. 39B, a first portion of the insulating material 3906 is removed from above the first fin 3904, but not from above the second fin 3954, to expose a first 3908 and second 3910 source or drain region of the first fin 3904 adjacent to the first gate structure 3902. In one embodiment, the first 3908 and second 3910 source or drain region are epitaxial regions formed within recessed portions of the first fin 3904, as shown. In such an embodiment, the first 3908 and second 3910 source or drain region include silicon and germanium.

[0295] With reference to Fig. In 39C, a first metal silicide layer 3912 is formed on the first 3908 and second 3910 source or drain region of the first fin 3904. In one embodiment, the first metal silicide layer 3912 is formed by depositing a layer including nickel and platinum onto the structure made of Fig. 39B, Tempering of the layer including nickel and platinum and removal of unreacted parts of the layer including nickel and platinum formed.

[0296] With reference to Fig. Following the formation of the first metal silicide layer 3912, a second portion of the insulating material 3906 is removed from above the second fin 3954 to expose a third 3958 and fourth 3960 source or drain region of the second fin 3954 adjacent to the second gate structure 3952. In one embodiment, the second 3958 and third 3960 source or drain regions are formed within the second fin 3954, such as within a second silicon fin, as shown. In another embodiment, however, the third 3958 and fourth 3960 source or drain regions are epitaxial regions formed within recessed portions of the second fin 3954. In such an embodiment, the third 3958 and fourth 3960 source or drain regions include silicon.

[0297] With reference to Fig. 39E will apply a first metal layer 3914 to the structure made of Fig. 39D, i.e., on the first 3908, second 3910, third 3958, and fourth 3960 source or drain region. A second metal silicide layer 3962 is then formed on the third 3958 and fourth 3960 source or drain region of the second fin 3954. The second metal silicide layer 3962 is formed from the first metal layer 3914, e.g., using a tempering process. In one embodiment, the second metal silicide layer 3962 differs in composition from the first metal silicide layer 3912. In one embodiment, the first metal layer 3914 is or includes a titanium layer. In one embodiment, the first metal layer 3914 is a conformal metal layer, e.g., conformal to the open trenches of Fig. 39D, formed as shown.

[0298] With reference to Fig. 39F the first metal layer 3914 is reset to form a U-shaped metal layer 3916 above both the first 3908, second 3910, third 3958 and fourth 3960 source or drain region.

[0299] With reference to Fig. In one embodiment, 39G, a second metal layer 3918 is applied to the U-shaped metal layer 3916 of the structure. Fig. 39F formed. In one embodiment, the second metal layer 3918 differs in composition from the U-shaped metal layer 3916.

[0300] With reference to Fig. In one embodiment, a third metal layer 3920 is added to the second metal layer 3918 of the structure. Fig. 39G formed. In one embodiment, the third metal layer 3920 has the same composition as the U-shaped metal layer 3916.

[0301] Again with reference to Fig. 3H comprises an integrated circuit structure 3900 according to an embodiment of the present disclosure, comprising a p-type semiconductor device (PMOS) above a substrate. The p-type semiconductor device includes a first fin 3904, such as a first silicon fin. It is understood that the first fin has a top surface (shown as 3904A) and side walls (e.g., extending into and out of the side). A first gate electrode 3902 comprises a first gate dielectric layer over the top surface 3904A of the first fin 3904 and laterally adjacent to the side walls of the first fin 3904. The first gate electrode 3902 has a first side 3902A and a second side 3902B facing the first side 3902A.

[0302] The first 3908 and second 3910 semiconductor source or drain regions are adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902, respectively. The first 3930 and second 3932 trench contact structures are located above the first 3908 and second 3910 semiconductor source or drain regions, adjacent to the first 3902A and second 3902B sides of the first gate electrode 3902, respectively. A first metal silicide layer 3912 is located directly between the first 3930 and second 3932 trench contact structures and the first 3908 and second 3910 semiconductor source or drain regions, respectively.

[0303] The integrated circuit structure 3900 includes an n-type semiconductor device (NMOS) above the substrate. The n-type semiconductor device includes a second fin 3954, such as a second silicon fin. It is understood that the second fin has a top surface (shown as 3954A) and side walls (e.g., extending into and out of the side). A second gate electrode 3952 includes a second gate dielectric layer over the top surface 3954A of the second fin 3954 and laterally adjacent to the side walls of the second fin 3954. The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite the first side 3952A.

[0304] The third 3958 and fourth 3960 semiconductor source or drain regions are adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952, respectively. The third 3970 and fourth 3972 trench contact structures are located above the third 3958 and fourth 3960 semiconductor source or drain regions, adjacent to the first 3952A and second 3952B sides of the second gate electrode 3952, respectively. A second metal silicide layer 3962 is located directly between the third 3970 and fourth 3972 trench contact structures and the third 3958 and fourth 3960 semiconductor source or drain regions. In one embodiment, the first metal silicide layer 3912 includes at least one metal species that is not contained in the second metal silicide layer 3962.

[0305] In one embodiment, the second metal silicide layer 3962 comprises titanium and silicon. The first metal silicide layer 3912 comprises nickel, platinum, and silicon. In another embodiment, the first metal silicide layer 3912 further comprises germanium. In yet another embodiment, the first metal silicide layer 3912 further comprises titanium, for example, as incorporated into the first metal silicide layer 3912 during the subsequent formation of the second metal silicide layer 3962 with the first metal layer 3914. In such an embodiment, a silicide layer already formed on a PMOS source or drain region is further modified by an annealing process used to form a silicide region on an NMOS source or drain region. This can result in a silicide layer on the PMOS source or drain region containing a fractional percentage of all silicifying metals.However, in other embodiments, such as a silicide layer already formed on a PMOS source or drain region, a annealing process used to form a silicide region on an NMOS source or drain region does not change or significantly alter the properties.

[0306] In one embodiment, the first 3908 and second 3910 semiconductor source or drain regions are first and second embedded semiconductor source or drain regions including silicon and germanium. In such an embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are third and fourth embedded semiconductor source or drain regions including silicon. In another embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are formed in the fin 3954 and are not epitaxially embedded regions.

[0307] In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all comprise a U-shaped metal layer 3916 and a T-shaped metal layer 3918 on and over the entirety of the U-shaped metal layer 3916. In one embodiment, the U-shaped metal layer 3916 comprises titanium, and the T-shaped metal layer 3918 comprises cobalt. In one embodiment, the first 3930, second 3932, third 3970, and fourth 3972 trench contact structures all further comprise a third metal layer 3920 on the T-shaped metal layer 3918. In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition. In a particular embodiment, the third metal layer 3920 and the U-shaped metal layer comprise titanium, and the T-shaped metal layer 3918 comprises cobalt.

[0308] Another aspect describes trench contact structures, e.g., for source or drain areas. An example illustrates this. Fig. 40A a cross-sectional view of an integrated circuit structure with trench contacts for an NMOS device according to an embodiment of the present disclosure. Fig. Figure 40B illustrates a cross-sectional view of an integrated circuit structure with trench contacts for a PMOS device according to another embodiment of the present disclosure.

[0309] With reference to Fig. 40A comprises an integrated circuit structure 4000 and a fin 4002, such as a silicon fin. A gate dielectric layer 4004 is located over the fin 4002. A gate electrode 4006 is located over the gate dielectric layer 4004. In one embodiment, the gate electrode 4006 comprises a conformal conductive layer 4008 and a conductive filling 4010. In another embodiment, a dielectric cap 4012 is located over the gate electrode 4006 and over the gate dielectric layer 4004. The gate electrode has a first side 4006A and a second side 4006B opposite the first side 4006A. Dielectric spacers 4013 are located along the side walls of the gate electrodes 4006.In one embodiment, the gate dielectric layer 4004 is further located between a first of the dielectric spacers 4013 and the first side 4006A of the gate electrode 4006, and between a second of the dielectric spacers 4013 and the second side 4006B of the gate electrode 4006, as shown. In another embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is located between the fin 4002 and the gate dielectric layer 4004.

[0310] The first 4014 and second 4016 semiconductor source or drain region are adjacent to the first 4006A and second 4006B sides of the gate electrode 4006, respectively. In one embodiment, the first 4014 and second 4016 semiconductor source or drain region are located in the fin 4002, as shown. However, in another embodiment, the first 4014 and second 4016 semiconductor source or drain region are located in the fin 4002, as shown. or -drain area embedded epitaxial areas formed in depressions of fin 4002.

[0311] The first 4018 and second 4020 trench contact structures are located above the first 4014 and second 4016 semiconductor source or drain regions adjacent to the first 4006A and second 4006B sides of the gate electrode 4006, respectively. Both the first 4018 and second 4020 trench contact structures comprise a U-shaped metal layer 4022 and a T-shaped metal layer 4024 on and above the entirety of the U-shaped metal layer 4022. In one embodiment, the composition of the U-shaped metal layer 4022 and the T-shaped metal layer 4024 differs. In such an embodiment, the U-shaped metal layer 4022 comprises titanium, and the T-shaped metal layer 4024 comprises cobalt. In one embodiment, the first 4018 and second 4020 trench contact structure both further include a third metal layer 4026 on the T-shaped metal layer 4024.In such an embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 have the same composition. In a particular embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 contain titanium, and the T-shaped metal layer 4024 contains cobalt.

[0312] A first trench contact via 4028 is electrically connected to the first trench contact 4018. In a particular embodiment, the first trench contact via 4028 is located on and coupled to the third metal layer 4026 of the first trench contact 4018. The first trench contact via 4028 is further located above and in contact with a portion of one of the dielectric spacers 4013 and above and in contact with a portion of the dielectric cap 4012. A second trench contact via 4030 is electrically connected to the second trench contact 4020. In a particular embodiment, the second trench contact via 4030 is located on and coupled to the third metal layer 4026 of the second trench contact 4020. The second trench contact via 4030 is further located above and in contact with a part of another of the dielectric spacers 4013 and above and in contact with another part of the dielectric cap 4012.

[0313] In one embodiment, a metal silicide layer 4032 is located directly between the first 4018 and second 4020 trench contact structure and the first 4014 and second 4016 semiconductor source and drain regions, respectively. In one embodiment, the metal silicide layer 4032 comprises titanium and silicon. In a particular embodiment, the first 4014 and second 4016 semiconductor source or drain regions are first and second n-type semiconductor source or drain regions.

[0314] With reference to Fig. 40B includes an integrated circuit structure 4050 and a fin 4052, such as a silicon fin. A gate dielectric layer 4054 is located over the fin 4052. A gate electrode 4056 is located over the gate dielectric layer 4054. In one embodiment, the gate electrode 4056 includes a conformal conductive layer 4058 and a conductive filling 4060. In another embodiment, a dielectric cap 4062 is located over the gate electrode 4056 and over the gate dielectric layer 4054. The gate electrode has a first side 4056A and a second side 4056B opposite the first side 4056A. Dielectric spacers 4063 are located along the side walls of the gate electrodes 4056.In one embodiment, the gate dielectric layer 4054 is further located between a first of the dielectric spacers 4063 and the first side 4056A of the gate electrode 4056, and between a second of the dielectric spacers 4063 and the second side 4056B of the gate electrode 4056, as shown. In another embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is located between the fin 4052 and the gate dielectric layer 4054.

[0315] The first 4064 and second 4066 semiconductor source or drain regions are adjacent to the first 4056A and second 4056B sides of the gate electrode 4056, respectively. In one embodiment, the first 4064 and second 4066 semiconductor source or drain regions are embedded epitaxial regions formed in recesses 4065 and 4067 of the fin 4052, respectively, as shown. However, in another embodiment, the first 4064 and second 4066 semiconductor source or drain regions are located within the fin 4052.

[0316] The first 4068 and second 4070 trench contact structures are located above the first 4064 and second 4066 semiconductor source or drain regions adjacent to the first 4056A and second 4056B sides of the gate electrode 4056, respectively. Both the first 4068 and second 4070 trench contact structures comprise a U-shaped metal layer 4072 and a T-shaped metal layer 4074 on and above the entirety of the U-shaped metal layer 4072. In one embodiment, the composition of the U-shaped metal layer 4072 and the T-shaped metal layer 4074 differs. In such an embodiment, the U-shaped metal layer 4072 comprises titanium, and the T-shaped metal layer 4074 comprises cobalt. In one embodiment, the first 4068 and second 4070 trench contact structure both further include a third metal layer 4076 on the T-shaped metal layer 4074.In such an embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 have the same composition. In a particular embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 contain titanium, and the T-shaped metal layer 4074 contains cobalt.

[0317] A first trench contact via 4078 is electrically connected to the first trench contact 4068. In a particular embodiment, the first trench contact via 4078 is located on and coupled to the third metal layer 4076 of the first trench contact 4068. The first trench contact via 4078 is furthermore located above and in contact with a portion of one of the dielectric spacers 4063 and above and in contact with a portion of the dielectric cap 4062. A second trench contact via 4080 is electrically connected to the second trench contact 4070. In a particular embodiment, the second trench contact via 4080 is located on and coupled to the third metal layer 4076 of the second trench contact 4070. The second trench contact via 4080 is further located above and in contact with a part of another of the dielectric spacers 4063 and above and in contact with another part of the dielectric cap 4062.

[0318] In one embodiment, a metal silicide layer 4082 is located directly between the first 4068 and second 4070 trench contact structure and the first 4064 and second 4066 semiconductor source and drain regions, respectively. In one embodiment, the metal silicide layer 4082 comprises nickel, platinum, and silicon. In a particular embodiment, the first 4064 and second 4066 semiconductor source or drain regions are first and second p-type semiconductor source or drain regions. In one embodiment, the metal silicide layer 4082 further comprises germanium. In another embodiment, the metal silicide layer 4082 further comprises titanium.

[0319] One or more embodiments described herein relate to the use of metal-chemical vapor deposition for encapsulated semiconductor contacts. Embodiments may involve or include chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, and / or thin films.

[0320] Certain embodiments may involve the fabrication of a titanium or similar metallic layer using low-temperature chemical vapor deposition (e.g., less than 500 degrees Celsius or in the 400–500 degree Celsius range) of a contact metal to provide a conformal source or drain contact. Implementing such a conformal source or drain contact can improve the performance of a three-dimensional (3D) complementary metal-oxide-semiconductor (CMOS) transistor.

[0321] To provide the necessary junction, metal-to-semiconductor contact layers can be deposited using sputtering. Sputtering is a line-of-sight process and may not be well-suited for 3D transistor fabrication. Known sputtering solutions exhibit poor or incomplete metal-semiconductor junctions on device contact surfaces at an angle to the deposition incidence.

[0322] According to one or more embodiments of the present disclosure, a low-temperature chemical vapor deposition process is implemented for the fabrication of a contact metal to provide three-dimensional conformity and maximize the metal-semiconductor junction contact area. The resulting larger contact area can reduce the junction resistance. Embodiments may involve deposition on semiconductor surfaces with a non-flat topography, wherein the topography of a surface refers to the surface shapes and features themselves, and a non-flat topography includes surface shapes and features, or parts of surface shapes and features, that are not flat, i.e., surface shapes and features that are not completely flat.

[0323] The embodiments described here may include the fabrication of encapsulation contact structures. In one such embodiment, the use of pure metal is described, conformally deposited onto the transistor source-drain contacts by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or plasma-enhanced atomic layer deposition. Such conformal deposition can be used to increase the available area of ​​the metal-semiconductor contact and reduce the resistance, thereby improving the performance of the transistor device. In one embodiment, the relatively low deposition temperature results in a minimized junction resistance per unit area.

[0324] It is understood that a variety of integrated circuit structures can be fabricated using an integration scheme involving a metallic layer deposition process as described herein. According to one embodiment of the present disclosure, a method for fabricating an integrated circuit structure includes providing a substrate in a chemical vapor deposition (CVD) chamber with an RF source, wherein the substrate has a feature thereon. The method also includes reacting titanium tetrachloride (TiCl4) and hydrogen (H2) such that a titanium (Ti) layer is formed on the feature of the substrate.

[0325] In one embodiment, the titanium layer has an overall atomic composition comprising 98% or more titanium and 0.5–2% chlorine. In alternative embodiments, a similar process is used to form a metallic layer of high purity zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb), or vanadium (V). In one embodiment, there is relatively little variation in film thickness; for example, in one embodiment, the overall coverage is greater than 50% and is nominally 70% or greater (i.e., a thickness variation of 30% or less). In one embodiment, the thickness is measurably greater on silicon (Si) or silicon germanium (SiGe) than on other surfaces because the Si or SiGe reacts during deposition and accelerates the uptake of the Ti. In one embodiment, the film composition includes approximately 0.5% chlorine (or less than 1%) as an impurity, with essentially no other impurities observed.In one embodiment, the deposition process enables metal coating on non-line-of-sight surfaces, such as surfaces hidden from a sputter deposition line of sight. The embodiments described here can be implemented to improve transistor device control by reducing the external resistance of current driven through the source and drain contacts.

[0326] According to one embodiment of the present disclosure, the feature of the substrate is a source or drain contact trench that exposes a semiconductor source or drain structure. The titanium layer (or another high-purity metallic layer) is a conductive contact layer for the semiconductor source or drain structure. Exemplary embodiments of such an implementation are described below in association with Fig. 41A, 41B, 42, 43A-43C and 44 described.

[0327] Fig. Figure 41A illustrates a cross-sectional view of a semiconductor device with a conductive contact on a source or drain region according to an embodiment of the present disclosure.

[0328] With reference to Fig. 41A comprises a semiconductor structure 4100 and a gate structure 4102 above a substrate 4104. The gate structure 4102 includes a gate dielectric layer 4102A, a discharge layer 4102B, and a gate filling 4102C. A source region 4108 and a drain region 4110 are located on opposite sides of the gate structure 4102. Source or drain contacts 4112 are electrically connected to the source region 4108 and the drain region 4110 and are spaced from the gate structure 4102 by an interlayer dielectric layer 4114 and / or gate dielectric spacers 4116. The source region 4108 and the drain region 4110 are regions of the substrate 4104.

[0329] In one embodiment, the source or drain contacts 4112 comprise a high-purity metallic layer 4112A, as described above, and a conductive trench filler 4112B. In one embodiment, the high-purity metallic layer 4112A has a total atomic composition containing 98% or more titanium. In such an embodiment, the total atomic composition of the high-purity metallic layer 4112A includes 0.5–2% chlorine. In one embodiment, the high-purity metallic layer 4112A has a thickness variation of 30% or less. In one embodiment, the conductive trench filler 4112B consists of a conductive material such as, among others, Cu, Al, W, or alloys thereof.

[0330] Fig. Figure 41B illustrates a cross-sectional view of another semiconductor device with a conductive element on a raised source or drain area according to an embodiment of the present disclosure.

[0331] With reference to Fig. 41B comprises a semiconductor structure 4150 and a gate structure 4152 above a substrate 4154. The gate structure 4152 includes a gate dielectric layer 4152A, a work surface layer 4152B, and a gate filling 4152C. A source region 4158 and a drain region 4160 are located on opposite sides of the gate structure 4152. Source or drain contacts 4162 are electrically connected to the source region 4158 and the drain region 4160 and are spaced from the gate structure 4152 by an interlayer dielectric layer 4164 and / or gate dielectric spacers 4166. The source region 4158 and the drain region 4160 are epitaxial or embedded material regions formed in etched areas of the substrate 4154. As shown, in one embodiment, the source region 4158 and the drain region 4160 form a raised source and drain region.In a particular embodiment of this type, the elevated source and drain region is an elevated silicon source and drain region or an elevated silicon germanium source and drain region.

[0332] In one embodiment, the source or drain contacts 4162 comprise a high-purity metallic layer 4162A, as described above, and a conductive trench filler 4162B. In one embodiment, the high-purity metallic layer 4162A has a total atomic composition containing 98% or more titanium. In such an embodiment, the total atomic composition of the high-purity metallic layer 4162A includes 0.5–2% chlorine. In one embodiment, the high-purity metallic layer 4162A has a thickness variation of 30% or less. In one embodiment, the conductive trench filler 4162B consists of a conductive material such as, among others, copper, aluminum, tungsten, or alloys thereof.

[0333] Accordingly, in one embodiment, with common reference to Fig. 41A and Fig. 41B, an integrated circuit structure, is a feature with a surface (source or drain contact trench exposing a semiconductor source or drain structure). A metallic layer 4112A or 4162A is located on the surface of the source or drain contact trench. It is understood that contact formation processes may involve the consumption of exposed silicon or germanium or silicon-germanium material in a source or drain region. Such consumption may degrade device performance. In contrast, according to one embodiment of the present disclosure, a surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure is not eroded or consumed, or is not substantially eroded or consumed below the source or drain contact trench.In such an embodiment, the absence of consumption or erosion results from the low-temperature deposition of the high-purity metallic contact layer.

[0334] Fig. Figure 42 illustrates a top view of several gate lines over a pair of semiconductor fins according to an embodiment of the present disclosure.

[0335] With reference to Fig. 42 Several active gate lines 4204 are formed over several semiconductor fins 4200. Dummy gate lines 4206 are located at the ends of the several semiconductor fins 4200. Spacings 4208 between the gate lines 4204 / 4206 are positions where trench contacts are formed as conductive contacts to source or drain regions, such as source or drain regions 4251, 4252, 4253 and 4254.

[0336] Fig. Figures 43A-43C illustrate cross-sectional views along the a-a' axis. Fig. 42 for various operations in a method for manufacturing an integrated circuit structure according to an embodiment of the present disclosure.

[0337] With reference to Fig. 43A several active gate lines 4304 are formed over a semiconductor fin 4302 which is formed over a substrate 4300. Dummy gate lines 4306 are located at the ends of the semiconductor fin 4302. A dielectric layer 4310 is located between the active gate lines 4304, between the dummy gate lines 4306 and the active gate lines 4304, and outside the dummy gate lines 4306. Embedded source or drain structures 4308 are located in the semiconductor fin 4302 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304. The active gate lines 4304 comprise a gate dielectric layer 4312, a work-function gate electrode portion 4314, a fill gate electrode portion 4316, and a dielectric cover layer. 4318. Dielectric spacers 4320 line the side walls of the active gate lines 4304 and the dummy gate lines 4306.

[0338] With reference to Fig. 43B, the portion of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304 is removed to provide openings 4330 at positions where trench contacts are to be formed. Removing the portion of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304 may result in erosion of the embedded source or drain structures 4308, providing eroded embedded source or drain structures 4332 that may exhibit an upper saddle-shaped topography, as shown in Fig. 43B is shown.

[0339] With reference to Fig. Trench contacts 4334 are formed in openings 4330 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304. Each of the trench contacts 4334 can include a metallic contact layer 4336 and a conductive filler material 4338.

[0340] Fig. Figure 44 illustrates a cross-sectional view along the b-b' axis. Fig. 42 for an integrated circuit structure according to an embodiment of the present disclosure.

[0341] With reference to Fig. Figure 44 shows fins 4402 above a substrate 4404. Lower portions of the fins 4402 are surrounded by a trench insulation material 4404. Upper portions of the fins 4402 have been removed to allow the growth of embedded source and drain structures 4406. A trench contact 4408 is formed in an opening in a dielectric layer 4410, the opening exposing the embedded source and drain structure 4406. The trench contact comprises a metallic contact layer 4412 and a conductive filler material 4414. It is understood that, according to one embodiment, the metallic contact layer 4412 extends to the top of the trench contact 4408, as shown in Figure 4402. Fig. 44. In another embodiment, however, the metallic contact layer 4412 does not extend to the top of the trench contact 4408 and is recessed within the trench contact 4408 in some way, e.g. similar to the representation of the metallic contact layer 4336 in Fig. 43C.

[0342] Accordingly, an integrated circuit structure includes, with common reference to Fig. Figures 42, 43A-43C and 44 of an embodiment of the present disclosure describe a semiconductor fin (4200, 4302, 4402) above a substrate (4300, 4400). The semiconductor fin (4200, 4302, 4402) has a top surface and side walls. A gate electrode (4204, 4304) is located above the top surface and adjacent to the side walls of a portion of the semiconductor fin (4200, 4302, 4402). The gate electrode (4204, 4304) defines a channel region in the semiconductor fin (4200, 4302, 4402). A first semiconductor source or drain structure (4251, 4332, 4406) is located at a first end of the channel region on a first side of the gate electrode (4204, 4304), wherein the first semiconductor source or drain structure (4251, 4332, 4406) has a non-flat topography.A second semiconductor source or drain structure (4252, 4332, 4406) is located at a second end of the channel region on a second side of the gate electrode (4204, 4304), with the second end opposite the first end and the second side opposite the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non-planar topography. A metallic contact material (4336, 4412) is located directly on the first semiconductor source or drain structure (4251, 4332, 4406) and directly on the second semiconductor source or drain structure (4252, 4332, 4406). The metallic contact material (4336, 4412) conforms to the non-flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and conforms to the non-flat topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0343] In one embodiment, the metallic contact material (4336, 4412) has an overall atomic composition that includes 95% or more of a single metal species. In another embodiment, the metallic contact material (4336, 4412) has an overall atomic composition that includes 98% or more of titanium. In a particular embodiment, the overall atomic composition of the metallic contact material (4336, 4412) further includes 0.5-2% chlorine. In another embodiment, the metallic contact material (4336, 4412) has a thickness variation of 30% or less along the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406).

[0344] In one embodiment, both the non-flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-flat topography of the second semiconductor source or drain structure (4252, 4332, 4406) include a raised central part and lower side parts, as shown, for example, in Fig. Figure 44 illustrates this. In one embodiment, both the non-flat topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-flat topography of the second semiconductor source or drain structure (4252, 4332, 4406) include saddle-shaped parts, such as those shown in Figure 44. Fig. 43C is shown.

[0345] In one embodiment, both the first semiconductor source and drain structure (4251, 4332, 4406) and the second semiconductor source and drain structure (4252, 4332, 4406) include silicon. In another embodiment, both the first semiconductor source and drain structure (4251, 4332, 4406) and the second semiconductor source and drain structure (4252, 4332, 4406) also include germanium, e.g., in the form of silicon germanium.

[0346] In one embodiment, the metallic contact material (4336, 4412) is located directly on the first semiconductor source or drain structure (4251, 4332, 4406) and furthermore along side walls of a trench in a dielectric layer (4320, 4410) above the first semiconductor source or drain structure (4251, 4332, 4406), the trench exposing a portion of the first semiconductor source or drain structure (4251, 4332, 4406). In such an embodiment, the thickness of the metallic contact material (4336) decreases along the side walls of the trench from the first semiconductor source or drain structure (4336A at 4332) to a position (4336B) above the first semiconductor source or drain structure (4332), an example of which is shown in Fig. Figure 43C illustrates this. In one embodiment, a conductive filler material (4338, 4414) is located on the metallic contact material (4336, 4412) within the trench, as shown in Figure 43C. Fig. 43C and Fig. 44 is shown.

[0347] In one embodiment, the integrated circuit structure further includes a second semiconductor fin (e.g., the upper fin 4200 made of Fig. 42, Fig. 4302, Fig. 4402) with a top surface and side walls. The gate electrode (4204, 4304) is further located above the top surface and adjacent to the side walls of a portion of the second semiconductor fin, the gate electrode defining a channel region in the second semiconductor fin. A third semiconductor source or drain structure (4253, 4332, 4406) is located at a first end of the channel region of the second semiconductor fin on the first side of the gate electrode (4204, 4304), the third semiconductor source or drain structure having a non-flat topography. A fourth semiconductor source or drain structure (4254, 4332, 4406) is located at a second end of the channel region of the second semiconductor fin on the second side of the gate electrode (4204, 4304), with the second end opposite the first end, the fourth semiconductor source or drain structure (4254, 4332, 4406) having a non-flat topography.The metallic contact material (4336, 4412) is located directly on the third semiconductor source or drain structure (4253, 4332, 4406) and directly on the fourth semiconductor source or drain structure (4254, 4332, 4406), wherein the metallic contact material (4336, 4412) conforms to the non-flat topography of the third semiconductor source or drain structure (4253, 4332, 4406) and conforms to the non-flat topography of the fourth semiconductor source or drain structure (4254, 4332, 4406). In one embodiment, the metallic contact material (4336, 4412) is continuous between the first semiconductor source and drain structure (4251, 4332, left side of 4406) and the third semiconductor source or drain structure (4253, 4332, right side of 4406) and continuously between the second semiconductor source or drain structure (4252) and the fourth semiconductor source or drain structure (4254).

[0348] In another aspect, a hard mask material can be used to protect (prevent erosion of) a dielectric material in trench conductor positions, and can be maintained above this where conductive trench contacts are interrupted, e.g., at contact plug positions. For example, illustrate Fig. 45A and Fig. 45B a top view or corresponding cross-sectional view of an integrated circuit structure including trench contact plug with a hard mask material thereon according to an embodiment of the present disclosure.

[0349] With reference to Fig. 45A and Fig. 45B includes an integrated circuit structure 4500, in one embodiment a fin 4502A, such as a silicon fin. Several gate structures 4506 are located above the fin 4502A. Individual gate structures 4506 are located along a direction 4508 orthogonal to the fin 4502A and have a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is located above the fin 4502A and directly between the dielectric sidewall spacers 4510 of a first pair 4506A / 4506B of the gate structures 4506. A contact plug 4514B is located above the fin 4502A and directly between the dielectric sidewall spacers 4510 of a second pair 4506B / 4506C of the gate structures 4506. The contact plug 4514B includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0350] In one embodiment, the lower dielectric material 4516 of the contact plug 4516B comprises silicon and oxygen, such as a silicon oxide or silicon dioxide material. The upper hard mask material 4518 of the contact plug 4516B comprises silicon and nitrogen, such as silicon nitride, silicon-rich nitride, or silicon-poor nitride.

[0351] In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514B, as shown.

[0352] In one embodiment, individual gate structures 4506 include a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is located on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of individual gate structures 4506 has an upper surface coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514B, as shown. In another embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is located between the fin 4502A and the gate dielectric layer 4526.

[0353] Again with reference to Fig. 45A and Fig. 45B includes an integrated circuit structure 4500, in one embodiment comprising multiple fins 4502, such as multiple silicon fins. Individual fins 4502 are located along a first direction 4504. Multiple gate structures 4506 are located above the multiple fins 4502. Individual gate structures 4506 are located along a second direction 4508 orthogonal to the first direction 4504. Individual gate structures 4506 have a pair of dielectric sidewall spacers 4510. A trench contact structure 4512 is located above a first fin 4502A of the multiple fins 4502 and directly between the dielectric sidewall spacers 4510 of a pair of gate structures 4506. A contact plug 4514A is located above a second fin 4502B of the multiple fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures 4506.Similar to the cross-sectional view of a contact plug 4514B, the contact plug 4514A includes a lower dielectric material 4516 and an upper hard mask material 4518.

[0354] In one embodiment, the lower dielectric material 4516 of the contact plug 4516A comprises silicon and oxygen, such as a silicon oxide or silicon dioxide material. The upper hard mask material 4518 of the contact plug 4516A comprises silicon and nitrogen, such as a silicon nitride-rich nitride or silicon-poor nitride material.

[0355] In one embodiment, the trench contact structure 4512 comprises a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520. In one embodiment, the dielectric cap 4522 of the trench contact structure 4512 has an upper surface coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as shown.

[0356] In one embodiment, individual gate structures 4506 include a gate electrode 4524 on a gate dielectric layer 4526. A dielectric cap 4528 is located on the gate electrode 4524. In one embodiment, the dielectric cap 4528 of individual gate structures 4506 has an upper surface coplanar with an upper surface of the upper hard mask material 4518 of the contact plug 4514A or 4514B, as shown. In another embodiment, although not shown, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is located between the fin 4502A and the gate dielectric layer 4526.

[0357] One or more embodiments of the present disclosure relate to a gate alignment contact process. Such a process can be implemented to form contact structures for semiconductor fabrication, e.g., for integrated circuit fabrication. In one embodiment, a contact structure is formed aligned with an existing gate structure. In contrast, other approaches typically involve an additional lithography process with close overlap accuracy of a lithographic contact structure with an existing gate structure in combination with selective non-contact etching. For example, another process may involve structuring a poly(gate) grid with separate structuring of contacts and contact plugs.

[0358] According to one or more embodiments described herein, a contact formation method involves creating a contact pattern that is essentially perfectly aligned with an existing gate pattern, while eliminating the need for a lithographic operation with an extremely tight coverage accuracy budget. In such an embodiment, this approach allows the use of an intrinsically highly selective wet etching (e.g., compared to dry or plasma etching) to create contact openings. In another embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In such an embodiment, the approach eliminates the need for an otherwise critical lithography operation to create a contact pattern, as is used in other approaches.In one embodiment, a trench contact grid is not structured separately, but is instead formed between poly(gate) lines. For example, in such an embodiment, a trench contact grid is formed after the gate grid structuring, but before gate grid cuts.

[0359] Fig. 46A and Fig. Figure 46D illustrates cross-sectional views representing various operations in a method for manufacturing an integrated circuit structure including trench contact plugs with a hard mask material thereon, according to an embodiment of the present disclosure.

[0360] With reference to Fig. 46A includes a method for fabricating an integrated circuit structure forming multiple fins, wherein individual 4602 of the multiple fins are located along a first direction 4604. Individual 4602 of the multiple fins may include diffusion regions 4606. Multiple gate structures 4608 are formed over the multiple fins. Individual of the multiple gate structures 4608 are located along a second direction 4610 orthogonal to the first direction 4604 (e.g., the direction 4610 is into and out of the side). A sacrificial material structure 4612 is formed between a first pair of the gate structures 4608. A contact plug 4614 is formed between a second pair of the gate structures 4608. The contact plug includes a lower dielectric material 4616. A hard mask layer 4618 is located on the lower dielectric material 4616.

[0361] In one embodiment, the gate structures 4608 include sacrificial or dummy gate stacks and dielectric spacers 4609. The sacrificial or dummy gate stacks may consist of polycrystalline silicon or silicon nitride columns or any other sacrificial material, which may be referred to as gate dummy material.

[0362] With reference to Fig. 46B the sacrificial material structure 4612 is removed from structure 46A to form an opening 4620 between the first pair of gate structures 4608.

[0363] With reference to Fig. In 46C, a trench contact structure 4622 is formed in the opening 4620 between the first pair of gate structures 4608. Furthermore, in one embodiment, the hard mask 4618 is made of Fig. 46A and Fig. 46B is planarized as part of the formation of the trench contact structure 4622. Finally, the finalized contact plugs 4614' comprise the lower dielectric material 4616 and an upper hard mask material 4624 formed from the hard mask material 4618.

[0364] In one embodiment, the lower dielectric material 4616 of each of the contact plugs 4614' comprises silicon and oxygen, and the upper hard mask material 4624 of each of the contact plugs 4614' comprises silicon and nitrogen. In one embodiment, each of the trench contact structures 4622 comprises a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626. In one embodiment, the dielectric cap 4628 of the trench contact structure 4622 has an upper surface coplanar with an upper surface of the upper hard mask material 4624 of the contact plug 4614'.

[0365] With reference to Fig. 46D Sacrificial or dummy gate stacks of the gate structures 4608 are replaced in a substitute gate process scheme. In such a scheme, dummy gate material, such as polysilicon or silicon nitride column material, is removed and replaced with a permanent gate electrode material. In such an embodiment, a permanent gate dielectric layer is also formed in this process instead of being carried through by a previous processing step.

[0366] Accordingly, permanent gate structures 4630 comprise a permanent gate dielectric layer 4632 and a permanent gate electrode layer or stack 4634. Furthermore, in one embodiment, an upper part of the permanent gate structures 4630 is removed, e.g., by an etching process, and replaced with a dielectric cap 4636. In one embodiment, the dielectric cap 4636 of each of the permanent gate structures 4630 has an upper surface coplanar with an upper surface of the upper hard mask material 4624 of the contact plugs 4614'.

[0367] Again with reference to Fig. In one embodiment, as shown in 46A-46D, a replacement gate process is performed after the formation of the trench contact structures 4622. However, in other embodiments, a replacement gate process is performed before the formation of the trench contact structures 4622.

[0368] Another aspect describes COAG structures (COAG: Contact Over Active Gate) and processes. One or more embodiments of this disclosure relate to semiconductor structures or devices with one or more gate contact structures (e.g., as gate contact vias) arranged over active portions of the gate electrodes of the semiconductor structures or devices. One or more embodiments of this disclosure relate to methods for fabricating semiconductor structures or devices with one or more gate contact structures formed over active portions of the gate electrodes of the semiconductor structures or devices. The approaches described here can be used to reduce a standard cell area by enabling gate contact formation over active gate regions.In one or more embodiments, the gate contact structures designed to contact the gate electrodes are self-aligned via structures.

[0369] In technologies where space and layout constraints are somewhat less restrictive compared to current generations, contact with a gate structure can be established by making contact with a portion of the gate electrode positioned above an insulating region. As an example, this is illustrated... Fig. 47A a top view of a semiconductor device with a gate contact arranged over a non-active part of a gate electrode.

[0370] With reference to Fig. 47A comprises a semiconductor structure or device 4700A, a diffusion region or active region 4704, which is located in a substrate 4702 and within an isolation region 4706. One or more gate lines (also known as poly lines), such as gate lines 4708A, 4708B, and 4708C, are located over the diffusion region or active region 4704 and over a portion of the isolation region 4706. Source or drain contacts (also known as trench contacts), such as contacts 4710A and 4710B, are located over source and drain regions of the semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contact to the trench contacts 4710A and 4710B, respectively. A separate gate contact 4714, and an overlying gate contact via 4716, provides a contact to the gate line 4708B.Unlike the source or drain contacts 4710A or 4710B, the gate contact 4714 is located above the isolation region 4706 in a top-down perspective, but not above the diffusion region or active region 4704. Furthermore, neither the gate contact 4714 nor the gate contact via 4716 is located between the source or drain trench contacts 4710A and 4710B.

[0371] Fig. Figure 47b illustrates a cross-sectional view of a non-planar semiconductor device with a gate contact positioned over a non-active portion of a gate electrode. With reference to Fig. 47B includes a semiconductor structure or device 4700B, e.g. a non-planar version of the device 4700A made of Fig. 47A, a non-planar diffusion region or active region 4704C (e.g., a fin structure) formed by the substrate 4702 and within the isolation region 4706. The gate line 4708B is arranged over the non-planar diffusion region or active region 4704B and over part of the isolation region 4706. As shown, the gate line 4708B includes a gate electrode 4750 and a gate dielectric layer 4752 together with a dielectric cap layer 4754. The gate contact 4714 and the overlying gate contact via 4716 are also seen from this perspective, together with an overlying metal intermediate 4760, all arranged in interlayer dielectric stacks or layers 4770. Also when viewed from the perspective of Fig. 47B is the gate contact 4714 located above the isolation area 4706, but not above the non-planar diffusion or active area 4704B.

[0372] Again with reference to Fig. 47A and Fig. In embodiment 47B, the semiconductor structure or device arrangement 4700A or 4700B places the gate contact over the isolation regions. Such an arrangement wastes layout space. However, placing the gate contact over active regions would either require an extremely tight coverage accuracy budget or would necessitate an increase in gate dimensions to provide sufficient space for the gate contact. Furthermore, historically, a gate over diffusion regions has been avoided due to the risk of drilling through other gate material (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described here address the above problems by providing feasible approaches, and the resulting structures, for fabricating contact structures that contact portions of a gate electrode formed over a diffusion or active region.

[0373] As an example, it illustrates Fig. 48A A top view of a semiconductor device with a gate contact via arranged over an active part of a gate electrode, according to an embodiment of the present disclosure. With reference to Fig. 48A comprises a semiconductor structure or device 4800A, a diffusion or active region 4804, which is located in a substrate 4802 and within an isolation region 4806. One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are located over the diffusion or active region 4804 and over a portion of the isolation region 4806. Source or drain trench contacts, such as trench contacts 4810A and 4810B, are located over source and drain regions of the semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contact to trench contacts 4810A and 4810B, respectively. A gate contact via 4816 without an intervening separate gate contact layer provides contact to gate lines 4808B. In contrast to Fig. 47A is the gate contact 4816, located above the diffusion or active area 4804 and between the source or drain contacts 4810A and 4810B from a top-down perspective.

[0374] Fig. Figure 48B illustrates a cross-sectional view of a non-planar semiconductor device with a gate contact via arranged over an active part of a gate electrode, according to an embodiment of the present disclosure. With reference to Fig. 48B includes a semiconductor structure or device 4800B, e.g. a non-planar version of the device 4800A made of Fig. 48A, a non-planar diffusion region or active region 4804B (e.g., a fin structure) formed by the substrate 4802 and within the isolation region 4806. The gate line 4808B is arranged over the non-planar diffusion or active region 4804B and over part of the isolation region 4806. As shown, the gate line 4808B includes a gate electrode 4850 and a gate dielectric layer 4852 together with a dielectric cap layer 4854. The gate contact via 4816 is also seen from this perspective together with an overlying metal intermediate 4860, both arranged in interlayer dielectric stacks or layers 4870. Also when viewed from the perspective of Fig. 48B is the Gate Via 4816 located above the non-planar diffusion or active area 4804B.

[0375] Accordingly, with reference to Fig. 48A and Fig. In one embodiment, trench contact vias 4812A, 4812B and gate contact via 4816 are formed in the same layer and are essentially coplanar. In comparison to Fig. 47A and Fig. 47B would otherwise include the contact to the gate line and an additional gate contact layer, which could, for example, run perpendicular to the corresponding gate line. In the case of the (the) in association with Fig. 48A and Fig. However, the structure(s) described in 48B enable the fabrication of structures 4800A and 4800B, respectively, to establish a contact directly from a metal interleaved layer onto an active gate portion without short-circuiting to adjacent source-drain regions. In one embodiment, such an arrangement provides a significant area reduction in a circuit layout by eliminating the need for transistor gates to extend onto insulation to form a reliable contact. As used throughout, in one embodiment, a reference to an active portion of a gate refers to that part of a gate trace or structure that is located (from a top-down perspective) over an active or diffusion region of an underlying substrate.In one embodiment, a reference to an inactive part of a gate refers to that part of a gate line or structure which (from a top-down perspective) is arranged above an isolation area of ​​an underlying substrate.

[0376] In one embodiment, the semiconductor structure or device 4800 is a non-planar device, such as, among others, a FinFET or Tri-Gate device. In such an embodiment, a corresponding semiconducting channel region consists of or is formed within a three-dimensional body. In such an embodiment, the gate electrode stacks of the gate lines 4808A-4808C surround at least one top surface and a pair of side walls of the three-dimensional body. In another embodiment, at least the channel region is manufactured such that it is a discrete three-dimensional body, as in a gate all-around device. In such an embodiment, the gate electrode stacks of the gate lines 4808A-4808C each completely surround the channel region.

[0377] More generally, one or more embodiments relate to approaches for, and structures formed from, placing a gate-contact via directly on an active transistor gate. Such approaches can eliminate the need to extend a gate line on insulation for contact purposes. Such approaches can also eliminate the need for a separate gate-contact (GCN) layer to conduct signals from a gate line or structure. In one embodiment, the elimination of the above features is achieved by recessing contact metals in a trench contact (TCN) and introducing an additional dielectric material (e.g., TILA) into the process flow.The additional dielectric material is included as a trench contact dielectric cap layer with etching characteristics different from the gate dielectric material cap layer already used for trench contact alignment in a GAP processing scheme (GAP: Gate Aligned contact Process - Gate-aligned contact process) (e.g. GILA).

[0378] To illustrate as an exemplary manufacturing technique Fig. 49A-49D Cross-sectional views representing various operations in a method for manufacturing a semiconductor structure with a gate contact structure arranged over an active part of the gate, according to an embodiment of the present disclosure.

[0379] With reference to Fig. In Figure 49A, a semiconductor structure 4900 is provided following trench contact (TCN) formation. It is understood that the specific arrangement of structure 4900 is used for illustrative purposes only and that a variety of possible layouts of embodiments described herein can benefit. The semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A-4908E, arranged above a substrate 4902. The gate stack structures can include a gate dielectric layer and a gate electrode. Trench contacts, e.g., B. Contacts to diffusion regions of the substrate 4902, such as trench contacts 4910A-4910C, are also contained in the structure 4900 and are spaced from the gate-stack structures 4908A-4908E by dielectric spacers 4920. An insulating cap layer 4922 can be arranged on the gate-stack structures 4908A-4908E (e.g.GILA), as also in . Fig. 49A is shown. As also shown in Fig. As shown in 49A, contact blocking regions or “contact plugs”, such as region 4923 made of an interlayer dielectric material, may be included in areas where contact formation is to be blocked.

[0380] In one embodiment, providing structure 4900 involves forming a contact pattern that is essentially perfectly aligned with an existing gate pattern, while eliminating the need for a lithographic process with an extremely tight coverage accuracy budget. In such an embodiment, this approach allows the use of an intrinsically highly selective wet etching (e.g., compared to dry or plasma etching) to create contact openings. In another embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography process. In such an embodiment, the approach eliminates the need for an otherwise critical lithography process to generate a contact pattern, as used in other approaches.In one embodiment, a trench contact grid is not structured separately, but is instead formed between poly(gate) lines. For example, in such an embodiment, a trench contact grid is formed after the gate grid structuring, but before gate grid cuts.

[0381] Furthermore, the gate stack structures 4908A-4908E can be fabricated using a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride column material, can be removed and replaced with a permanent gate electrode material. In this embodiment, a permanent gate dielectric layer is also formed in this process instead of being carried over from a previous processing step. In one embodiment, dummy gates are removed by a dry or wet etching process. In one embodiment, dummy gates consist of polycrystalline silicon or amorphous silicon and are removed by a dry etching process including SF6. In another embodiment, dummy gates consist of polycrystalline silicon or amorphous silicon and are removed by a wet etching process including aqueous NH4OH or tetramethylammonium hydroxide.In one embodiment, dummy gates consist of silicon nitride and are removed by wet etching including aqueous phosphoric acid.

[0382] In one embodiment, one or more of the approaches described herein essentially consider a dummy or substitute gate process in combination with a dummy and substitute contact process to arrive at structure 4900. In such an embodiment, the substitute contact process is carried out after the substitute gate process to enable high-temperature annealing of at least a portion of the permanent gate stack. For example, in a particular embodiment, annealing of at least a portion of the permanent gate structures is carried out at a temperature greater than approximately 600 degrees Celsius, e.g., after a gate dielectric layer has been formed. The annealing is performed before the formation of the permanent contacts.

[0383] With reference to Fig. In 49B, the trench contacts 4910A-4910C of structure 4900 are recessed within the spacers 4920 to provide recessed trench contacts 4911A-4911C that have a height below the upper surface of the spacers 4920 and the insulating cap layer 4922. An insulating cap layer 4924 is then formed on the recessed trench contacts 4911A-4911C (e.g., TILA). According to one embodiment of the present disclosure, the insulating cap layer 4924 on the recessed trench contacts 4911A-4911C consists of a material with a different etching characteristic than the insulating cap layer 4922 on the gate stack structures 4908A-4908E. As can be seen in subsequent processing operations, such a difference can be exploited to selectively etch one of 4922 / 4924 from the other of 4922 / 4924.

[0384] The trench contacts 4910A-4910C can be selectively reset for the materials of the spacers 4920 and the insulating cap layer 4922 by a process. For example, in one embodiment, the trench contacts 4910A-4910C are reset by an etching process, such as a wet etching process or a dry etching process. The insulating cap layer 4924 can be formed by a process suitable for providing a conformal and sealing layer above the exposed portions of the trench contacts 4910A-4910C. For example, in one embodiment, the insulating cap layer 4924 is formed as a conformal layer above the entire structure by a chemical vapor deposition (CVD) process. The conformal layer is then planarized, e.g., by etching. B. by chemical-mechanical polishing (CMP) to provide the insulating cap layer material 4924 only above the trench contacts 4910A-4910C.and re-exposing the spacers 4920 and the insulation cap layer 4922.

[0385] Regarding suitable material combinations for the insulating cap layers 4922 / 4924, in one embodiment, one of the pair 4922 / 4924 consists of silicon oxide, while the other consists of silicon nitride. In another embodiment, one of the pair 4922 / 4924 consists of silicon oxide, while the other consists of carbon-doped silicon nitride. In another embodiment, one of the pair 4922 / 4924 consists of silicon oxide, while the other consists of silicon carbide. In another embodiment, one of the pair 4922 / 4924 consists of silicon oxide, while the other consists of carbon-doped silicon nitride. In yet another embodiment, one of the pair 4922 / 4924 consists of silicon nitride, while the other consists of silicon carbide. In another embodiment, one of the pair of 4922 / 4924 consists of carbon-doped silicon nitride, while the other consists of silicon carbide.

[0386] With reference to Fig. 49C a stack of an interlayer dielectric (ILD) 4930 and a hard mask 4932 is formed and structured to provide, for example, a trench 4934 made of a metal (0) above the structure made of Fig. 49B is structured.

[0387] The interlayer dielectric (ILD) 4930 can consist of a material suitable for electrically insulating metal features that are ultimately formed within it, while maintaining a robust structure between the front-end and back-end processing. Furthermore, in one embodiment, the composition of the ILD 4930 is selected to be consistent with via etch selectivity for trench contact dielectric cap layer structuring, as described in more detail below in association with Fig.49D. In one embodiment, the ILD 4930 consists of one or more layers of silicon oxide or one or more layers of a carbon-doped oxide (CDO) material. However, in other embodiments, the ILD 4930 has a bilayer composition with an upper part consisting of a different material than an underlying lower part of the ILD 4930. The hard mask layer 4932 can consist of a material suitable for acting as a subsequent sacrificial layer. For example, in one embodiment, the hard mask layer 4932 consists essentially of carbon, e.g., as a layer of a cross-linked organic polymer. In other embodiments, a silicon nitride or carbon-doped silicon nitride layer is used as a hard mask 4932.The stack of interlayer dielectric (ILD) 4930 and hard mask 4932 can be structured by a lithography and etching process.

[0388] With reference to Fig. 49D via openings 4936 (e.g., VCT) are formed in the interlayer dielectric (ILD) 4930, extending from the metal trench 4934 (0) to one or more of the recessed trench contacts 4911A-4911C. For example, in Fig. 49D via openings are formed to create recessed trench contacts 4911A and 4911C. The formation of the via openings 4936 involves etching both the interlayer dielectric (ILD) 4930 and respective portions of the corresponding insulating cap layer 4924. In such an embodiment, a portion of the insulating cap layer 4922 is exposed during the structuring of the interlayer dielectric (ILD) 4930 (e.g., a portion of the insulating cap layer 4922 is exposed above the gate stack structures 4908B and 4908E). In this embodiment, the insulating cap layer 4924 is etched to selectively form via openings 4936 (i.e., without significant etching or affecting the insulating cap layer 4922).

[0389] In one embodiment, a via-opening structure is ultimately transferred to the insulation cap layer 4924 (i.e., the trench contact insulation cap layers) by an etching process without etching the insulation cap layer 4922 (i.e., the gate insulation cap layers). The insulation cap layer 4924 (TILA) can consist of any of the following or a combination thereof, including silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon intrides, carbon-doped silicon oxides, amorphous silicon, various metal oxides, and silicates, including zirconium oxide, hafnium oxide, lanthanum oxide, or a combination thereof. The layer can be deposited using any of the following techniques, including CVD, ALD, PECVD, PVD, HDP-assisted CVD, and low-temperature CVD. A corresponding plasma dry etching process is being developed as a combination of chemical and physical sputtering mechanisms.Simultaneous polymer deposition can be used to control material removal rate, etch profiles, and film selectivity. Dry etching is typically performed with a mixture of gases including NF3, CHF3, C4F8, HBr, and O2, at typical pressures in the range of 30–100 mTorr and a plasma bias of 50–1000 watts. Dry etching can be designed to achieve significant etch selectivity between the 4924 (TILA) cap layer and the 4922 (GILA) layers, minimizing the loss of 4922 (GILA) during dry etching of 4924 (TILA) to form contacts with the transistor's source-drain regions.

[0390] Again with reference to Fig. 49D understands that a similar approach can be implemented to fabricate a via opening structure which is ultimately transferred to the insulation cap layer 4922 (i.e. the trench contact insulation cap layers) by an etching process without etching the insulation cap layer 4924 (i.e. the gate insulation cap layers).

[0391] To further illustrate the concepts of a Contact-over-Active-Gate (COAG) technology, the following is illustrated Fig. 50 a top view and corresponding cross-sectional views of an integrated circuit structure with trench contacts including an overlying insulating cap layer according to an embodiment of the present disclosure.

[0392] With reference to Fig. 50 comprises an integrated circuit structure 5000 and a gate line 5004 above a semiconductor substrate or fin 5002, such as a silicon fin. The gate line 5004 includes a gate stack 5005 (e.g., including a gate dielectric layer or stack and a gate electrode on the gate dielectric layer or stack) and a gate insulating cap layer 5006 on the gate stack 5005. Dielectric spacers 5008 are located along the side walls of the gate stack 5005 and, in one embodiment, along the side walls of the gate insulating cap layer 5006, as shown.

[0393] Trench contacts 5010 abut the side walls of the gate line 5004 with dielectric spacers 5008 between the gate line 5004 and the trench contacts 5010. Individual trench contacts 5010 include a conductive contact structure 5011 and a trench contact insulation cap layer 5012 on the conductive contact structure 5011.

[0394] Again with reference to Fig. In 50, a gate contact via 5014 is formed in an opening of the gate insulation cap layer 5006 and electrically contacts the gate stack 5005. In one embodiment, the gate contact via 5014 electrically contacts the gate stack 5005 at a position above the semiconductor substrate or fin 5002 and laterally between the trench contacts 5010, as shown. In such an embodiment, the trench contact insulation cap layer 5012 on the conductive contact structure 5011 prevents a gate-to-source short circuit or a gate-to-drain short circuit through the gate contact via 5014.

[0395] Again with reference to Fig. Trench contact vias 5016 are formed in an opening of the trench contact insulation cap layer 5012 and electrically contact the respective conductive contact structures 5011. In one embodiment, the trench contact vias 5016 electrically contact the respective conductive contact structures 5011 at positions above the semiconductor substrate or the fin 5002 and adjacent to the gate stack 5005 of the gate line 5004, as shown. In such an embodiment, the gate insulation cap layer 5006 on the gate stack 5005 prevents a source-to-gate short circuit or a drain-to-gate short circuit through the trench contact via 5016.

[0396] It is understood that different structural relationships can be established between an isolation gate cap layer and an isolation trench contact cap layer. Examples illustrate this. Fig. 51A-51F Cross-sectional views of various integrated circuit structures, each with trench contacts including an overlying insulation cap layer and with gate stacks including an overlying insulation cap layer, according to an embodiment of the present disclosure.

[0397] With reference to Fig. 51A, Fig. 51B and Fig. The integrated circuit structures 5100A, 5100B, and 5100C include a fin 5102, such as a silicon fin. Although shown in a cross-sectional view, it is understood that the fin 5102 has a top surface 5102A and side walls (extending into and out of the paper in the perspective shown). The first 5104 and second 5106 gate dielectric layers are located above the top surface 5102A of the fin 5102 and laterally adjacent to the side walls of the fin 5102. The first 5108 and second 5110 gate electrodes are located above the first 5104 and second 5106 gate dielectric layers, respectively, above the top surface 5102A of the fin 5102 and laterally adjacent to the side walls of the fin 5102. The first 5108 and second 5110 gate electrodes each contain a conformal conductive layer 5109A, such as an exit function setting layer, and a conductive filler material 5109B above the conformal conductive layer 5109A.The first 5108 and second 5110 gate electrodes each have a first side 5112 and a second side 5114 opposite the first side 5112. The first 5108 and second 5110 gate electrodes also each have an insulating cap 5116 with a top surface 5118.

[0398] A first dielectric spacer 5120 is located adjacent to the first side 5112 of the first gate electrode 5108. A second dielectric spacer 5122 is located adjacent to the second side 5114 of the second gate electrode 5110. A semiconductor source or drain region 5124 is adjacent to the first 5120 and second 5122 dielectric spacers. A trench contact structure 5126 is located above the semiconductor source or drain region 5124 adjacent to the first 5120 and second 5122 dielectric spacers.

[0399] The trench contact structure 5126 includes an insulating cap 5128 on a conductive structure 5130. The insulating cap 5128 of the trench contact structure 5126 has an upper surface 5129 that is substantially coplanar with the upper surfaces 5118 of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes. In one embodiment, the insulating cap 5128 of the trench contact structure 5126 extends laterally into recesses 5132 in the first 5120 and second 5122 dielectric spacers. In such an embodiment, the insulating cap 5128 of the trench contact structure 5126 projects beyond the conductive structure 5130 of the trench contact structure 5126. In other embodiments, however, the insulating cap 5128 of the trench contact structure 5126 does not extend laterally into the recesses 5132 in the first 5120 and second 5122 dielectric spacers and therefore does not project beyond the conductive structure 5130 of the trench contact structure 5126.

[0400] It is understood that the conductive structure 5130 of the trench contact structure 5126 may not be rectangular, as shown in Fig. 51A-51C. For example, the conductive structure 5130 of the trench contact structure 5126 may have a cross-sectional geometry similar to or the same as that of the conductive structure 5130A, which is shown in the projection from Fig. 51A is illustrated.

[0401] In one embodiment, the insulating cap 5128 of the trench contact structure 5126 has a composition different from the composition of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes. In such an embodiment, the insulating cap 5128 of the trench contact structure 5126 comprises a carbide material, such as a silicon carbide material. The insulating caps 5116 of the first 5108 and second 5110 gate electrodes comprise a nitride material, such as a silicon nitride material.

[0402] In one embodiment, the insulating caps 5116 of the first 5108 and second 5110 gate electrodes both have a lower surface 5117A below a lower surface 5128A of the insulating cap 5128 of the trench contact structure 5126, as shown in Fig. 51A. In another embodiment, the insulating caps 5116 of the first 5108 and second 5110 gate electrodes both have a lower surface 5117B substantially coplanar with a lower surface 5128B of the insulating cap 5128 of the trench contact structure 5126, as shown in Fig. 51B. In another embodiment, the insulating caps 5116 of the first 5108 and second 5110 gate electrodes both have a lower surface 5117C above a lower surface 5128C of the insulating cap 5128 of the trench contact structure 5126, as shown in Fig. 51C is shown.

[0403] In one embodiment, the conductive structure 5130 of the trench contact structure 5128 comprises a U-shaped metal layer 5134, a T-shaped metal layer 5136 on and over the entirety of the U-shaped metal layer 5134, and a third metal layer 5138 on the T-shaped metal layer 5136. The insulating cap 5128 of the trench contact structure 5126 is located on the third metal layer 5138. In such an embodiment, the third metal layer 5138 and the U-shaped metal layer 5134 comprise titanium, and the T-shaped metal layer 5136 comprises cobalt. In a particular embodiment, the T-shaped metal layer 5136 further comprises carbon.

[0404] In one embodiment, a metal silicide layer 5140 is located directly between the conductive structure 5130 of the trench contact structure 5126 and the semiconductor source or drain region 5124. In such an embodiment, the metal silicide layer 5140 comprises titanium and silicon. In a particular embodiment, the semiconductor source or drain region 5124 is an n-type semiconductor source or drain region. In another embodiment, the metal silicide layer 5140 comprises nickel, platinum, and silicon. In a particular embodiment, the semiconductor source or drain region 5124 is a p-type semiconductor source or drain region. In yet another particular embodiment, the metal silicide layer further comprises germanium.

[0405] In one embodiment, with reference to Fig. 51D a conductive via 5150 on a part of the first gate electrode 5108 above the top surface 5102A of the fin 5102 and is electrically connected to it. The conductive via 5150 is located in an opening 5152 in the insulating cap 5116 of the first gate electrode 5108. In such an embodiment, the conductive via 5150 is located on a part of the insulating cap 5128 of the trench contact structure 5126, but is not electrically connected to the conductive structure 5130 of the trench contact structure 5126. In a particular such embodiment, the conductive via 5150 is an eroded part 5154 of the insulating cap 5128 of the trench contact structure 5126.

[0406] In one embodiment, with reference to Fig. 51E a conductive via 5160 on a part of the trench contact structure 5126 and is electrically connected to it. The conductive via is located in an opening 5162 of the insulating cap 5128 of the trench contact structure 5126. In such an embodiment, the conductive via 5160 is located on a part of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes, but is not electrically connected to the first 5108 and second 5110 gate electrodes. In a particular such embodiment, the conductive via 5160 is an eroded part 5164 of the insulating caps 5116 of the first 5108 and second 5110 gate electrodes.

[0407] Again with reference to Fig. In one embodiment, conductive via 5160 is a second conductive via in the same structure as conductive via 5150. Fig. 51D. In one such embodiment, such a second conductive via 5160 is isolated from the conductive via 5150. In another such embodiment, such a second conductive via 5160 is combined with the conductive via 5150 to form an electrically short-circuiting contact 5170, as shown in Fig. 51F is shown.

[0408] The approaches and structures described here can enable the creation of other structures or devices that could not be manufactured, or were difficult to manufacture, using other methodologies. A first example illustrates this. Fig. 52A A top view of another semiconductor device with a gate-contact via arranged over an active part of a gate, according to another embodiment of the present disclosure. With reference to Fig. 52A comprises a semiconductor structure or device 5200 with multiple gate structures 5208A-5208C interlaced in a finger-like manner with multiple trench contacts 5210A and 5210B (these features are arranged above an active region of a substrate not shown). A gate contact via 5280 is formed on an active part of the gate structure 5208B. The gate contact via 5280 is further arranged on the active part of the gate structure 5208C, coupling gate structures 5208B and 5208C. It is understood that the intervening trench contact 5210B can be isolated from the contact 5280 by using a trench contact insulating cap layer (e.g., TILA). The contact configuration of Fig. 52A can provide a simpler approach to bridging adjacent gate lines in a layout without the need to route the bridge connection through upper layers of a metallization, thereby enabling smaller cell areas or less complicated wiring schemes, or both.

[0409] A second example illustrates Fig. 52B a top view of another semiconductor device with a trench contact via coupling a pair of trench contacts, according to another embodiment of the present disclosure. With reference to Fig. 52B comprises a semiconductor structure or device 5250 and several gate structures 5258A-5258C, which are interlaced in a finger-like manner with several trench contacts 5260A and 5260B (these features are arranged above an active region of a substrate not shown). A trench contact via 5290 is formed on the trench contact 5260A. The trench contact via 5290 is further arranged on the trench contact 5260B, coupling the trench contacts 5260A and 5260B. It is understood that the intervening gate structure 5258B can be isolated from the trench contact via 5290 by using a gate insulation cap layer (e.g., by a GILA process). The contact configuration of Fig. 52B can provide a simpler approach to bridging adjacent trench contacts in a layout without the need to route the bridge connection through upper layers of a metallization, thereby enabling smaller cell areas or less complicated wiring schemes, or both.

[0410] An insulating cap layer for a gate electrode can b...

Claims

[1] An integrated circuit structure (700), comprising: a first fin (702) which contains silicon; a second fin (702) which contains silicon; an insulating structure (704) between the first fin and the second fin; a first epitaxial source or drain structure (910) on the first fin, wherein the first epitaxial source or drain structure and the first fin meet at a first interface; a second epitaxial source or drain structure (910) on the second fin, wherein the second epitaxial source or drain structure and the second fin meet at a second interface; a dielectric material layer (714) extending continuously from above the first interface but below a top surface of the first epitaxial source or drain structure, along a section of a side wall of the first fin, on the insulating structure, along a section of a side wall of the second fin, to above the second interface but below a top surface of the second epitaxial source or drain structure. [2] Integrated circuit structure according to claim 1, wherein the dielectric material layer (714) lies directly on the section of the side wall of the first fin (702), and wherein the dielectric material layer lies directly on the section of the side wall of the second fin (702). [3] Integrated circuit structure according to one of claims 1 to 2, wherein the first epitaxial source or drain structure (910) extends laterally beyond the section of the dielectric material layer (714) along the section of the side wall of the first fin (702), and wherein the second epitaxial source or drain structure (910) extends laterally beyond the section of the dielectric material layer along the section of the side wall of the second fin (702). [4] Integrated circuit structure according to one of claims 1-3, wherein the dielectric material layer (714) comprises silicon and nitrogen. [5] Integrated circuit structure according to any one of claims 1 to 4, wherein the insulating structure (704) comprises silicon and oxygen. [6] An integrated circuit structure (700), comprising: a first fin (702) which contains silicon; a second fin (702) which contains silicon; an insulating structure (704) between the first fin and the second fin; a first source or drain structure (910), wherein at least a part of the first source or drain structure is directly above and in contact with the first fin, wherein the first source or drain structure comprises silicon and germanium; a second source or drain structure (710) on the second fin, wherein at least part of the second source or drain structure is directly above and in contact with the second fin, wherein the second source or drain structure comprises silicon and germanium; a dielectric material layer (714) extending continuously from a first position, which is laterally adjacent to a section of the first source or drain structure but below a top surface of the first source or drain structure, along a section of a side wall of the first fin, on the insulating structure, along a section of a side wall of the second fin, to a second position, which is laterally adjacent to a section of the second source or drain structure but below a top surface of the second source or drain structure. [7] Integrated circuit structure according to claim 6, wherein the dielectric material layer (714) is directly on the section of the side wall of the first fin (702), and wherein the dielectric material layer is directly on the section of the side wall of the second fin (702). [8] Integrated circuit structure according to one of claims 6 to 7, wherein the first source or drain structure (910) extends laterally over the section of the dielectric material layer (714) along the section of the side wall of the first fin (702), and wherein the second source or drain structure (910) extends laterally over the section of the dielectric material layer (714) along the section of the side wall of the second fin (702). [9] Integrated circuit structure according to one of claims 6-8, wherein the dielectric material layer (714) comprises silicon and nitrogen. [10] Integrated circuit structure according to one of claims 6-9, wherein the insulating structure (704) comprises silicon and oxygen. [11] A computing device (8700), comprising: a circuit board (8702); and a component coupled to the circuit board, wherein the component has an integrated circuit structure (700) comprising the following: a first fin (702) which contains silicon; a second fin (702) which contains silicon; an insulating structure (704) between the first fin and the second fin; a first epitaxial source or drain structure (910) on the first fin, wherein the first epitaxial source or drain structure and the first fin meet at a first interface; a second epitaxial source or drain structure (910) on the second fin, wherein the second epitaxial source or drain structure and the second fin meet at a second interface; a dielectric material layer (714) extending continuously from above the first interface but below a top surface of the first epitaxial source or drain structure, along a section of a side wall of the first fin, on the insulating structure, along a section of a side wall of the second fin, to above the second interface but below a top surface of the second epitaxial source or drain structure. [12] The computing device according to claim 11, further comprising a data storage device coupled to the circuit board (8702). [13] The calculating device according to one of claims 1 to 12, which further comprises: a communication chip (8706) coupled to the circuit board (8702). [14] The computing device according to one of claims 1 1-13, which further comprises a camera coupled to the circuit board (8702). [15] The computing device according to one of claims 1 1-14, which further comprises a battery coupled to the circuit board (8702). [16] The calculating device according to one of claims 1 1-15, which further comprises: an antenna coupled to the circuit board (8702). [17] The computer device according to one of claims 11-16, wherein the component is a packed integrated circuit die. [18] The computing device according to one of claims 11-17, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor. [19] The computing device according to one of claims 11-18, wherein the computing device (8700) is selected from the group consisting of a mobile phone, a laptop, a desktop computer, a server and a set-top box. [20] The calculating device according to one of claims 11-19, wherein the dielectric material layer (714) is directly on the section of the side wall of the first fin (702), and wherein the dielectric material layer is directly on the section of the side wall of the second fin (702). [21] Computing device according to one of claims 1 1-20, wherein the first epitaxial source or drain structure (910) extends laterally over the section of the dielectric material layer (714) along the section of the side wall of the first fin (702), and wherein the second epitaxial source or drain structure (910) extends laterally over the section of the dielectric material layer (714) along the section of the side wall of the second fin (702). [22] Computing device according to one of claims 11-21, wherein the dielectric material layer (714) comprises silicon and nitrogen. [23] The computer device according to one of claims 11-22, wherein the insulating structure (704) comprises silicon and oxygen.

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