Gate structure and methods for its manufacture

Abstract

Semiconductor structure (200), comprising: an active fin area (206) that protrudes from a semiconductor substrate; a gate stack (216), wherein the gate stack (216) comprises a gate dielectric layer (218) and a gate electrode (220) arranged on the gate dielectric layer (218), wherein the gate dielectric layer (218) comprises a first dielectric; and a dielectric gate (240) made of a second dielectric material, which is arranged on the active fin area (206), wherein the gate dielectric layer (218) extends from a side wall of the gate electrode (220) to a side wall of the dielectric gate (240), the second dielectric differs from the first dielectric in composition; and a gate cut feature (230) made of a third dielectric arranged between the gate electrode (220) and the dielectric gate (240), wherein the third dielectric differs in composition from the second dielectric.

Description

BACKGROUND

[0001] An integrated circuit is formed on a semiconductor substrate and includes various devices, such as transistors, diodes, and / or resistors, configured and interconnected into a functional circuit. In particular, the integrated circuit further includes field-effect transistors, such as metal-oxide-semiconductor FETs (MOSFETs) or complementary MOSFETs, each including a gate electrode for controlling the channel region of the corresponding FET. When a semiconductor device, such as a MOSFET, is scaled down across multiple technology nodes, high-k dielectrics and metal are used to form a gate stack. However, a method for forming metal gate stacks for n-MOS (nMOS) transistors and p-MOS (pMOS) transistors can encounter various problems when integrating the methods and materials for this purpose.For example, when forming a metal gate by gate replacement, there is an insufficient end-of-line process window because the gate dielectric layer is also formed on the sidewalls, leaving a smaller opening that can be filled with the metal or metal alloy. Furthermore, the profile of the metal gate stack depends on the layout of the gate cut feature and the gate dielectric. This affects the threshold voltage and saturation current, causing the device performance to vary. Therefore, it is desirable to obtain a new device structure and its manufacturing process to solve the above problems with improved circuit performance.

[0002] US 2017 / 0 125 579 A1 discloses a semiconductor device comprising a substrate having a first and a second fin structure, a shallow trench isolation around the fin structures, a gate isolation directly on the second fin structure, and a gate line on the shallow trench isolation and the first fin structure.

[0003] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of description. Fig. 1 is a flow diagram of a method of fabricating a semiconductor structure having a multi-fin structure constructed in accordance with various aspects of the present disclosure in some embodiments. Fig. 2 is a cross-sectional view of a semiconductor structure at a manufacturing stage constructed in accordance with some embodiments. Fig. Figure 3A is a top view of the semiconductor structure of Fig. 2 in a subsequent manufacturing stage constructed in accordance with some embodiments. Fig. Figure 3B is a cross-sectional view of the semiconductor structure of Fig. 3A along dashed line AA' constructed in accordance with some embodiments. The Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A and Fig. 11A are top views of the semiconductor structure at various stages of manufacture constructed in accordance with some embodiments. The Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B and Fig. 11B are cross-sectional views of the semiconductor structure along dashed line AA' at respective manufacturing stages constructed according to some embodiments. The Fig. 4C, Fig. 5C, Fig. 6C, Fig. 7C, Fig. 8C, Fig. 9C, Fig. 10C and Fig. 11C are cross-sectional views of the semiconductor structure along dashed line BB' at respective manufacturing stages constructed according to some embodiments. The Fig. 12A and Fig. 13A are top views of the semiconductor structure at various stages of manufacture constructed in accordance with further embodiments. The Fig. 12B and Fig. 13B are sectional views of the semiconductor structure along the dashed line AA' at respective manufacturing stages constructed according to further embodiments. The Fig. 12C and Fig. 13C are sectional views of the semiconductor structure along the dashed line BB' at respective manufacturing stages constructed according to further embodiments. Fig. 14 is a top view of the semiconductor structure constructed in accordance with some embodiments. Fig. 15 is a top view of the semiconductor structure constructed according to further embodiments. Fig. 16 is a top view of the semiconductor structure constructed in accordance with some embodiments. Fig. 17 is a plan view of the semiconductor structure constructed according to further examples. DETAILED DESCRIPTION

[0005] It should be understood that the following disclosure provides many different embodiments or examples for implementing various features of various embodiments. Specific examples of components and arrangements are described below to simplify the present disclosure. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, impose any relationship between the various described embodiments and / or configurations.

[0006] Further, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one feature or device to one or more other features or devices, as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements described as being "below" or "below" other elements or features are then oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation below and above.The device may be oriented differently (rotated by 90 degrees or in a different orientation) and the spatially relative terms used here may also be interpreted accordingly.

[0007] The present disclosure provides various embodiments of a semiconductor structure formed on a semiconductor substrate. The semiconductor structure includes various devices, such as field-effect transistors (FETs) with metal gate stacks, wherein the gate dielectric layer is made of a high-k dielectric and the gate electrode is made of metal or metal alloy. The semiconductor structure further includes dielectric gates and gate cut features integrated into the metal gate stacks. The semiconductor structure is formed by the disclosed method with an improved process window and improved device performance.

[0008] Fig. 1 is a flowchart of a method 100 for fabricating a semiconductor structure with fin-like transistors and metal gate stacks constructed in accordance with some embodiments. Fig. 2 to 17 are plan or cross-sectional views of a semiconductor structure 200 in various stages of fabrication. The semiconductor structure 200 and its fabrication method 100 are described below together with reference to Fig. 1 to 17 described.

[0009] Referring to Fig. 2, the method 100 begins with block 102 by providing a semiconductor substrate 202. The semiconductor substrate 202 comprises silicon. In some further embodiments, the substrate 202 comprises germanium, silicon-germanium, or other suitable semiconductor materials. The substrate 202 may alternatively be made of another suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor such as silicon-germanium carbide, gallium arsenophosphide, or gallium-indium phosphide.

[0010] The semiconductor substrate 202 also includes various doped regions, such as n-wells and p-wells. In one embodiment, the semiconductor substrate 202 includes an epitaxial (or epi) semiconductor layer. In another embodiment, the semiconductor substrate 202 includes a buried dielectric layer for isolation, formed by a suitable technology, for example, a technology referred to as isolation by implanted oxygen (SIMOX). In some embodiments, the substrate 202 may be a semiconductor-on-insulator, such as a silicon-on-insulator (SOI).

[0011] Still referring to Fig. 2, the method 100 proceeds to an operation 104 in which shallow trench isolation (STI) features 204 are formed on the semiconductor substrate 202. In some embodiments, the STI features 204 are formed by forming trenches, filling the trenches with dielectric material, and polishing them to remove excess dielectric and planarize the top surface. One or more etching processes are performed on the semiconductor substrate 202 through soft mask or hard mask openings formed by lithography patterning and etching. The formation of the STI features 204 is further described below, according to some embodiments.

[0012] In the present example, a hard mask is deposited on the substrate 202 and patterned using a lithography process. The hard mask layers comprise a dielectric, such as semiconductor oxide, semiconductor nitride, semiconductor oxynitride, and / or semiconductor carbide, and in one exemplary embodiment, the hard mask layer comprises a silicon oxide film and a silicon nitride film. The hard mask layer can be formed using thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), or other suitable deposition methods.

[0013] A photoresist layer (or resist) used to define the fin structure can be formed on the hardmask layer. An exemplary resist layer comprises a photosensitive material that causes the layer to undergo a property change when exposed to light, such as ultraviolet (UV) light, deep UV (DUV) light, or extreme UV (EUV) light. This property change can be used to selectively remove exposed or unexposed portions of the resist layer through one of the aforementioned development processes. This method of forming a patterned resist layer is also referred to as lithographic patterning.

[0014] In one embodiment, the resist layer is patterned to leave portions of the photoresist material disposed over the semiconductor structure 200 behind through the lithography process. After patterning the resist, an etching process is performed on the semiconductor structure 200 to open the hard mask layer, thereby transferring the pattern from the resist layer to the hard mask layer. The remaining resist layer may be removed after patterning the hard mask layer. An exemplary lithography process includes spin-coating a resist layer, soft-baking the resist layer, mask alignment, exposure, post-exposure baking, developing the resist layer, rinsing, and drying (e.g., hard baking). Alternatively, a lithography process may be implemented, supplemented, or replaced by other processes, such as maskless photolithography, electron beam writing, and ion beam writing.The etching process for patterning the hard mask layer may include wet etching, dry etching, or a combination thereof. The etching process may include multiple etching steps. For example, the silicon oxide film in the hard mask layer may be etched using a diluted hydrogen fluoride solution, and the silicon nitride film in the hard mask layer may be etched using a phosphoric acid solution.

[0015] An etching process then follows to etch the portions of the substrate 202 not covered by the patterned hard mask layer. The patterned hard mask layer is used as an etch mask during the etching processes to pattern the substrate 202. The etching processes may include any suitable etching technique, such as dry etching, wet etching, and / or other etching processes (e.g., reactive ion etching (RIE)). In some embodiments, the etching process includes multiple etching steps with different etching chemistries designed to etch the substrate to form the trenches with a specific trench profile for improved device performance and feature density. In some examples, the semiconductor material of the substrate may be etched by a dry etching process using a fluorine-based etchant. In particular, the etching process applied to the substrate is controlled such that the substrate 202 is partially etched.This can be achieved by controlling the etching time or by controlling one or more other etching parameters. After the etching processes, active regions 206 are defined on the substrate 202.

[0016] One or more dielectrics are filled into the trenches to form the STI feature 204. Suitable dielectric fill materials include semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, fluorinated silica (FSG), low-k dielectrics, and / or combinations thereof. In various exemplary embodiments, the dielectric is deposited using an HDP-CVD process, a subatmospheric CVD (SACVD) process, a high aspect ratio process (HARP), a flowable CVD (FCVD), and / or a spin-coating process.

[0017] The deposition of the dielectric may be followed by a chemical mechanical polishing / planarization (CMP) process to remove the excess dielectric and planarize the top surface of the semiconductor structure. The CMP process may use the hard mask layers as a polishing stop layer to prevent polishing of the semiconductor layer 202. In this case, the CMP process completely removes the hard mask. Alternatively, the hard mask may be removed by an etching process. Nevertheless, in further embodiments, a portion of the hard mask layers remains after the CMP process.

[0018] Referring to the Fig. 3A and Fig. 3B, the method 100 proceeds to an operation 106 in which the fin structure 206 is formed with a plurality of active fin regions (or fin features). Fig. 3A and Fig. 3B are a top view and a cross-sectional view along dashed line AA' of the semiconductor structure 200, respectively. The process 106 includes recessing the STI features 204 such that the active fin regions 206 protrude upward from the STI features 204. The recessing process uses one or more etching steps (such as dry etching, wet etching, or a combination thereof) to selectively etch back the STI features 204. For example, a wet etching process using hydrofluoric acid may be used for etching when the STI features 204 are made of silicon oxide. The example active fin regions 206 are spaced apart from each other in a first direction (X-direction). The active fin regions 206 have an elongated shape and are aligned along a second direction (Y-direction) that is perpendicular to the X-direction.In alternative embodiments, the active fin regions 206 are formed by epitaxial growth with one or more semiconductor materials, such as silicon and silicon-germanium. In further embodiments, the active fin regions 206 are formed by a combination of etching to deepen the STI features 204 and epitaxially growing the semiconductor material selectively on the active regions.

[0019] Various doping processes can be applied to the semiconductor regions at the current stage or prior to process 106 to form various doped wells, such as n-wells and p-wells. The various doped wells can be formed in the semiconductor substrate by appropriate ion implantations.

[0020] Referring to the Fig. 4A, Fig. 4B and Fig. 4C, the method 100 proceeds to an operation 108 in which dummy gate stacks 208 are formed on the active fin regions 206. Fig. 4A is a plan view; Fig. 4B is a sectional view taken along the dashed line AA'; and Fig. 4C is a partial cross-sectional view along dashed line BB' of the semiconductor structure 200 constructed in accordance with some embodiments. Some features are omitted for simplicity. For example, the substrate 202 in the Fig. 4A - 4C not shown; and the STI features 204 are in Fig. 4A not shown. In the present embodiment, the gate stacks 208 include five exemplary gate stacks, as shown in Fig. 4C. The dummy gate stacks 208 have elongated shapes and are aligned in the X direction. Each of the dummy gate stacks 208 is disposed over one or more active fin regions 206.

[0021] The dummy gate stacks 208 may each include a gate dielectric layer and a gate electrode above the gate dielectric layer. The gate dielectric layer includes a dielectric, such as silicon oxide, and the gate electrode includes a conductive material, e.g., polysilicon. Forming the dummy gate stacks 208 includes depositing the gate materials (e.g., forming silicon oxide and polysilicon in the present example); and patterning the gate materials through a lithography process and etching. A hard mask layer 210 may be formed on the gate materials and used as an etch mask during the formation of the dummy gate stacks. The hard mask layer 210 may include any suitable material, such as a silicon oxide, a silicon nitride, a silicon carbide, a silicon oxynitride, other suitable materials, and / or combinations thereof.In one embodiment, the hard mask layer 210 comprises multiple layers, such as silicon oxide and silicon nitride. In some embodiments, the patterning process for forming the gate stacks includes forming a patterned resist layer using a lithography process; etching the hard mask layer using the patterned resist layer as an etch mask; and etching the gate materials to form the gate stacks 208 using the patterned hard mask layer as an etch mask.

[0022] One or more gate spacers (not shown) are formed on the sidewalls of the dummy gate stacks 208. The gate spacers may be used to offset the subsequently formed source / drain features and may be used to shape or modify the source / drain structure profile. The gate spacers may comprise any suitable dielectric, for example, a semiconductor oxide, a semiconductor nitride, a semiconductor carbide, a semiconductor oxynitride, other suitable dielectrics, and / or combinations thereof. The gate spacers may comprise multiple films, such as two films (a silicon oxide film and a silicon nitride film) or three films (a silicon oxide film; a silicon nitride film; and a silicon oxide film). The formation of the gate spacers includes deposition and anisotropic etching, such as dry etching.

[0023] The dummy gate stacks 208 are configured on the active fin regions for various field-effect transistors (FETs), which are therefore also referred to as FinFETs. These dummy gate stacks 208 are replaced with metal gates at later stages of fabrication. The field-effect transistors include n-type transistors and p-type transistors integrated together. In some examples, these field-effect transistors are configured to form a logic gate, such as a NOR logic gate, a NAND logic gate; memory devices such as one or more static random access memory (SRAM) cells; other devices such as I / O devices; or a combination thereof.

[0024] The method 100 may proceed to a process 110 in which various source / drains (not shown) are formed for the respective FinFETs. The source / drains may include both lightly doped drain (LDD) features and heavily doped source / drain (S / D). For example, each field-effect transistor includes source / drains formed on the respective active fin region, with the corresponding dummy gate stack 208 sandwiched between them. A channel is formed in the active fin region in a portion underlying the corresponding gate stack and extending between the source / drains.

[0025] The raised source / drains may be formed by selective epitaxial growth for a stress effect with improved carrier mobility and device performance. The dummy gate stacks 208 and the gate spacer confine the source / drains to the source / drain regions. In some embodiments, the source / drains are formed by one or more epitaxial techniques, thereby growing Si features, SiGe features, SiC features, and / or other suitable features in a crystalline state on the active fin regions 206. Alternatively, an etching process is applied to recess the source / drain regions prior to epitaxial growth. Suitable epitaxial techniques include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable techniques.The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the active fin regions 206.

[0026] The source / drains may be doped in situ during the epitaxial growth process by introducing dopant species, for example: p-type dopants such as boron or BF2; n-type dopants such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If the source / drains are not doped in situ, an implantation process (i.e., a junction implantation process) is performed to introduce the appropriate dopant into the source / drains. In an exemplary embodiment, the source / drains in an nFET comprise SiC or Si doped with phosphorus, while those in a pFET comprise Ge or SiGe doped with boron. In some further embodiments, the raised source / drains comprise more than one layer of semiconductor material.For example, a silicon-germanium layer is epitaxially grown on the substrate in the source / drain regions, and a silicon layer is epitaxially grown on the silicon-germanium layer. One or more annealing processes can then be performed to activate the source / drain regions. Suitable annealing processes include rapid thermal annealing (RTA), laser annealing, other suitable annealing techniques, or a combination thereof.

[0027] Referring to the Fig. 5A, Fig. 5B and Fig. 5C, the method 100 proceeds to an operation 112 in which an interlayer dielectric layer 212 is formed on the active fin regions 206 and the dummy gate stacks 208. Fig. 5A is a plan view; Fig. 5B is a sectional view taken along the dashed line AA'; and Fig. 5C is a cross-sectional view along dashed line BB' of the semiconductor structure 200 in parts constructed according to some embodiments.

[0028] The ILD 212 surrounds the dummy gate stacks 208 and allows the dummy gate stacks 208 to be removed and replacement gates to be formed in the resulting cavity (also referred to as a gate trench). The ILD layer 212 may also be part of an electrical interconnect structure that electrically connects various devices of the semiconductor structure 200. In such embodiments, the ILD layer 212 acts as an insulator that supports and insulates the conductive lines. The ILD layer 212 may comprise any suitable dielectric, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, other suitable dielectrics, or combinations thereof. In some embodiments, the formation of the ILD layer 212 comprises deposition and CMP to provide a planarized top surface. The hard mask 210 may be removed at this stage, for example, by CMP or an additional etching process.

[0029] Referring to the Fig. 6A, Fig. 6B and Fig. 6C, the method 100 proceeds to an operation 114 in which the dummy gate stacks 208 are removed, resulting in gate trenches 214 in the ILD layer 212. Fig. 6A is a plan view; Fig. 6B is a sectional view taken along the dashed line AA'; and Fig. 6C is a partial cross-sectional view along dashed line BB' of the semiconductor structure 200 constructed according to some embodiments. In some embodiments, the gate stacks 208 are removed by an etching process, such as a wet etch, to selectively remove the gate stacks 208. The etching process may include multiple etching steps to remove the dummy gate if multiple materials are present.

[0030] Referring to the Fig. 7A, Fig. 7B and Fig. 7C, the method 100 proceeds to an operation 116 in which gate stacks (or gates) 216 are formed in the gate trenches 214. Fig. 7A is a plan view; Fig. 7B is a sectional view taken along the dashed line AA'; and Fig. 7C is a partial cross-sectional view along dashed line BB' of the semiconductor structure 200 constructed according to some embodiments. In process 116, the gate stacks 216 are formed with a high-k dielectric and metal, which is therefore also referred to as high-k metal gate stacks 216. The gate stacks 216 are formed in the gate trenches 214 by a suitable process, for example, a process comprising deposition and CMP. The gate materials, such as high-k dielectrics and metal, are deposited in the gate trenches 214; and a CMP process is implemented to polish and remove the excess gate materials over the top surface of the ILD layer 212.

[0031] The gate stacks 216 are formed on the substrate 202 above the channel region of the active fin region 206. The gate stacks 216 each include a gate dielectric layer 218 and a gate electrode 220 disposed on the gate dielectric layer 218. In the present embodiment, the gate dielectric layer 218 comprises a high-k dielectric, and the gate electrode 220 comprises metal or metal alloy. In some examples, the gate dielectric layer and the gate electrode may each comprise a number of sublayers. The high-k dielectric may comprise metal oxide, metal nitride such as LaO, AlO, ZrO, TiO, Ta2O3, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3 or other suitable dielectrics such as Si3N4 or oxynitrides (SiON).

[0032] In some embodiments, the gate dielectric layer 218 is formed on the bottom surface and sidewalls of each gate trench and is U-shaped. The gate dielectric layer 218 may further include an interface layer disposed between the high-k dielectric layer and the active fin region 206. The interface layer may include silicon oxide, silicon nitride, silicon oxynitride, and / or another suitable material. The interface layer is deposited by a suitable method such as ALD, CVD, ozone oxidation, etc. The high-k dielectric layer is deposited on the interface layer (if the interface layer is present) by a suitable technique such as ALD, CVD, metal-organic CVD (MOCVD), PVD, thermal oxidation, combinations thereof, and / or other suitable techniques.

[0033] The gate electrode 220 may comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, or any suitable conductive material. In some embodiments, different metal materials are used for nFET and pFET devices with respective work functions. The gate electrode 220 may comprise multiple conductive materials. In some embodiments, the gate electrode 220 comprises a cap layer, a first barrier layer, a work function metal layer, a second barrier layer, and a fill metal layer. In further embodiments, the cap layer comprises titanium nitride, tantalum nitride, or another suitable material formed by a suitable deposition technique such as ALD. Both the first and second barrier layers comprise titanium nitride, tantalum nitride, or another suitable material formed by a suitable deposition technique such as ALD.In some examples, the barrier layers may not be present, or only one of them may be present in the gate electrode. The work function metal layer comprises a conductive layer of metal or a metal alloy with a suitable work function so that the corresponding FET is improved in terms of its device performance. The work function (WF) metal layer differs for a pFET and an nFET and is referred to as n-WF metal and p-WF metal, respectively. The choice of WF metal depends on which FET is to be formed on the active region. For example, the semiconductor structure 200 comprises a first active region for an nFET and a second active region for a pFET, and accordingly, the n-WF metal and the p-WF metal are formed in the corresponding gate stacks.In particular, an n-WF metal is a metal with a first work function, such that the threshold voltage of the corresponding nFET is reduced. The n-WF metal is close to the silicon conduction band energy (Ec) or at a lower work function, allowing for easier electron migration. For example, the n-WF metal has a work function of about 4.2 eV or less. A p-WF metal is a metal with a second work function, such that the threshold voltage of the corresponding pFET is reduced. The p-WF metal is close to the silicon valence band energy (Ev) or at a higher work function, allowing for strong electron binding energy with the nuclei. For example, the p-work function metal has a WF of about 5.2 eV or more. In some embodiments, the n-WF metal comprises tantalum (Ta). In further embodiments, the n-WF metal comprises titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or combinations thereof.In further embodiments, the n-type metal comprises Ta, TiAl, TiAlN, tungsten nitride (WN), or combinations thereof. The n-type WF metal may comprise various metal-based films as stacks for optimized device performance and processing compatibility. In some embodiments, the p-type WF metal comprises titanium nitride (TiN) or tantalum nitride (TaN). In further embodiments, the p-type metal comprises TiN, TaN, tungsten nitride (WN), titanium aluminum (TiAl), or combinations thereof. The p-type WF metal may comprise various metal-based films as stacks for optimized device performance and processing compatibility. The work function metal is deposited by a suitable technique such as PVD. In various embodiments, the fill metal layer comprises aluminum, tungsten, or another suitable metal. The fill metal layer is deposited by a suitable technique such as PVD or plating.

[0034] Thereafter, the gate cut features and the dielectric gates are formed on the substrate as described below.

[0035] Referring to the Fig. 8A, Fig. 8B and Fig. 8C, the method 100 proceeds to an operation 118 in which a gate cutting process is performed on the gate stacks 216. Fig. 8A is a plan view; Fig. 8B is a sectional view taken along the dashed line AA'; and Fig. 8C is a partial cross-sectional view along dashed line BB' of the semiconductor structure 200 constructed according to some embodiments. For manufacturing reasons, such as to improve the patterning quality and properties of the gate stacks 216, the gate stacks 216 are formed with long geometries and then cut into segments according to the IC design layout. The process 118 includes patterning the gate stacks 216 by a process including lithography patterning and etching. In the present embodiment, the process 118 includes forming a patterned hard mask 222 on the substrate 202 with openings 224 defining the regions of the gate stacks 216 to be cut; and then performing an etching process on the gate stacks 216 through the openings 224 of the hard mask 222 using the hard mask 222 as an etch mask. The process 118 forms gate cut openings 226 in the gate stacks 216.The hard mask 222 may use any suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, another suitable dielectric, or a combination thereof. The hard mask 222 is formed by depositing a hard mask; forming a patterned resist layer by lithography; and etching the hard mask in the openings of the patterned resist layer. The etching process applied to the gate stacks 216 may include multiple etching steps with etchants for the respective gate materials and may include a wet etch, a dry etch, or a combination thereof.

[0036] Referring to the Fig. 9A, Fig. 9B and Fig. 9C, the method 100 proceeds to an operation 120 in which a dielectric is filled into the gate cut openings 226, thereby forming dielectric gate cut features 230 in the gate cut openings 226. Fig. 9A is a plan view; Fig. 9B is a sectional view taken along the dashed line AA'; and Fig. 9C is a partial cross-sectional view along dashed line BB' of the semiconductor structure 200 constructed according to some embodiments. In the present embodiment, the formation of the gate cut features 230 comprises a deposition and may further comprise a post-deposition CMP process. The deposition process may deposit any suitable dielectric using a suitable deposition technique such as CVD, flowable chemical vapor deposition (FCVD), high-density plasma CVD (HDPCVD), another suitable technique, or a combination thereof. After the formation of the gate cut features 230, the deposited dielectric may include a top layer 232 remaining on the gate stacks 216 and the gate cut features 230. This top layer 232 may be used as a hard mask for the subsequent process.In alternative embodiments, the deposited dielectric is planarized after the CMP process to be coplanar with the gate stacks 216; and then a hard mask 232 is deposited on the top surface of the semiconductor structure 200.

[0037] Referring to the Fig. 10A, Fig. 10B and Fig. 10C, the method 100 proceeds to an operation 122 in which portions of the gate stacks 216 are removed to form trenches 234. Fig. 10A is a plan view; Fig. 10B is a sectional view taken along the dashed line AA'; and Fig. 10C is a cross-sectional view along dashed line BB' of the semiconductor structure 200 in parts, constructed according to some embodiments. In operation 122, the portions of the gate stacks 216 are removed and replaced with dielectric gates. Operation 122 includes patterning the hard mask 232 by a lithography process and etching to form a patterned hard mask with openings 236; and etching to remove the portions of the gate stacks 216 in the openings 236, resulting in the trenches 234. In some embodiments, Fig. 10C, the process 122 selectively removes only the one or more materials of the gate electrode 220 in the openings 236, and the gate dielectric layer 218 remains in the trenches 234 after the process 122. Thereafter, the hard mask 232 may be removed, for example, by etching.

[0038] Referring to the Fig. 11A, Fig. 11B and Fig. 11C, the method 100 proceeds to an operation 124 in which the trenches 234 are filled with a dielectric 238 to form dielectric gates 240. Fig. 11A is a plan view; Fig. 11B is a sectional view taken along the dashed line AA'; and Fig. 11C is a cross-sectional view along dashed line BB' of the semiconductor structure 200 in parts, constructed according to some embodiments. In process 124, dielectric gates 240 are formed to replace the portions of gate stacks 216. Dielectric gates 240 are dielectric features that serve to provide insulation. Process 124 includes deposition and may further include a CMP process. The deposition may include any suitable deposition technique, such as CVD, FCVD, HDPCVD, or a combination thereof. Dielectric gates 240 differ in composition from gate cut features 230 for various reasons, such as etch selectivity. Gate cut features 230 and dielectric gates 240 both differ in composition from gate dielectric layer 218 for similar reasons, such as etch selectivity.

[0039] As mentioned above, the gate dielectric layer 218 comprises a high-k dielectric or, alternatively, an interface layer of silicon oxide and a high-k dielectric on the interface layer. In some embodiments, both the gate cut features 230 and the dielectric gates 240 may comprise silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but with different compositions. For example, the gate cut features 230 are made of silicon oxide, and the dielectric gates 240 are made of silicon nitride. The gate cut features 230 and the dielectric gates 240 may have a multi-layer structure. For example, the gate cut features 230 include a silicon oxide layer and a silicon nitride layer over the silicon oxide layer, while the dielectric gates 240 include a silicon nitride layer and a silicon oxide layer over the silicon nitride layer.

[0040] The semiconductor structure 200 thus formed has one or more dielectric gates 240 having the gate dielectric layer 218 on sidewalls, as shown in Fig. 11C and further in Fig. 14 is shown. Fig. 14 is a partial top view of the semiconductor structure 200 constructed in accordance with some embodiments. Only the active fin regions and the gate structure are shown. The gate dielectric layer 218 is formed on the sidewalls of the gate electrode 220 and is also formed on the sidewalls of the gate cut features 230 and the sidewalls of the gate dielectric 240. Furthermore, the interface between the gate electrode 220 and the gate cut feature 230 is free of the gate dielectric layer 218, resulting in an increased dimension of the gate electrode 220 and improved device performance. In the present embodiment, the gate electrode 220 is in the center of the Fig. 14 are interrupted by the gate cut features 230, which are further interrupted by the gate dielectric 240. They are all aligned to form a continuous structure completely surrounded by the gate dielectric layer 218.

[0041] In further examples, the process 122 removes both the gate dielectric layer 218 and the gate electrode 220 in the trenches 234, as shown in the Fig. 12A, Fig. 12B and Fig. 12C. After filling the trenches 234 with a dielectric 238 by the process 124, the dielectric gates 240 are formed as shown in the Fig. 13A, Fig. 13B and Fig. 13C. The thus formed dielectric gates 240 have a structure that differs from that of the Fig. 11C. In Fig. 13C, the gate dielectric layer 218 is not present on the outer sidewalls of the dielectric gates 240, and the dielectric gates 240 directly contact the ILD layer 212 at the outer sidewalls.

[0042] Furthermore, when the process 118 removes both the gate dielectric layer 218 and the gate electrode 220 in the trenches 226, the gate cut features 230 are also free of the gate dielectric layer 218 on the outer sidewalls. The semiconductor structure 200 thus formed is further Fig. 15 shown. Fig. 15 is a partial top view of the semiconductor structure 200 constructed in accordance with some embodiments. Only the active fin regions and the gate structure are shown. The gate dielectric layer 218 is formed on the sidewalls of the gate electrode 220, but the dielectric gates 240 and the gate cut features 230 are free of the gate dielectric layer 218 on respective outer sidewalls. Furthermore, the interface between the gate electrode 220 and the gate cut feature 230 is free of the gate dielectric layer 218, resulting in an increased dimension of the gate electrode 220 and improved device performance. In the present embodiment, the gate electrode 220 is in the center of the Fig. 15 are interrupted by gate cut features 230, which are further interrupted by gate dielectric 240. All are aligned to form a continuous structure, and gate electrode 220 is protected by gate dielectric layer 218 on respective outer sidewalls. Accordingly, gate cut features 230 and dielectric gates 240 have a larger dimension along the Y direction than gate electrode 220.

[0043] The semiconductor structure 200 and the method 100 for fabricating it are described together above according to various embodiments. Variations and alternatives exist within the scope of the present disclosure. For example, the formation of the gate cut features 230 and the dielectric gates 240 may have a different order. For example, the dielectric gates 240 are formed first, and then the gate cut features 230 are formed. However, both are formed after the formation of the gate stacks 216. In this case, operations 122 and 124 are implemented before operations 118 and 120, but after operations 114 and 116.In another example, the gate cut features 230 and the dielectric gates 240 are formed simultaneously by a common, reduced-cost process, such as patterning, to define both the openings for the dielectric gates 240 and the gate cut features 230. Both are further described below.

[0044] In a Fig. 16, the gate cut features 230 are formed by a first lithography process using a mask structure having openings 224 (such as the hard mask openings 224 in the embodiment shown in Fig. 8A) and the dielectric gates 240 are formed by a second lithography process using a mask structure with openings 236 (such as the hard mask openings 236 in the process shown in Fig. 10A shown process 122).

[0045] In an alternative example, shown in Fig. As shown in Figure 17, the gate cut features and the dielectric gates are jointly defined by a single mask pattern with openings 246 and are defined by a single lithography process. Thus, the gate cut features and the dielectric gates are formed simultaneously in a single process that includes lithography patterning, etching, and deposition. Accordingly, the gate cut features and the dielectric gates have the same composition and are Fig. 17 together with the reference number 248.

[0046] The present disclosure provides the semiconductor structure 200 and its manufacturing method 100 according to various embodiments. The method forms the gate cut features 230 and the dielectric gates 240 after the formation of the high-k metal gate stacks 216. Various advantages may be present in various embodiments. By using the disclosed method, the interface between the gate electrode 220 and the gate cut feature 230 (or the dielectric gate 240) is free of the gate dielectric layer 218, resulting in an increased dimension of the gate electrode 220 and improved device performance. The formation of the dielectric gates 240 and the formation of the gate cut features 230 are both self-aligned processes with better alignment and improved device performance.

Claims

[1] Semiconductor structure (200) comprising: an active fin region (206) protruding from a semiconductor substrate; a gate stack (216), wherein the gate stack (216) comprises a gate dielectric layer (218) and a gate electrode (220) arranged on the gate dielectric layer (218), wherein the gate dielectric layer (218) comprises a first dielectric; and a dielectric gate (240) made of a second dielectric disposed on the active fin region (206), wherein the gate dielectric layer (218) extends from a sidewall of the gate electrode (220) to a sidewall of the dielectric gate (240), the second dielectric differs from the first dielectric in composition; and a gate cut feature (230) of a third dielectric disposed between the gate electrode (220) and the gate dielectric (240), the third dielectric differing in composition from the second dielectric. [2] The semiconductor structure (200) of claim 1, wherein the gate dielectric layer (218) is disposed on a sidewall of the gate cut feature (230). [3] The semiconductor structure (200) of any preceding claim, wherein an interface between the gate electrode (220) and the gate cut feature (230) is free of the gate dielectric layer (218). [4] The semiconductor structure (200) of any preceding claim, wherein the gate cut feature (230) is substantially aligned with the dielectric gate (240) and the gate electrode (220), the gate cut feature (230) contacting the gate electrode (220) at a first end and contacting the dielectric gate (240) at a second end opposite the first end. [5] The semiconductor structure (200) of any preceding claim, wherein the gate dielectric layer (218) is a continuous feature extending from the sidewall of the gate electrode (220) across the sidewall of the gate cut feature (230) and to the sidewall of the gate dielectric (240). [6] The semiconductor structure (200) of any preceding claim, wherein the gate electrode (220) comprises metal and the gate dielectric layer (218) comprises a high-k dielectric. [7] Semiconductor structure (200) comprising: an active fin region (206) protruding from a semiconductor substrate (202); a gate stack (216), the gate stack (216) comprising a gate dielectric layer (218) and a gate electrode (220) arranged on the gate dielectric layer (218); and a dielectric gate (240) made of a first dielectric disposed on the active fin region (206), wherein the gate dielectric layer (218) comprises a second dielectric that differs in composition from the first dielectric, the gate dielectric layer (218) is arranged on a first sidewall of the gate electrode (220) and is free from a second sidewall of the gate electrode (220); and a gate cut feature (230) of a third dielectric disposed between the gate electrode (220) and the gate dielectric (240), the third dielectric differing in composition from the first dielectric. [8] The semiconductor structure (200) of claim 7, wherein all sidewalls of the dielectric gate (240) are free of the gate dielectric layer (218). [9] The semiconductor structure (200) of claim 7 or 8, wherein the gate electrode (220) directly contacts the gate cut feature (230). [10] The semiconductor structure (200) of any one of claims 7 to 9, wherein the gate dielectric layer (218) comprises a high-k dielectric and the gate electrode (220) comprises metal. [11] The semiconductor structure (200) of any one of claims 7 to 10, wherein the first dielectric comprises silicon oxide and the third dielectric comprises silicon nitride. [12] The semiconductor structure (200) of any one of claims 7 to 11, further comprising a shallow trench isolation feature (204) formed on the semiconductor substrate (202) and contacting the dielectric gate (240). [13] A method of forming an integrated circuit structure, the method comprising: Forming (106) a plurality of active fin regions (206) on a semiconductor substrate; Forming (108) a dummy gate stack (208) on the active fin regions (206); Forming (112) an interlayer dielectric layer (204) in gaps between the dummy gate stacks (208); removing (114) the dummy gate stack (208) to form a first trench in the interlayer dielectric layer (204); Filling (116) the first trench by depositing a gate dielectric layer (218) of a first dielectric and depositing a layer (220) of conductive material on the gate dielectric layer (218), thereby forming a high-k metal gate stack (216); performing (118) a first patterning process on the layer (220) of conductive material to form a second trench; filling (120) the second trench with a second dielectric that differs in composition from the first dielectric; performing (122) a second patterning process on the layer (220) of conductive material to form a third trench; and Filling (124) the third trench with a third dielectric that differs in composition from the first and second dielectrics. [14] The method of claim 13, wherein performing the first patterning process on the layer (220) of conductive material is performed after filling the first trench to form the high-k metal gate stack (216). [15] A method according to claim 13 or 14, wherein: depositing the gate dielectric layer (218) from the first dielectric comprises depositing a high-k dielectric layer; and depositing the layer (220) of conductive material comprises depositing metal or a metal alloy. [16] The method of any one of claims 13 to 15, wherein depositing the layer (220) of conductive material further comprises depositing a cap layer; depositing a work function metal layer over the cap layer; and depositing a metal-containing fill layer over the work function metal layer, wherein performing the first patterning process on the layer (220) of conductive material comprises patterning the cap layer, the work function metal layer, and the metal-containing fill layer such that the first dielectric layer is exposed in the second trench. [17] A method according to any one of claims 13 to 16, further comprising: Performing a first chemical-mechanical polishing process on the gate dielectric layer (218) and the layer (220) of conductive material before performing the first patterning process on the layer (220) of conductive material to form the second trench; Performing a second chemical-mechanical polishing process on the second dielectric after filling the second trench with the second dielectric; and Performing a third chemical mechanical polishing process on the third dielectric after filling the third trench with the third dielectric. [18] Method according to one of claims 13 to 17, wherein performing the first patterning process on the layer (220) of conductive material to form the second trench further comprises etching the gate dielectric layer (218) exposed in the second trench; and performing the second patterning process on the layer (220) of conductive material to form the third trench further comprises etching the gate dielectric layer (218) exposed in the third trench.

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