METHOD FOR PRODUCING SEMICONDUCTOR STRUCTURES

Abstract

Procedure with the following steps: Creating a first mask layer (108) over a target layer (102, 2316, 2416, 2516); Creating a plurality of spacers (124) over the first mask layer (108); Producing a second mask layer (130) over the plurality of spacers (124) and structuring the second mask layer (130) to create a first opening (134), wherein in a top view a principal axis of the opening (134) extends in a direction perpendicular to a principal axis of a spacer (124) of the plurality of spacers (124); Depositing a sacrificial material (136) in the opening (134), wherein the sacrificial material (136) directly contacts the first mask layer (108); Structuring the sacrificial material (136); Etching of the first mask layer (108) using the majority of spacers (124) and the structured sacrificial material (136); Etching the target layer (102, 2316, 2416, 2516) using the etched first mask layer (108) to create second openings (150) in the target layer (102, 2316, 2416, 2516); and Filling the second openings (150) in the target layer (102, 2316, 2416, 2516) with a conductive material (164).

Description

Background of the invention

[0001] With the increasing miniaturization of semiconductor devices, various processing techniques (e.g., photolithography) are being adapted to enable devices with ever smaller dimensions to be manufactured. For example, as the density of gates increases, the manufacturing processes for various structural elements within the device (e.g., those arranged over interconnect elements) are being adapted to be compatible with the overall miniaturization of device structures. However, as semiconductor processes have ever smaller process windows, the fabrication of these devices has reached and even exceeded the theoretical limits of photolithographic devices. As semiconductor devices continue to shrink, the spacing to be achieved between elements of a device (i.e.,the pitch), smaller than the pitch that can be produced using conventional optical masks and photolithographic devices.

[0002] A method for producing a semiconductor structure is known from US 2016 / 0 035 571 A1. Short description of the drawings

[0003] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. The Fig. 1 to 11 show cross-sectional views of various intermediate stages in the fabrication of a semiconductor device according to some embodiments. The Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 22A and Fig. 22B illustrate cross-sectional and top views of various intermediate stages in the fabrication of a semiconductor device according to some embodiments. The Fig. 23 and Fig. 24 show cross-sectional views of various intermediate stages in the fabrication of a semiconductor device according to some embodiments. The Fig. 25A and Fig. 25B show a cross-sectional view and a top view of an intermediate stage in the fabrication of a semiconductor device according to some embodiments. Fig. 26 is a flow diagram of a method according to some embodiments. The Fig. 27 to 30 show top views of semiconductor devices according to some embodiments. Fig. 31 is a block diagram of a processing system according to some embodiments. Fig. 32 is a top view of a semiconductor device according to some embodiments. The Fig. 33A and Fig. 33B are top views of virtual layouts and semiconductor devices according to some embodiments. The Fig. 34 to 43 are cross-sectional views of intermediate stages in the fabrication of a semiconductor device according to some embodiments. The Fig. 44A, Fig. 44B, Fig. 45A and Fig. 45B show cross-sectional and top views of intermediate stages in the fabrication of a semiconductor device according to some embodiments. The Fig. 46 and Fig. 47 show cross-sectional views of intermediate stages in the fabrication of a semiconductor device according to some embodiments. Fig. 48 is a flow diagram of a method according to some embodiments. Detailed description

[0004] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments where the first and second elements are fabricated in direct contact, and may also include embodiments where additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the component in use or operation, in addition to the orientation illustrated in the figures. The component may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] Semiconductor devices and methods for fabricating the same are provided according to some embodiments. In some embodiments, a patterning process is performed to pattern lines in a target layer of a semiconductor device. A dielectric layer is patterned by photolithography to form spacers. A patterned sacrificial material (sometimes referred to as a reversal material) is deposited over the spacers. The patterned sacrificial material may be an inorganic material and is fabricated by patterning openings in a mask (where the openings expose selected portions of the patterned lines) and depositing the inorganic material in the openings using a suitable layer deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and the like.After the sacrificial material has been deposited, it is patterned by creating an opening therein. The spacers and sacrificial material are used to pattern an underlying mask layer, which in turn is used to pattern a target layer. The underlying target layer can be a layer used for various purposes. For example, the target layer can be a low-k dielectric layer in which openings are patterned using the mask layer. Subsequently, one or more conductive materials can be filled into the openings of the low-k dielectric layer to define interconnect lines, wherein the interconnect lines have line cuts defined by the patterned sacrificial material.The interconnect lines may have a small pitch, and / or the one or more line cuts may have a small pitch, and / or the interconnect lines and the line cuts may be formed with small pitches using a simplified patterning process. For example, the target layer may be patterned with a simplified patterning process to create interconnect lines with small pitches that have one or more line cuts. Because the target layer is patterned in a single patterning process and / or with a simplified patterning process, as set forth herein, higher pattern accuracy may be achieved and manufacturing costs may be reduced.For example, if a target layer 102 is etched in two or more different processes, the pattern actually etched into the target layer 102 may deviate from the desired pattern, for example, due to difficulties in precisely aligning etch masks to parts to be etched. However, if the target layer 102 is etched with only a single etching step and / or the patterning process is simplified, as set forth herein, greater accuracy is possible. Therefore, multiple interconnect lines having multiple line cuts can be fabricated to have the same dimensions or substantially the same dimensions, allowing for greater control over the resistance of the interconnect lines. Furthermore, due to simplified processing, manufacturing costs can be reduced.

[0007] In some embodiments, the processes described herein can be used to fabricate power line and metal island structures with narrower power lines, metal islands with substantially similar dimensions, and / or groups of metal islands precisely aligned with other groups of metal islands. Due to the processes used to fabricate the power line and metal island structures, the fabricated power line may have kinks. Kinks may reduce the reliability of contacts made to the power line. To avoid the kinks, contacts to the power line may be made outside a "no-contact zone" where kinks may only be present at the edges of the power line.

[0008] In some embodiments, interconnects may have one or more line cuts, which may be referred to as a physical separation between two adjacent portions of an interconnect. Line cuts may be created by physically removing a portion of the interconnect after manufacturing. Alternatively, the interconnect may be manufactured using suitable techniques such that a line cut is present after the interconnect is manufactured. In some devices, multiple adjacent interconnects may have a line cut at the same position in a mid-portion of the interconnects. The line cut may be created such that an unwanted portion of one or more interconnects subsequently remains. For example, a line cut may be created at the same position of a group of adjacent interconnects.An interconnect line of the group of adjacent interconnect lines may be connected to a via that is more than a minimum distance from a line edge formed by the line cut, and the portion of the interconnect line between the line edge formed by the line cut and the via may not be required or desired in a particular design. An unnecessary or unwanted interconnect line that is not removed from a semiconductor device can be detrimental, for example, because the RC behavior of the device may degrade and / or the space occupied by unnecessary line edges may undesirably increase the size or mounting area of ​​a semiconductor device.In some embodiments, lead ends may be removed from a semiconductor device being manufactured, thereby improving the RC behavior of the semiconductor device and / or reducing the size or mounting area required for the device.

[0009] The Fig. 1 to 25B illustrate cross-sectional and / or top views of intermediate stages in the formation of structural elements in a target layer 102 on a semiconductor device 100, according to some example embodiments. The target layer 102 is a layer in which a structure is to be formed according to embodiments of the present invention. In some embodiments, the semiconductor device 100 is processed as part of a larger wafer. In these embodiments, after the formation of various structural elements (e.g., active devices, interconnect structures, and the like) of the semiconductor device 100, a singulation process may be performed on scribe regions between individual dies of the wafer to separate individual semiconductor dies from the wafer (also referred to as singulation).

[0010] In some embodiments, the target layer 102 is an IMD (inter-metal dielectric) layer. In these embodiments, the target layer 102 comprises a low-k dielectric material having a dielectric constant (k value) that is, for example, less than about 3.8, less than about 3.0, or less than about 2.5. In alternative embodiments, the target layer 102 is an IMD layer comprising a low-k dielectric material having a k value greater than 3.8. Using the processes of the embodiments, openings may be patterned in the target layer 102, and conductive lines and / or vias may be formed in the openings, as will be explained later.

[0011] In some embodiments, the target layer 102 is a semiconductor substrate. The semiconductor substrate may be made of a semiconductor material, such as silicon, silicon germanium, or the like. In some embodiments, the semiconductor substrate is a crystalline semiconductor substrate, such as a crystalline silicon substrate, a crystalline silicon carbon substrate, a crystalline silicon germanium substrate, a III-V compound semiconductor substrate, or the like. The semiconductor substrate may be patterned using a process of the embodiments, and subsequent process steps may be used to form shallow trench isolation (STI) regions in the substrate. Semiconductor fins may protrude between the formed STI regions.Source / drain regions can be fabricated in the semiconductor fins, and dielectric gate and electrode layers can be fabricated over channel regions of the fins to create semiconductor devices such as fin field-effect transistors (FinFETs).

[0012] In some embodiments, the target layer 102 is a conductive layer, such as a metal layer or a polysilicon layer, deposited as a protective layer. Patterning processes of the embodiments can be used for the target layer 102 to pattern semiconductor gates and / or dummy gates of the FinFETs. By using the processes of the embodiments to pattern a conductive target layer 102, the gap between adjacent gates can be reduced and the gate density can be increased.

[0013] In Fig. 1, a layer stack including the target layer 102 is formed in the semiconductor device 100. In some embodiments, the target layer 102 may be formed over a semiconductor substrate 104. The semiconductor substrate 104 may be made of a semiconductor material, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 104 may include: other semiconductor materials, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.Components (not shown), such as transistors, diodes, capacitors, resistors, and the like, may be formed in and / or on an active surface of the semiconductor substrate 104. In other embodiments where the target layer 102 is a semiconductor substrate used to fabricate FinFETs, the semiconductor substrate 104 may be omitted.

[0014] Fig. While Figure 1 shows the target layer 102 in physical contact with the semiconductor substrate 104, any number of intermediate layers may be disposed between the target layer 102 and the semiconductor substrate 104. These intermediate layers may include an interlayer dielectric (ILD) layer comprising a low-k dielectric and contact studs formed therein, further IMD layers in which conductive lines and / or vias are formed, one or more intermediate layers (e.g., etch stop layers, adhesion layers, etc.), combinations thereof, and the like. For example, an optional etch stop layer (not shown) may be disposed directly beneath the target layer 102. The etch stop layer may function as a stop layer for an etch process later performed on the target layer 102.The materials and processes used to form the etch stop layer may depend on the material of the target layer 102. In some embodiments, the etch stop layer may be made of silicon nitride, SiON, SiCON, SiC, SiOC, or SiC. x N y , SiO x , other dielectrics, combinations thereof, or the like, and can be fabricated by plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), plasma vapor deposition (PVD), or the like. Other materials and processes may also be used.

[0015] The layer stack further includes an anti-reflective coating (ARC) 106 formed over the target layer 102. The ARC 106 assists in the exposure and focusing of overlying photoresist layers (discussed later) during patterning of the photoresist layers. In some embodiments, the ARC 106 may be made of SiON, silicon carbide, materials doped with oxygen (O) and nitrogen (N), or the like. In some embodiments, the ARC 106 is substantially free of nitrogen and may be made of an oxide. In these embodiments, the ARC 106 may also be referred to as a nitrogen-free ARC (NFARC). The material composition of the ARC 106 may be selected to avoid reflection in some embodiments. The ARC 106 may be formed by plasma-enhanced chemical vapor deposition (PECVD), high-density plasma deposition (HDP deposition), or the like.Other methods and materials may also be used.

[0016] The layer stack may further include a hard mask layer 108 formed over the ARC 106 and the target layer 102. The hard mask layer 108 may be made of a material including a metal, such as titanium nitride, titanium, tantalum nitride, tantalum, a metal-doped carbide (e.g., tungsten carbide), or the like, and / or a semimetal, such as silicon nitride, boron nitride, silicon carbide, or the like. In some embodiments, the material composition for the hard mask layer 108 may be determined to provide high etch selectivity, for example, with respect to the ARC 106 and / or the target layer 102. The hard mask layer 108 may be formed by PVD, radio frequency PVD (RFPVD), atomic layer deposition (ALD), or the like. Other methods and materials may also be used.In subsequent processing steps, a patterning process of the embodiments is used to create a pattern on the hard mask layer 108. Subsequently, the hard mask layer 108 is used as an etching mask for etching the target layer 102, transferring the pattern of the hard mask layer 108 to the target layer 102.

[0017] The layer stack further comprises a dielectric layer 110, which in some embodiments is formed over the hard mask layer 108. During subsequent processing, the dielectric layer 110 may be used to form a plurality of spacers used to pattern a target layer (see Fig. 18A and Fig. 18B and 19A and 19B). The dielectric layer 110 may be made of silicon oxide, such as borophosphosilicate tetraethylorthosilicate (BPTEOS) or undoped tetraethylorthosilicate (TEOS) oxide, and may be formed by CVD, ALD, spin coating, or the like. Other methods and materials may also be used.

[0018] A three-layer masking layer 120 is formed on the layer stack above the dielectric layer 110. The three-layer masking layer 120 includes a bottom layer 112, a middle layer 114 above the bottom layer 112, and a top layer 116 above the middle layer 114. The top layer 116 may be made of a photoresist (e.g., a photosensitive material) comprising organic materials, and it may be a positive photosensitive material or a negative photosensitive material. The bottom layer 112 may be made of a polymer in some embodiments. The bottom layer 112 may also be a bottom anti-reflective coating (BARC) layer or an ashing removal dielectric (ARD) layer (such as amorphous carbon).The middle layer 114 may comprise an inorganic material, which may be a nitride (such as silicon nitride), an oxide nitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The middle layer 114 may have a high etch selectivity for the upper layer 116 and the lower layer 112. The various layers of the three-layer masking layer 120 may be deposited sequentially by protective deposition, for example, using spin-on techniques. Other methods and materials may also be used. Although a three-layer masking layer 120 is discussed here, in other embodiments, the three-layer masking layer 120 may actually be a single-layer masking layer or a two-layer masking layer (e.g., comprising only the lower layer 112 and the upper layer 116 without the middle layer 114). The type of masking layer used (e.g.,The masking layer (single-layer masking layer, two-layer masking layer, or three-layer masking layer) may depend on the photolithographic process used to pattern the dielectric layer 110. For example, in EUV (extreme ultraviolet) lithography, a single-layer masking layer or a two-layer masking layer may be used.

[0019] In some embodiments, the upper layer 116 is patterned using a photolithographic process. Subsequently, the upper layer 116 is used as an etch mask to pattern the middle layer 114 (see Fig. 2). Then, the middle layer 114 is used as an etch mask to pattern the lower layer 112, and the lower layer 112 is subsequently used to pattern the dielectric layer 110 (see Fig. 3). It has been found that by using a three-layer photoresist (e.g., a three-layer photoresist 120) to etch a target layer (e.g., the dielectric layer 110), improved resolution can be achieved for structures with a small pitch in the target layer (e.g., the dielectric layer 110).

[0020] The upper layer 116 is patterned using a suitable photolithographic process to create openings 122 therein. As an example of patterning the openings 122 in the upper layer 116, a photomask (not shown) may be disposed over the upper layer 116. The upper layer 116 may then be exposed to a radiation beam, for example, a UV or an excimer laser, such as a 248 nm beam from a krypton fluoride (KrF) excimer laser, a 193 nm beam from an argon fluoride (ArF) excimer laser, or a 157 nm beam from an F2 excimer laser, or the like, while the photomask masks portions of the upper layer 116. The exposure of the upper photoresist layer can be performed using an immersion lithography system or an EUV lithography system to increase resolution and reduce the achievable minimum pitch. One or more exposure steps can be performed.A drying or curing step may be performed to harden the upper layer 116, and a developer may be used to remove the exposed or unexposed portions of the upper layer 116 (depending on whether a positive or negative resist is used). The openings 122 may have stripe shapes in plan view (not shown). A minimum width W1 of the openings 122 may be approximately 19 nm. Other widths of the openings 122 are also contemplated.

[0021] In Fig. 2, after structuring the upper layer 116, its structure is transferred to the middle layer 114 in an etching process. The etching process is anisotropic, so that the openings 122 in the upper layer 116 are extended by the middle layer 114 and have approximately the same dimensions in the middle layer 114 as in the upper layer 116 (or are slightly smaller). The resulting structure is shown in Fig. 2 shown.

[0022] As in Fig. 3, an etch process may be performed to transfer the structure of the middle layer 114 to the bottom layer 112, thereby extending the openings 122 through the bottom layer 112. The etch process for the bottom layer 112 is anisotropic, so that the openings 122 in the middle layer 114 are extended through the bottom layer 112 and have approximately the same dimensions (or slightly smaller) in the bottom layer 112 as in the middle layer 114. The top layer 116 may be consumed during the etching of the bottom layer 112.

[0023] In Fig. 4, the structure of the lower layer 112 is transferred to the dielectric layer 110 using an etching process. The etching process is anisotropic, so that the openings 122 in the lower layer 112 are extended through the dielectric layer 110 and have approximately the same dimensions in the dielectric layer 110 as in the lower layer 112 (or are slightly smaller). Thus, spacers 124 are defined from remaining portions of the dielectric layer 110 (e.g., portions of the dielectric layer 110 between the openings 122). During the etching of the dielectric layer 110, the middle layer 114 is consumed, and the lower layer 112 may be at least partially consumed. In embodiments where the lower layer 112 is not completely consumed during the etching of the dielectric layer 110, a stripping process may be performed to remove the remaining residue of the lower layer 112.The remaining structure is in . Fig. 5. In a top view, gaps between the spacers 124 define areas where conductive lines are formed in the target layer 102. The spacers 124 may have a line pitch P1 greater than or equal to 30 nm.

[0024] In Fig. 6, a masking layer 130 is formed over the patterned dielectric layer 110. The masking layer 130 may include a bottom layer 126, a middle layer 128, and a top layer 132. The top layer 132 may be made of a photoresist (e.g., a photosensitive material) comprising organic materials. The top layer 132 may be a positive photosensitive material or a negative photosensitive material. In some embodiments, the bottom layer 126 may be a polymer, a BARC layer, an ARD layer, or the like. The middle layer 128 may include an inorganic material, which may be a nitride (such as silicon nitride), an oxide nitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The middle layer 128 may have a high etch selectivity for the top layer 132 and the bottom layer 126.The various layers of masking layer 130 can be deposited sequentially by protective deposition, for example, using spin-on techniques. Other methods and materials can also be used. Although a three-layer masking layer 130 is discussed here, in other embodiments, masking layer 130 can be a single-layer masking layer or a two-layer masking layer (e.g., comprising only the bottom layer 126 and the top layer 132 without the middle layer 128).

[0025] In Fig. 7, the upper layer 132 is patterned using a photolithographic process to create an opening 134 therein. Subsequently, the upper layer 132 is used as an etch mask to pattern the middle layer 128 (see Fig. 7). Then, the middle layer 128 is used as an etch mask to pattern the lower layer 126, and then the lower layer 126 is used to define a perimeter of a sacrificial material that will be deposited later (see Fig. 10 and Fig. 11).

[0026] In Fig. 7, the upper layer 132 is patterned using a suitable photolithographic process to create the opening 134 therein. As an example of patterning the opening 134 in the upper layer 132, a photomask (not shown) may be arranged over the upper layer 132. The upper layer 132 may then be exposed to a radiation beam, for example, a UV or an excimer laser, such as a 248 nm beam from a KrF excimer laser, a 193 nm beam from an ArF excimer laser, a 157 nm beam from an F2 excimer laser, or the like, while the photomask masks portions of the upper layer 132. The exposure of the upper photoresist layer may be performed using an immersion lithography system or an EUV lithography system to increase the resolution and reduce the achievable minimum pitch. One or more exposure steps can be performed.A drying or curing step may be performed to harden the upper layer 132, and a developer may be used to remove the exposed or unexposed portions of the upper layer 132 (depending on whether a positive or negative resist is used).

[0027] In Fig. 8, after structuring the upper layer 132, its structure is transferred to the middle layer 128 in an etching process. The etching process is anisotropic, so that the opening 134 in the upper layer 132 is extended by the middle layer 128 and has approximately the same size in the middle layer 128 as in the upper layer 132 (or is slightly smaller). The resulting structure is shown in Fig. 8 shown.

[0028] As in Fig. 9, an etch process may be performed to transfer the pattern of the middle layer 128 to the bottom layer 126, thereby extending the opening 134 through the bottom layer 126. The etch process for the bottom layer 126 is anisotropic, so that the opening 134 in the middle layer 128 is extended through the bottom layer 126 and is approximately the same size (or slightly smaller) in the bottom layer 126 as in the middle layer 128. The top layer 132 may be consumed during the etching of the bottom layer 126. After patterning the bottom layer 126, the opening 134 may expose one or more spacers 124 comprised of the remaining dielectric layer 110. The opening 134 may also expose portions of the hard mask layer 108 that extend between adjacent spacers 124.

[0029] In Fig. 10, a sacrificial material 136 is deposited in the opening 134. As will be explained in more detail later, during later processing, the sacrificial material 136 is further patterned, and the patterned sacrificial material may be used to define a line cut between two adjacent conductive lines formed in the target layer 102. Although in Fig. 10 shows the deposition of the sacrificial material in only one opening 134, in some embodiments, there may be more than one opening 134, and the sacrificial material may be deposited in more than one opening 134 (e.g., to make additional line cuts). In some embodiments, the sacrificial material 136 may be deposited in the opening 134 over the spacers 124 and over exposed portions of the hard mask layer 108. The sacrificial material may be deposited along sidewalls and along a top surface of the middle layer 128 (or a top surface of the bottom layer 126 if the middle layer 128 has been removed).

[0030] In various embodiments, the sacrificial material 136 is an inorganic material. The sacrificial material 136 may, for example, be an inorganic oxide, such as titanium oxide, tantalum oxide, silicon oxide, or the like. Other materials may also be used, such as silicon nitride, silicon carbide, a metal nitride, a metal oxide, or the like. The sacrificial material 136 may be selected, at least in part, by considering etch selectivity between the sacrificial material 136 and the material used to form the hard mask layer 108, the middle layer 128, and / or the bottom layer 126. In some embodiments, the inorganic material is a low-temperature oxide (LTO). The term "LTO" as used herein refers to an oxide deposited at a relatively low process temperature (e.g., 200°C or lower).It has been determined that in these embodiments, the low-temperature deposition process does not significantly damage the lower layer 126. Other materials may also be used.

[0031] The sacrificial material 136 may be deposited using a semiconductor layer deposition process, such as CVD, PVD, ALD, spin coating, or the like. Other processes may also be used. The semiconductor layer deposition process may be a conformal process in which a layer is deposited on sidewalls and a bottom surface of the opening 134. As deposition continues, portions of the sacrificial material 136 on opposite sidewalls of the opening 134 may fuse, filling the opening. Due to the semiconductor layer deposition process, a top surface of the sacrificial material 136 may be non-planar.

[0032] Then in Fig. 11, a planarization process, e.g., chemical mechanical polishing (CMP), dry etching, combinations thereof, or the like, may be performed to remove excess portions of the sacrificial material 136 outside the opening 134. In some embodiments (not shown), the planarization process may continue until the middle layer 128 and portions of the sacrificial material adjacent to the middle layer 128 are also removed.

[0033] Then, the middle layer 128 and the bottom layer 126 are removed using a stripping process. After the bottom layer 126 has been removed, the sacrificial material 136 remains and covers a portion of the spacers 124 and the hard mask layer 108. Removing the bottom layer 126 exposes other spacers 124 and portions of the hard mask layer 108. The remaining structure is shown in Fig. 12A (in a sectional view) and in Fig. 12B (in a top view). The section of Fig. 12A runs along the line A - A', which in the plan view of Fig. 12B. As shown in Fig. 12B in plan view, the sacrificial material 136 forms a rectangle having a major axis extending in a direction substantially perpendicular to the direction of the spacers 124 in plan view. Therefore, a line cut defined by the sacrificial material 136 is substantially perpendicular to conductive lines formed in recesses between adjacent spacers 124, resulting in a wider coverage process window.

[0034] As in the Fig. 9 to 12B, a thickness of the sacrificial material 136 may be determined at least in part based on a thickness of the lower layer 126. For example, by reducing the thickness of the lower layer 126, the thickness of the sacrificial material 136 is also reduced. As will be explained later, in some embodiments, if the sacrificial material 136 has a relatively small thickness, no subsequent planarization process may be required. This may reduce manufacturing costs and time.

[0035] In some embodiments, a length of the strip of sacrificial material 136 that is inserted into the Fig. 12A and Fig. 12B, for example, to extend the line section to further conductive lines. Although in Fig. 12B, only one strip of sacrificial material 136 is shown, in some embodiments, additional strips of sacrificial material 136 may be formed using the same or similar methods described above, for example, to create additional line cuts. In some embodiments, multiple strips of sacrificial material 136 may be formed, with each strip of sacrificial material 136 extending in a direction parallel to other strips of sacrificial material 136 and perpendicular to a direction in which spacers 124 extend in plan view.

[0036] In the Fig. 13A and Fig. 13B, a masking layer 140 is formed over the spacers 124, the hard mask layer 108, and the sacrificial material 136. The masking layer 140 may include a bottom layer 142, a middle layer 144, and a top layer 148. Although a three-layer masking layer 140 is shown here, in other embodiments, the masking layer 140 may be a single-layer masking layer or a two-layer masking layer, as set forth above. The bottom layer 142, in some embodiments, may completely cover the sacrificial material 136 and may extend along the exposed spacers 124 and the hard mask layer 108, as shown in Fig. 14A is shown.

[0037] In some embodiments, the upper layer 148 may be composed of a photoresist (e.g., a photosensitive material) comprising organic materials. The upper layer 148 may be a positive photosensitive material or a negative photosensitive material. In some embodiments, the lower layer 142 may be a polymer, a BARC layer, and / or an ARD layer, or the like. The middle layer 144 may comprise an inorganic material, which may be a nitride (such as silicon nitride), an oxide nitride (such as silicon oxynitride), an oxide (such as silicon oxide), or the like. The middle layer 144 may have high etch selectivity for the upper layer 148 and the lower layer 142. The various layers of the three-layer masking layer 140 may be deposited sequentially by protective deposition, for example, using spin-on techniques. Other techniques and materials may also be used.

[0038] In the Fig. 14A and Fig. 14B, the upper layer 148 is patterned using a photolithographic process. Subsequently, the upper layer 148 is used as an etch mask to pattern the middle layer 144 (see Fig. 15A and Fig. 15B). Then, the middle layer 144 is used as an etch mask for patterning the lower layer 142 (see Fig. 16A and Fig. 16B).

[0039] The upper layer 148 is patterned using a suitable photolithographic process, for example, the processes already mentioned, to create the opening 146 therein. For example, a photomask (not shown) can be arranged over the upper layer 148. The upper layer 148 can then be exposed to a radiation beam, for example, a UV or an excimer laser, such as a 248 nm beam from a KrF excimer laser, a 193 nm beam from an ArF excimer laser, a 157 nm beam from an F2 excimer laser, or the like, while the photomask masks areas of the upper layer 148. The exposure of the upper photoresist layer can be performed using an immersion lithography system or an EUV lithography system to increase the resolution and reduce the achievable minimum pitch. One or more exposure steps can be performed.A drying or curing step may be performed to harden the upper layer 148, and a developer may be used to remove the exposed or unexposed portions of the upper layer 148 (depending on whether a positive or negative resist is used). The opening 146 may have a width W2, where W2 is approximately 50 nm in some embodiments.

[0040] In the Fig. 15A and Fig. 15B, after structuring the upper layer 148, its structure is transferred to the middle layer 144 in an etching process. The etching process is anisotropic, so that the opening 146 in the upper layer 148 is extended through the middle layer 144 and has approximately the same size in the middle layer 144 as in the upper layer 148 (or is slightly smaller). The resulting structure is shown in the Fig. 15A and Fig. 15B shown.

[0041] As in the Fig. 16A and Fig. 16B, an etch process may be performed to transfer the structure of the middle layer 144 to the lower layer 142 and the sacrificial material 136, thereby extending the opening 146 through the lower layer 142 and the sacrificial material 136. The etch process for the lower layer 142 is anisotropic, so that the opening 146 in the middle layer 144 is extended through the lower layer 142 and is approximately the same size (or slightly smaller) in the lower layer 142 as in the middle layer 144. The etch process may be performed using CH4, Cl2, SF6, CH x F y , He, BCl3, N2, O2, H2, CF x , CHF x , NF3, Ar, SiCl4, a combination thereof or the like.

[0042] The upper layer 148 may be consumed during the etching of the lower layer 142. After patterning the lower layer 142, the opening 146 may expose a sidewall of one or more spacers 124 comprised of the remaining dielectric layer 110. The opening 146 may also expose portions of the hard mask layer 108 that extend between adjacent spacers 124. In some embodiments, additional portions of the spacers 124, such as top surfaces, or additional portions of the hard mask layer 108 may be exposed.

[0043] In the Fig. 17A and Fig. 17B, ​​the lower layer 142 and remaining portions of the middle layer 144 are removed, for example, using a stripping process. As shown in the top view of Fig. 17B, ​​the sacrificial layer 136 has been patterned into two individual pieces, and each piece is located (at least partially) over a gap between two adjacent spacers 124. The two individual pieces each extend in directions perpendicular to a direction in which the spacers 124 extend.

[0044] Then in the Fig. 18A and Fig. 18B, a planarization process is performed to remove excess portions of the sacrificial material 136 and to planarize the top surface of the sacrificial material 136 so that it is level with the top surfaces of the spacers 124. In some embodiments, the planarization process includes one or more etching processes. For example, it may be a dry etching process using CH4, Cl2, SF6, CH x F y , He, SiCl4, HBr, N2, O2, H2, CF x , CHF x, NF3, Ar, NF3, or the like. In some embodiments, a wet etching process may be performed, for example, using dilute hydrofluoric acid (DHF) as the etching chemical. In other embodiments, a grinding process, such as CMP, is used. The resulting structure is shown in the Fig. 18A and Fig. 18B. The section of Fig. 18A runs along the line A - A', which in the plan view of Fig. 18B. As shown in the Fig. 18A and Fig. As can be seen in Figure 18B, the planarization of the sacrificial material has created multiple individual pieces of sacrificial material, each individual piece located over a gap between two adjacent spacers. In some embodiments, each individual piece is located over an area where a line cut is created between two adjacent pieces of a conductive line.

[0045] In some embodiments, the Fig. 18A and Fig. 18B is not performed. In embodiments in which the planarization process shown in the Fig. 18A and Fig. 18B is not performed, the subsequent process may continue by offsetting the top surfaces of the sacrificial material 136 relative to the top surfaces of the spacers 124. As already described, for example, in connection with the Fig. 9 to 12B, in some embodiments, the thickness of the sacrificial material 136 may be controlled by controlling the thickness of the lower layer 126 (which is shown in the Fig. 9 to 12B). If the sacrificial material 136 is relatively thin, for example, since the lower layer 126 is made relatively thin, the Fig. 18A and Fig. The planarization process shown in Figure 18B is not required. Therefore, manufacturing costs and / or time can be reduced.

[0046] The Fig. 19A / 19B to 22A / 22B show the structuring of the hard mask layer 108 and the target layer 102. In the Fig. 19A / 19B to 22A / 22B are figures ending with an "A", each being a sectional view taken along the line A - A' shown in the plan view of the corresponding figure ending with a "B".

[0047] In the Fig. 19A and Fig. 19B, the hard mask layer 108 is patterned using the spacers 124 and the sacrificial material 136 as an etch mask to create an opening 150. The pattern of the spacers 124 and the sacrificial material 136 is transferred to the hard mask layer 108. In some embodiments, the etching of the hard mask layer 108 comprises an anisotropic dry etch and / or a wet etch. The resulting structure is shown in FIGS. Fig. 19A and Fig. 19B. The section of Fig. 19A runs along the line A - A', which in the plan view of Fig. 19B is shown.

[0048] As in the Fig. 19A and Fig. 19B, the remaining portions of sacrificial material 136 have prevented the etching of hard mask layer 108 beneath the remaining portions of sacrificial material 136 and, where present, have effectively caused a break or "cut" in opening 150 that would otherwise be created in hard mask layer 108 between two adjacent spacers 124. As will be explained in more detail later, when the pattern of hard mask layer 108 is later transferred to target layer 102 and conductive features are fabricated in the recesses, sacrificial material 136 causes a gap, gap, or "line cut" between adjacent portions of a conductive line.

[0049] After the hard mask layer 108 has been patterned, a wet cleaning may be performed to remove remaining portions of the spacers 124 and the sacrificial material 136. The resulting structure is shown in the Fig. 20A and Fig. 20B shown.

[0050] Afterwards, the Fig. 21A and Fig. 21B, the hard mask layer 108 is used as an etch mask for extending the opening 150 into the target layer 102. The etching of the target layer 102 may comprise an anisotropic etching process and / or a wet etching process that successively etches through the ARC layer 106 to the target layer 102. Remaining parts of the target layer 102 may have the same structure as the spacers 124 and the sacrificial material 136 of the Fig. 19A and Fig. 19B. Thus, the target layer 102 is patterned in only one patterning step.

[0051] After the openings 150 have been patterned, a wet cleaning process may be performed to remove remaining portions of the hard mask layer 108 and the ARC layer 106. The resulting structure is shown in the Fig. 22A and Fig. 22B shown.

[0052] After the openings 150 in the target layer 102 have been patterned, features can be formed in the openings. In one embodiment, the target layer 102 is a low-k dielectric, and the patterned target layer 102 provides an IMD for an interconnect structure. Conductive features, such as copper lines, copper vias, and / or cobalt pins, can be formed in the IMD.

[0053] In Fig. 23, one or more capping layers 162 may be formed along sidewalls and a bottom surface of the openings 150. The capping layers 162 may comprise TiO, TiN, TaO, TaN, Ru, Co, Ta, or the like, and may provide diffusion barrier, adhesion, and / or seed layers for the conductive feature. The capping layers may be deposited using a suitable process, such as PVD, CVD, ALD, and the like.

[0054] As in Fig. 24, the remaining parts of the openings 150 (which are shown in Fig. 23) may be filled with a conductive material 164, such as copper, for example, by PVD, plating, or the like. The conductive material 164 may initially be deposited to overfill the openings 150.

[0055] In the Fig. 25A and Fig. 25B, a planarization process is performed to remove excess portions of the conductive material 164 above the target layer 102. This allows conductive features to be formed in the target layer 102. In embodiments where the conductive features in the target layer 102 are conductive lines, the areas that were under the portions of the sacrificial material 136 (see Fig. 19A and Fig. 19B), when the hard mask layer 108 was patterned, areas where the conductive lines have gaps or “line cuts.”

[0056] As mentioned above in connection with the Fig. 12A and Fig. 12B, in some embodiments, the length of the strip of sacrificial material 136 included in the Fig. 12A and Fig. 12B, or additional strips of the sacrificial material 136 may be produced. If the length of the sacrificial material 136 is extended, the Fig. 25, so that further conductive lines have the line section shown. If several strips of the sacrificial material 136 are produced, the lines shown in Fig. 25B may have further line cuts that are offset from the line cuts shown. By using the embodiments discussed herein, conductive lines with a small pitch having line cuts with a line cut pitch of approximately 85.5 nm or more may be formed. If an EUV lithography tool is used in the patterning processes discussed herein, for example, to pattern the upper layer 132, as described above in connection with Fig. As demonstrated in Figure 7, a reduced line-cut distance can be achieved. For example, a line-cut distance of approximately ≥30 nm can be achieved.

[0057] When the processes discussed here are used multiple times, conductive lines with a line cut pitch of about ≥30 nm or about ≥48 nm can be fabricated with fewer manufacturing defects and a higher yield. For example, the processes described above in connection with the Fig. 6 to 12B may be repeated several times to produce multiple lines from the patterned sacrificial material (for example, to produce multiple adjacent line cuts during later processing), followed by the further processes associated with the Fig. 13A to 25B, for transferring the conductive lines with multiple adjacent line cuts to the target layer. With the additional processing, a line cut pitch of about ≥30 nm or about ≥48 nm can be achieved. However, since the Fig. 6 to 12B are repeated several times and the dimensions of the interconnecting lines are reduced, the dimensions of the manufactured interconnecting lines may deviate slightly from the target dimensions and / or alignment problems may occur.

[0058] In Fig. 26, a method 200 for forming an interconnect line in a target layer is provided. In step 168, a photoresist is patterned into a mask, such as in FIGS. Fig. 1 to 3. In step 170, a dielectric layer is etched using the mask as an etch mask, such as in Fig. 4. In step 172, another photoresist is prepared and patterned into another mask, as shown in the Fig. 6 to 9. In step 174, a sacrificial material is deposited in an opening of the mask, such as in the Fig. 10 and Fig. 11. In step 176, the mask is removed, as shown in the Fig. 12A and Fig. 12B. In some embodiments, steps 172 to 176 may be repeated multiple times, for example, to form conductive lines with multiple line cuts with a smaller line cut pitch. In step 178, another photoresist is formed and patterned into another mask, such as shown in FIGS. Fig. 13A to 15B. In step 180, the mask is used to pattern the sacrificial material, as shown in Fig. 16A and Fig. 16B. In step 182, the mask is removed, as shown, for example, in the Fig. 17A and Fig. 17B. In step 184, the sacrificial material is thinned, such as in the Fig. 18A and Fig. 18B. In step 186, a metal hard mask layer is etched, such as in the Fig. 19A and Fig. 19B. In step 188, the metal hard mask layer is used to pattern a target layer, such as in the Fig. 21A and Fig. 21B. In step 190, conductive lines are formed with one or more line cuts in openings of the target layer, such as in the Fig. 23 to 25B.

[0059] In some embodiments, the patterning techniques described herein may be used to form interconnect lines in a target layer, as described in the Fig. 25A and Fig. 25B. The interconnect lines can be formed with a small pitch, and multiple line cuts can be created with a small line cut pitch. The interconnect lines can be formed with higher accuracy using a simplified patterning process. For example, the target layer can be patterned with only one patterning process to produce interconnect lines with a small pitch and one or more line cuts. Since the target layer is patterned in only one patterning process (or a simplified patterning process), higher pattern accuracy can be achieved.For example, if a target layer 102 is etched using two or more different processes, the actual pattern etched into the target layer 102 may deviate from the desired pattern, for example, due to difficulties in precisely aligning an etch mask to a part to be etched. However, if the target layer 102 is etched using only one etching step and / or using a simplified patterning process described herein, greater accuracy is possible. Therefore, multiple interconnect lines having one or more line cuts can be fabricated to have the same dimensions or substantially the same dimensions, allowing for greater control over the resistance of the interconnect lines.

[0060] In some embodiments, the processes described above in connection with the Fig. 1 to 25B, for producing operating voltage line and / or metal island structures, such as the operating voltage line and metal island structures described in the Fig. 27 to 30. For example, the operating voltage line and metal island structures shown in the Fig. 27 to 30, in the target layer 102 using the processes described above in connection with the Fig. 1 to 25B. In some embodiments, a plurality of spacers may be fabricated over a dielectric layer as described above in connection with the Fig. 1 to 5, wherein a gap between one or more spacers of the plurality of spacers defines a recess created in a target layer for producing an operating voltage line, and gaps between other spacers of the plurality of spacers define recesses created in a target layer for producing a plurality of conductive lines adjacent to the operating voltage line, wherein the conductive lines extend in a direction parallel to a main axis of the operating voltage line. A sacrificial material may be deposited and patterned over the dielectric layer (as described in connection with the Fig. 6 to 18B), wherein the sacrificial material defines a plurality of line cuts extending in a direction perpendicular to the direction of the operating voltage line and the conductive lines. The spacers and the sacrificial material together define the structures shown in the Fig. 27 to 30. The structure of the sacrificial material and the spacers is transferred to a target layer, as shown in the Fig. 19A to 22B. In the structured target layer, conductors are produced as shown in the Fig. 23 to 25B to control the Fig. 27 to 30 structures shown.

[0061] In some embodiments, the processes described herein in connection with the Fig. 1 through 25B may be used to fabricate narrower power lines and / or groups of metal islands that are precisely aligned with other groups of metal islands. Due to the processes used to fabricate the power line and metal island structures, the fabricated power line may contain kinks. Kinks may reduce the reliability of contacts made to the power line. To avoid the kinks, contacts to the power line may be limited to portions of the power line that are outside a "no-contact zone" in which kinks may only be present at the edges of the power line.

[0062] Fig. Figure 27 shows a power line and metal island structure 2300 that can be formed in a target layer 2316 using the processes described herein. In some embodiments, the target layer 2316 is the same as or similar to the target layer 102 that can be formed in conjunction with the Fig. 1 to 25B. The power line and metal island structure 2300 includes a power line 2302. In some embodiments, the power line 2302 may assist in distributing a voltage source, such as Vdd, or a ground source within a device. For example, the power line 2302 may be electrically connected to a voltage source or a ground node, and contacts (not shown) may be formed at various locations along the power line 2302 that electrically connect to the power line 2302 and thereby connect the power line 2302 to the voltage source or ground node. The processes described herein may be used to fabricate a power line 2302 that has relatively small dimensions.For example, in some embodiments, the operating voltage line 2302 may have a thickness T4 of about 55 nm or less.

[0063] The power line and metal island structure 2300 may also include metal islands 2312. In some embodiments, the metal islands 2312 may be used to distribute power and / or signals in a device. As shown in Fig. 27, the processes described herein may be used to create an array of metal islands 2312 having a line cut pitch P2 greater than or equal to about 85.5 nm and a line cut pitch P5 greater than or equal to about 30 nm. Because the processes described herein may create an array of metal islands 2312 with a small line cut pitch and a small line cut pitch, a larger number of metal islands 2312 may be formed in the spaces adjacent to the power line 2302. Furthermore, the processes described herein may be used to create a group 2304 of metal islands 2312 that is precisely aligned with another group 2306 of metal islands 2312.In some embodiments, the metal island group 2304 is precisely aligned with the other metal island group 2306, for example, because the metal island group 2304 and the metal island group 2306 may be fabricated using the same line cut (i.e., the same strip of sacrificial material 136). Sidewalls of the metal islands 2312 of the metal island group 2304 may be aligned with the sidewalls of the metal islands 2312 of the metal island group 2306. As shown in FIG. Fig. 27, the processes described herein may also be used to fabricate a group of metal islands 2312 having a small line cut pitch P2, for example, greater than or equal to about 85.5 nm, where each metal island 2312 has the same or substantially the same dimensions as other metal islands 2312 in the group. For example, in some embodiments, each metal island 2312 may have a length L1 of about 45 nm to about 60 nm.

[0064] In some embodiments, the processes described herein may be used to form a power line and metal island structure 2400 in a target layer 2416, as shown in Fig. 28. In some embodiments, the target layer 2416 is the same as or similar to the target layer 102 used in conjunction with the Fig. 1 to 25B. The power line and metal island structure 2400 includes a power line 2402. In some embodiments, the power line 2402 may support the distribution of a voltage source, such as Vdd or ground, within a device. The power line 2402 may be similar to the power line 2302 described above in connection with Fig. 27. For example, in some embodiments, the power line 2402 may have a thickness T5 of about 55 nm or less. The power line and metal island structure 2400 may further include metal islands 2412. The metal islands 2412 may be similar or identical to the metal islands 2312 described above in connection with Fig. 27. The metal islands 2412 may have a line cut pitch P3 that is equal to or similar to the line cut pitch P2 used in conjunction with Fig. 27 has been discussed.

[0065] As in Fig. 28, the processes described herein used to form the power line and metal island structure 2400 may also create kinks 2414 that extend into the power line 2402. For example, the processes used to form the power line and metal island structure may have their own accuracy limitations, such as a limitation on the ability to align an etch mask to a specific portion of an underlying layer to be etched. The processing equipment used to form the power line and metal island structure 2400 may have inaccuracies or defects. Therefore, the processes described herein may result in the creation of kinks at the edges of the power line 2402.Kinks 2414 may reduce the reliability of physical or electrical connections to power line 2402 made in the edge portions of power line 2402 where kinks 2414 may form. In some embodiments, kinks 2414 may extend a distance D1 into power line 2402, where D1 is about 5 nm to about 8 nm.

[0066] To avoid the formation of contacts that could be affected by one or more kinks 2414 and therefore have a lower reliability, in some embodiments, one or more contact-free zones 2408 may be provided along the edges of the operating voltage line 2402, in which kinks 2414 may form. For example, semiconductor devices may be designed and manufactured such that physical and / or electrical connections to the operating voltage line 2402 are made outside the contact-free zone 2408 of the operating voltage line 2402. In some manufacturing processes, a semiconductor device may be processed prior to its manufacture using a computer-aided processing system (for example, a processing system 300 of Fig. 31, which will be discussed in more detail later). The computer-aided processing system may enable the use of one or more design rules that may be used to guide a designer in routing electrical connections in a virtual semiconductor device layout, for example, to ensure that minimum clearances specified by a particular processing technology are observed in a particular design. In some embodiments, the no-contact zone 2408 may be included in a design rule that prevents physical and / or electrical connections to the power line 2402 from being made within the no-contact zone 2408.Thus, when a design is completed and a semiconductor device is manufactured according to the planned design, all contacts with the operating voltage line 2402 outside the contact-free zone 2408 are made according to the design rule.

[0067] In some embodiments, the non-contact zone 2408 may extend into the operating voltage line 2402 by a distance D2, wherein the distance D2 is about 5 nm to about 10 nm. Multiple non-contact zones 2408 may be provided (for example, on opposite sides of the operating voltage line 2402), or in one embodiment, only one non-contact zone 2408 may be provided.

[0068] Fig. Figure 29 shows a power line and metal island structure 2500 formed in a target layer 2516, according to some embodiments. In some embodiments, the target layer 2516 is the same or similar to the target layer 102 formed in conjunction with the Fig. 1 to 25B. The operating voltage line and metal island structure 2500 can be manufactured using the processes described above in connection with the Fig. 1 to 25B. The power line and metal island structure 2500 includes a power line 2502 and metal islands 2512. The power line 2502 may be the same as or similar to the power line 2402, and the metal islands 2512 may be the same as or similar to the metal islands 2412.

[0069] In some embodiments, certain processes associated with the Fig. 1 to 25B, for example those in connection with the Fig. 6 to 12B may be used multiple times, allowing the formation of metal islands 2512 with a smaller line cut pitch. For a 10 nm technology node, the metal islands 2512 may have a line cut pitch P4 that is approximately 30 nm to 48 nm. In some embodiments, the inaccuracies that may occur during manufacturing (some examples are discussed above) may become more problematic as the pitch is reduced. In some embodiments, as the pitch of the metal islands (e.g., metal islands 2512) is reduced, it may become more difficult to manufacture multiple metal islands 2512 with the same or substantially the same dimensions. Therefore, for a pitch P4 of the metal islands 2512 of approximately 30 nm to 48 nm, the dimensions of the metal islands 2512 may change.For example, certain metal islands 2512 may have a length L2 equal to the length L1 of the metal islands 2312 used in conjunction with . Fig. 27. Other metal islands 2512 may have a length L3 of about 10 nm to about 35 nm.

[0070] As stated above, in some embodiments, the accuracy of the structure formed in the target layer 102 with the parameters associated with the Fig. 1 to 25B depends on the accuracy of various processing steps (e.g., the accuracy with which the patterning masks used in the patterning processes are manufactured and patterned, and / or the accuracy that can be achieved in an etching process in which the pattern of an upper mask is transferred to an underlying layer). Minor deviations in the desired pattern may occur, in particular when the target pitch of the metal islands 2512 is reduced, for example, to a pitch P4 of approximately 30 nm to 48 nm. The minor deviations may lead to minor misalignment of groups of metal islands. As in Fig. 29, for example, a metal island group 2504 is offset relative to a metal island group 2506. The deviations may also lead to the formation of kinks 2514, as explained above. The kinks 2514 may be the same or similar to the kinks 2414 that may be associated with Fig. 27. Therefore, contact-free zones 2508 may be required. The contact-free zones 2508 may be the same or similar to the contact-free zones 2408 used in conjunction with Fig. 28 have been discussed.

[0071] In some embodiments, a single operating voltage line and metal island structure may be fabricated that includes some or all of the structural elements described above in connection with the Fig. 27 to 29 have been discussed. Fig. 30 shows an operating voltage line and metal island structure 2900. The operating voltage line and metal island structure 2900 may include various parts manufactured according to different specifications. For example, in a first part, the operating voltage line and metal island structure 2900 is manufactured to include the structural elements of the operating voltage line and metal island structure 2300 described above in connection with Fig. 27. In a second part, the operating voltage line and metal island structure 2900 is manufactured to include the structural elements of the operating voltage line and metal island structure 2400 described above in connection with Fig. 28. In a third part, the operating voltage line and metal island structure 2900 is manufactured to include the structural elements of the operating voltage line and metal island structure 2500 described above in connection with Fig. 29 has been discussed.

[0072] As explained above, a processing system, such as a computer, can be used to design and optimize a virtual layout of a semiconductor device to be manufactured. After the virtual layout has been optimized on the processing system, the optimized layout can be used as a guide for the subsequent fabrication of a semiconductor chip.

[0073] In Fig. Figure 31 shows a block diagram of elements of a processing system 300 that can be used to generate a diagram depicting a virtual layout of a semiconductor chip to be manufactured. The processing system 300 may include a processor 302 provided with one or more input / output devices, such as a graphics card or graphics processing unit (GPU). The processor 302 may include a central processing unit (CPU) or CSP, memory, and a hardware accelerator connected to a bus 304.

[0074] The bus 304 may include one or more types of different bus architectures, such as a memory bus or memory controller, a peripheral bus, a video bus, or the like. The CPU may be manufactured with any type of electronic data processor. The memory may be manufactured with any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), read-only memory (ROM), non-volatile random access memory (NVRAM), a combination thereof, or the like. In one embodiment, the memory may include ROM for use during boot and DRAM for data storage for use during program execution. The memory may store programs that allow users to view, modify, and / or optimize virtual layouts of semiconductor chips to be manufactured.The memory may store parameters, rules, or the like to assist a user in designing, modifying, and / or optimizing virtual layouts of semiconductor chips to be manufactured. For example, the memory may store one or more design rules that may be used to ensure that minimum clearances specified for a particular technology or process are maintained, thus optimizing the virtual layout of a semiconductor chip to be manufactured.

[0075] The graphics card / GPU provides an interface for connecting an external input and output from a display 306 to the processor. The display 306 can display a virtual layout of a semiconductor chip being manufactured. Other devices can also be connected to the processor 302, and additional or fewer interface cards can be used. For example, a serial interface card (not shown) can be used to provide a serial interface for a printer.

[0076] Processor 302 may also include a network interface (not shown), which may be a wired connection, such as an Ethernet cable or the like, and / or a wireless connection, to enable communication with a network, such as a cellular communication network. The network interface enables the processor to communicate with remote devices over the network. In one embodiment, processor 302 is connected to a local area network or a wide area network to establish connections with remote devices, such as other processors, the Internet, remote storage devices, or the like.

[0077] It should be noted that processing system 300 may include additional components. For example, processing system 300 may include power connectors, cables, a motherboard, removable storage media, enclosures, and the like. These additional components, although not shown, are considered part of processing system 300.

[0078] In some embodiments, a planned semiconductor device may include conductive lines and interconnect lines, and a layout of a semiconductor chip to be manufactured may be optimized by removing unwanted portions of the conductive lines. For example, a plurality of conductive lines may have one or more line cuts, which in some embodiments may be manufactured using the methods described above in connection with the Fig. 1 to 25B. The line cuts may be made up to a central portion of a conductive line. After making the plurality of conductive lines with one or more line cuts, a portion of one or more of the conductive lines may be unnecessary or undesirable. As in Fig. For example, as shown in Figure 32, a conductive line 308 may be used to establish an electrical connection between a first end 312 of the conductive line 308 and a via 316, and between a second end 323 and a via 318. A line cut 320 may be created between the via 316 and the via 318. As shown in Fig. 32, a portion 322 of the conductive line 308 extending between the line cut 320 and the via 316 may be unused (e.g., this portion 322 of the conductive line may not be required for a desired electrical connection in a given layout). For some devices, unnecessary or unwanted metal lines in a semiconductor device may be detrimental. For example, unnecessary or unwanted metal lines may degrade the RC behavior of the semiconductor device and / or adversely increase the size and / or mounting area of ​​the semiconductor device.

[0079] In some embodiments, conductive lines may be fabricated so that unnecessary or undesired line ends are not created, and thereby the RC behavior of the semiconductor device may be improved and / or its size or mounting area may be reduced. Fig. 33A shows a comparison of virtual layouts (e.g., 324, 330) with physical conductive features (e.g., 326, 332) that could be fabricated using the virtual layouts as a guide. Fig. 33A also shows parameters that can be used to calculate a nominal cut width of a line cut that is used when creating a physical conductive line (see Fig. 34 to 47) so that an unnecessary or undesired lead end can be eliminated in a fabricated semiconductor device, thereby improving the RC constant of the device and / or reducing its size or mounting area.

[0080] Fig. 33A shows a virtual layout 324 overlaid on a physical conductive line 326 that may be fabricated using the virtual layout 324 as a guide. Fig. 33A further shows a virtual layout 330 superimposed on a physical conductive line 332, which may be fabricated using the virtual layout 330 as a guide. For the physical conductive line 326, the portion extending between a via 328 and a line end 338 is unused and would be convenient to remove or not fabricate in a semiconductor device being fabricated. For the physical conductive line 332, the portion extending between a via 334 and a line end 336 is unused and would be convenient to remove or not fabricate in a semiconductor device being fabricated.

[0081] For the physical conductive line 326 and the physical conductive line 332, EN is a width of a target cut of a virtual conductive line in a virtual layout, and W is a minimum distance between an edge of a virtual via in the virtual layout (e.g., 328 or 334) and a nearest edge of the target virtual line cut EN. In some embodiments, W is a parameter specified by design rules of a particular technology, for example, to ensure that when manufacturing a semiconductor device using the virtual layouts as a guide, the physical conductive line 326 over the via 328 and the physical conductive line 332 over the via 334 are not removed, for example, due to inaccuracies introduced into processing technologies used to manufacture the semiconductor device.

[0082] As in Fig. As shown in Figure 33A, a physical conductive line fabricated using a virtual layout as a guide may differ from the virtual layout in several respects, for example, due to inaccuracies that arise in various processing technologies or defects or variations in the fixtures used in processing. Fig. 33A, the physical conductive line 326 (which has been manufactured using the virtual layout 324 as a guide) is manufactured such that the line end 338 does not reach the planned line end of the virtual layout 324. In some embodiments, a distance between the line end 338 of the physical conductive line 326 and the planned line end of the virtual layout 324 may deviate by a maximum distance S. The physical conductive line 332, on the other hand, may be manufactured such that the line end 336 extends the maximum distance S beyond the planned line end of the virtual layout 330. In other words, there may be a deviation of ±S or 2S between a planned line end of a planned conductive line and a real line end of a real conductive line, where the real line end may be manufactured up to the maximum distance S on either side of the planned line end.Thus, a real line end can be manufactured within a predistortion range of 2S of a planned line end. In some embodiments, S can be about 0 nm to about 5 nm.

[0083] In some embodiments, during the manufacture of a semiconductor device, it may be desirable to adapt a planned line cut to a specific position of a conductive line. For example, it may be desirable to position a center axis of a planned line cut so that it intersects a center point of the line EN. However, due to the processing limitations discussed herein, precise adaptation may be difficult, and some deviation may occur during normal processing. Fig. 33B shows that, during the manufacture of a real component, a planned center axis 341 of a planned line cut 343 may be offset from a center axis 345 of a real line cut 347, which is manufactured using the planned line cut 343 as a guide. A coverage distance V may be defined, where V is a distance along the x-axis (which is Fig. 33B) is the distance by which a line cut can be shifted between the actual position and the planned position. In Fig. 33A shows that a generated real line section 340 has been shifted such that a center axis 342 is offset from a center point of the virtual line EN. In Fig. 33B, in a real manufacturing process, the conductive cut 347 may actually be arranged at a distance / spacing V from a first side of the planned conductive cut 343 along the x-axis, or at the distance / spacing V from a second side along the x-axis, with the second side opposite the first side. In some embodiments, V may be about 0 nm to about 6 nm. The value of V may depend on the processing equipment used to form the conductive cut 340 and / or the conductive lines 326 and 332, and on processing limitations or inaccuracies attributable to the equipment.

[0084] A deviation from a target cut width CD may also be taken into account. For example, in some embodiments, it may be specified (e.g., using a virtual layout) that a line cut 340 with a target cut width CD should remove an unwanted line end of a particular conductive line. However, when the line cut 340 is used in manufacturing a physical conductive line, the line cut 340 may have a real cut width that deviates slightly from the target cut width CD, for example, due to accuracy limitations of a processing technology or variations in the processing apparatus. In some embodiments, the real cut width may be larger than the target cut width CD by an amount Z (not shown). In some embodiments, the real cut width may be smaller than the target cut width CD by an amount Z.Thus, a cutting width variance of ±Z or 2Z can be accommodated. In some embodiments, Z can be about 0 nm to about 1 nm.

[0085] In some embodiments, an optimal cutting width CD can be determined according to the aforementioned parameters. The optimal cutting width CD can be determined according to the following relationship: Cutting width CD=2X+S+2(Z2+V2)0.5, where 2X EN is the nominal length of the virtual conductive line to be removed in the virtual layout, S is half of the pre-distortion range 2S, Z is half of the cut width variance 2Z, and V is the distance that a line cut can be moved between a real position and a planned position. The determined optimal cut width CD can be used when manufacturing a conductive line in which an unused line end has been removed, as explained later (see Fig. 34 to 47). A conductive line manufactured using a line cut having a cut width CD determined using this relationship may have a larger process window in the manufacture of the conductive line.

[0086] The Fig. 34 to 47 illustrate the fabrication of a conductive line according to some embodiments. In Fig. 34, a layer stack 415 is formed over a semiconductor substrate 402. The layer stack 415 includes: a dielectric layer 404 formed over the semiconductor substrate 402; a dielectric layer 406 formed over the dielectric layer 404; a hard mask layer 408 formed over the dielectric layer 406; a second cap layer 410 formed over the hard mask layer 408; an etch stop layer 412 formed over the second cap layer 410; and a first cap layer 414 formed over the etch stop layer 412. Each layer will be described in more detail below.

[0087] As in Fig. 34, the layer stack 415 is formed over the semiconductor substrate 402. The semiconductor substrate 402 may be formed of a semiconductor material, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 402 may include other semiconductor materials, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Components (not shown), such as transistors, diodes, capacitors, resistors, and the like, may be fabricated in and / or on an active surface of the semiconductor substrate 402.One or more interconnect lines and / or vias (not shown) may be provided in the semiconductor substrate 402. For example, a via 416 may be electrically connected to one or more devices (not shown) in the semiconductor substrate 402, for example, using one or more conductive lines (not shown) and / or one or more conductive vias (not shown).

[0088] Dielectric layer 404 is formed over semiconductor substrate 402. In some embodiments, dielectric layer 404 is an IMD (inter-metal dielectric) layer. In these embodiments, dielectric layer 404 comprises a low-k dielectric material having a dielectric constant (k value) that is, for example, less than 3.8, less than about 3.0, or less than about 2.5. In alternative embodiments, dielectric layer 404 is an IMD layer comprising a high-k dielectric material with a k value higher than 3.8. Other materials may also be used.

[0089] As in Fig. 34, the via 416 is formed in the dielectric layer 404. In some embodiments, the via 416 may provide an electrical connection from a conductive line formed in the dielectric layer 406 (see Fig. 47) to a device in the semiconductor substrate 402 (not shown). The via 416 may be formed by creating an opening in the dielectric layer 404, for example, using suitable lithographic techniques, such as the lithographic techniques described herein. One or more capping layers may be deposited in the opening. Subsequently, a conductive material may be deposited in the opening over the one or more capping layers, for example, using a plating process. After the plating process is completed, excess conductive material may overfill the opening and extend along a top surface of the dielectric layer 404 (not shown).Using a planarization process, such as chemical mechanical polishing, the excess conductive material may be removed and a top surface of the via 416 may be brought level with a top surface of the dielectric layer 404, as shown in FIG. Fig. 34. Other methods may also be used.

[0090] Dielectric layer 406 is formed over dielectric layer 404. In some embodiments, a conductive line is formed in dielectric layer 404. The conductive line may be formed such that no unwanted line end is created. Dielectric layer 406 may be formed using the same or similar methods described in connection with dielectric layer 404. In some embodiments, dielectric layer 406 has the same material composition as dielectric layer 404. In other embodiments, dielectric layer 406 has a different material composition than dielectric layer 404.

[0091] A hard mask layer 408 is formed over the dielectric layer 406. The hard mask layer 408 may be formed of a material including a metal, e.g., titanium nitride, titanium, tantalum nitride, tantalum, a metal-doped carbide (e.g., tungsten carbide), or the like, and / or a semimetal, such as silicon nitride, boron nitride, silicon carbide, or the like, and may be formed by PVD, radio frequency PVD (RFPVD), atomic layer deposition (ALD), or the like. Other methods and materials may also be used. In subsequent processing steps, a structure is formed on the hard mask layer 408 (see Fig. 44A and Fig. 44B). The hard mask layer 408 is then used as an etch mask for etching the dielectric layer 406.

[0092] The second cap layer 410 is formed over the hard mask layer 408. The second cap layer 410 may be formed using a silicon oxide, such as borophosphosilicate tetraethylorthosilicate (BPTEOS) or undoped tetraethylorthosilicate (TEOS) oxide, or the like. In some embodiments, the second cap layer 410 is a low-temperature oxide (LTO). The term "LTO" as used herein refers to an oxide deposited at a relatively low process temperature (e.g., 200°C or lower). The second cap layer 410 may be formed by PVD, CVD, ALD, spin coating, or the like. Other methods and materials may also be used.

[0093] The etch stop layer 412 is formed over the second cap layer 410. In some embodiments, the etch stop layer may be formed using SiC, SiOC x , SiN, SiON xor the like. The etch stop layer 412 may be made of a suitable material that has high etch selectivity for the first cap layer 414, and it may be formed by PVD, CVD, ALD, spin coating, or the like. Other methods and materials may also be used.

[0094] The first cap layer 414 is formed over the etch stop layer 412. The first cap layer 414 may be formed using a silicon oxide, such as BPTEOS or undoped TEOS oxide, or the like. In some embodiments, the first cap layer 414 is an LTO. The first cap layer 414 may be formed using the same material as the second cap layer 410. In other embodiments, the first cap layer 414 is made of a different material than the second cap layer 410 and may be formed by PVD, CVD, ALD, spin coating, or the like. Other methods and materials may also be used.

[0095] In Fig. 35, the first cap layer 414 is patterned to create an opening 418. The opening 418 is located above a region of the dielectric layer 406 in which a mask 420 is formed (see Fig. 37). The opening 418 may have a nominal width CD, which is determined as described above in connection with Fig. 33. The opening 418 can be formed using suitable lithographic techniques, such as those described herein.

[0096] In Fig. 36, a mask material 421 is deposited over the first cap layer 414 and in the opening 418 such that the opening 418 is filled with the mask material 421. In some embodiments, the mask material 421 comprises SiO x , SiN x , SiC x , a metal oxide, a metal nitride, or the like. In some embodiments, the mask material 421 may comprise a suitable inorganic material that has high etch selectivity for the material of the hard mask layer 408. The mask material 421 may be formed by PVD, CVD, ALD, spin coating, or the like. Other methods and materials may also be used.

[0097] In Fig. 37, excess portions of the mask material 421 are removed, forming the mask 420. In some embodiments, the excess portions of the mask material may be removed using a grinding process, such as chemical mechanical polishing. In other embodiments, an etching process may be used to remove the excess portions of the mask material 421. After the excess portions of the mask material 421 have been removed, the top and bottom surfaces of the mask 420 are flush with the top and bottom surfaces of the first cap layer 414. Other methods and materials may also be used.

[0098] As in Fig. 37, the first cap layer 414 and the mask 420 have a thickness T1, and the etch stop layer 412 has a thickness T2. In some embodiments, T1 is greater than or equal to half the cutting width CD, wherein the cutting width CD is determined as described in connection with the Fig. 33A and Fig. 33B. In other words, in some embodiments, T1 ≥ 0.5CD. In some embodiments, a combined thickness of T1 and T2 satisfies the following relationship: T1+T2=T3⋅(1+target 0E% / SEL(hard mask layer 408 / etch stop layer 412), where T1 is the thickness of the first cap layer 414, T2 is the thickness of the etch stop layer 412, T3 is the thickness of the hard mask layer 408, “target OE%” is the target overetch percentage used in the fabrication of a semiconductor device, and “SEL (hard mask layer 408 / etch stop layer 412)” is the etch selectivity of the hard mask layer 408 compared to the etch stop layer 412. If the above relationships are satisfied, when etching a hard mask layer (see Fig. 44A and Fig. 44B) the mask layer 420, the etch stop layer 412, and the first cap layer 414 are consumed. By consuming the mask layer 420, the etch stop layer 412, and the first cap layer 414, the hard mask layer 408 and the second cap layer 410 have a substantially uniform height after completion of the etch process. Therefore, a subsequent etch of the dielectric layer 406 to form a conductive line therein may be performed more reliably and with fewer defects, and / or the etch window may be maintained and is not undesirably reduced, which could lead to difficulties in filling the openings in the dielectric layer 406 with a conductive material.

[0099] In Fig. 38, a three-layer masking layer is formed over the first cap layer 414 and the mask 420. The triple layer includes a bottom layer (sometimes referred to as an underlayer) 422, a middle layer 424 over the bottom layer 422, and a top layer 426 over the middle layer 424. In some embodiments, the top layer 426 may be made of a photoresist. A positive or negative photoresist material may be used. The middle layer 424 may be made of an inorganic material, which may be a nitride (such as silicon nitride), an oxide nitride (such as silicon oxynitride), an oxide (such as silicon oxide), a silicon-rich photoresist, or the like. The bottom layer 422 may be a polymer or an anti-reflective material. The middle layer 424 may have a high etch selectivity to the top layer 426 and the bottom layer 422.Therefore, the upper layer 426 can be used as an etch mask for patterning the middle layer 424, and the middle layer 424 can be used as an etch mask for patterning the lower layer 422. Other materials can also be used.

[0100] In Fig. 39, the upper layer 426 is patterned to create openings 428 and 429. The openings 429 have the structure of conductive lines formed in the dielectric layer 406. The opening 428, together with the mask 420, has the structure of another conductive line formed in the dielectric layer 406. As shown in Fig. 39, the opening 428 may have a sidewall that is offset from a sidewall of the mask 420, for example, due to accuracy limitations of the processing technologies or variances in the equipment used to manufacture the semiconductor device.

[0101] Then in Fig. 40, the middle layer 424 is etched using the patterned upper layer 426 as an etch mask, so that the pattern of the upper layer 426 is transferred to the middle layer 424.

[0102] After the middle layer 424 has been etched through, Fig. 41, the lower layer 422 is patterned, using the middle layer 424 as an etch mask. During the patterning of the lower layer 422, the upper layer 426 may be consumed. By patterning the lower layer 422, a portion of the upper surface of the mask 420 and portions of a top surface of the first cap layer 414 are exposed. After the lower layer 422 has been patterned, remaining portions of the middle layer 424 may be removed.

[0103] In Fig. 42, the lower layer 422 is then used as an etch mask for etching the underlying first capping layer 414, the etch stop layer 412, and the second capping layer 410. Any suitable etching method may be used, such as wet etching or dry etching. In some embodiments, the etching process is anisotropic. As shown in Fig. As shown in Figure 42, the mask 420 prevents a portion 440 of the etch stop layer 412 and the second cap layer 410 located beneath the mask 420 from being etched. Therefore, a conductive line later formed in the opening 428 has a smaller dimension than if the mask 420 is not formed. Thus, no line end (e.g., an unused line end) is formed.

[0104] After the first cover layer 414, the etch stop layer 412 and the second cover layer 410 have been structured, Fig. 43, remaining portions of the lower layer 422 are removed, for example, in a stripping process. In some embodiments, the lower layer is consumed during patterning of the first cap layer 414, the etch stop layer 412, and the second cap layer 410, and a separate step for removing the lower layer 422 may be omitted.

[0105] Then, the hard mask layer 408 is etched so that the openings 428 and 429 extend into the hard mask layer 408. The Fig. 44A and Fig. 44B show a top view and a cross-sectional view of a semiconductor device 400 after etching the hard mask layer 408. The section of Fig. 44A runs along the line A - A', which in the plan view of Fig. 44B. Any suitable etching method may be used for the hard mask layer 408, such as wet etching or dry etching. In some embodiments, the etching process is anisotropic. During the etching of the hard mask layer 408, the mask layer 420, the etch stop layer 412, and the first capping layer 414 are consumed. By consuming the mask layer 420, the etch stop layer 412, and the first capping layer 414, the hard mask layer 408 and the second capping layer 410 have a substantially uniform height after the etching process is completed. Therefore, a later etch of the dielectric layer 406 to form a conductive line therein may be performed more reliably and with fewer defects, and / or the etch window may be maintained and is not undesirably reduced, which could lead to difficulties in filling the openings in the dielectric layer 406 with a conductive material.

[0106] In the Fig. 45A and Fig. 45B, the dielectric layer 406 is etched using the hard mask layer 408 as an etch mask. The etching process extends the openings 428 and 429 into the dielectric layer 406. Any suitable etching technique may be used. In some embodiments, the etching process is anisotropic. By etching the dielectric layer 406, a top surface of the dielectric layer 404 and the via 416 is exposed. Although the via 416 in Fig. 45B has a rectangular top-down view, in other embodiments, the via 416 may have any suitable shape, such as a circle, an oval, a polygon, a square, or the like.

[0107] In Fig. 46, the openings 428 and 429 are filled with a conductive material 430. For example, in some embodiments, one or more capping layers (not shown) may be deposited in the openings 428 and 429 and on top of the hard mask layer 408. The capping layers may include TiO, TiN, TaO, TaN, or the like, and may provide diffusion barrier, adhesion, and / or seed layers. The capping layers may be deposited using a suitable process, such as PVD, CVD, ALD, and the like. The remaining portions of the openings 428 and 429 may then be filled with the conductive material 430, for example, using a plating process. The capping layers and / or the conductive material 430 contact the via 416. Any suitable conductive material 430, such as copper or another material, may be used. The resulting structure is shown in Fig. 46 shown.

[0108] In Fig. 47, excess conductive material 430 is removed, for example, using a grinding process, such as chemical mechanical polishing. Remaining portions of the hard mask layer 408 may also be removed using the grinding process. After completion of the grinding process, conductive lines 444 have been formed in the dielectric layer 406. Top surfaces of the conductive lines 444 are planar with a top surface of the dielectric layer 406. Due to the use of the mask 420, a conductive line 444A has a length that is shortened compared to the length a conductive line 444A would have if the mask 420 had not been used. A region 442 shows a portion of the conductive line 444A that would have been formed without the mask 420, but was not formed in the semiconductor device 400.

[0109] During later processing, additional dielectric layers, with or without conductive lines, may be formed over the dielectric layer 406. External contacts may be formed over the semiconductor device 400, through which the semiconductor device 400 may be electrically and / or physically connected to additional devices.

[0110] Fig. Figure 48 shows a method according to some embodiments. In step 502, an optimal width of a line cut is determined, such as in connection with the Fig. 33A and Fig. 33B. In step 504, an opening with the optimal width is patterned in a first cover layer, such as in Fig. 35. In step 506, the opening is filled with a mask material, such as that shown in Fig. 36. In step 508, the mask material is planarized, as shown, for example, in Fig. 37. In step 510, a photoresist is deposited and patterned to create openings, as shown, for example, in the Fig. 38 to 41. In step 512, an etching process is performed using the mask, as shown, for example, in Fig. 42. In step 514, a hard mask layer is patterned, as shown, for example, in the Fig. 44A and Fig. 44B. In step 516, a dielectric layer is patterned using the patterned hard mask, as shown, for example, in the Fig. 45A and Fig. 45B. In step 518, the openings in the dielectric layer are filled with a conductive material, such as that shown in Fig. 46. ​​In step 520, the conductive material is planarized, as shown, for example, in Fig. 47 is shown.

[0111] As set forth herein, a semiconductor device and a method for fabricating the same are disclosed. A patterning process is performed to pattern lines in a target layer of a semiconductor device. In some embodiments, a dielectric layer is patterned by photolithography, and a patterned sacrificial material (sometimes referred to as a reversal material) is deposited over the patterned dielectric layer. After the sacrificial material is deposited, it is patterned by creating an opening therein. The patterned dielectric layer and the sacrificial material are then used to pattern an underlying mask layer, which in turn is used to pattern a target layer with only one patterning step.Subsequently, one or more conductive materials may be filled into the openings of the low-k dielectric layer to define interconnect lines, wherein the interconnect lines have a line cut defined by the patterned sacrificial material. The conductive lines may have a smaller pitch than that achievable with other similar patterning processes and / or the interconnect lines may be formed with a smaller pitch using a simplified patterning process. For example, the target layer may be patterned with only one patterning process to form conductive lines with a small pitch having one or more line cuts. Because the target layer is patterned in only one patterning process and / or using a simplified process, as set forth herein, higher pattern accuracy may be achieved.Therefore, multiple interconnect lines can be manufactured to have the same or substantially the same dimensions, allowing greater control over the resistance of the interconnect lines.

[0112] In some embodiments, a target width of a line cut of a line end may be specified, for example, using a virtual layout, as set forth herein. During fabrication of a semiconductor device, a mask having the specified optimal width may be fabricated. The mask may prevent patterning of a portion of a dielectric layer beneath the mask, thereby avoiding the formation of a line end in the dielectric layer during later processing. As set forth herein, the RC behavior of the semiconductor device may be improved, and / or the size or mounting area required for the device may be reduced.

[0113] The invention is defined by the main claim. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] Procedure with the following steps: Forming a first mask layer (108) over a target layer (102, 2316, 2416, 2516); forming a plurality of spacers (124) over the first mask layer (108); Producing a second mask layer (130) over the plurality of spacers (124) and structuring the second mask layer (130) to create a first opening (134), wherein in a plan view a major axis of the opening (134) extends in a direction that is perpendicular to a major axis of a spacer (124) of the plurality of spacers (124); Depositing a sacrificial material (136) in the opening (134), wherein the sacrificial material (136) directly contacts the first mask layer (108); Structuring the sacrificial material (136); Etching the first mask layer (108) using the plurality of spacers (124) and the patterned sacrificial material (136); Etching the target layer (102, 2316, 2416, 2516) using the etched first mask layer (108) to create second openings (150) in the target layer (102, 2316, 2416, 2516); and Filling the second openings (150) in the target layer (102, 2316, 2416, 2516) with a conductive material (164). [2] The method of claim 1, wherein patterning the sacrificial material (136) comprises patterning the sacrificial material (136) with an extreme ultraviolet photolithographic process or an immersion exposure process. [3] The method of claim 1 or 2, wherein gaps between adjacent spacers (124) of the plurality of spacers (124) have a pitch of 85.5 nm or less. [4] The method of any preceding claim, wherein the sacrificial material (136) comprises an inorganic material having a high etch selectivity with respect to a material used to form the first mask layer (108). [5] A method according to any one of the preceding claims, wherein the sacrificial material (136) is a metal oxide, an inorganic oxide or a metal nitride. [6] The method of any preceding claim, further comprising planarizing the sacrificial material (136), wherein after planarizing, a top surface of the sacrificial material (136) is flush with a top surface of the plurality of spacers (124). [7] The method of any preceding claim, wherein after patterning the sacrificial material (136), the sacrificial material (136) is located over one or more gaps between adjacent spacers (124). [8] The method of any preceding claim, wherein forming the plurality of spacers (124) over the target layer (102, 2316, 2416, 2516) comprises: forming a triple layer (120) over a spacer layer (110); Structuring an upper layer (116) of the triple layer (120) by lithography; Etching a middle layer (114) of the triple layer (120) through the patterned upper layer (116); Etching a lower layer (112) of the triple layer (120) through the middle layer (114); and Etching the spacer layer (110) through the lower layer (112) to produce the plurality of spacers (124). [9] The method of any preceding claim, further comprising planarizing the conductive material (164) to form a plurality of interconnect lines (2312), wherein two adjacent interconnect lines (2312) of the plurality of interconnect lines (2312) have a physical gap separating the two adjacent interconnect lines (2312), the gap being located in a region underlying a portion of the sacrificial material (136) remaining after patterning the sacrificial material (136). [10] The method of any preceding claim, wherein the second mask layer (130) comprises a bottom layer (126), a middle layer (128) and a top layer (132). [11] The method of claim 10, wherein, in the structuring of the second mask layer (130), the upper layer (132) is structured using a photolithographic process so that the first opening (134) is created in the upper layer (132). [12] The method of claim 11, wherein after patterning the upper layer (132), its structure is transferred to the middle layer (128) by etching. [13] The method of claim 12, wherein an etching process is performed to transfer the structure of the middle layer (128) to the lower layer (126) and to extend the opening (134) through the lower layer (126). [14] The method of claim 13, wherein the etching process consumes the upper layer (132). [15] Method according to one of the preceding claims 10 to 14, wherein after the deposition of the sacrificial material (136) the lower layer (126) and the middle layer (128) are removed. [16] The method of any preceding claim, wherein a masking layer (140) is formed over the spacers (124), the first mask layer (108) and the sacrificial material (136). [17] The method of claim 16, wherein a second opening (146) is formed in the masking layer (140) and is extended into the sacrificial material (136). [18] The method of claim 17, wherein the second opening (146) exposes a side wall of one or more spacers (124). [19] The method of claim 17 or 18, wherein the second opening (146) exposes portions of the mask layer (108). [20] Method according to one of the preceding claims 16 to 19, wherein the masking layer (140) is removed during the structuring of the sacrificial material (136).

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