Semiconductor device performance improvement

Abstract

Structure comprehensive: an active region on a substrate (70), the active region comprising a channel region; a gate structure over the channel region of the active area, the gate structure comprising: an intermediate layer (80) over the active region; a conformal dielectric layer (120) over the intermediate layer (80); and a gate electrode layer (122) over the intermediate layer (80); and wherein a ratio of a peak concentration of hydrogen in the intermediate layer (80) to a peak concentration of hydrogen in the conformal dielectric layer (120) is in a range of 2.7 to 5.

Description

[0001] The invention relates to a structure comprising an active region on a substrate, wherein the active region has a channel region; a gate structure over the channel region of the active region, wherein the gate structure comprises; an interlayer over the active region; a conformal dielectric layer over the interlayer; and a gate electrode layer over the interlayer; and wherein a ratio of a peak concentration of hydrogen in the interlayer to a peak concentration of hydrogen in the conformal dielectric layer is in a range from approximately 0.1 to approximately 5. A semiconductor structure is known from US 2016 / 0 247 907 A1. Further semiconductor structures are known from US 2005 / 0 164 445 A1, DE 695 29 942 T2 or US 6 913 961 B2. GENERAL STATE OF THE ART

[0002] As the semiconductor industry has progressed into nanometer technology process nodes in the pursuit of higher density, higher performance, and lower cost, both manufacturing and design challenges have resulted in the development of three-dimensional designs such as a fin field-effect transistor (FinFET). FinFET devices typically comprise semiconductor fins with high aspect ratios in which source / drain and channel regions are formed. A gate is formed over and along the sides of the fin structure (e.g., cladding), taking advantage of the increased area of the channel to produce faster, more reliable, and better-controlled semiconductor transistor devices. However, as scaling decreases, new challenges emerge. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. The Fig. 1A-C, 2A-B, 3A-B, 4A-B, 5A-B, 6A-B, 7A-B, and 8A-B are various views of respective intermediate structures at intermediate stages in an example process of forming a semiconductor device according to some embodiments. Fig. 9 is a cross-sectional view of a channel region of a transistor device after a high pressure anneal process according to some embodiments. Fig. 10 is a cross-sectional view of the channel region of the transistor device after a post-anneal treatment process according to some embodiments. Fig. 11 includes example hydrogen concentration profiles in devices formed with and without an example post-anneal treatment process according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional functions may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.

[0005] Further, for ease of discussion, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device during use or operation of the device, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. The term "hydrogen" may include hydrogen (H), deuterium (D), and other isotopes of hydrogen.

[0006] Methods for forming a semiconductor device, such as including a fin field-effect transistor (FinFET), along with structures formed by the methods, are described herein. In particular, one embodiment of the present disclosure provides a method for improving FinFET performance through a high-pressure annealing process and a post-annealing treatment process for threshold voltage recovery.

[0007] Example embodiments described herein are described in the context of forming gate structures on FinFETs. Implementations of some aspects of the present disclosure may be used in other processes, in other devices, and / or for other layers. For example, other example devices may include planar FETs, horizontal gate wraparound (HGAA) FETs, vertical gate wraparound (VGAA) FETs, and other devices. Some variations of the example methods and structures are described. One of ordinary skill in the art will readily understand that other modifications may be made and are contemplated within the scope of other embodiments.Although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than what is described herein.

[0008] The Fig. 1A-C to 8A-B are views of respective intermediate structures at intermediate stages in an example process for forming a semiconductor device according to some embodiments. In particular, the Fig. 1A-C to 8A-B Stages of forming FinFET structures using an exchange gate process.

[0009] The Fig. 1A, Fig. 1B and Fig. 1C illustrate different views of an intermediate structure in a stage in an example process for forming a semiconductor device according to some embodiments. Fig. 1A and Fig. 1B are different cross-sectional views of the intermediate structure and Fig. Figure 1C is a perspective view of the intermediate structure.

[0010] The fins 74 are located on a semiconductor substrate 70. The isolation regions 78 are located on the semiconductor substrate 70 and are arranged between the adjacent fins 74. The fins 74 each protrude above and between adjacent isolation regions 78. Gate stacks (or more generally, gate structures), each comprising an interface dielectric 80, a dummy gate layer 82, and a mask 84, are formed along sidewalls and above top surfaces of the fins 74. The source / drain regions 52a-f are arranged in the corresponding regions of the fins 74.

[0011] Fig. 1C further illustrates reference sections used in other figures. Section AA is in a plane along, for example, channels in a fin 74 between opposing source / drain regions 52a-c. Section BB is in a plane perpendicular to section AA and across source / drain region 52a and source / drain region 52d in adjacent fins 74. Figures ending with an "A" in the label illustrate cross-sectional views of various instances of processing corresponding to section AA, and figures ending with a "B" in the label illustrate cross-sectional views of various instances of processing corresponding to cross-section BB. In some figures, some reference numbers of components or features illustrated herein may be omitted to avoid obscuring other components or features; this is for ease of illustrating the figures.

[0012] The semiconductor substrate 70 may be or include a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, or the like, which may be doped or undoped (e.g., with a p-type or an n-type dopant). The semiconductor material of the semiconductor substrate 70 may include an elemental semiconductor including silicon (Si) or germanium (Ge); a compound semiconductor; an alloy semiconductor; or a combination thereof.

[0013] The fins 74 may be formed from the semiconductor substrate 70, for example, by etching trenches between the fins 74. The isolation regions 78 may be formed in the trenches between the fins 74. The isolation regions 78 may comprise or be an insulating material such as an oxide (such as silicon oxide), a nitride, the like, or a combination thereof. The fins 74 protrude between adjacent isolation regions 78, which may at least partially define the fins 74 as active areas on the semiconductor substrate 70. The fins 74 and isolation regions 78 may be formed by any acceptable processes and may comprise any acceptable material. In some examples, the fins 74 may comprise heteroepitaxial structures (e.g., a material that is lattice-mismatched to the semiconductor material of the semiconductor substrate 70) or other structures.

[0014] The gate stacks are located above and extend laterally perpendicular to the fins 74. The interface dielectric 80, the dummy gate layer 82, and the mask 84 for the gate stacks may be formed by sequentially forming corresponding layers and then patterning these layers into the gate stacks. The interface dielectric 80 may comprise or be silicon oxide, silicon nitride, the like, or multiple layers thereof. The dummy gates may comprise or be silicon (e.g., polysilicon) or another material. The mask 84 may comprise or be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or a combination thereof. The layers for the interface dielectrics 80, the dummy gate layers 82, and the masks 84 may be deposited and then patterned using any acceptable processes to form the mask 84, dummy gate layer 82, and the interface dielectric 80 for each gate stack.

[0015] The Fig. 2A and Fig. 2B illustrate the formation of gate spacers 86 along the gate stacks, epitaxial source / drain regions 92 in the fins 74, a contact etch stop layer (CESL) 96 over various components, and a first interlayer dielectric (ILD) 100 over the CESL 96. The gate spacers 86 are formed along sidewalls of the gate stacks (e.g., sidewalls of the interface dielectric 80, the dummy gate layer 82, and the mask 84) and over the fins 74. The remaining gate spacers 86 may remain along sidewalls of the fins 74, for example, depending on the height of the fins 74, above the isolation regions 78. The gate spacers 86 may be formed by conformally depositing one or more layers for the gate spacers 86 and, for example, anisotropic etching of the one or more layers.The one or more layers for the gate spacers 86 may include or be silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, the like, multiple layers thereof, or a combination thereof.

[0016] After forming the gate spacers 86, recesses are formed in the fins 74 using the gate stacks and gate spacers 86 as masks, and epitaxial source / drain regions 92 are epitaxially grown in the recesses. The recesses, and therefore the epitaxial source / drain regions 92, are formed in the fins 74 on opposite sides of the gate stacks. The recessing may be performed by an etching process, and due to the nature of the etching process, the recesses may have various cross-sectional profiles. The epitaxial source / drain regions 92 may comprise or be silicon germanium, silicon carbide, silicon phosphorus, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The epitaxial source / drain regions 92 may extend beyond sidewalls and top surfaces of the fins 74 (e.g.,increased) and may have facets that may correspond to crystalline planes of the semiconductor substrate 70.

[0017] One of ordinary skill in the art will also readily understand that the recessing and epitaxial growth of the source / drain regions 92 may be omitted, and that source / drain regions may be formed by implanting dopants into the fins 74 using the gate stacks and gate spacers 86 as masks. In some examples where epitaxial source / drain regions 92 are implemented, the epitaxial source / drain regions 92 may also be doped, for example, by in-situ doping during epitaxial growth and / or by implanting dopants into the epitaxial source / drain regions 92 after epitaxial growth. Therefore, a source / drain region can be defined by doping (e.g., optionally by implantation and / or in situ during epitaxial growth) and / or optionally by epitaxial growth, which can further define the active area in which the source / drain region is defined.

[0018] The CESL 96 is conformally deposited on surfaces of the epitaxial source / drain regions 92, sidewalls and top surfaces of the gate spacers 86, top surfaces of the mask 84, and top surfaces of the isolation regions 78. In general, an etch stop layer may provide a mechanism to stop an etch process when, for example, contacts or vias are formed. An etch stop layer may be formed from a dielectric with a different etch selectivity from adjacent layers or components. The CESL 96 may include or be silicon nitride, silicon carbonitride, carbonitride, the like, or a combination thereof. The first ILD 100 is then deposited over the CESL 96. The first ILD 100 may include silicon dioxide, a low-k dielectric (e.g.,a material with a dielectric constant lower than silicon dioxide), such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), SiO. x C y , spin-on glass, spin-on polymer, silicon carbon material, a compound thereof, a composition thereof, the like, or a combination thereof.

[0019] The Fig. 3A and Fig. 3B illustrates the removal of portions of the first ILD 100, portions of the CESL layer 96, and the mask 84 to expose the dummy gate layer 82. The first ILD 100 and the CESL 96 are formed such that upper surfaces are coplanar with upper surfaces of the dummy gate layers 82. A planarization process, such as CMP, may be performed to align the upper surface of the first ILD 100 and the CESL 96 with the upper surfaces of the dummy gate layers 82. The CMP may also remove the mask 84 (and in some cases, upper portions of the gate spacers 86) on the dummy gate layers 82. Accordingly, upper surfaces of the dummy gate layers 82 are exposed by the first ILD 100 and the CESL 96.

[0020] The Fig. 4A and Fig. 4B illustrate the removal of the dummy gate layers 82, such as through one or more etch processes, after the dummy gate layers 82 have been exposed by the first ILD 100 and the CESL 96. The dummy gate layers 82 may be removed through an etch process selective to the dummy gate layers 82, with the interface dielectrics 80 acting as etch stop layers. The recesses 101 are formed between the gate spacers 86.

[0021] In some examples, the interface dielectrics 80 may be removed by an etch process that is selective to the interface dielectrics 80, and channel regions of the fins 74 are exposed through the recesses 101. Another replacement interface dielectric 80 may then be formed in the recesses 101 over the channel regions of the fins 74. In some embodiments, the replacement interface dielectric 80 may be a native oxide, such as silicon oxide, formed over the fins 74. In some embodiments, the replacement interface dielectric 80 may comprise or be silicon oxide, silicon nitride, the like, or multiple layers thereof, and may be thermally and / or chemically grown on the fins 74 or conformally deposited by PECVD, ALD, or another deposition technique.

[0022] In some examples, the interface dielectrics 80 are not removed and remain, so that corresponding exchange gate structures are formed on the interface dielectrics 80, as described below. The following description may refer to an interface dielectric 80 applied to the interface dielectrics 80 as described with respect to the Fig. 1A-C, and / or applies to the exchange interface dielectric 80 described above.

[0023] The Fig. 5A and Fig. 5B illustrate a gate dielectric layer 120 formed in the recesses 101. The gate dielectric layer 120 may be conformally deposited in the recesses 101 where gate stacks have been removed (e.g., on top surfaces of the isolation regions 78, sidewalls, and top surfaces of the interface dielectric 80 above the fins 74, along the channel regions and sidewalls of the gate spacers 86), and on the top surfaces of the first ILD 100, the CESL 96, and gate spacers 86. The gate dielectric layer 120 may be or include silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), a high-k dielectric, multiple layers thereof, or other dielectric. A high-k dielectric may have a k value greater than about 7.0. The high-k dielectric may comprise a metal oxide or a metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb or a combination thereof.Gate dielectric layer 120 may be deposited by ALD, PECVD, MBD, or another deposition technique. In some embodiments, gate dielectric layer 120 may include a high-k dielectric layer formed immediately above interface dielectric 80 over the channel regions of fin 74.

[0024] After forming the gate dielectric layer 120, an annealing process and / or a post-annealing treatment process may be performed. The annealing process and / or the post-annealing treatment process may be performed immediately after forming the gate dielectric layer 120 and / or after any process following the formation of the gate dielectric layer 120. Additional details of an exemplary annealing process and post-annealing treatment process are described in more detail below.

[0025] Then, if implemented, one or more conformal layers 121 may be conformally deposited on the gate dielectric layer 120. The one or more conformal layers 121 may include any combination of one or more barrier layers, capping layers, and workfunction tuning layers. Each implemented conformal layer 121 may be conformally deposited on the gate dielectric layer 120 or the preceding conformal layer 121, as appropriate. The barrier layer, capping layer, and workfunction tuning layer may each include or be tantalum, tantalum nitride, titanium, titanium nitride, the like, or a combination thereof, and may be deposited by ALD, PECVD, MBD, or another deposition technique.

[0026] A conductive fill material 122 is formed over the one or more conformal layers 121, if implemented, or the gate dielectric layer 120. The conductive fill material 122 may fill the remaining recesses 101 where the dummy gate stacks were removed. The conductive fill material 122 may be or include a metal-containing material such as Co, Ru, Al, W, Cu, multiple layers thereof, or a combination thereof. The conductive fill material 122 may be deposited by ALD, PECVD, MBD, PVD, or another deposition technique.

[0027] Excess conductive fill material 122, one or more conformal layers 121, and the gate dielectric layer 120 over the top surfaces of the first ILD 100, the CESL 96, and the gate spacers 86 are removed by a planarization process such as a CMP. The replacement gate structures, each comprising a gate dielectric layer 120 and a gate electrode, wherein the gate electrode is considered to comprise the conductive fill material 122 and one or more conformal layers 121, may therefore be formed as illustrated in the Fig. 6A and Fig. 6B can be formed.

[0028] A second ILD 130 is formed over the first ILD 100, the replacement gate structures, gate spacers 86, and the CESL 96. Although not illustrated, in some examples, an etch stop layer (ESL) may be deposited over the first ILD 100, etc., and the second ILD 130 may be deposited over the ESL. If implemented, the etch stop layer may include or be silicon nitride, silicon carbonitride, silicon carbon monoxide, carbonitride, the like, or a combination thereof, and may be deposited by CVD, PECVD, ALD, or another deposition technique. The second ILD 130 may comprise silicon dioxide, a low-k dielectric such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiO x C y, spin-on glass, spin-on polymer, silicon-carbon material, a compound thereof, a composition thereof, the like, or a combination thereof. The second ILD 130 may be deposited by spin-on, CVD, FCVD, PECVD, PVD, or another deposition technique.

[0029] As shown in the Fig. 7A and Fig. 7B, conductive features 134 are formed by the second ILD 130 and the first ILD 100 at the epitaxial source / drain regions 92. The conductive features 134 may, for example, include an adhesion and / or barrier layer and conductive material on the adhesion and / or barrier layer. In some examples, the conductive features 134 may include silicide regions 136 on the epitaxial source / drain regions 92, as illustrated. The adhesion and / or barrier layer may be conformally deposited in openings exposing the epitaxial source / drain regions 92 and over the second ILD 130. The adhesion and / or barrier layer may be or include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide, the like, or a combination thereof, and may be deposited by ALD, CVD, or another deposition technique.The silicide regions 136 may be formed on upper portions of the epitaxial source / drain regions 92 by reacting upper portions of the epitaxial source / drain regions 92 with the adhesion and / or barrier layer. An anneal may be performed to facilitate the reaction of the epitaxial source / drain regions 92 with the adhesion and / or barrier layer. The conductive material may be deposited on the adhesion and / or barrier layer and may fill the openings. The conductive material may be or include tungsten, copper, aluminum, gold, silver, alloys thereof, the like, or a combination thereof, and may be deposited by CVD, ALD, PVD, or another deposition technique. After the material of the conductive features 134 is deposited, excess material may be removed using a planarization process, such as CMP, for example, such that upper surfaces of the conductive features 134 and the second ILD 130 may be coplanar.The conductive features 134 may be or may be referred to as contacts, plugs, etc.

[0030] Subsequently, additional conductive features are formed within multiple intermetallization dielectric (IMD) layers to implement electrical connections for the devices. For example, twelve IMD layers can be formed over transistors in an SRAM device. Fig. 8A and Fig. 8B illustrate subsequent IMDs 140, 142 formed over the second ILD 130. The conductive features 144 are formed therein, for example, by a damascene process (e.g., a dual damascene process) according to the device design.

[0031] According to some embodiments, an annealing process and a post-annealing treatment process are performed to improve device performance. In some embodiments, the annealing process and the post-annealing treatment process are performed each time after the gate dielectric layer 120 is formed. The annealing process and the post-annealing treatment process may improve charge carrier mobility in the device.

[0032] In some embodiments, the annealing process is a high-pressure annealing (HPA) process. The high-pressure annealing process may be performed to introduce small-sized atoms to passivate dangling bonds at an interface and reduce interface defects. For example, small-sized atoms, such as hydrogen or deuterium, may be introduced into the interface region (e.g., the interface dielectric 80) between the channel region of the fins 74 and the gate dielectric layer 120 to reduce interface defects and improve charge carrier mobility in the transistor.

[0033] In some embodiments, the high-pressure annealing process is performed in a thermal process chamber, such as a multi-substrate processing furnace, a single-substrate process tool, or other suitable tools. In some embodiments, the high-pressure annealing process may be performed in an environment of hydrogen (H2), deuterium (D2), nitrogen (N2), argon (Ar), helium (He), or a combination thereof. The high-pressure annealing process may be performed at a pressure in a range of about 506.6 kPa to about 7092.8 kPa. The process temperature may be in a range of about 200°C to about 700°C. In some embodiments, the process temperature may be in a range of about 350°C to about 500°C, such as about 400°C.The high pressure annealing process may be carried out for a period of time ranging from about 3 minutes to about 4 hours, such as from about 10 minutes to about 1 hour.

[0034] Fig. 9 is a cross-sectional view of a portion of the channel region in a fin 74 and the replacement gate structure (e.g., the interface dielectric 80 and the gate dielectric layer 120) of the transistor device after the high-pressure anneal process, according to some embodiments. Hydrogen 150 is introduced into the gate dielectric layer 120 and the interface dielectric 80, or the interface between the channel region of the fins 74 and the gate dielectric layer 120.

[0035] The channel material in the fins 74 may be or include silicon, germanium, a Group IV compound such as silicon germanium (SiGe), a III-V compound, another semiconductor material, or a combination thereof.

[0036] The gate dielectric layer 120 may, for example, be a high-k dielectric layer of the FinFET. In some embodiments, the gate dielectric layer 120 may comprise a high-k dielectric, such as a metal oxide or metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof, silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), or a combination thereof. In some embodiments, the gate dielectric layer 120 may have a thickness in a range from about 1 nm to about 10 nm.

[0037] The interface dielectric 80 may comprise a native oxide formed over the channel regions of the fins 74, or a silicon oxide, silicon nitride, or the like formed by thermal growth, chemical growth, or a conformal deposition process such as ALD, CVD, and the like. In some embodiments, the interface dielectric 80 may have a thickness ranging from greater than 0 nm to about 5.0 nm, such as about 1.0 nm.

[0038] The hydrogen atoms in the interface dielectric 80 and / or an interface between the channel region of the fin 74 and the gate dielectric layer 120 can reduce interface defects and improve charge carrier mobility in the transistor. However, hydrogen atoms in the gate dielectric layer 120 or the bulk portion of the gate dielectric layer 120 can cause various problems, such as shifting the threshold voltage (Vt) of the transistor, particularly in P-type transistors.

[0039] Measurements show that after the high-pressure annealing process, hydrogen has a higher peak concentration at the interface dielectric 80 and a lower peak concentration at the bulk gate dielectric layer 120. In a structure where the bulk gate dielectric layer 120 has a thickness of approximately 10 nm and the interface dielectric 80 has a thickness of 2.5 nm, the total amount of hydrogen atoms in the bulk gate dielectric layer 120 is higher than the total amount of hydrogen in the interface dielectric 80. In some embodiments, a P-type field-effect transistor has an initial threshold voltage of approximately 0.7 volts. Hydrogen introduced during the high-pressure annealing can cause the threshold voltage to shift by approximately 120 mV.

[0040] Some embodiments provide a post-anneal treatment process to restore the threshold voltage shift caused by the high-pressure annealing process. In some embodiments, the post-anneal treatment process is a rapid thermal process, a laser annealing process, or the like. The post-anneal treatment process reduces the hydrogen atoms in the bulk gate dielectric layer 120 while maintaining the hydrogen concentration in the interface dielectric 80.

[0041] In some embodiments, the post-annealing treatment process is performed in a thermal process chamber, such as a multi-substrate processing furnace, a single-substrate process tool, or other suitable tools such as laser annealing tools. In some embodiments, the high-pressure annealing process and the post-annealing treatment process may be performed back-to-back in the same tool.

[0042] The post-anneal treatment process may be performed in an environment comprising one or more of nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), deuterium (D2), or a combination thereof. The composition of the environment may be determined prior to the process by the amount of hydrogen in the bulk gate dielectric layer 120 and the interface dielectric 80. For example, the environment may comprise nitrogen (N2), argon (Ar), helium (He), or a combination, but without hydrogen (H2) or deuterium (D2) to reduce the hydrogen concentration in the bulk gate dielectric layer 120. For example, the environment comprises nitrogen. In another embodiment, the environment may comprise nitrogen (N2), argon (Ar), helium (He), or a combination, and with some hydrogen (H2) or deuterium (D2) to maintain the hydrogen concentration in the interface dielectric 80.In some examples, the composition of an environment may be adjusted, for example, by increasing or decreasing the ratio of H2 or D2 during the process to achieve a target effect, such as achieving a hydrogen concentration level in the interfacial dielectric 80. In some embodiments, the ratio of H2 or D2 in the processing gas to a total processing gas ranges from approximately 0 by flow volume to approximately 100 by flow volume.

[0043] In some embodiments, the post-annealing treatment process is performed in a range of approximately 0.133 Pa to approximately 506.6 kPa. In some embodiments, the post-annealing treatment process is performed at a low pressure, for example, in a range of 0.133 kPa to 1.33 kPa. In some embodiments, the post-annealing treatment process may be performed at a normal atmosphere, such as 101.3 kPa. In one embodiment, the post-annealing treatment process may be performed at a high pressure, such as in a range of 101.3 kPa to 506.6 kPa.

[0044] In some embodiments, the process temperature for the post-annealing treatment process ranges from approximately 200°C to approximately 700°C. If the process temperature is too low, atoms such as hydrogen atoms may not acquire sufficient kinetic energy to move into the dielectric layers. If the process temperature is too high, some layers in the substrate may melt or cause undesirable physical or chemical reactions. In some embodiments, the process temperature may range from approximately 350°C to approximately 500°C, such as approximately 400°C.

[0045] The post-anneal treatment process may be performed for a time ranging from about 5 minutes to about 150 minutes. In some embodiments, the post-anneal treatment process is performed for a time ranging from about 10 minutes to about 90 minutes. In some embodiments, the time duration of the post-anneal treatment process may be sufficiently long to retain hydrogen at an interface between the channel region and the gate dielectric layer 120 (e.g., in the interface dielectric 80) during the removal of hydrogen from the bulk portion of the gate dielectric layer 120.

[0046] Fig. 10 is a cross-sectional view of the portion of the channel region and the replacement gate structure of the transistor device after the post-anneal treatment process, according to some embodiments. Measurement shows that, after the post-anneal treatment process, hydrogen remains at a higher peak concentration at the interface dielectric 80 and at a lower peak concentration at the bulk gate dielectric layer 120. However, the total amounts of hydrogen atoms in the interface dielectric 80 and the bulk gate dielectric layer 120 are substantially the same. In some embodiments, the total amount of hydrogen atoms in the bulk gate dielectric layer 120 is lower than the total amount of hydrogen in the interface dielectric 80. The threshold voltage shift is, in some cases, within a range of approximately 10 mV to approximately 20 mV.In some embodiments, the initial threshold voltage prior to the high-pressure annealing process is approximately 0.7 volts. The final threshold voltage shift after the post-annealing treatment process may range from approximately 1.4% to approximately 2.9% of the initial threshold voltage.

[0047] In some embodiments, the annealing and post-annealing processes reduce the peak hydrogen concentration and total hydrogen in the bulk gate dielectric layer 120 and the interface dielectric 80. In some embodiments, the annealing and post-annealing processes increase the ratios of peak concentrations and total hydrogen numbers in the interface dielectric 80 and the bulk gate dielectric layer 120. In some embodiments, after the annealing and post-annealing processes are performed, the ratio of a peak concentration of hydrogen in the interface dielectric 80 to a peak concentration of hydrogen in the bulk gate dielectric layer 120 is in a range from about 0.1 to about 5, such as about 2.7.In some embodiments, the ratio of a peak concentration of hydrogen in the interface dielectric 80 to a peak concentration of hydrogen in the bulk gate dielectric layer 120 is greater than 2.5, such as in a range from greater than 2.5 to about 5. In some embodiments, the ratio of a peak concentration of hydrogen in the interface dielectric 80 to a peak concentration of hydrogen in the bulk gate dielectric layer 120 is greater than or equal to about 2.7, such as in a range from about 2.7 to about 5. In some embodiments, after the annealing and post-annealing processes are performed, the ratio of the total hydrogen numbers in the interface dielectric 80 and in the bulk gate dielectric layer 120 is in a range from about 0.1 to about 2, such as about 1.0.

[0048] Fig. 11 includes example hydrogen concentration profiles in devices with and without the post-annealing treatment process. Profile 202 shows a hydrogen concentration profile in the bulk gate dielectric layer 120 and the interface dielectric 80 without performing the annealing process and the post-annealing process described above. Profile 204 shows a hydrogen concentration profile in the bulk gate dielectric layer 120 and the interface dielectric 80 after performing the annealing process and the post-annealing process described above.

[0049] The concentration value Po bulk indicates a peak concentration in the bulk gate dielectric layer 120 in profile 202. The concentration value Po IL indicates a peak concentration in the interface dielectric 80 in profile 202. The concentration value P bulkindicates a peak concentration in the bulk gate dielectric layer 120 in profile 204. The concentration value P IL indicates a peak concentration in the interface dielectric 80 in profile 204. In the example of Fig. 11, the ratio of peak concentrations in the interface dielectric is 80 and in the bulk gate dielectric layer 120 (Po IL : Butt bulk ) is approximately 2.5 when the annealing process and the post-annealing process are not performed; the ratio of peak concentrations in the interface dielectric 80 and in the bulk gate dielectric layer 120 (p IL :P bulk ) is approximately 2.7 when the annealing process and the post-annealing process are performed. The ratio of peak concentrations in the interface dielectric 80 and in the bulk gate dielectric layer 120 increases by approximately 8.0% when the annealing process and the post-annealing process are performed.

[0050] In the example shown in Fig. 11, the total hydrogen atoms in the gate dielectric layer 120 and in the interface dielectric 80 are approximately 1.13×10 5 and approximately 9.95×10 4 , if the annealing process and the post-annealing process are not performed. The total hydrogen atoms in the gate dielectric layer 120 and the interface dielectric 80 are approximately 1.04×10 5 and approximately 9.63×10 4 if the annealing process and the post-annealing process are not carried out. If in the example of Fig. 11 When the annealing process and the post-annealing process are not performed, the ratio of the total hydrogen in the interface dielectric 80 and the bulk gate dielectric layer 120 is approximately 0.88, and when the annealing process and the post-annealing process are performed, the ratio of the total hydrogen in the interface dielectric 80 and the bulk gate dielectric layer 120 is approximately 1.0. The ratio of the total hydrogen in the interface dielectric 80 and the bulk gate dielectric layer 120 increases by approximately 13.7% when the annealing process and the post-annealing process are performed.

[0051] The inventors have observed that the increased ratio of the total hydrogen numbers or peak concentrations in the interface dielectric 80 and the bulk gate dielectric layer 120 reduces the threshold voltage shift caused by the high pressure annealing process.

[0052] With reference to Fig. 8A, the bulk gate dielectric layer 120 covers the interface dielectric 80 and sidewalls of the spacers 86. In some embodiments, the hydrogen concentration within the bulk gate dielectric layer 120 decreases in a direction away from the interface dielectric 80. Accordingly, the hydrogen concentration in the bulk gate dielectric layer 120 is higher at the portion near a bottom of the spacer 86 (near the epitaxial source / drain regions 92) than at the portion near the second ILD 130.

[0053] In some embodiments, the annealing process and the post-annealing treatment process may be performed after the conductive features in the topmost IMD are completed, as shown in the Fig. 8A and Fig. 8B. In another embodiment, the annealing process and the post-annealing treatment process are performed after forming the gate dielectric layer 120, as shown in FIGS. Fig. 5A and Fig. 5B, and before forming the one or more conformal layers 121 and the conductive fill material 122. In another embodiment, the annealing process and the post-annealing treatment process may be performed after the replacement gate structures are completed, as shown in FIGS. Fig. 6A and Fig. 6B. In another embodiment, the annealing process and the post-annealing treatment process may be performed as shown in the Fig. 7A and Fig.7B after forming the conductive features in the second ILD 130. The annealing process and the post-annealing treatment process may be performed back-to-back, such as back-to-back in the same process chamber. In some examples, the annealing process and the post-annealing treatment process may be performed separately at a suitable time.

[0054] Some embodiments provide a heat treatment process following a high-pressure anneal process to retain hydrogen at the interface between a channel region and a gate dielectric layer in a field-effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The heat treatment process may reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and heat treatment process may be performed at any time after the formation of the gate dielectric layer and therefore cause no interruption in the existing process flow.

[0055] One embodiment provides a method comprising performing a high pressure anneal process on a structure having a conformal dielectric layer formed over a channel region of an active area to introduce hydrogen at an interface between the conformal dielectric layer and the channel region, and, after performing the high pressure anneal process, performing a post-anneal treatment to reduce hydrogen in the conformal dielectric layer.

[0056] Another embodiment provides a structure. The structure includes an active region on a substrate. The active region has a channel region. The structure further includes a gate structure over the channel region of the active region. The gate structure includes an interlayer over the active region, a conformal dielectric layer over the interlayer, and a gate electrode layer over the interlayer. A ratio of a peak concentration of hydrogen in the interlayer to a peak concentration of hydrogen in the conformal dielectric layer ranges from about 0.1 to about 5.

[0057] Yet another embodiment provides a method comprising forming an active region on a substrate, the active region having a channel region, forming a dummy gate structure over the channel region of the active region, removing the dummy gate structure to expose the channel region of the active region, forming an interlayer over the channel region of the active region, forming a conformal dielectric layer over the interlayer, performing a high pressure anneal process to introduce hydrogen into the interlayer, and, after performing the high pressure anneal process, performing a post-anneal treatment to reduce hydrogen in the conformal dielectric layer.

[0058] Yet another embodiment provides a method comprising forming a gate structure over a channel region of an active area, the gate structure comprising a conformal dielectric layer over the active area, annealing the gate structure at a first pressure to introduce hydrogen at an interface between the conformal dielectric layer and the channel region, and performing a post-anneal treatment on the gate structure at a second pressure to reduce hydrogen in the conformal dielectric layer, the first pressure being higher than the second pressure.

Claims

[1] Structure comprising: an active region on a substrate (70), the active region comprising a channel region; a gate structure over the channel region of the active area, the gate structure comprising: an intermediate layer (80) over the active region; a conformal dielectric layer (120) over the intermediate layer (80); and a gate electrode layer (122) over the intermediate layer (80); and wherein a ratio of a peak concentration of hydrogen in the intermediate layer (80) to a peak concentration of hydrogen in the conformal dielectric layer (120) is in a range of 2.7 to 5. [2] The structure of claim 1, wherein the intermediate layer (80) comprises a native oxide, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. [3] The structure of claim 1 or 2, wherein the intermediate layer (80) has a thickness in a range of greater than 0 nm to 5 nm. [4] The structure of any preceding claim, wherein the conformal dielectric layer (120) comprises a high-k dielectric layer, a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, or a combination thereof. [5] The structure of any preceding claim, wherein a ratio of a total hydrogen number in the intermediate layer (80) to a total hydrogen number in the conformal dielectric layer (120) is in a range of 0.1 to 2. [6] A structure according to any preceding claim, wherein the hydrogen concentration in the conformal dielectric layer (120) is higher at a location near the intermediate layer (80) than at a location remote from the intermediate layer (80). [7] Method comprising: Performing a high-pressure annealing process on a structure having an interlayer (80) formed over a channel region of an active area and a conformal dielectric layer (120) formed over the interlayer (80), wherein the high-pressure annealing process introduces hydrogen into an interface between the interlayer (80) and the channel region, and wherein the high-pressure annealing process is performed at a pressure in a range of 506.6 kPa to 7092.8 kPa; and, after performing the high pressure annealing process, performing a post-annealing treatment to reduce hydrogen in the conformal dielectric layer (120), and after performing the post-annealing treatment, forming a gate electrode (122) over the conformal dielectric layer (120). [8] The method of claim 7, wherein performing the post-annealing treatment comprises: Exposing the structure to an environment comprising at least one of nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), deuterium (D2), or a combination thereof. [9] A method according to claim 7 or 8, wherein performing the treatment after annealing comprises: Exposing the structure to an environment at a temperature in the range of 200 °C to 700 °C. [10] A method according to any one of the preceding claims 7 to 9, wherein the post-annealing treatment is carried out at a pressure in a range of 0.133 Pa to 506.6 kPa. [11] A method according to any one of the preceding claims 7 to 10, wherein the high pressure annealing process and the post-annealing treatment are carried out in the same chamber. [12] A method according to any one of the preceding claims 7 to 10, wherein the high pressure annealing process and the post-annealing treatment are carried out in different chambers. [13] The method of claim 7, wherein performing the high pressure annealing process comprises: Exposing the structure to a glowing environment of hydrogen (H2), deuterium (D2), nitrogen (N2), argon (Ar), helium (He), or a combination thereof. [14] A method according to any one of claims 7 to 13, wherein: after performing the post-annealing treatment, a ratio of a peak concentration of hydrogen in the intermediate layer (80) to a peak concentration of hydrogen in the conformal dielectric layer (120) is in a range of 0.1 to 5. [15] A method according to any one of claims 7 to 14, wherein: after performing the post-annealing treatment, a ratio of a total hydrogen number in the intermediate layer (80) to a total hydrogen number in the conformal dielectric layer (120) is in a range of 0.1 to 2. [16] Method comprising: Forming a dielectric structure over a channel region of an active region, the dielectric structure comprising an intermediate layer (80) over the active region and a conformal dielectric layer (120) over the intermediate layer (80); Annealing the dielectric structure at a first pressure to introduce hydrogen into an interface between the intermediate layer (80) and the channel region, the first pressure being in a range from 506.6 kPa to 7092.8 kPa; and Performing a post-anneal treatment on the dielectric structure at a second pressure to reduce hydrogen in the conformal dielectric layer (120), the first pressure being higher than the second pressure, and after performing the post-anneal treatment, forming a gate electrode over the conformal dielectric layer (120). [17] The method of claim 16, wherein the second pressure is in a range of 0.133 Pa to 506.6 kPa. [18] A method according to claim 16 or 17, wherein the post-annealing treatment comprises an environment of nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), deuterium (D2) or a combination thereof. [19] The method of claim 18, wherein the environment is at a temperature in a range of 350°C to 500°C.

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