Device for supporting an error correction code and test procedure therefor

Abstract

Device for supporting a test mode for memory testing, wherein the device (10; 10b) comprises the following: a memory (300; 300b) designed to receive and store write data (D_WR) and to output read data (D_RD) having up to M error bits from the stored write data (D_WR), where M is a non-negative integer; an error correction code (ECC) engine (100; 100b), wherein the error set correctable by the ECC engine (100; 100b) is N bits, the ECC engine being designed to generate the write data (D_ENC, D_WR) by encoding input data (D_IN) and to generate output data (D_OUT) by error-bit correction of N bits or less contained in received data (D_RX), where N is a positive integer; and an error insertion circuit (200; 200b) designed to provide the error correction code engine (100; 100b) with the read data (D_RD) as the receive data (D_RX) in a normal mode and to provide the error correction code engine (100; 100b) with data determined by inverting at least one bit of NM bits of the read data (D_RD) as the receive data (D_RX) in test mode , where the M bits represent a maximum number of bit errors that can occur in memory (300; 300b) during a manufacturing process of memory (300; 300b), and the (NM) bits represent an error range for errors that can occur in memory (300; 300b) after manufacturing.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS BACKGROUND

[0001] The concepts according to the invention relate to devices for supporting an error correction code and, in particular, to devices for supporting an error correction code and / or a test procedure therefor.

[0002] An error correction code (ECC) system can be used to correct errors that occur in data transmitted through a noisy channel. For example, the ECC system can be used to correct an error in data received over a communication channel, or it can be used to correct an error in data read from memory. According to the ECC system, a codeword can be generated that adds redundancy to the original data, and the original data can be recovered by correcting the error in the data that passed through the noisy channel. The ECC system can have a correctable error set, and the larger the correctable error set, the greater both the resources required to implement the ECC system and the amount of redundancy added to it can be.Therefore, the number of errors occurring in the noisy channel can be limited to a range of error rates that can be corrected by a given ECC system. For example, if the noisy channel is a memory in the ECC system, it may be necessary to verify whether the number of errors that can occur in the memory is within the range of error rates that can be corrected by a given ECC system.

[0003] US 8 914 687 B2 discloses the provision of test coverage for integrated ECC logic and embedded memory. SUMMARY

[0004] The invention is described in the attached set of claims. The concepts according to the invention provide devices to support an error correction code (ECC), and in particular devices to support an ECC in order to easily determine whether a noisy channel has a range of error quantity that can be corrected by an ECC system, and / or a test method for this.

[0005] According to an exemplary embodiment, a device for supporting a test mode for memory testing may comprise: a memory configured to receive and store write data and to output read data from the stored write data; an error correction code (ECC) engine configured to generate the write data by encoding input data and to generate output data by error-bit correction of N bits or less contained in received data, where N is a positive integer; and an error insertion circuit configured to provide the ECC engine with the read data as the received data in a normal mode and to provide the ECC engine with data determined by inverting at least one bit of less than N bits of the read data as the received data in test mode.

[0006] According to an exemplary embodiment, a device for supporting a test mode for memory testing may comprise: a memory designed to receive and store write data and to output read data from the stored write data; an error correction code (ECC) engine designed to generate coded data by encoding input data and to generate output data by error-bit correction of N bits or less contained in read data, where N is a positive integer; and an error insertion circuit designed to provide the memory with the coded data as the write data in a normal mode and to provide the memory with data determined by inverting at least one bit of less than N bits of the coded data as the write data in test mode.

[0007] According to an exemplary embodiment, a method for testing a device comprising an error correction code (ECC) engine and a memory designed to correct error bits of N bits or less, where N is a positive integer, may include: generating write data by encoding input data from the ECC engine; writing the write data to the memory, reading the write data, and outputting the read data; and generating output data by correcting an error in the read data from the ECC engine, wherein writing the write data and outputting the read data include inverting at least one bit of less than N bits in at least one of the two, the write data and the read data. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Exemplary embodiments of the concepts according to the invention will be better understood with reference to the following detailed description in conjunction with the associated drawings: Fig. Figure 1 is a block diagram of a device for supporting an error correction code (ECC) according to an exemplary embodiment of the concepts according to the invention; Fig. 2A and Fig. 2B are block diagrams that provide examples of the device of Fig. 1. Illustrate, according to an exemplary embodiment of the concepts according to the invention; Fig. 3A and Fig. 3B are block diagrams that show examples of an error insertion circuit. Fig. 1. Illustrate, according to an exemplary embodiment of the concepts according to the invention; Fig. 4 is a view of examples of write data of the Fig. 2A in a test mode according to an exemplary embodiment of the concepts according to the invention; Fig. Figure 5 is a flowchart illustrating a method for testing a device to support the ECC, according to an exemplary embodiment of the concepts according to the invention; Fig. 6A and Fig. Figure 6B are flowcharts illustrating a method for testing a device to support the ECC, according to an exemplary embodiment of the concepts according to the invention; Fig. Figures 7A to 7C are block diagrams illustrating examples of bit selection circuits according to exemplary embodiments of the concepts according to the invention; Fig. Figure 8 is a flowchart illustrating a method for testing a device to support the ECC, according to an exemplary embodiment of the concepts according to the invention; Fig. 9 is a flowchart that provides an example of the S80 operation of the Fig. 8 illustrates, according to an exemplary embodiment of the concepts according to the invention; Fig. Figure 10 is a block diagram illustrating an example of a device for supporting the ECC, according to an exemplary embodiment of the concepts according to the invention; and Fig. Figure 11 is a block diagram illustrating an example of a device for supporting the ECC, according to an exemplary embodiment of the concepts according to the invention. DETAILED DESCRIPTION

[0009] Fig. Figure 1 is a block diagram of a device 10 for supporting an error correction code (ECC) according to an exemplary embodiment of the concepts according to the invention. More precisely, it shows Fig. 1 the device 10, which has a memory 300 as a noisy channel in an ECC system. As in Fig. As shown in Figure 1, the device 10 can include an ECC engine 100, an error insertion circuit 200 and / or the memory 300.

[0010] The device 10 can be any device 10 comprising the memory 300 to store input data D_IN and to use the stored data as output data D_OUT. In some exemplary embodiments, the device 10 can be a system-on-a-chip (SoC), such as an application processor (AP), but is not limited to this. In some exemplary embodiments, the device 10 can be a semiconductor memory device for storing the input data D_IN and outputting the output data D_OUT according to an external instruction, such as dynamic random-access memory (DRAM), flash memory, and the like, but is not limited to this.In some exemplary embodiments, the device 10 can be a storage system for storing the input data D_IN and outputting the output data D_OUT in response to a host request, such as a solid state drive (SSD), a memory card and the like, but is not limited to this.

[0011] The ECC engine 100 can generate coded data D_ENC by encoding the input data D_IN and can generate the output data D_OUT by decoding the received data D_RX. Memory 300 in the device 10 can be a noisy channel. For example, noise can occur due to defects in memory cells storing data in memory 300, and / or due to a defect in a path along which write data D_WR, provided to memory 300, moves, or in a path along which read data D_RD, output from memory 300, moves, but is not limited to these.The device 10 can include the ECC engine 100, and the ECC engine 100 can generate the coded data D_ENC by adding redundancy to the input data D_IN to be stored in memory 300, and it can generate the output data D_OUT by correcting errors based on the redundancy in the received data D_RX received from memory 300. In some exemplary embodiments, the coded data D_ENC can be provided to memory 300 in units of codewords that include a portion of the input data D_IN (or data generated therefrom) and redundancy.

[0012] The ECC Engine 100 can perform encoding and decoding in various ways. For example, the ECC Engine 100 can perform encoding and decoding based on an ECC, such as an AN code, BCH code, Hamming code, Polar code, Turbo code, and / or the like, but is not limited to these. In some exemplary embodiments, the ECC Engine 100 may include a processor and memory to store instructions to be executed by the processor, or it may include logic circuitry, which in some exemplary embodiments is designed by logic synthesis.

[0013] The ECC Engine 100 can have a correctable error set. For example, if the ECC Engine 100 is designed according to a 2-bit correction ECC system, it can detect and correct errors of less than 2 bits in the received data D_RX, such as 1-bit and 2-bit errors. In some exemplary embodiments, the ECC Engine 100 can detect that the amount of errors in the received data D_RX exceeds the amount of errors that the ECC Engine 100 can correct, or it can generate a signal indicating that error correction is not possible.

[0014] As the amount of errors that can be corrected by the ECC engine 100 increases, the redundancy added to the encoded data D_ENC can increase, and the storage capacity of memory 300 for storing the input data D_IN can decrease. With an increase in the amount of errors that can be corrected by the ECC engine 100, the resources consumed by the ECC engine 100, such as area, power, and / or time, can also increase. Accordingly, the ECC engine 100 can be designed to have a correctable error set determined based on a noisy channel, that is, a bit error rate (BER) occurring in memory 300. For example, if the expected BER of memory 300 is 0.2 and the data units processed by ECC engine 100 are 10-bit data units, then the correctable error set of ECC engine 100 may be designed to be 2 bits or more.If the ECC engine 100 has a correctable error set of N bits (N > 0), the ECC system can be called an N-bit correction ECC system, and the ECC engine 100 can be called the N-bit correction ECC engine 100.

[0015] The fault insertion circuit 200 can selectively insert a fault according to a mode signal C_MODE between the ECC engine 100 and the memory 300. As shown in Fig. As shown in Figure 1, the error insertion circuit 200 can receive the coded data D_ENC from the ECC engine 100 and provide the write data D_WR to the memory 300. The error insertion circuit 200 can also receive the read data D_RD from the memory 300 and provide the receive data D_RX to the ECC engine 100. The mode signal C_MODE can specify a mode of the device 10, and the device 10 can operate in a normal mode and in a test mode according to the mode signal C_MODE. The error insertion circuit 200 can include a processor and a memory to store instructions to be executed by the processor, or it can include a logic circuit, which in some exemplary embodiments is designed by logic synthesis.

[0016] The error insertion circuit 200 can include at least one bit error circuit BE. The bit error circuit BE can receive an input signal IN indicating the value of a bit and can output a signal OUT indicating the value of a bit. As in Fig. As shown in Figure 1, the bit error circuit BE can include an inverter INV and a switch SW, and the output signal OUT can be the same as the input signal IN, or it can be the same as a signal obtained by inverting the input signal IN. In some exemplary embodiments, the switch SW of the bit error circuit BE can be controlled based on the mode signal C_MODE input to the error insertion circuit 200. For example, if the mode signal C_MODE indicates a normal mode, the switch SW can be controlled so that the output signal OUT is the same as the input signal IN. For example, if the mode signal C_MODE indicates a test mode, the switch SW can be controlled so that the output signal OUT is the same as the signal obtained by inverting the input signal IN.When the output signal OUT, which matches the input signal IN, is output, the bit error circuit BE can be represented as disabled, and when the output signal OUT, which is determined by inverting the input signal IN, is output, the bit error circuit BE can be represented as enabled.

[0017] The error insertion circuit 200 can use the bit error circuit BE to insert an error into data received by the error insertion circuit 200 in a test mode. In some exemplary embodiments, the error insertion circuit 200 can generate the write data D_WR by inserting at least one bit error into the coded data D_ENC provided by the ECC engine 100 in response to the mode signal C_MODE indicating a test mode, as described below with reference to Fig. 2A is described. In some exemplary embodiments, the error insertion circuit 200, in response to the mode signal C_MODE indicating the test mode, can also generate the receive data D_RX by inserting at least one bit error into the read data D_RD provided from memory 300, as described below with reference to Fig. 2B is described. Furthermore, in some exemplary embodiments, the error insertion circuit 200 can insert at least one bit error into the encoded data D_ENC or the read data D_RD in response to the mode signal C_MODE indicating the test mode.

[0018] Therefore, at least one bit error can be inserted by the error insertion circuit 200 in test mode, and thus the memory 300 can be verified as acceptable or defective. Defects causing errors in the memory 300 can include not only an initial defect occurring during the manufacturing process of the memory 300, but also a subsequent defect occurring during the period in which the memory 300 or the device 10 comprising the memory 300 is shipped and / or used. Thus, during the manufacturing process of the memory 300 or the device 10, it can be verified whether the memory 300 has a certain error margin within a quantity of errors that can be corrected by the ECC engine 100. For example, if the ECC engine 100 corresponds to a 3-bit correction ECC system, the memory 300 can be manufactured to have a 1-bit error margin.Accordingly, memory 300 can normally be used even if a 1-bit error occurs due to a defect in memory 300. Therefore, during the manufacturing process of memory 300 or device 10, memory 300 can be tested to ensure that only those memory 300 units with a 2-bit error or less are shipped, that is, memory 300 units with a 1-bit error margin. This means that memory 300 or device 10 can be tested during the manufacturing process so that any error is corrected by the ECC engine 100 for 3-bit correction, preventing any problems in device 10, even if a 1-bit error occurs while the device 10 is in use by a user.

[0019] The error insertion circuit 200 can artificially reduce the error set of the ECC system that can be corrected by the ECC engine 100 by inserting an error set corresponding to the error span of memory 300. For example, if device 10 includes the 3-bit correction ECC engine 100 and the error insertion circuit 200 inserts a 1-bit error, then memory 300 can always be considered to contain a 1-bit error, and thus device 10 can function as a 2-bit ECC system. Additionally, in a test mode, the error insertion circuit 200 can insert an error between the ECC engine 100 and memory 300 using the bit error circuit BE with a simple structure, as shown in Fig. Figure 1 shows that the acceptance or failure of memory 300 or device 10 can be determined depending on whether the error correction by the ECC engine 100 is successful. For example, if memory 300 is manufactured to have a 1-bit error span, the error insertion circuit 200 can, in a test mode to test memory 300 or device 10, insert a 1-bit error and determine whether the ECC engine 100 successfully corrects the error. Thus, memory 300 in the device 10, which includes memory 300, can be easily verified to support ECC, and the productivity of device 10 can be improved accordingly. Fig. Figure 1 shows an example of memory 300 as a noisy channel, it is understood that an ECC system which provides an additional margin against an error quantity predictable from a channel with or without noise, for example a communication channel, can be readily verified according to exemplary embodiments of the concepts according to the invention.

[0020] Memory 300 can receive and store write data D_WR and can output read data D_RD from the stored write data D_WR. Memory 300 can comprise multiple memory cells for storing data. In some exemplary embodiments, memory 300 can include non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nano-floating-gate memory (NFGM), polymer random access memory (PoRAM), magnetoresistive random access memory (MRAM), or ferroelectric random access memory (FRAM)). In some exemplary embodiments, memory 300 may include volatile memory (e.g., DRAM, static RAM, mobile DRAM, synchronous double data rate DRAM (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphic DDR (GDDR) SDRAM, or Rambus DRAM (RDRAM)).

[0021] Fig. 2A and Fig. 2B are block diagrams that provide examples for device 10 of the Fig. 1 illustrate, according to an exemplary embodiment of the concepts according to the invention. As above with reference to Fig. As described in section 1, the devices 10a and 10b of the Fig. 2A and Fig. 2B each support a normal mode and a test mode according to the mode signal C_MODE, which is provided externally. Here, in Fig. 2A and Fig. 2B the same reference symbols as in Fig. 1. The same elements, and therefore no detailed descriptions of them will be given here.

[0022] With reference to Fig. 2A The device 10a can comprise an ECC engine 100a, an error insertion circuit 200a, and a memory 300a. The error insertion circuit 200a can provide the coded data D_ENC, which is provided to the memory 300a from the ECC engine 100a in normal mode as the write data D_WR, and / or it can provide the memory 300a with the write data D_WR, which is generated by inserting at least one bit error into the coded data D_ENC. The ECC engine 100a can receive the read data D_RD, which is output from the memory 300a, and accordingly, the read data D_RD and the received data D_RX of the Fig. 1. match each other in a test mode.

[0023] In a test mode, the input data D_IN can be stored in memory 300a, and then the output data D_OUT can be generated from the read data D_RD output from memory 300a. For example, after an operation to sequentially store identical input data D_IN across the entire memory 300a has been performed, the output data D_OUT can be generated from the read data D_RD output sequentially from the entire memory 300a. In some exemplary embodiments, the input data D_IN can be compared with the output data D_OUT generated by the ECC engine 100a, and if the input data D_IN and the output data D_OUT do not match, it can be determined that memory 300a is defective.If the ECC engine 100a cannot correct an error in the read data D_RD, that is, if an error in the read data exceeds an error quantity that the ECC engine 100a can correct, the ECC engine 100a can, in some exemplary embodiments, output a signal indicating this. Furthermore, a signal output from the ECC engine 100a can be used to determine that the memory 300a is defective.

[0024] The error insertion circuit 200a can change the position of at least one bit error that was inserted in a test mode. For example, the error insertion circuit 200a can write the write data D_WR, generated by inserting at least one bit error into the coded data D_ENC, into a specific area of ​​memory 300a and can output the read data D_RD by reading data stored in that specific area of ​​memory 300a. Next, the error insertion circuit 200a can write the write data D_WR, which includes at least one bit error inserted at a different position than the previous one in the same coded data D_ENC, into the same area as the previous area of ​​memory 300a and can read data stored in the same area as the previous area of ​​memory 300a, thereby outputting the read data D_RD.If a genuine bit error, actually caused by memory 300a, occurs in the same memory location where the bit error was inserted by error insertion circuit 200a, the bit error inserted by error insertion circuit 200a cannot serve as an error span of memory 300a. Accordingly, an operation to write the generated write data D_WR and output the read data D_RD can be repeated, while changing the position at which the bit error is inserted for the same range and the same encoded data D_ENC. Examples of changing the position of a bit error by error insertion circuit 200b are given later below with reference to [reference missing]. Fig. 3A and Fig. 3B and Fig. 4 described.

[0025] With reference to Fig. In 2B, the device 10b can comprise an ECC engine 100b, an error insertion circuit 200b, and a memory 300b. The error insertion circuit 200b can provide the read data D_RD, which in a normal mode of the ECC engine 100b is provided from the memory 300b as the receive data D_RX, and / or it can provide the ECC engine 100b with the receive data D_RX, which is generated by inserting at least one bit error into the read data D_RD. The memory 300b can receive the write data D_WR, which is output by the ECC engine 100b. According to the example of Fig. 2B can be used to process the encoded data D_ENC and the write data D_WR. Fig. 1. agree with each other in a test mode.

[0026] As above with reference to Fig. As described in section 2B, the error insertion circuit 200b can change the position of at least one bit error that was inserted in a test mode. For example, the error insertion circuit 200b can provide the ECC engine 100b with the receive data D_RX, which is generated by inserting at least one bit error into the read data D_RD, which is output by reading a range into which the write data D_WR is written. Subsequently, the error insertion circuit 200b can supply the ECC engine 100b with the receive data D_RX, which includes at least one bit error that has been inserted at a different position than the previous position into the read data D_RD, which is output by reading the same range as before. In device 10a of the Fig. 2A The read data D_RD can be output multiple times by writing the write data D_WR multiple times to an area identical according to the position of the bit error and reading the written data multiple times. However, the read data D_RD in device 10b of the Fig. 2B can be output multiple times by writing the data D_WR once to an identical area and reading the written data multiple times. As explained later below with reference to Fig. As described in 6B, a read operation for an identical area of ​​memory 300b can also be performed once in the device 10b. Fig. 2B will be carried out.

[0027] The following mainly describes exemplary embodiments of the concepts according to the invention with reference to an example in which the error insertion circuit 200a stores the write data D_WR, which is generated by inserting a bit error into the coded data D_ENC in memory 300a in a test mode, but is not limited to this. The exemplary embodiments of the concepts according to the invention can also be applied to a device which includes the entire device 10b of the Fig. 2B and the fault insertion circuits 200a and 200b of the Fig. 2A and Fig. 2B includes.

[0028] Fig. 3A and Fig. 3B are block diagrams that show examples of an error insertion circuit 200 of the Fig. 1. Illustrate, according to exemplary embodiments of the concepts according to the invention. Illustrate in more detail. Fig. 3A and Fig. 3B Examples for the fault insertion circuit 200a of the Fig. 2A. As above with reference to Fig. As described in section 2A, the fault insertion circuits 200a' and 200a'' of the Fig. 3A and Fig. 3B Insert at least one bit error into n-bit encoded data D_ENC in a test mode to generate n-bit write data D_WR (n > 0). The following are described below. Fig. 3A and Fig. 3B with reference to Fig. 2A described, and duplicate descriptions of Fig. 3A and Fig. 3B will not be performed here.

[0029] With reference to Fig. In 3A, the error insertion circuit 200a' can comprise one bit selection circuit 210' and m bit error circuits 220' (n > m > 0). The m bit error circuits 220' can comprise multiple bit error circuits BE1 to BEm. The bit selection circuit 210' can receive the mode signal C_MODE and can provide up to m bit error circuits 220' with selection signals SEL. In response to the mode signal C_MODE indicating a normal mode, the bit selection circuit 210' can generate a selection signal SEL, thus disabling all m bit error circuits 220'; that is, a bit signal of the encoded data D_ENC is directly output as a bit signal of the write data D_WR. On the other hand, the bit selection circuit 210' can, in response to thisthat the mode signal C_MODE indicates a test mode, generate the selection signal SEL so that at least one of the m bit error circuits 220' is activated, that is, a bit signal determined by inverting the bit signal of the encoded data D_ENC is output as the bit signal of the write data D_WR.

[0030] As in Fig. As illustrated in Figure 3A, the m bit error circuits 220' can be arranged in n bits of the encoded data D_ENC. The arrangement of the m bit error circuits 220' shown in Fig. Figure 3A is only an example, and the m bit error circuits 220' can, for example, be arranged in sequential m-bits D_ENC [n:n-m+1] from a most significant bit (MSB) of the encoded data D_ENC, or they can be arranged in sequential m-bits D_ENC [m:1] from the MSB of the encoded data D_ENC, in contrast to the one shown in Fig. 3A shown.

[0031] The bit selection circuit 210' can simultaneously activate bit error circuits of the number of bits among the m bit error circuits 220' in a test mode, corresponding to an error span of memory 300a. For example, if an error span required in memory 300a is one bit, the bit selection circuit 210' can activate one of m bit error circuits 220'. Additionally, the bit selection circuit 210' can modify a bit error circuit to be activated. For example, the bit selection circuit 210' can generate the selection signal SEL, so that different bit error circuits are activated each time in the same encoded data D_ENC, which is continuously written K times to an identical region of memory 300a. As will be explained later below with reference to Fig. As described in section 4, the number of times K the write data D_WR, which is generated from the same encoded data D_ENC, is written to the identical area of ​​memory 300a can be determined based on the number of correctable bits of the ECC engine 100a and the error range of memory 300a.

[0032] With reference to Fig. 3B can include the error insertion circuit 200a'', a bit selection circuit 210'', and n bit error circuits 220''. That is, the error insertion circuit 200a'' can include the n bit error circuits 220'', each corresponding to n bits of the encoded data D_ENC. The n bit error circuits 220'' can include multiple bit error circuits BE1 to BEn. The bit selection circuit 210'' can receive the mode signal C_MODE and can provide n bits of the selection signal SEL to each of the n bit error circuits 220''. The bit selection circuit 210'' can generate the selection signal SEL, so that all n bit error circuits 220'' are deactivated in response to the mode signal C_MODE indicating a normal mode. On the other hand, the bit selection circuit 210'' can generate the selection signal SEL, so that at least one of the n bit error circuits 220'' is activated in response to the mode signal C_MODE indicating a test mode.

[0033] The Fig. 4 is a view of examples of write data D_WR of the Fig. 2A in a test mode according to an exemplary embodiment of the concepts according to the invention. In more detail, it shows Fig. 4 write data D_WR, which are generated from the same coded data D_ENC and continuously written to memory 300a of the Fig. 2A should be written. In the example Fig. 4. The ECC engine 100a of the Fig. 2A corresponds to a 2-bit correction ECC system, and an error span required in memory 300a can be 1 bit. Accordingly, the error insertion circuit 200a can generate the write data D_WR in which 1-bit errors are inserted by inverting 1 bit in the encoded data D_ENC. Fig. Figure 4, a shaded portion, represents the bit that is inverted by the error insertion circuit 200a. The following section describes this. Fig. 4 with reference to Fig. 2A described.

[0034] The number of times K that the write data D_WR, generated from the same encoded data D_ENC, is written to the identical area of ​​memory 300a can be determined based on the number of correctable bits of the ECC engine 100a and the error margin of memory 300a. As in the example of the Fig. As shown in Figure 4, if N is 2 and the error span of memory 300a is 1 bit, memory 300a, which outputs the read data D_RD containing two or more real bit errors due to a defect in memory 300a, can be determined to be defective. If a bit error is inserted at the same position as the real bit errors due to the defect in memory 300a by the error insertion circuit 200a, the effect of the bit error insertion can be eliminated. This is because the read data D_RD contains fewer bit errors than the real bit errors, either because the real bit errors are corrected by the inserted bit error, or because the inserted bit error and the real bit errors are contained within the read data D_RD as a single bit error. Accordingly, in a process of the ECC engine 100a, which processes the read data D_RD, errors in the read data D_RD can be corrected normally, and the memory 300a, which is to be determined as defective, can be determined as acceptable.To prevent a bit error inserted by the error insertion circuit 200a from being placed in the same position as a real bit error, the error insertion circuit 200a can change the position at which the bit error is inserted. In an example of the... Fig. 4. The error insertion circuit 200a can determine that the memory 300a is defective, which outputs the read data D_RD, which includes two real bit errors, and sequentially generates the write data D_WR, which includes bit errors at three different positions.

[0035] With reference to Fig. 4. The write data D_WR can comprise the number x-bit data bits and the number y-bit parity bits (n = x + y), and the error insertion circuit 200a can insert a bit error by inverting the first data bit D1 of the data bits. The write data D_WR, determined by inverting the first data bit D1 of the encoded data, can be written to memory 300a, and the read data D_RD can be provided to the ECC engine 100a by reading data stored in a region of memory 300a into which the write data D_WR is written.

[0036] The error insertion circuit 200a can then insert a bit error by inverting a third data bit D3 of the data bits. The write data D_WR, determined by inverting the third data bit D3 from the encoded data, can be written to memory 300a, and the read data D_RD can be provided to the ECC engine 100a by reading data stored in the area of ​​memory 300a into which the write data D_WR is written.

[0037] Finally, the error insertion circuit 200a can insert a bit error by inverting the fifth data bit D5 of the data bits. The write data D_WR, obtained by inverting the fifth data bit D5 from the encoded data, can be written to memory 300a, and the read data D_RD can be provided to the ECC engine 100a by reading data stored in the area of ​​memory 300a where the write data D_WR is written. It is understood that positions where bit errors occur in Fig. 4 can be inserted, are just one example, and that bit errors can be inserted at any one of three different positions.

[0038] If the n-bit error correction ECC engine 100a is used and the error span of memory 300a is 1 bit, K, which is the number of repetitions of write and read operations for an identical area of ​​memory 300a, can be n+1. In some exemplary embodiments, it may be unlikely that all bit errors inserted at different locations will be in the same position as actual bit errors if n is relatively large, that is, if the data units processed by the ECC engine 100a are relatively large. Therefore, the error insertion circuit 200a may perform fewer than three, for example, two, write and read operations instead of three. In the example of the Fig. 4 For example, it may be unlikely that there are actual bit errors in both the first data bit D1 and the third data bit D3, so that a test period for memory 300a or device 10a can be shortened by performing only two write and read operations.

[0039] The Fig. Figure 5 is a flowchart illustrating a method for testing a device to support the ECC, according to an exemplary embodiment of the concepts according to the invention. More precisely, it shows Fig. 5 a method for testing the device 10a of the Fig. 2A in a test mode. The following is shown below. Fig. 5 with reference to Fig. 2A described.

[0040] In operation S110, an initialization operation can be performed. For example, as in Fig. As shown in Figure 5, a variable i is set to 1, and the variable i can specify the number of operations performed to insert a bit error at different positions in the encoded data D_ENC, that is, the number of times a subsequent series of operations (S121 to S126) is performed.

[0041] Operation S121 allows for the inversion of at least one bit of the encoded data D_ENC. For example, the error insertion circuit 200a can generate the write data D_WR by inverting at least one bit of the encoded data D_ENC in response to the mode signal C_MODE indicating a test mode.

[0042] An operation to write the data D_WR to memory 300a can be performed in operation S122, and an operation to read the data written to memory 300a can be performed in operation S123. The data D_RD can be output from memory 300a by reading data stored in the area of ​​memory 300a where the data D_WR is written.

[0043] Operation S124 can correct an error in the read data D_RD. For example, ECC engine 100a can receive the read data D_RD from memory 300a and correct an error in the read data D_RD. Then, operation S125 can determine whether the error correction is successful. For example, ECC engine 100a may have a limited number of correctable bits, and therefore, error correction of the error-containing read data D_RD, which exceeds the number of correctable bits, may fail. If the error correction fails, operation S130 can then be performed to determine whether memory 300a is defective. If, on the other hand, the error correction is successful, operation S126 can then be performed.

[0044] Operation S126 can determine whether the variable i equals K. That is, it can determine whether write and read operations have been performed K times. As above with reference to Fig. As described in section 4, K can be determined based on the correctable error set of the ECC engine 100a and the error range of the memory 300a. If the variable i is equal to K, operation S140 can then be performed, and an operation to determine that the memory 300a is acceptable can be carried out within operation S140. If, on the other hand, the variable i is not equal to K, the variable i can be incremented by one in operation S127, and then operation S121 can be carried out. In operation S121, a bit at a position different from the position of the previously inverted bit can be inverted.

[0045] Fig. 6A and Fig. Figure 6B are flowcharts illustrating a method for testing a device to support the ECC, according to an exemplary embodiment of the concepts according to the invention. More precisely, they show Fig. 6A and Fig. 6B a method for testing the device 10b of the Fig. 2B in a test mode. The following are shown below. Fig. 6A and Fig. 6B with reference to Fig. 2B described. Furthermore, the same reference symbols as in Fig. 2B the same elements, and therefore no duplicate descriptions are given here. Fig. 6A and Fig. 6B.

[0046] With reference to Fig. 6A, an initialization operation can be performed in operation S210. For example, as in Fig. As shown in Figure 6A, the variable i is set to 1, and the variable i can specify the number of operations performed to insert a bit error at different positions into the read data D_RD, that is, the number of times a series of operations (S231 to S235) is performed.

[0047] In operation S220, the write data D_WR can be written. As in Fig. As illustrated in Figure 6A, the write data D_WR can be written once to verify a specific area of ​​memory 300b, and an operation to output the read data D_RD by reading the stored write data D_WR can be repeated, as described later below. In comparison to the example of Fig. 5 can be the number of write operations itself in the example of the Fig. 6A and Fig. 6B can be reduced, and thus the time required to test the 300B memory can be relatively shortened.

[0048] In operation S231, the stored write data D_WR can be read. The read data D_RD can be output from memory 300b by reading the data stored in the area of ​​memory 300b where the write data D_WR is written.

[0049] In operation S232, at least one bit of the read data D_RD can be inverted. For example, the error insertion circuit 200b can generate the receive data D_RX by inverting at least one bit of the read data D_RD in response to the mode signal C_MODE indicating a test mode.

[0050] Operation S233 can correct an error in the received data D_RX. For example, ECC engine 100b can receive the received data D_RX from error insertion circuit 200b and correct an error in the received data D_RX. Operation S234 can then determine whether the error correction is successful. For example, ECC engine 100b may have a limited number of correctable bits, and therefore, error correction of the received data D_RX containing errors exceeding this number may fail. If the error correction fails, operation S240 can then be performed to determine whether memory 300b is defective. If, on the other hand, the error correction is successful, operation S235 can then be performed.

[0051] Operation S235 can determine whether the variable i equals K. That is, it can determine whether read operations have been performed K times. As above, with reference to Fig. As described in section 4, K can be determined based on the correctable error set of the ECC engine 100b and the error range of the memory 300b. If the variable i is equal to K, operation S250 can then be performed, and an operation to determine that the memory 300b is acceptable can be carried out within operation S250. If, on the other hand, the variable i is not equal to K, the variable i can be incremented by one in operation S236, and then operation S231 can be carried out. In operation S231, a bit at a position different from the position of the previously inverted bit can be inverted.

[0052] With reference to Fig. 6B can be compared to the example of the Fig. 6A The write operation of the write data D_WR can be performed once to verify a specific area of ​​memory 300b, and the read operation of the stored write data D_WR can also be performed once. That is, since the read data D_RD output by repeatedly reading the stored write data D_WR is identical, an operation to change only the position of a bit error in the read data D_RD by the error insertion circuit 200b can be repeated.

[0053] As in Fig. As illustrated in 6B, operations of Fig. 6B is the same as or similar to the corresponding operations of the Fig. 6A. However, if in operation S235' the Fig. 6B If the variable i is not equal to K, the variable i can be incremented by 1 in operation S236', and operation S232' can be performed instead of operation S231' following operation S236'. Therefore, the operation to write the data D_WR in operation S220' and the operation to read data written in operation S231' can each be performed once, and the operation to invert at least one bit of the read data D_RD can be repeated in operation S232'. Compared to the example of Fig. 6A can therefore determine the number of read operations of memory 300b according to an example of the Fig. 6B will be reduced.

[0054] Fig. Figures 7A to 7C are block diagrams illustrating examples of bit selection circuits according to exemplary embodiments of the concepts according to the invention. As above with reference to Fig. 3A and Fig. As described in 3B, the bit selection circuits 210a, 210b and 210c of the Fig. 7A to 7C receive the mode signal C_MODE and output the selection signal SEL. The following are described below. Fig. 7A and Fig. 7B with reference to Fig. 1 described, and duplicate descriptions of the Fig. 7A to 7C will not be carried out here.

[0055] With reference to Fig. 7A The bit selection circuit 210a can include the bit patterns 211. The bit selection circuit 210a can generate the selection signal SEL in response to the mode signal C_MODE indicating a test mode, so that a bit error occurs at a position according to the bit patterns 211. As shown above with reference to Fig. As described in section 4, the bit patterns 211 can comprise three different patterns if bit errors are inserted at three different positions.

[0056] With reference to Fig. In 7B, the bit selection circuit 210b can include a random number generator 212. In response to the mode signal C_MODE indicating a test mode, the bit selection circuit 210b can generate the selection signal SEL, causing a bit error at a position according to a random number generated by the random number generator 212. In some exemplary embodiments, the random number generator 212 can be a pseudorandom number generator.

[0057] With reference to Fig. The bit selection circuit 210c can also receive a setting signal C_SET. The setting signal C_SET can, for example, be generated from a signal coming from outside the device 10. Fig. 1 is received and can include setting information for the bit selection circuit 210c. In some exemplary embodiments, the setting signal C_SET can determine the number of error correction operations for an identical range of memory 300, that is, K. For example, if the correctable error quantity of the ECC engine 100 is fixed, K can be changed according to the setting signal C_SET to adjust the error range of memory 300. As above with reference to Fig. As described in section 4, in order to shorten a test period, K can additionally be changed, for example according to the setting signal C_SET, so that it is equal to or less than the number corresponding to the correctable error quantity of the ECC engine 100.

[0058] The Fig. Figure 8 is a flowchart illustrating a method for testing a device to support the ECC, according to an exemplary embodiment of the concepts of the invention. For example, the method of Fig. 8 a method for testing the device 10 the Fig. 1 in a test mode. Fig. 8. The coded data D_ENC and the write data D_WR can be used. Fig. The data D_1 and D_2 can be collectively referred to as write data, and the read data D_RD and the receive data D_RX can collectively be referred to as read data. For example, generating the write data D_WR by inserting an error into the encoded data D_ENC can be described as follows: Fig. 1. Inserting an error into write data, and generating the receive data D_RX by inserting an error into the read data D_RD can be described as inserting an error into read data. This is explained below. Fig. 8 with reference to Fig. 1 described.

[0059] In operation S20, write data can be generated by encoding input data. For example, the ECC engine 100 of the Fig. 1. Generate write data by adding redundancy to the input data D_IN.

[0060] In operation S40, write data can be written to memory 300, and read data can be output from memory 300. For example, write data can be written to a specific area of ​​memory 300, and read data can be output by reading data stored in the area where the write data is written. The error insertion circuit 200 can insert an error into data that is to be written to memory 300 (i.e., write data), or it can insert an error into data that is being read from memory 300 (i.e., read data). In some exemplary embodiments, the error insertion circuit 200 can insert an error into both write and read data. As in Fig. As illustrated in section 8, operation S40 can include operation S42.

[0061] In operation S42, at least one bit of the write data and / or the read data can be inverted. For example, the error insertion circuit 200 can include the bit error circuit BE and can invert at least one bit of the write data and / or the read data by activating at least one bit error circuit BE. The deactivated bit error circuit BE can output an input bit signal.

[0062] In operation S60, the output data D_OUT can be generated by correcting an error in the read data. For example, the ECC engine 100 of the Fig. 1. Generate the output data D_OUT by correcting an error in the read data.

[0063] Operation S80 can detect a defect in memory 300. As above, with reference to Fig. As described in section 5 and the like, in some exemplary embodiments a defect in memory 300 can be detected depending on whether the error correction in operation S60 is successful or not. As described below with reference to Fig. As described in section 9, in some exemplary embodiments a defect in memory 300 can be detected based on the output data generated in operation S60.

[0064] The Fig. 9 is a flowchart that provides an example of the S80 operation of the Fig. Figure 8 illustrates an exemplary embodiment of the concepts according to the invention. As above with reference to Fig. As described in section 8, a memory defect can be detected. As in Fig. As illustrated in 9, the operation S80' can include several operations S82, S84 and S86, and Fig. 9 can be used with reference to Fig. 1 and Fig. 8 will be described.

[0065] In some exemplary embodiments, the operation S80' can be performed by a test device that provides the device 10 with the input data D_IN outside of the device 10. Fig. The test device provides input data D_IN and receives output data D_OUT. The test device can set device 10 to a test mode using the mode signal C_MODE. It is possible to provide device 10, which is set to a test mode, with input data D_IN and to receive output data D_OUT corresponding to the provided input data D_IN.

[0066] Operation S82 can determine whether the input data D_IN and the output data D_OUT match. For example, the test device can determine whether the input data D_IN provided to device 10 and the corresponding output data D_OUT match. The error-corrected output data D_OUT can be received from data read from memory 300 after the input data D_IN has been stored in memory 300 via an encoding process, and the test device can compare the input data D_IN with the output data D_OUT. As described above with reference to the drawings, an error can be inserted into data encoded from the input data D_IN, and an error can be inserted into data read from memory 300.

[0067] If the input data D_IN and the output data D_OUT match despite the inserted error, it can be determined that memory 300 has a sufficient error margin, and memory 300 is accepted in operation S84. Conversely, if the input data D_IN and the output data D_OUT do not match, it can be determined that memory 300 has an insufficient error margin, and in operation S86 it can be determined that memory 300 is defective.

[0068] Fig. Figure 10 is a block diagram illustrating an example of a device for supporting the ECC, according to an exemplary embodiment of the concepts according to the invention. More precisely, it shows Fig. 10 a storage device 20 comprising a cell array 21 as a noisy channel.

[0069] Storage device 20 can receive a CMD instruction and an ADDR address, and it can receive or transmit DATA. For example, storage device 20 can receive the CMD instruction, such as a write instruction, a read instruction, and the like, and the address corresponding to the CMD instruction from a memory controller. Additionally, storage device 20 can receive DATA (i.e., input data) from the memory controller or provide DATA (i.e., output data) to the memory controller. Fig. Figure 10 shows the CMD command, the ADDR address, and the DATA data separately. In some exemplary embodiments, at least two of the following—the CMD command, the ADDR address, and the DATA data—can be transmitted over an identical channel. As shown in Fig. As shown in Figure 10, the storage device 20 can include the cell array 21, a read / write circuit 22, an error insertion circuit 23, an ECC engine 24, a row decoder 25_1, a column decoder 25_2, an address register 26_1, a data register 26_2, a control logic 27 and an input / output circuit 28.

[0070] The cell array 21 can comprise multiple memory cells and store data. An error, in which data read from the cell array 21 by the read / write circuit 22 differs from data written to the cell array 21, can occur due to a defect contained within the cell array 21. To correct the error, the ECC engine 24 can generate data by encoding the received data DATA (i.e., input data) along with the write command CMD, and can generate data DATA (i.e., output data) in response to the read command CMD, which is generated by correcting errors in data read from the cell array 21.

[0071] The error insertion circuit 23 can receive the mode signal C_MODE from the input / output circuit 28 and, in response to the mode signal C_MODE indicating a test mode, can insert an error into data transmitted between the read / write circuit 22 and the ECC engine 24. Furthermore, the error insertion circuit 23 can change the position of the error to be inserted. The amount of error inserted by the error insertion circuit 23 can correspond to an error range of the cell array 21. Thus, it can be easily verified whether the cell array 21 has a sufficient error range or not, and consequently, a defect in the storage device 20 can be easily detected.

[0072] The row decoder 25_1 can activate at least one of several word lines connected to the cell array 21, according to a row address provided by the address register 26_1. The column decoder 25_2 can select some of the signals output from the memory cells connected to the activated word line, according to a column address provided by the address register 26_1.

[0073] Address register 26_1 can receive and store the address ADDR from input / output circuit 28. Data register 26_2 can store data received from input / output circuit 28 and provide this data to ECC engine 24. Additionally, data register 26_2 can store data received from ECC engine 24 and provide this data to input / output circuit 28.

[0074] The control logic 27 can generate control signals for an operation of the storage device 20 according to the command CMD received by the input / output circuit 28, or the control signals can be provided to components contained in the storage device 20.

[0075] The input / output circuit 28 can receive the command CMD, the address ADDR, and the data DATA from outside the storage device 20 and output the data DATA. In some exemplary embodiments, the input / output circuit 28 can decode the command CMD and provide the control logic 27 with a result of the decoding.

[0076] The Fig. Figure 11 is a block diagram illustrating an example of a device for supporting the ECC, according to an exemplary embodiment of the concepts according to the invention. More precisely, it shows Fig. 11 a storage system 30 comprising a storage device 32 as a noisy channel, and a host 40 communicating with it.

[0077] The storage system 30 can communicate with the host 40 via an interface 50. The interface 50, through which the storage system 30 and the host 40 communicate, can use an electrical and / or optical signal and can be implemented by, but is not limited to, a Serial Advanced Technology Attachment (SATA) interface, a SATA Express (SATAe) interface, a Serial Attached Small Computer System (SAS) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Non-Volatile Memory Express (NVMe) interface, an Advanced Host Controller Interface (AHCI), or a combination thereof.

[0078] In some exemplary embodiments, the storage system 30 can communicate with the host 40 by being detachably coupled to the host 40. The storage device 32 can be non-volatile memory, such as resistive memory, and the storage system 30 can be referred to as a storage system. For example, the storage system 30 can be implemented by, but is not limited to, a solid-state drive or solid-state disk (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded MMC (eMMC), and the like.

[0079] As in Fig. As illustrated in Figure 11, the storage system 30 can comprise a controller 31 and at least one storage device 32. The at least one storage device 32 can receive the command CMD and the address ADDR received from the controller 31, and it can receive or transmit the data DATA.

[0080] The controller 31 can control at least one storage device 32 in response to a request received from the host 40 via the interface 50. For example, the controller 31 can write data received in response to a write request to the at least one storage device 32, or it can provide data stored in the at least one storage device 32 to the host 40 in response to a read request. As in Fig. As shown in Figure 11, the controller 31 can include an error insertion circuit 31_1 and an ECC engine 31_2.

[0081] In some exemplary embodiments, the error insertion circuit 31_1 can insert an error into data determined by encoding data that has been requested by the ECC engine 31_2 in a test mode to be written from the host 40, and can provide the data with the inserted errors as write data to the at least one storage device 32. In some exemplary embodiments, the error insertion circuit 31_1 can insert an error into data read from the at least one storage device 32 in response to a read request from the host 40 in a test mode, and can provide the data with the inserted errors to the ECC engine 31_2. Furthermore, the error insertion circuit 31_1 can change the position of the error to be inserted.A quantity of errors inserted by the error insertion circuit 31_1 can correspond to an error margin of the at least one storage device 32. Thus, it can be easily verified whether the at least one storage device 32 has a sufficient error margin or not.

Claims

[1] Device for supporting a test mode for memory testing, wherein the device (10; 10b) comprises: a memory (300; 300b) designed to receive and store write data (D_WR) and to output read data (D_RD) having up to M error bits from the stored write data (D_WR), where M is a non-negative integer; an error correction code (ECC) engine (100; 100b), wherein the error set correctable by the ECC engine (100; 100b) is N bits, the ECC engine being designed to generate the write data (D_ENC, D_WR) by encoding input data (D_IN) and to generate output data (D_OUT) by error-bit correction of N bits or less contained in received data (D_RX), where N is a positive integer; and an error insertion circuit (200; 200b) designed to provide the error correction code engine (100; 100b) with the read data (D_RD) as the receive data (D_RX) in a normal mode and to provide the error correction code engine (100; 100b) with data determined by inverting at least one bit of NM bits of the read data (D_RD) as the receive data (D_RX) in test mode , where the M bits represent a maximum number of bit errors that can occur in memory (300; 300b) during a manufacturing process of memory (300; 300b), and the (NM) bits represent an error range for errors that can occur in memory (300; 300b) after manufacturing. [2] Device according to claim 1, wherein the error insertion circuit (200; 200b) is further configured to change a position of the at least one bit in the read data (D_RD) in test mode, which is continuously output from memory (300; 300b) K times, where K is an integer equal to or greater than 2. [3] Device according to claim 2, wherein K is equal to (N+1). [4] Device according to claim 2, wherein K is equal to or less than N and is determined on the basis of the amount of data processed by the error correction code engine (100). [5] Device according to claim 2, wherein the fault insertion circuit (200; 200b) is further designed to determine K according to a setting signal received from outside the device (10; 10b). [6] Device for supporting a memory test mode, wherein the device (10; 10a) comprises: a memory (300; 300a) designed to receive and store write data (D_WR) and to output read data (D_RD) having up to M error bits from the stored write data (D_WR), where M is a non-negative integer; an error correction code (ECC) engine (100; 100a), wherein the set of errors correctable by the ECC engine (100; 100a) is N bits, the ECC engine being designed to generate coded data (D_ENC) by encoding input data (D_IN) and to generate output data (D_OUT) by error-bit correction of N bits or less contained in the read data (D_RD), where N is a positive integer; and an error insertion circuit (200; 200a; 200a'; 200a'') designed to provide the memory with the encoded data (D_ENC) as the write data (D_WR) in normal mode and to provide the memory (300; 300a) with data determined by inverting at least one bit of NM bits equal to or less than NM bits of the encoded data (D_ENC) as the write data (D_WR) in test mode, where the M bits represent a maximum number of bit errors that can occur in the memory (300; 300a) during a manufacturing process of the memory (300; 300a), and the (NM) bits represent an error range for errors that can occur in the memory (300; 300a) after manufacturing. [7] Device according to claim 6, wherein the error insertion circuit (200; 200a; 200a'; 200a'') is further configured to change a position of the at least one bit in the coded data (D_ENC) in test mode, which is continuously written to the memory K times, where K is an integer equal to or greater than 2. [8] Method for testing a device comprising an error correction code (ECC) engine (100; 100a; 100b) designed to correct error bits of N bits or less, and a memory (300; 300a; 300b), wherein N is a positive integer, the method comprising: Generating (S20) write data (D_ENC, D_WR) by encoding input data (D_IN) through the error correction code engine (100; 100a; 100b); Writing (S122; S220; S220') the write data (D_ENC, D_WR) to memory (300; 300a; 300b), reading (S123; S231; S231') the write data (D_ENC, D_WR) and outputting the read data (D_RD) which may contain up to M error bits, where M is a non-negative integer; and Generating (S60) output data by correcting an error in the read data (D_RD) using the error correction code engine, where The writing (S122; S220; S220') of the write data (D_ENC, D_WR) and the output of the read data includes an inversion (S121; S232; S232') of at least one bit, wherein the total number of inverted bits is equal to or less than NM bits in at least one of the two, the write data (D_ENC, D_WR) or the read data (D_WR), where the M bits represent a maximum number of bit errors that can occur in the memory (300; 300a; 300b) during a manufacturing process of the memory (300; 300a; 300b), and the (NM) bits represent an error range for errors that can occur in the memory (300; 300a; 300b) after manufacturing. [9] The method of claim 8, further comprising: Detecting (S80; S80') a defect in the memory (300; 300a; 300b) based on the input data (D_IN) and the output data (D_OUT). [10] Method according to claim 8, wherein generating the output data comprises detecting by the error correction code engine (100; 100a; 100b) whether a correction of error bits in the read data (D_RD) is successful, and detecting a defect of the memory (300; 300a; 300b) based on whether the correction is successful or not.

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