ANCHOR STRUCTURES AND METHODS FOR UNIFORM WAFER PLANARIZATION AND BONDING

Abstract

Image sensor device (100, 200, 300), comprising: a first The, comprehensive: a first substrate; a first dielectric layer directly on the first substrate; a first armature layer directly on the first dielectric layer; a first interconnection structure formed in the first dielectric layer and the first armature layer; and a first anchor pad formed in the first anchor layer and directly on the first dielectric layer; and a second die that is bonded to the first die, the second die comprising: a second substrate; a second dielectric layer directly on the second substrate; a second armature layer directly on top of the second dielectric layer; a second interconnection structure in contact with the first interconnection structure, wherein the second interconnection structure is formed in the second dielectric layer and the second armature layer; and a second anchor pad formed in the second anchor layer and directly on the second dielectric layer, wherein the first and second interconnected structure, the first and second anchor layers and the first and second anchor pads are each bonded together, wherein the first and second anchor pads comprise a conductive material, the conductive material comprising transparent tin oxide or zinc oxide.

Description

BACKGROUND

[0001] Semiconductor image sensor devices are used to detect radiation, such as light. Complementary metal-oxide-semiconductor (CMOS) image sensors and CCD sensors (charge-coupled element sensors) are used in various applications, such as digital camera and mobile phone camera applications. These devices use an array of pixels (which may include photodiodes and transistors) in a substrate to absorb (e.g., detect) radiation projected onto the substrate and convert the detected radiation into electrical signals. Semiconductor image sensors are described in US 2006 / 0146233A1, US 2015 / 0076649A1, US 2018 / 0138223A1, and US 2015 / 0108644A1.

[0002] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various elements are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased as appropriate for clarity of illustration and description. Fig. Figure 1 is a cross-sectional view of a back-illuminated image sensor device according to some embodiments. Fig. Figure 2 is a cross-sectional view of an image sensor device according to some embodiments. Fig. Figure 3 is a cross-sectional view of an image sensor device according to some embodiments. The Fig. Figures 4A - 4B are an isometric and / or a top view of an image sensor device according to some embodiments. Fig. Figure 5 is an isometric view of an image sensor device according to some embodiments. Fig. Figure 6 is an isometric view of an image sensor device according to some embodiments. Fig. Figure 7 is a flowchart of an exemplary method for forming image sensor devices according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over a second feature in the following description may include embodiments in which the first and second features are in direct contact, and also embodiments in which additional features are arranged between the first and second features, such that the first and second features are not in direct contact.

[0005] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar terms can be used here for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as shown in the figures. These spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative terms used here may be interpreted accordingly.

[0006] The term “essentially”, as used here, indicates that the value of a given quantity varies by ± 5% of the value.

[0007] The term "approximately," as used here, indicates the value of a given quantity, which can vary based on a specific technology node associated with the semiconductor device in question. Based on the respective technology node, the term "approximately" can indicate a value of a given quantity that varies, for example, within 5–30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0008] Integrated circuit (IC) packaging has evolved to allow multiple dies to be stacked vertically, saving space for horizontal fixtures and increasing fixture density. Vertical stacking also offers the advantage of fabricating each die separately prior to stacking, providing manufacturing flexibility. For example, dies with different heat budgets can be fabricated separately under varying temperature conditions and then stacked together. Before stacking, one contact surface of each die is planarized, and the dies are bonded to these contact surfaces using appropriate bonding techniques such as melt bonding, hybrid bonding, anodic bonding, direct bonding, room temperature bonding, press bonding, and / or combinations thereof. Essentially, planar contact surfaces are necessary to achieve a strong bond between the stacked dies.When the planarization process is performed on the surface of a die, portions of the substrate surface can be "dished" due to the device density and / or differing material selectivity (e.g., material removal rate) of the planarization process. These portions may form a concave surface or protrude, forming a convex surface. When the planar surfaces of two dies are subsequently joined, the concave or convex surfaces meet, forming one or more bubbles or cavities at the interface between the two dies. These bubbles or cavities weaken structurally stacked devices and cause defects that can lead to device failure. Therefore, uniform and planar bond interfaces are essential for achieving high yields in semiconductor devices.

[0009] Semiconductor image sensor devices are examples of semiconductor devices that can be formed by vertically stacking multiple dies. Image sensor devices are used to detect electromagnetic radiation such as light (e.g., visible light). Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and computed-disk sensor (CCD) sensors can be used in various applications, such as digital camera and mobile phone camera applications. These devices use an array of pixels (which may include photodiodes and transistors) in a substrate to absorb (e.g., detect) radiation projected onto the substrate. The absorbed radiation can be converted by the photodiodes (in the pixel) into electrical signals such as charge or current, which can be further analyzed and / or processed by other modules of the image sensor device.

[0010] An image sensor device comprises a silicon substrate or a semiconductor material layer in which light-sensitive pixels or photodetectors are formed. The image sensors comprise an array of photodetectors arranged in a semiconductor substrate overlying an interconnection structure. Interconnection structures or redistribution structures are formed in image sensor devices to provide an electrical power or signal connection to the image sensor devices and are used interchangeably in the present disclosure. Examples of interconnection structures include contact pad structures located in peripheral openings of the semiconductor structure and laterally adjacent to the photodetectors. The interconnection structures are formed in dielectric layers such as silicon oxide or silicon nitride, which are formed on the silicon substrate or the semiconductor material layer.

[0011] Image sensor devices can be fabricated by stacking multiple dies of an integrated chip. These multiple dies can be fabricated separately by forming one or more metallization layers in interlayer deposited with low-density laminates (ILDs) over separate semiconductor substrates. One or more redistribution layers can then be formed in the ILDs over the metallization layers. A planarization process (e.g., a chemical-mechanical polishing process) can be performed to create a planar surface encompassing the redistribution layers and the ILD. The planar surfaces of the separated dies of the integrated chip can then be brought together and bonded, thus joining the redistribution layers of the separated dies.

[0012] When the planarization process is performed on the separate integrated die, portions of the substrate surface may undergo "dishing" and form a concave surface that dips below that of the surrounding ILD layer. In some embodiments, portions of the substrate surface may protrude from the surrounding ILD layer. When the planar surfaces of two dies of an integrated chip are subsequently joined, the concave or protruding surfaces come together to form one or more bubbles or cavities at the interface of the two integrated dies. These bubbles or cavities structurally weaken the image sensor device structure, so that if the force used to form a bond structure is too great, the structure beneath the bond pad may fracture and damage the multidimensional integrated chip.Therefore, uniform and planar bond interfaces are important to achieve a high yield of the image sensor devices.

[0013] This disclosure describes anchor structures and methods for forming anchor structures that promote uniformity in planarization and wafer bonding processes. Such uniformity reduces device defects and provides reliable electrical connections between IC dies. The anchor structures and methods for forming the anchor structures described in this disclosure can be applied to any suitable semiconductor device in which multiple devices are planarized and bonded together. The anchor structures can comprise (i) thin anchor layers (e.g., anchor layers with a thickness between 20 nm and 200 nm (200 Å and 2000 Å)) on the surface of a dielectric layer and (ii) anchor pads in the anchor layers and on the surface of the dielectric layer. Interconnect structures can be formed in the dielectric layer and also through the anchor layers.A planarization process can be performed on the top surfaces of the anchor layer, the interconnect, and the anchor, resulting in coplanar surfaces. The anchor layers can be formed on the top surface of an ILD layer (e.g., directly on top of it). The anchor layers can provide uniform planarization because the anchor layer material can be selected such that the planarization selectivity of the anchor layer material and an interconnect material is essentially the same. The anchor pad material can be selected to promote wafer bonding between the IC dies.

[0014] The uniformity of planarization can also be influenced by the structure density of the structures formed on the surface to be planarized. Image sensor devices can exhibit varying structure densities across their structure. Some areas on the image sensor device may contain regions with a higher relative structure density (e.g., more device structures per unit area), while others may contain regions with a lower relative structure density (e.g., fewer device structures per unit area). However, it should be noted that any relative comparison of "more" and "fewer" is within the scope of this disclosure. To provide a uniform structure density, anchor pads are formed in the anchor layers and on the dielectric layer to ensure a uniform density of structures (e.g.,to provide substantially the same number of device structures per unit area, comprising the same or a similar material. For example, the anchor pads may be formed from the same or a substantially similar material as the connecting or redistributing structures and thus exhibit the same or similar planarization selectivity as the connecting material. For example, the connecting metal and the anchor pad material may comprise any conductive material, such as transparent indium tin oxide, zinc oxide, any other suitable materials, or a combination thereof. Materials forming the anchor pads may be metallic or adhesive materials. The anchor pad may function as a passive device or be electrically connected to passive / active devices. The anchor pad may be embedded in the anchor layer and have substantially the same thickness as the anchor layer.Since the anchor layer has a small thickness, the anchor pad also offers the advantage that only a small amount of fixture space is required, thereby improving the fixture density in the image sensor devices.

[0015] Before describing the embodiments relating to anchor layer and anchor pad structures in an image sensor device, in Fig. 1. A back-illuminated image sensor device is described, which has a pixel area of ​​the image sensor device. The back-illuminated image sensor device, which is in Fig. As shown in Figure 1, this can be formed by planarizing and stacking multiple dies, for example a radiation detection die and a connection die.

[0016] Fig. Figure 1 is a simplified cross-sectional view of a back-illuminated image sensor device 100 according to some embodiments of the present disclosure. The back-illuminated image sensor device 100 comprises a radiation detection structure 101 stacked on a connecting structure 132. The radiation detection structure 101 and the connecting structure 132 can be fabricated separately before being bonded together to form the back-illuminated image sensor device 100.

[0017] The radiation detection structure 101 comprises a semiconductor layer 102 with radiation detection areas 104. By way of example and without limitation, the semiconductor layer 102 comprises silicon with a p-type dopant, such as boron. Alternatively, the semiconductor layer 102 can comprise silicon with an n-type dopant, such as phosphorus or arsenic. The semiconductor layer 102 can also comprise other elemental semiconductors, such as germanium or diamond. The semiconductor layer 102 can optionally comprise a compound semiconductor and / or an alloy semiconductor. Furthermore, the semiconductor layer 102 can comprise an epitaxial layer, which may be stretched to improve performance. The semiconductor layer 102 can comprise a silicon-on-insulator (SOI) structure.

[0018] The semiconductor layer 102 has a front face 106 (also referred to here as the "bottom surface") and a back face 108 (also referred to here as the "top surface"). The semiconductor layer 102 has a thickness that can range from approximately 100 µm to approximately 3000 µm. The radiation detection structure 101 can be prepared for bonding by performing a planarization process (e.g., a CMP process) on the front face 106 such that it is essentially planar.

[0019] The radiation detection areas, or pixels 104, are formed in the semiconductor layer 102. As disclosed herein, the terms "radiation detection areas" and "pixels" may be used interchangeably. The pixels 104 are configured to detect radiation, such as incident light rays striking the semiconductor layer 102 from the rear side 108. According to some embodiments of this disclosure, each of the radiation detection areas, or pixels 104, includes a photodiode capable of converting photons into charge. In some embodiments of this disclosure, the pixels 104 may include photodiodes, transistors, amplifiers, other similar devices, or combinations thereof. The pixels 104 are also referred to herein as "radiation detection devices" or "light sensors."

[0020] For the sake of simplicity, in Fig. Figure 1 shows two pixels 104; however, additional pixels 104 can be implemented in the semiconductor layer 102. As an example, and without limitation, the pixels 104 can be formed on the semiconductor layer 102 from the front face 106 using an ion implantation process. The pixels 104 can also be formed by a dopant diffusion process.

[0021] The pixels 104 are electrically isolated from each other by shallow trench insulation (STI) structures 110. The STI structures 110 are trenches etched into the semiconductor layer 102 and filled with a dielectric such as silicon oxide, silicon nitride, silicon oxynitride, fluorodoped silicate glass (FSG), a low-k dielectric (e.g., a material with a k-value of less than 3.9), any other suitable insulating material, or a combination thereof. According to some embodiments of the present disclosure, the STI structures 110 have an antireflection coating (ARC) 112 on the back side 108 of the semiconductor layer 102. The ARC 112 is a lining layer that can prevent incident light rays from being reflected away from the radiation detection areas / pixels 104. The ARC 112 can be a high-k material (e.g.,The material may include a material with a k-value greater than 3.9, such as hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), or any other high-k material. ARC 112 can be deposited using a sputtering process, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) technique, or any other suitable deposition technique. In some embodiments of the present disclosure, the thickness of ARC 112 can be in the range of about 1 nm (about 10 Å) to about 50 nm (about 500 Å) (e.g., 1 nm to 50 nm (10 Å to 500 Å)).

[0022] The back-illuminated image sensor device 100 also includes a cover layer 114 formed over the semiconductor layer 102, such as over the ARC 112, as shown in Fig. Figure 1 is shown. In some embodiments of the present disclosure, the cover layer 114 can provide a planar surface on which additional layers of the back-illuminated image sensor device 100 can be formed. The cover layer 114 can comprise a dielectric such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or any other suitable dielectric. Furthermore, the cover layer 114 can be deposited using CVD or another suitable deposition technique. In some embodiments of the present disclosure, the thickness of the cover layer 114 can be between about 50 nm and 200 nm (500 Å and about 2000 Å, e.g., between 50 nm and 200 nm (500 Å and 2000 Å)). Furthermore, the back-illuminated image sensor device can have a composite lattice structure (for simplification in Fig. (1 not shown) comprise a structure formed above the cover layer 114. The composite grid structure can further comprise cells arranged in columns and rows, each cell being aligned with a specific radiation detection area. The cells can accommodate a red, green, or blue color filter.

[0023] A connection structure 132 can be bonded to the radiation structure 101 to form a stacked device. The connection structure 132 is bonded to the radiation detection structure 101 at the front face 106 of the semiconductor layer 102. The connection structure 132 can include structured dielectric layers and conductive layers that form intermediate connections (e.g., wiring) between the pixels 104 and other components, which for simplicity are shown in Fig. 1 are not shown. The interconnect structure 132 can, for example, consist of one or more multilayer interconnect (MLI) structures 134 embedded in an interlayer dielectric (ILD) layer 136. According to some embodiments of the present disclosure, the MLI structures 134 can comprise contacts / vias and metal conductors. For illustrative purposes, several conductor tracks 138 and vias / contacts 140 are shown in Fig. Figure 1 shows the position and configuration of the conductor tracks 138 and the vias / contacts 140, depending on the design requirements, and are not limited to the illustration. Fig. 1 limited. Furthermore, the interconnection structure 132 can include detection devices 142. The detection devices 142 can, for example, be an array of field-effect transistors (FETs) and / or memory cells electrically connected to respective radiation detection areas (or pixels) 104 and configured to detect electrical signals generated as a result of a light-to-charge conversion process in these areas.

[0024] Fig. Figure 2 is a cross-sectional view of an image sensor device 200 according to some embodiments, comprising armature layer and armature pad structures. The image sensor device 200 may comprise a die (e.g., a chip) 201. The die 201 comprises a substrate 202, a redistribution structure 203, an etch stop layer 204, an interlayer dielectric (ILD) layer 206, an armature layer 208, and an armature pad 210. The image sensor device 200 may include additional structures, such as further dielectric layers, conductive interconnect structures, and light sensors (for clarity and simplicity, shown in Figure 2). Fig. 2 not shown). The Die 201 can comprise a redistribution area A, which includes redistribution structures, and a pixel area B, which includes one or more radiation detection areas or pixel structures.

[0025] The substrate 202 can be a p-substrate, such as a silicon material doped with a p-doper (e.g., boron). In some embodiments, the substrate 202 can be an n-substrate, such as a silicon material doped with an n-doper (e.g., phosphorus or arsenic). In some embodiments, the substrate 202 can comprise germanium, diamond, a compound semiconductor, an alloy semiconductor, a silicon-on-insulator (SOI) structure, any other suitable material, or combinations thereof. The substrate 202 can have an initial thickness in the range of about 100 µm to about 3000 µm (e.g., from 100 µm to 3000 µm). The substrate 202 can consist of a sensor device, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a storage device, a microelectromechanical system (MEMS), any suitable device, or a combination thereof.

[0026] The etch stop layer 204 can be used to form a redistribution region. The etch stop layer 204 can comprise a dielectric such as silicon nitride. In some embodiments, the etch stop layer can comprise silicon oxide, spin-on glass, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, any other insulating material, or combinations thereof. The etch stop layer 204 can be formed by depositing an etch stop layer material using any suitable deposition method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), flowable CVD (FCVD), any other suitable method, or combinations thereof.

[0027] The interlayer dielectric (ILD) layer 206 is arranged on the etch stop layer 204. The ILD layer 206 can comprise a dielectric such as silicon oxide. Conductive layers and structures that provide connections (e.g., wiring) between various doped features, circuits, and the input / output of the image sensor device 200 can be embedded in the ILD layer 206. The conductive layers and structures can be part of a multilayer interconnect (MLI) structure that includes contacts, vias, and / or metal conductors.

[0028] The anchor layer 208 is arranged on the ILD layer 206. The anchor layer 208 can provide uniform planarization because its material exhibits essentially the same planarization selectivity as the bonding material or the material of the redistribution structure. In some embodiments, the anchor layer 208 can comprise a material that promotes wafer-wafer bonding. In some embodiments, the anchor layer 208 can comprise an adhesive material. In some embodiments, the material of the anchor layer 208 can consist of a compound comprising silicon, oxygen, fluoride, carbon, and nitride (SiO₂). x F y C z N a), comprising a polymer, a resin, a low-k dielectric, a high-k dielectric, insulating layers, any other suitable material, or combinations thereof. An ultraviolet light curing process can be used to form the anchor layer 208. The anchor layer 208 can also offer the advantage of preventing copper diffusion between the redistribution structures, the anchor pads, and other structures of the image sensor device 200. The anchor layer 208 can be formed by depositing an anchor layer material using any suitable deposition method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), flowable CVD (FCVD), any other suitable method, or combinations thereof. With reference to Fig. 2. The thickness T of the anchor layer 208 can be between approximately 20 nm (approximately 200 Å) and approximately 200 nm (approximately 2000 Å) (e.g., between 20 nm and 200 nm (200 Å and 2000 Å)). In some embodiments, the thickness T of the anchor layer 208 can be between approximately 40 nm (approximately 400 Å) and approximately 120 nm (approximately 1200 Å) (e.g., between 40 nm and 120 nm (400 Å and 1200 Å)). In some embodiments, the thickness T of the anchor layer 208 can be approximately 80 nm (approximately 800 Å). In some embodiments, the thickness T of the anchor layer 208 can be approximately 75 nm (approximately 750 Å).

[0029] The redistribution structure 203 is formed in the redistribution area A of the image sensor device 200. The redistribution structure 203 can be a connection structure configured to provide an electrical connection between metal conductors in different layers of the image sensor structure and / or between the image sensor device 200 and structures subsequently bonded to it. A lower section of the redistribution structure 203 can be formed in the substrate 202. The lower section can be formed by creating a trench in the substrate 202 and depositing a conductive material in the trench. The redistribution structure 203 can extend vertically through the etch stop layer 204, the ILD layer 206, and the anchor layer 208 and be exposed at the upper surface of the image sensor device 200.In some embodiments, the redistribution structure can comprise a conductive material such as copper, aluminum, tungsten, silver, titanium, any other suitable conductive material, alloys thereof, or combinations thereof. In some embodiments, the redistribution structure 203 can be formed using transparent indium tin oxide, zinc oxide, or another suitable material. The redistribution structure 203 can be a single-damascene structure, a dual-damascene structure, or any other suitable structure.

[0030] The redistribution structure 203 can be fabricated using suitable processes such as structuring and etching. The structuring process can include forming a photoresist layer overlying the anchor layer 208, exposing the photoresist layer with a structure, performing post-exposure baking processes, and developing the photoresist layer to form a masking element containing the resist. The masking element can protect areas of the anchor layer 208, while etching processes are used to create an opening in the anchor layer 208 and underlying layers. The etching process can be a reactive ion etching (RIE) process and / or another suitable process. The etching process can be continued until the substrate 202 is exposed or can be continued to a nominal depth into the substrate 202.Once an opening has been formed, conductive metal, such as the materials described above, can be deposited into the opening using any suitable process. Other methods for forming the redistribution structure 203 in the image sensor device 200 may also be suitable. The width of the redistribution structure 203 can be in a range of approximately 0.01 µm to approximately 200 µm (e.g., from 0.01 µm to 200 µm).

[0031] The anchor pads 210 can be formed in pixel area B of the image sensor 200. In Fig. Figure 2 shows only one anchor pad, and for simplicity, other anchor pads have been omitted. Since planarization uniformity is influenced by the structure density, for example, by the structure density of the interconnect structures, anchor pads are used in image sensor devices to provide a uniform structure density of metallic structures, which in turn ensures planarization uniformity. To provide a uniform structure density, anchor pads of the same or a similar material are formed in the anchor layer 208 and on the ILD layer 206. For example, the anchor pads can be formed using a material that is identical to or substantially similar to the material used to form the redistribution structure 203. The anchor pads can have a rectangular conductive structure. In some embodiments, the anchor pads can be solid conductive structures.In some embodiments, the anchor pads can be hollow structures. In some embodiments, the anchor pads can have conductive metal slot structures.

[0032] The anchor pad material can have the same or similar planarization selectivity as the redistribution structure material. For example, the redistribution structure metal and the anchor pad material can comprise any conductive material, such as transparent indium tin oxide, zinc oxide, any other suitable material, or any combination thereof. Materials forming the anchor pads can be metallic or adhesive materials. Examples of adhesive materials include polymers, conductive adhesive materials, any other suitable materials, or a combination thereof. The anchor pads can be formed by structuring the anchor layer to create openings and depositing an anchor pad material into these openings.The structuring process can include forming a photoresist layer overlying the anchor layer 208, exposing the photoresist layer with a structure, performing post-exposure baking processes, and developing the photoresist layer to form a masking element containing the resist. The masking element can protect areas of the anchor layer 208 while etching processes are used to create an opening in the anchor layer 208 and underlying layers. The etching process can be a reactive ion etching (RIE) process and / or another suitable process. The etching process can continue until the dielectric substrate layer 206 is exposed or can be continued into the dielectric layer 206 to a nominal depth.After forming an opening, an anchor pad material, such as the materials described above, can be deposited into the opening using any suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), flowable CVD (FCVD), any other suitable process, or combinations thereof.

[0033] The anchor pad can also function as a passive device or be electrically connected to passive / active devices. The anchor pad width can range from approximately 0.01 µm to approximately 200 µm (e.g., between 0.01 µm and 200 µm). In some embodiments, the anchor pad can have a thickness similar to that of the anchor layer 208. In some embodiments, the anchor pad can extend vertically into the ILD layer 206. In some embodiments, the thickness of the anchor pad can range from 10 nm to 700 nm (100 Å and 7000 Å). The anchor pad width W1 can also be substantially similar to the width of the redistribution structure 203. The width of the anchor pads can range from 0.01 µm to approximately 200 µm. The anchor pad thickness can be less than the thickness of the interconnect structure. The distance between the redistribution structure 203 and the anchor pads can be in a range between approximately 0.1 µm and approximately 100 µm (e.g.between 0.1 µm and 100 µm). The distance between adjacent anchor pads can be in a range between approximately 0.1 µm and approximately 100 µm (e.g., between 0.1 µm and 100 µm).

[0034] Once the above structures have formed, a planarization process such as CMP can be used to planarize the top surfaces of the redistribution structure 203, the anchor layer 208, and the anchor pads 210. Since the anchor pads can be made of a material with the same or similar planarization selectivity as the bonding material and the anchor layer, the planarization rate can be similar across the top surfaces, resulting in a substantially planar surface. Furthermore, the anchor pads formed in the anchor layer and on the dielectric layer provide a uniform structure density of structures made of the same or similar material, which can also promote uniform planarization.

[0035] Fig. Figure 3 is a cross-sectional view of an image sensor device 300 according to some embodiments, including armature layer and armature pad structures. The image sensor device 300 may comprise a first die (e.g., a chip) 301 bonded to a second die 311 at a bond interface 330. The first and second dies 301 and 311 comprise substrates 302 and 312, respectively, redistribution structures 303 and 313, etch stop layers 304 and 314, respectively, ILD layers 306 and 316, armature layers 308 and 318, respectively, and armature pads 310a, 310b, and 320a and 320b, respectively. The image sensor device 300 may include additional structures, such as further dielectric layers, conductive interconnect structures, and light sensors (for clarity and simplicity, shown in Figure 3). Fig. 3 not shown). Each Die can comprise a redistribution area A with redistribution structures and a pixel area B with pixel structures.

[0036] Substrates 302 and 312 can each be a p-substrate, such as a silicon material doped with a p-doper (e.g., boron). In some embodiments, substrates 302 and 312 can each be an n-substrate, such as a silicon material doped with an n-doper (e.g., phosphorus or arsenic). Substrates 302 and 312 can be adapted to the above in Fig. Substrate 202, as described in section 2, is similar to substrate 202 and is not described in detail here. Substrates 302 and 312 can have an initial thickness ranging from approximately 100 µm to approximately 3000 µm.

[0037] The etch stop layers 304 and 314 can be used in the subsequent formation of a redistribution region. The etch stop layers 304 and 314 can comprise a dielectric such as silicon nitride. In some embodiments, the etch stop layers 304 and 314 can be formed using materials similar to those of the etch stop layer 204 described above. Fig. 2 is described. The etch stop layers 304 and 314 can be deposited using any suitable deposition methods such as CVD, PECVD, ALD, PVD, FCVD, any other suitable method or combinations thereof.

[0038] The ILD layers 306 and 316 are arranged on the etch stop layers 304 and 314, respectively. The ILD layers 306 and 316 may comprise a dielectric such as silicon oxide. In some embodiments, the ILD layers 306 and 316 may comprise materials similar to those described above. Fig. 2. The ILD layers 206 described above are formed. The ILD layers 306 and 316 can be deposited using any suitable deposition method, for example CVD, PECVD, ALD, PVD, FCVD, any other suitable method or combinations thereof.

[0039] The anchor layers 308 and 318 are arranged on the ILD layers 306 and 316, respectively. As described above, the anchor layers can be formed in pixel region B and provide uniform planarization because their material exhibits essentially the same planarization selectivity as the bonding material or the redistribution structure material. In some embodiments, the anchor layers 308 and 318 can include a material that promotes wafer-wafer bonding. In some embodiments, the anchor layers 308 and 318 can include an adhesive material. The anchor layers 308 and 318 can be formed using materials and processes similar to those described above. Fig. The anchor layers are similar to the anchor layer 208 described in section 2. The anchor layers can also prevent copper diffusion between redistribution structures, anchor pads, and other structures of the image sensor device. The anchor layers 308 and 318 can be deposited using any suitable deposition process, such as CVD, PECVD, ALD, PVD, FCVD, any other suitable process, or combinations thereof.

[0040] In some embodiments, the material of the anchor layers 308 and 318 can consist of a compound containing silicon, oxygen, fluoride, carbon and nitride (SiO₂). x F y C z N a), comprising a polymer, a resin, a low-k dielectric, a high-k dielectric, insulating layers, or any other suitable material. For example, the anchor layer may comprise silicon oxynitride. An ultraviolet light curing process may be used to form the anchor layers 308 and 318. The thickness of the anchor layers 308 and 318 may range from approximately 20 nm (about 200 Å) to approximately 200 nm (about 2000 Å). In some embodiments, the thickness T of the anchor layers 308 and 318 can be between approximately 40 nm (approximately 400 Å) and approximately 120 nm (approximately 1200 Å) (e.g., between 40 nm and 120 nm (400 Å and 1200 Å)). In some embodiments, the thickness T of the anchor layers 308 and 318 can be approximately 80 nm. In some embodiments, the thickness T of the anchor layers 308 and 318 can be approximately 75 nm (approximately 750 Å).In some embodiments, the anchor layers 308 and 318 can have different thicknesses. In some embodiments, the anchor layers 308 and 318 can have the same or substantially the same thickness.

[0041] The redistribution structures 303 and 313 are formed in the redistribution area A of the image sensor device 300. The redistribution structures 303 and 313 can be interconnection structures configured to establish electrical connections between metal conductors in different layers of the image sensor structure and / or between die 301 and die 311. The redistribution structures 303 and 313 can extend vertically through the etch stop layers 304 and 314, respectively, the ILD layers 306 and 316, and the anchor layers 308 and 318, respectively. In some embodiments, the redistribution structures 303 and 313 can comprise conductive materials such as copper, aluminum, tungsten, silver, titanium, any other suitable conductive material or alloys thereof, or combinations thereof. In some embodiments, the redistribution structures 303 and 313 can be formed using transparent indium tin oxide and zinc oxide.In some embodiments, the redistribution structures 303 and 313 can be formed using similar materials and processes as the redistribution structure 203 described above. Fig. The width of the redistribution structures 303 and 313 can range from 0.01 µm to approximately 200 µm. In some embodiments, the width of the redistribution structures 303 and 313 can be equal or substantially equal. In other embodiments, the width of the redistribution structures 303 and 313 can be different. The redistribution structures 303 and 313 can be formed by any number of suitable techniques, such as PVD, CVD, electrochemical deposition (ECD), molecular beam epitaxy (MBE), ALD, electroplating, and the like. For example, the redistribution structures 303 and 313 can be formed from copper, nickel, platinum, gold, silver, or combinations thereof.

[0042] Anchor pads 310a-310b and 320a-320b can be formed in pixel area B of image sensor 300. Anchor pads 310a-310b and 320a-320b are formed in anchor layers 308 and 318, respectively, and on ILD layers 306 and 316, respectively, to provide a uniform density of structures made of the same or a similar material. Anchor pads 310a-310b and 320a-320b can be formed using a material similar to that described above. Fig. The anchor pads 210 described in section 2 may be formed. For example, the anchor pads 310a-310b and 320a-320b may be formed using a material that is identical or substantially similar to the material used to form the redistribution structures 303 and 313. The anchor pad material may have the same or similar planarization selectivity as the redistribution structure material. For example, the redistribution structure material and the anchor pad material may be any conductive material, such as transparent indium tin oxide, zinc oxide, any other suitable material, or any combination thereof. The materials forming the anchor pads may be metallic or adhesive materials. Examples of adhesive materials include polymers, conductive adhesive materials, any other suitable material, or a combination thereof.The anchor pads 310a-310b and 320a-320b can be formed by creating openings in the anchor layer 308 and 318, respectively. In some embodiments, an anchor layer structuring process can include photolithography and etching processes. The photolithography process can include forming a photoresist layer over the anchor layers 308 and 318, exposing the resist, performing post-exposure baking processes, and developing the resist to form a masking element encompassing the resist. The masking element can then be used to protect specific areas of the anchor layers 308 and 318, while an etching process removes exposed anchor layer material and creates openings. The etching process can be reactive ion etching (RIE) or any other suitable process.Once the openings are formed, the anchor pads 310a - 310b and 320a - 320b can be formed by any number of suitable techniques, for example CVD, PECVD, ALD, PVD, FCVD, ECD, MBE, electroplating and the like.

[0043] The anchor pads 310a-310b and 320a-320b can also function as passive devices or be electrically connected to passive / active devices. The width of the anchor pads 310 and 320 can range from approximately 0.01 µm to approximately 200 µm. The width of the anchor pads 310 and 320 can also be substantially similar to the width of the redistribution structure 203. In some embodiments, the anchor pads 310 and 320 can each have a thickness similar to that of the anchor layers 308 and 318. The anchor pad thickness can be less than the thickness of the interconnect structure. In some embodiments, the anchor pads 310 and 320 can extend vertically into the ILD layers 306 and 316, respectively. In some embodiments, the thickness of the anchor pads 310 and 320 can range from 10 nm to 700 nm (100 Å and 7000 Å). The distance between the redistribution structure 303 and the anchor pads 310 and 320 can range from 0.1 µm to 100 µm.The distance between anchor pads 310 and 320 can be in a range between 0.1 µm and 100 µm.

[0044] According to some embodiments, dies 301 and 311 are wafer-bonded to each other at the interface 330. The anchor and connection structures of dies 301 and 311 can be aligned and bonded to each other during the wafer bonding process. Dies 301 and 311 are bonded by a suitable bonding method, such as melt bonding, hybrid bonding, anodic bonding, direct bonding, room temperature bonding, any other suitable bonding process, or combinations thereof. Due to the improved uniformity of planarization in the anchor layers and anchor pads, the adhesion and bonding between dies 301 and 311 reduces or eliminates the formation of voids at the bond interface 330. Thus, reliable electrical connections between the redistribution structures 303 and 313 can be established. In some embodiments, anchor pads of a first die are aligned with anchor pads of a second die.For example, anchor pad 310a of die 301 is aligned with anchor pad 320a of die 311. In some embodiments, anchor pads of the first die are partially aligned with anchor pads of a second die and still retain their full function as if they were fully aligned, but additionally offer the advantage of increased latitude for alignment and overlap requirements of the photolithography process. For example, anchor pad 310b of die 301 and anchor pad 320b of die 311 can be partially aligned, as shown in [Figure 1]. Fig. 3 shown.

[0045] In some embodiments, the anchor pads of a first die can be parallel to the anchor pads of a second die during the bonding process. In some embodiments, the anchor pads of the first and second dies can be perpendicular to each other or formed at an angle between 0° and 90° to each other. In some embodiments, the anchor pads and / or connection structures can also be partially aligned and connected after the wafer bonding process. Fig. Figures 4A-4B, 5, and 6 describe different arrangements of anchor pads between a first die and a second die. These figures show exemplary configurations of anchor pads, and other structures have been omitted for simplicity and clarity. Other suitable structures can also be formed within the structures shown in these figures.

[0046] The Fig. Figures 4A-4B are an isometric view or a top view of an image sensor device 400, which has anchor pad structures that are formed at an angle to each other. Fig. 4A - 4B comprise an array of anchor pads 402 of a first die and an array of anchor pads 403 of a second die. As in Fig. As shown in Figure 4A, the array of anchor pads 402 is bonded to the array of anchor pads 403. Each anchor pad in the array of anchor pads 402 is substantially perpendicular to an anchor pad in the array of anchor pads 403. In some embodiments, the arrays of anchor pads 402 and 403 can be configured at an angle between approximately 0° and approximately 90°. In some embodiments, the anchor pads in the arrays of anchor pads 402 and 403 can have a thickness between 10 nm and 700 nm (100 Å and 7000 Å). The anchor pad widths can range from 0.01 µm to approximately 200 µm. The spacing between adjacent anchor pads can range from 0.1 µm to 100 µm. According to some embodiments, the array of anchor pads 402 can have substantially similar dimensions to the array of anchor pads 403. In some embodiments, the anchor pads of the two arrays can have different dimensions.

[0047] Fig. Figure 5 is an isometric view of an image sensor device 500, which according to some embodiments includes anchor pad structures designed with a lateral offset. Fig. 5 comprises an array of anchor pads 501 of a first die and an array of anchor pads 503 of a second die. As in Fig. As shown in Figure 5, the array of anchor pads 501 is bonded to the array of anchor pads 503. Each anchor pad in the array of anchor pads 501 is essentially parallel to an anchor pad in the array of anchor pads 503. In some embodiments, an anchor pad of one array can be electrically connected to two anchor pads of the other array by forming an overlap region. In some embodiments, the overlap region has a width W4 between 0% and 100% of the anchor pad width. In some embodiments, the anchor pads in the arrays of anchor pads 501 and 503 can have a thickness between 10 nm and 700 nm (100 Å and 7000 Å). The anchor pad widths W2 and W3 can range from 0.01 µm to about 200 µm. The distance between adjacent anchor pads can range from 0.1 µm to 100 µm. The array of 501 anchor pads can have essentially similar dimensions to the array of 503 anchor pads.In some embodiments, the anchor pads of the two arrays may have different dimensions.

[0048] Fig. Figure 6 is an isometric view of an image sensor device 600 which, according to some embodiments, includes anchor pad structures designed with a lateral offset. Fig. 6 comprises an array of anchor pads 601 of a first die and an array of anchor pads 603 of a second die. As in Fig. As shown in Figure 6, an array of anchor pads 601 is bonded to an array of anchor pads 603. Each anchor pad in the array of anchor pads 601 is essentially parallel to an anchor pad in the array of anchor pads 603. In some embodiments, an anchor pad of one array can be electrically connected to an anchor pad of the other array by forming an overlap region. In some embodiments, the overlap region has a width between 0% and 100% of the anchor pad width. In some embodiments, the anchor pads in the arrays of anchor pads 601 and 603 can have a thickness between 10 nm and 700 nm (100 Å and 7000 Å). The anchor pad widths can range from 0.01 µm to about 200 µm. The distance between adjacent anchor pads can be in a range between 0.1 µm and 100 µm. According to some embodiments, the array of anchor pads 601 can have essentially similar dimensions to the array of anchor pads 603.In some embodiments, the anchor pads of the two arrays may have different dimensions.

[0049] Fig. Figure 7 is a flowchart of an exemplary method 700 for forming a stacked semiconductor device with armature layers and armature pads according to some embodiments of the present disclosure. Based on the disclosure herein, operations in method 700 may be performed in a different sequence and / or may differ.

[0050] In some embodiments of process 702, a semiconductor substrate with devices formed thereon is provided. The semiconductor devices are formed on and / or in a semiconductor structure. In some embodiments, the substrate may be a silicon substrate. In some embodiments, the substrate may consist of (i) another semiconductor, such as germanium; (ii) a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, indium antimonide, any other material, or any combination thereof; (iii) an alloy semiconductor comprising SiGe; or (iv) combinations thereof. In some embodiments, the substrate may be a SOI. In some embodiments, the substrate may consist of an epitaxial material.In some embodiments, the substrate may also comprise a machined wafer with integrated circuits, including, for example, several transistors arranged as CMOS circuits, RF circuits, and the like. In some embodiments, active and passive devices—such as transistors, diodes, capacitors, resistors, inductors, and the like—may be formed on and / or in the semiconductor substrate. An example of the substrate is substrate 202, as described in [reference to relevant section]. Fig. 2 described.

[0051] In process 704, according to some embodiments, etch stop layers, dielectric layers, and other suitable structures are formed on the substrate. The substrate can include any suitable layers / structures, such as etch stop layers, dielectric layers, vias, interconnects, or any suitable structures. The dielectric layer can include a dielectric such as silicon oxide, spin-on glass, SiN, silicon oxynitride, FSG, a low-k dielectric, any other suitable insulating material, or a combination thereof. The deposition of the dielectric layer can be accomplished by any suitable process. Examples of etch stop layers include etch stop layers 204, 304, and 314, which are described above. Fig. 2 and Fig. 3 are described. Examples of the dielectric layers can be the ILD layers 206, 306 and 316, which are described above in the Fig. 2 and Fig. 3 are described.

[0052] In process 706, according to some embodiments, an anchor layer is deposited on the dielectric layer. The anchor layers can be arranged on the ILD layers and formed in pixel regions to provide uniform planarization. The anchor layers can be formed using a material with substantially the same planarization selectivity as the bonding material or the redistribution structure material. In some embodiments, the anchor layers can include a wafer-to-wafer bonding material or an adhesive material. Furthermore, the anchor layers can also prevent copper diffusion between different structures of the image sensor device. The anchor layers can be deposited using any suitable deposition process, such as CVD, PECVD, ALD, PVD, FCVD, any other suitable process, or combinations thereof.Examples of the anchor layers can be anchor layers 208, 308 and 318, which are shown above in the . Fig. 2 and Fig. 3 are described.

[0053] In process 708, according to some embodiments, redistribution structures are formed on the substrate and extend through the etch stop layer, the dielectric layer, and the armature layer. The redistribution structure can be formed within the redistribution area of ​​an image sensor device. The redistribution structure can be a connecting structure configured to provide an electrical connection between metal conductors in different layers of the image sensor structure and / or between the image sensor devices and downstream bonded structures. A lower section of a redistribution structure can be formed in the substrate by forming a trench in the substrate and depositing a conductive material in the trench. The redistribution structures can extend vertically through the etch stop layer, the ILD layer, and the armature layer.The redistribution structures may also be exposed on the upper surface of the image sensor device. Examples of redistribution structures include redistribution structures 203, 303, and 313, which are shown at the top of the... Fig. 2 and Fig. 3 are described.

[0054] In process 710, according to some embodiments, anchor pads are formed in the anchor layer and on the dielectric layer. The anchor pads can be formed in the pixel region of an image sensor. The anchor pads are formed in the anchor layers and on the ILD layers to provide a uniform density of structures that have the same or a similar material. For example, the anchor pads can be formed using a material that is identical to or substantially similar to the material used to form the redistribution structures. The anchor pad material can have the same or a similar planarization selectivity as the material of the redistribution structure. In some embodiments, the materials forming the anchor pads can be metallic or adhesive materials.In some embodiments, the anchor pads can also function as a passive device or be electrically connected to passive / active devices. When the dies are aligned and bonded, the anchor structures and connection structures of the respective dies are aligned and bonded together. Due to the improved uniformity of planarization in the anchor layers and anchor pads, the adhesion and bonding between the dies reduces or eliminates the formation of voids at the bond interface. Therefore, reliable electrical connections can be established between opposing and bonded redistribution structures. In some embodiments, anchor pads of a first die are aligned with anchor pads of a second die.In some embodiments, anchor pads of the first die are partially aligned with anchor pads of the second die and still fully retain their function as if they were aligned, but additionally offer the advantage of increased latitude for alignment and overlap requirements of the photolithography process. In some embodiments, anchor pads of the first die can be parallel to anchor pads of the second die. In some embodiments, the anchor pads of the first and second dies can be perpendicular to each other or formed at an angle between 0° and 90° to each other. In some embodiments, the anchor pads and / or connecting structures can also be partially aligned and joined after the wafer bonding process. Examples of the anchor pads include anchor pads 210, 310a-310b, 320a-320b, 402, 403, 501, 503, 601, and 603, which are described above. Fig. 2 - 6 are described.

[0055] In process 712, according to some embodiments, contact surfaces are planarized and devices are bonded to the contact surfaces. The anchor pads are formed in the anchor layer and can provide a uniform structural density that improves the uniformity of the planarization. For example, the anchor pads can be formed from the same or substantially similar material as the joining or redistribution structures and thus exhibit the same or similar planarization selectivity as the joining material. In some embodiments, the joining metal and the anchor pad material can comprise any suitable conductive material. Materials forming the anchor pads can be metallic or adhesive materials. The anchor pad can function as a passive device or be electrically connected to passive / active devices.The anchor pad can be embedded in the anchor layer and have essentially the same thickness as the anchor layer. Since the anchor layer is thin (e.g., between 10 nm and 700 nm (100 Å and 7000 Å)), the anchor pad also offers the advantage of requiring little fixture space, thus improving fixture density in image sensor devices. The anchor layer can consist of a compound containing silicon, oxygen, fluoride, carbon, and nitride (SiO₂). x F y C z N a The anchor layers may include a polymer, a resin, a low-k dielectric, a high-k dielectric, insulating layers, any other suitable material, or combinations thereof. The anchor layers can also offer the advantage of preventing copper diffusion between redistribution structures, anchor pads, and other structures of the image sensor device.

[0056] Various embodiments of this disclosure describe anchor structures and methods for forming the anchor structures such that the planarization and wafer bonding process can be uniform, which in turn reduces device defects and provides reliable electrical connections between devices. The anchor structures can include anchor layers formed on the surface of a dielectric layer and anchor pads formed in the anchor layer and on the surface of the dielectric layer. Since the interconnection structures are formed in the dielectric layer and through the anchor layer, the top surfaces of the anchor layer, the interconnection structure, and the anchor are coplanar after the planarization process. The anchor layer can provide uniform planarization because the anchor layer material can exhibit essentially the same planarization selectivity as the interconnection material.Anchor pads are formed in the armature layer and on the dielectric layer to provide a uniform density of structures made of the same or similar material. The anchor pad material can have the same or similar planarization selectivity as the interconnect material. The anchor pads and / or interconnect structures of two different IC dies can be partially aligned and joined after a wafer bonding process. The anchor pads of the two IC dies can have substantially similar or different dimensions.

[0057] In some embodiments, an image sensor device comprises a first die with a first dielectric layer directly on a substrate and a first armature layer formed directly on the first dielectric layer. The image sensor device also comprises a first interconnection structure formed in the first dielectric layer and the first armature layer. The image sensor device further comprises a first armature pad formed in the first armature layer and a second die in contact with the first die. The second die comprises a second armature layer on a second dielectric layer. The image sensor device also comprises a second interconnection structure in contact with the first interconnection structure, and the second interconnection structure is formed in the second dielectric layer and the second armature layer.The image sensor device also includes a second anchor pad formed in the second anchor layer. The first and second interconnect structures, the first and second anchor layers, and the first and second anchor pads exhibit essentially the same planarization selectivity.

[0058] In some embodiments, a method for forming an image sensor device comprises providing a substrate and depositing an etch stop layer directly onto the substrate. The method further comprises depositing a dielectric layer directly onto the etch stop layer and depositing an anchor layer directly onto the dielectric layer. The method also comprises forming a redistribution structure on the substrate and through the dielectric layer and the anchor layer. The method further comprises forming a plurality of anchor pads in the anchor layer.

[0059] In some embodiments, an image sensor system comprises a redistribution area with a first redistribution structure and a second redistribution structure bonded at an interface. The image sensor system also comprises a pixel area with a first and a second plurality of anchor pads bonded at the interface. The pixel area comprises a plurality of pixels. The image sensor system further comprises a first and a second anchor layer bonded at the interface and extending over the redistribution area and the pixel area. The first and second anchor pads are formed in the first and second anchor layers, respectively.

Claims

[1] Image sensor device (100, 200, 300), comprising: a first The, comprehensive: a first substrate; a first dielectric layer directly on the first substrate; a first armature layer directly on the first dielectric layer; a first interconnection structure formed in the first dielectric layer and the first armature layer; and a first anchor pad formed in the first anchor layer and directly on the first dielectric layer; and a second die that is bonded to the first die, the second die comprising: a second substrate; a second dielectric layer directly on the second substrate; a second armature layer directly on top of the second dielectric layer; a second interconnection structure in contact with the first interconnection structure, wherein the second interconnection structure is formed in the second dielectric layer and the second armature layer; and a second anchor pad formed in the second anchor layer and directly on the second dielectric layer, wherein the first and second interconnected structure, the first and second anchor layers and the first and second anchor pads are each bonded together, wherein the first and second anchor pads comprise a conductive material, the conductive material comprising transparent tin oxide or zinc oxide. [2] Image sensor device (100, 200, 300) according to claim 1, wherein the thickness of the first and second anchor layer is between 20 nm and 200 nm. [3] Image sensor device (100, 200, 300) according to claim 1, wherein the thickness of the first and second anchor pads is between 10 nm and 700 nm. [4] Image sensor device (100, 200, 300) according to one of the preceding claims, wherein the width of the first anchor pad is between 0.01 µm and 200 µm. [5] Image sensor device (100, 200, 300) according to one of the preceding claims, wherein the first and second interconnect structure, the first and second anchor layer and the first and second anchor pad have substantially the same planarization selectivity. [6] Image sensor device (100, 200, 300) according to one of the preceding claims, wherein both the first and the second anchor layer are silicon, oxygen, fluoride, carbon or nitride (SiO₂). x F y C z N a ) include. [7] Image sensor device (100, 200, 300) according to any of the preceding claims, wherein both the first and the second anchor layer comprise a polymer, a resin, a low-k dielectric, a high-k dielectric or an insulating material. [8] Image sensor device (100, 200, 300) according to one of the preceding claims, wherein the distance between the first anchor pad and the first connection structure is between 0.1 µm and 200 µm. [9] Method for forming an image sensor device (100, 200, 300), the method comprising: Providing a substrate; Deposition of an etch stop layer (204, 304, 314) directly onto the substrate; Deposition of a dielectric layer (206) directly onto the etch stop layer (204, 304, 314); Deposition of an armature layer (208, 308, 318) directly onto the dielectric layer (206); Formation of a redistribution structure (203, 303) on the substrate and through the dielectric layer (206) and the armature layer (208, 308, 318); and Forming a plurality of anchor pads (108, 208, 308) in the anchor layer (208, 308, 318) and directly on the dielectric layer, wherein the plurality of anchor pads (108, 208, 308) comprise a conductive material, wherein the conductive material comprises transparent tin oxide or zinc oxide. [10] Method according to claim 9, wherein the deposition of the anchor layer (208, 308, 318) comprises the deposition of an anchor layer material having a thickness between 20 nm and 200 nm. [11] Method according to claim 9 or 10, wherein the anchor layer material is silicon, oxygen, fluoride, carbon or nitride, SiO₂ x F y C z N a, includes. [12] Method according to claim 9 or 10, wherein the anchor layer material comprises a polymer, a resin, a low-k dielectric, a high-k dielectric or an insulating material. [13] Method according to any one of claims 9 to 12, wherein the distance between the plurality of anchor pads (108, 208, 308) is between 0.1 µm and 100, 200, 300 µm. [14] Image sensor system, comprising: a redistribution area (A) comprising a first redistribution structure and a second redistribution structure bonded at an interface; a pixel area (B) comprising a first and a second plurality of anchor pads bonded to the interface, wherein the pixel area (B) comprises a plurality of pixels; and a first and a second anchor layer bonded at the interface and extending over the redistribution area (A) and the pixel area (B), wherein the first and second anchor pads are formed in the first and second anchor layers respectively, the first and second anchor pads comprising a conductive material, the conductive material comprising transparent tin oxide or zinc oxide. [15] Image sensor system according to claim 14, wherein the first and second plurality of anchor pads are parallel to each other. [16] Image sensor system according to claim 14, wherein the first and second plurality of anchor pads are perpendicular to each other. [17] Image sensor system according to one of claims 14 to 16, wherein each anchor pad from the first plurality of anchor pads is aligned with another anchor pad from the second plurality of anchor pads. [18] Image sensor system according to one of claims 14 to 17, wherein an anchor pad from the first plurality of anchor pads partially overlaps with another anchor pad from the second plurality of anchor pads.

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