SEMICONDUCTOR COMPONENT WITH A SIC SEMICONDUCTOR BODY AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT

Abstract

A method for manufacturing a semiconductor device, the method comprising: Providing a silicon carbide substrate (700) and a mask (740) on a main surface (701) of the silicon carbide substrate (700), wherein a mask opening (741) in the mask (740) exposes a first portion of the main surface (701); Forming a trench (750) in the silicon carbide substrate (700), the trench (750) being formed under the mask opening (741); Forming a source region (110) in the silicon carbide substrate (700), wherein the formation of the source region (110) comprises introducing first dopant atoms through the mask opening (741); and Forming a shielding region (140), wherein forming the shielding region comprises introducing second dopant atoms through a bottom of the trench (750), wherein the first dopant atoms and the second dopant atoms have complementary doping types.

Description

TECHNICAL FIELD

[0001] The present application relates to semiconductor components with a SiC semiconductor body, in particular semiconductor switches with low on-resistance and high dielectric strength, as well as methods for producing semiconductor components. BACKGROUND

[0002] Power semiconductor components carry a comparatively high load current with high dielectric strength. In power semiconductor components with a vertical structure, the load current flows between two opposing main surfaces of a semiconductor body. The current-carrying capacity can be adjusted by the horizontal extent of the semiconductor body, and the dielectric strength can be adjusted by the vertical extent of a drift zone formed in the semiconductor body. In power semiconductor switches such as MOSFETs (metal oxide semiconductor field-effect transistors) and IGBTs (insulated gate bipolar transistors), a gate electrode capacitively couples into the body regions via a gate dielectric and switches the load current, for example, by temporarily forming an inversion channel in the body regions.In semiconductor bodies made of a material with an intrinsically high breakdown field strength, such as silicon carbide (SiC), the gate dielectric is exposed to a strong electric field in the blocking case, so that the breakdown strength of the gate dielectric can specify up to which voltage the dielectric strength of the semiconductor switch can be adjusted by the vertical extension of the drift zone.

[0003] The document US 2009 / 0 272 982 A1 describes the self-aligned formation of source regions to gate trenches in a SiC TMOSFET. The documents US 2018 / 0 286 944 A1 and DE 11 2004 002 608 B4 show, in particular, silicon MOSFETs with a trench gate electrode and a field electrode formed below the gate electrode in the gate trench and insulated from the surrounding substrate. The document US 2007 / 0 032 020 A1 also describes power transistors with a trench gate electrode and a field electrode formed below the gate electrode in the gate trench and insulated from the surrounding substrate. After the gate electrode has been formed in the gate trench, self-aligned source regions are formed by oblique implantation to the gate electrode.

[0004] The document DE 10 2018 104 581 A1 describes SiC trench MOSFETs. The gate electrode is formed in the upper part of strip-shaped or grid-shaped trenches. An auxiliary electrode is formed in the lower part of the trenches, which directly borders a shielding region formed below the trenches. The shielding region forms a pn junction with the drift zone. In the event of breakdown, charge carriers flow out of the shielding region via the auxiliary electrode. The source regions of the transistor cells are sections of a source layer formed before the trenches were etched.

[0005] The general aim is to further reduce the on-resistance of semiconductor components without sacrificing blocking voltage strength. SUMMARY

[0006] The present disclosure relates to a method for fabricating a semiconductor device. A silicon carbide substrate and a mask on a main surface of the silicon carbide substrate are provided. A mask opening in the mask exposes a first portion of the main surface. A trench and a source region are formed in the silicon carbide substrate. The trench is formed below the mask opening. Forming the source region includes introducing first dopant atoms through the mask opening.

[0007] The present disclosure further relates to a semiconductor device comprising a SiC semiconductor body. A gate electrode structure extends from a first surface of the SiC semiconductor body into the SiC semiconductor body. The gate electrode structure comprises a gate electrode and an interlayer dielectric. The interlayer dielectric is formed between the first surface and the gate electrode.

[0008] Further features and advantages of the disclosed subject matter will become apparent to the person skilled in the art from the following detailed description and from the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings provide a more in-depth understanding of embodiments of a semiconductor device and a method for manufacturing a semiconductor device, are incorporated in and constitute a part of this disclosure. The drawings merely illustrate embodiments and, together with the description, serve to explain the principles thereof. Other embodiments and intended advantages will become apparent from an understanding of the following detailed description, as well as from combinations of the embodiments described below, even if not explicitly described. The elements and structures shown in the drawings are not necessarily to scale. Like reference numerals refer to like or corresponding elements and structures. Fig. 1 is a simplified schematic flow diagram illustrating a method of manufacturing a semiconductor device according to one embodiment. Fig. 2A-2B show schematic vertical cross-sectional views of a silicon carbide substrate for illustrating a method of fabricating a SiC semiconductor device according to one embodiment. Fig. 3A-3G show schematic vertical cross-sectional views of a silicon carbide substrate illustrating a method according to an embodiment in which trenches for gate electrode structures are formed after the introduction of dopant atoms to form source regions. Fig. 4A-4B show schematic vertical cross-sectional views of a silicon carbide substrate according to another embodiment concerning a complementary mask. Fig. 5A-5F show schematic vertical cross-sectional views of a silicon carbide substrate illustrating a method according to an embodiment in which dopant atoms are introduced to form source regions after forming trenches for gate electrode structures. Fig. 6-8 show further embodiments for the introduction of dopant atoms to form source regions after the formation of gate electrode structures. Fig. 9A-9D show three horizontal and one vertical cross-sections through SiC semiconductor devices according to further embodiments. Fig. 10A-10G show schematic cross-sectional views of a silicon carbide substrate for illustrating a method for manufacturing a SiC semiconductor device according to another embodiment with complementary masks for forming source regions and body contact regions. DETAILED DESCRIPTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure, and in which, for purposes of illustration, specific embodiments of a semiconductor device and a method of fabricating a semiconductor device are shown. The existence of other embodiments will be understood.

[0011] The terms "have," "contain," "comprise," "have," and the like are open-ended terms that, on the one hand, indicate the presence of the elements or characteristics in question, but, on the other hand, do not exclude the presence of further elements or characteristics. The indefinite and definite articles include both the plural and the singular, unless the context clearly indicates otherwise.

[0012] The term or expression "electrically connected" describes a low-resistance connection between the electrically connected elements, for example, a direct contact between the elements in question or a connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more intermediate elements suitable for signal transmission may be present between the "electrically coupled" elements, for example, elements that can be controlled to temporarily establish a low-resistance connection in a first state and a high-resistance decoupling in a second state.

[0013] Some figures represent relative dopant concentrations by indicating "-" or "+" next to the doping type. For example, the designation "n-" indicates a dopant concentration that is lower than the dopant concentration of an "n"-doped region, while an "n+"-doped region has a higher dopant concentration than the "n"-doped region. The indication of the relative dopant concentration does not imply that doped regions with the same relative dopant concentration must have the same absolute dopant concentration, unless otherwise stated. Accordingly, two different "n"-doped regions can have the same or different absolute dopant concentrations.

[0014] If a range of values ​​is defined for a physical quantity by specifying one or two limit values, the terms "from" and "to" or "less" and "more" include the respective limit value. A specification of the type "from ... to" is therefore understood as "from at least ... to at most." Similarly, a specification of the type "less ..." ("more ...") is understood as "at most ..." ("at least ...").

[0015] The abbreviation IGFET (insulated gate field effect transistor) refers to voltage-controlled semiconductor switches and includes not only MOSFETs (metal oxide semiconductor FETs) but also FETs whose gate electrode has doped semiconductor material and / or whose gate dielectric does not have an oxide or does not consist exclusively of an oxide.

[0016] According to one embodiment, a method of manufacturing a semiconductor device may comprise providing a silicon carbide substrate.

[0017] The silicon carbide substrate has a main surface along which the silicon carbide substrate extends in lateral (also: horizontal) directions. Perpendicular to the lateral directions, in a vertical direction, the silicon carbide substrate has a thickness that is small compared to the extent of the silicon carbide substrate along the lateral directions. The main surface can define a top side (also: "front side") of the silicon carbide substrate, and a back surface opposite the main surface can define a bottom side (also: "back side") of the silicon carbide substrate. The vertical direction runs from the back surface towards the main surface. Directional references such as "top" and "bottom" refer to the vertical direction below.

[0018] The method may further comprise providing a mask on the main surface of the silicon carbide substrate. The mask may, for example, be a hard mask, which may be formed, for example, with carbon, silicon dioxide, or polycrystalline silicon. A mask opening in the mask may expose a first portion of the main surface. In other words, the main surface may be free of the mask at the first portion. For example, the mask opening is formed after the mask has been applied to the main surface.

[0019] A trench is formed in the silicon carbide substrate. The trench can be formed below the mask opening. Forming the trench includes, for example, an etching process in which a portion of the silicon carbide substrate is removed.

[0020] Furthermore, a source region may be formed in the silicon carbide substrate. Forming the source region may include introducing first dopant atoms through the mask opening. For example, forming the source region may include one or more vertical or nearly vertical implantations.

[0021] Since both the source region and the trench are defined by the same mask, the source region and the trench are formed self-aligned to each other and defined by the same lithography process.

[0022] If the trench and the source region are structured using different lithographic masks and in two exposure processes, the design of mask openings in the different masks that define the trench or the source region usually takes into account a possible alignment error between the two lithographic masks and / or a possible deviation of the realized structure width of the mask opening on the silicon carbide substrate from the originally intended value. Both of these - alone or in combination - can lead to a resulting imaging error. The deviation can be caused, for example, by small statistical deviations in the manufacturing process. In particular, in such a case the source region must usually be provided with a minimum lateral dimension, whereby the maximum expected imaging error between two exposure processes, the larger the lateral minimum dimension.

[0023] If, however, the source region and the trench are defined by the same exposure process, the described aberration can be completely eliminated and / or affect the source region and the trench equally. This allows the source region to be formed with a very small lateral and, above all, very well-defined width. The process can therefore enable a significantly smaller distance between adjacent source regions, a significantly smaller center-to-center distance between adjacent transistor cells—and thus a larger overall channel width in a semiconductor device of a given size—and ultimately a lower on-resistance without compromising long-term reliability and / or blocking voltage capability.

[0024] According to one embodiment, the first dopant atoms can be introduced after the formation of the trench. In particular, the formation of the source region can take place after the formation of the trench. For example, the dopant atoms can be introduced at least partially via the sidewall of the trench. This can enable a distance between a lower edge of the source region and the main surface to be adjusted independently of a kinetic energy of the dopant atoms. For example, the distance can be adjusted such that a sufficiently thick interlayer dielectric can be formed between an upper edge of a gate electrode provided in the trench and a plane spanned by the main surface.

[0025] A "bottom edge" of a component formed or disposed in the silicon carbide substrate (such as the source region) may be the part of the component farthest from the main surface (in other words, the lowest). Conversely, a "top edge" of a component (such as the gate electrode) may be the part of the component farthest from the main surface (in other words, the topmost).

[0026] A "sufficiently thick" interlayer dielectric can, for example, have a thickness of at least 25 nm, for example at least 50 nm or at least 100 nm or at least 300 nm. Typically, the thickness is at least 20 nm and at most 80 nm. Whether the thickness of the interlayer dielectric is sufficiently high can result, for example, from the requirements for strength against a maximum electric field applied to the interlayer dielectric. Alternatively or additionally, it is possible that the requirements for the thickness of the interlayer dielectric are process-dependent, such as minimizing a distance between the plane spanned by the main surface and an upper edge of the interlayer dielectric, so that subsequently applied layers can be applied on a surface that is as planar as possible.

[0027] According to one embodiment, a gate electrode can be formed in the trench. The gate electrode can be formed before the introduction of the first dopant atoms and / or before the formation of the source region. The upper edge of the gate electrode, in conjunction with an oblique implant, can define a suitable vertical extension of the source region.

[0028] According to one embodiment, after the formation of the trench and before the introduction of the first dopant atoms, auxiliary spacer structures can be formed on sidewalls of the mask opening. The auxiliary spacer structures can reduce a lateral extent (i.e., a width) of the mask opening. The auxiliary spacer structures can at least partially compensate for a process-related widening of the mask opening before the introduction of the first dopant atoms, for example, during and / or after the formation of the trench. The use of auxiliary spacer structures is possible, mutatis mutandis, in alternative embodiments of the method in which the trench is formed after the introduction of the first dopant atoms.

[0029] According to a further embodiment, the trench can be formed after the introduction of the first dopant atoms. During the formation of the trench, a portion of the source region formed by introducing the dopant atoms can be removed.

[0030] Forming the trench after introducing the first dopant atoms can make it possible to heal crystal damage after implantation of the dopant atoms and / or to activate the dopant atoms before structures that could be damaged by heat treatment, such as oxide structures, are formed in the trench. A comparatively high temperature and / or a high temperature budget can be used for the heat treatment to heal implantation damage and activate the implanted dopant atoms, without affecting dielectric structures formed in the trench.

[0031] According to one embodiment, the mask opening can be reduced in size after the introduction of the first dopant atoms and before the formation of the trench. For example, auxiliary structures and / or auxiliary spacer structures can be used for this purpose. The lateral width of the source regions can be precisely adjusted via the extent of the reduction. The "extent of the reduction" can correspond to a lateral reduction of the mask opening (e.g., a lateral width of the auxiliary structures and / or the auxiliary spacer structures). In one embodiment, the extent of the reduction can be used to define which part of the source region (in particular the part of the source region accessible in the mask opening) is removed during the formation of the trench.

[0032] According to one embodiment, after the introduction of the first dopant atoms and before the formation of the trench, auxiliary structures can be formed on sidewalls of the mask opening. A layer thickness of the auxiliary structures can be less than half the width of the mask opening, so that the auxiliary structures do not completely fill the mask opening. The trench can be introduced through a central portion of the mask opening between the auxiliary structures. The use of auxiliary structures is possible, mutatis mutandis, in alternative embodiments of the method in which the trench is formed before the introduction of the first dopant atoms.

[0033] The formation of the auxiliary structures can comprise an anisotropic etching of a conformal auxiliary layer, wherein the width of the auxiliary structures in the lateral direction and thus the width of the source regions can be precisely adjusted via the layer thickness of the conformal auxiliary layer. A conformal layer covers a structured substrate with a uniform layer thickness that is largely independent of the alignment of subsections of the substrate to one another. The layer thickness of a conformal layer can exhibit slight fluctuations that are small compared to the average layer thickness of the conformal layer. A conformal layer can be formed, for example, by a thin-film deposition process, such as CVD (chemical vapor deposition) in a furnace or plasma process.

[0034] According to one embodiment, a gate electrode structure can be formed in the trench. The gate electrode structure can have at least one conductive gate electrode and a gate dielectric that electrically and / or spatially separates the gate electrode from at least one body region in the silicon carbide substrate. In addition, the gate electrode can have further conductive structures and / or further dielectric structures. For example, the gate electrode structure can have a conductive connection structure connected to a source electrode and an isolation dielectric that electrically and / or spatially separates the gate electrode from the connection structure. A field dielectric can electrically and / or spatially separate the connection structure from doped regions in the silicon carbide body, at least in sections.

[0035] The connecting structure can, for example, be connected to a shielding region arranged beneath the gate electrode structure. In the case of multiple adjacent gate electrode structures, a shielding region can be arranged beneath each gate electrode structure. Adjacent shielding regions can form part of a JFET (Junction Field-Effect Transistor), by means of which the gate dielectric can be shielded from high electric fields and / or high voltages during operation.

[0036] According to one embodiment, a complementary mask with a complementary mask opening can be formed on the main surface. The complementary mask can cover the first portion of the main surface. For example, the complementary mask can partially or completely cover the first portion. The complementary mask opening can expose a second portion of the main surface. The second portion can differ from the first portion at least partially, in particular completely. Second dopant atoms can be introduced into the silicon carbide substrate through the complementary mask opening. The first dopant atoms and the second dopant atoms can have complementary doping types.

[0037] The first section of the main surface exposed by the mask opening is covered by the complementary mask. The second section of the main surface exposed by the complementary mask opening is covered by the mask. The complementary mask and the mask can be self-aligned to each other, so that source regions and heavily doped body contact regions can be formed side by side with only minimal lateral overlap in a single exposure process.

[0038] Both the source regions and the heavily doped body contact regions can be formed without counterdoping a heavily doped region of the opposite conductivity type. Both the source regions and the body contact regions can be formed with low ohmic resistance and low contact resistance to a metal formed on the main surface.

[0039] The complementary mask enables a low-resistance and low-loss connection of a body region to a source electrode and a sufficiently high avalanche and / or commutation strength even for those transistor cells in which an avalanche current and / or a commutation current of a bipolar body diode flows through the body region.

[0040] According to one embodiment, the mask and / or the complementary mask may be removed, and a metal layer may be applied to the first main surface. The metal layer may, for example, have a bottom surface, wherein the bottom surface may face the first main surface. The metal layer may span the trench. An interlayer dielectric separating the gate electrode from the metal layer may be formed entirely in the trench. For example, the metal layer may be applied directly to the interlayer dielectric.

[0041] The floor area may have a slight height difference in the area of ​​the trench, for example in the form of a step, whereby the height difference corresponds, for example, to a maximum of 20% or a maximum of 10% of the thickness of the interlayer dielectric.

[0042] The metal layer can directly contact both the source regions and the body contact regions of all transistor cells in a transistor cell array without further patterning. An otherwise common lithographic process for forming contact structures extending from a front-side electrode through an interlayer dielectric lying on the main surface to the source regions and the body contact regions can be omitted.

[0043] A further embodiment of the present disclosure relates to a semiconductor component. The semiconductor component can, in particular, have been manufactured using one of the methods described here. This means that all features disclosed in connection with embodiments of the method are, mutatis mutandis, disclosed for embodiments of the semiconductor component, and vice versa.

[0044] The semiconductor device comprises a SiC semiconductor body and a gate electrode structure that may extend from a first surface of the SiC semiconductor body into the SiC semiconductor body. The SiC semiconductor body may be a part of the silicon carbide substrate described in connection with embodiments of the method. The gate electrode structure may comprise a gate electrode and an interlayer dielectric. The interlayer dielectric may be formed between the first surface and the gate electrode.

[0045] The interlayer dielectric can be self-aligned to the gate electrode structure. Source regions and body regions can be contacted by a metal structure, for example, with a base area that alternately rests on the interlayer dielectric and the first surface. In particular, the source regions and body regions can be connected to an unstructured metal layer without the need for a further photolithographically patterned mask. Due to the self-aligned design, source regions can be made narrower for a given exposure wavelength, since minimum widths and minimum distances specified by an exposure process can be disregarded.

[0046] Furthermore, the semiconductor component may comprise a gate dielectric that electrically and / or spatially separates the gate electrode from the silicon carbide body.

[0047] According to one embodiment, the gate electrode structure comprises a conductive interconnect structure and an isolation dielectric. The interconnect structure can directly adjoin the SiC semiconductor body along a bottom of the gate electrode structure. The isolation dielectric can be formed between the interconnect structure and the gate electrode.

[0048] The conductive connection structure can divert a current flow through a semiconductor region at the bottom of the gate electrode structure with low resistance through the gate electrode structure. In particular, the forward current of a body diode and / or an avalanche current can be diverted through the gate electrode structure. Diversion through doped regions adjacent to the gate electrode structures can be eliminated. This allows a larger portion of the SiC semiconductor body to be allocated to the semiconducting parts of transistor cells. A parasitic bipolar transistor formed by the source region, body region, and drift structure remains inactive even at high avalanche currents and / or high currents through the body diode, particularly during commutation of the body diode.

[0049] According to one embodiment, the semiconductor component may comprise a first load electrode with a bottom surface, wherein the bottom surface may be in direct contact with the first surface of the SiC semiconductor body. The formation of contact structures connecting the first load electrode to doped regions in the SiC semiconductor body by means of a lithographic process may be omitted. This allows semiconductor mesas between adjacent gate electrode structures to be narrowed and the overall channel width in the semiconductor component to be further increased.

[0050] According to one embodiment, the gate electrode structure may have a longitudinal extension along a first horizontal direction, two end sections along the longitudinal extension, and a central section between the two end sections. The central section has a first width orthogonal to the longitudinal extension, and at least one of the end sections has a second width, which may be greater than the first width. A widened end section of the gate electrode structure may enable the connection of the gate electrode and / or the connection structure using a comparatively uncritical lithographic process.

[0051] According to one embodiment, the semiconductor device comprises a plurality of gate electrode structures with a respective trench width. Each gate electrode structure can extend from the first surface into the SiC semiconductor body. A portion of the SiC semiconductor body between adjacent gate electrode structures forms a SiC mesa with a mesa width. The mesa width can be smaller than the trench width.

[0052] A small mesa width can be associated with a significantly smaller center-to-center distance between neighboring transistor cells and thus with a larger overall channel width in a semiconductor device of a given size.

[0053] According to Fig. According to claim 1, a method for fabricating a semiconductor device comprises providing a silicon carbide substrate and a mask on a main surface of the silicon carbide substrate (902), wherein a mask opening in the mask exposes a first portion of the main surface. A trench and a source region are formed in the silicon carbide substrate (904), wherein the trench is formed beneath the mask opening, and forming the source region comprises introducing first dopant atoms through the mask opening.

[0054] By forming a trench and a source region based on the same mask opening, the source region can be self-aligned to a gate electrode structure formed in the trench. The widths of the gate electrode structure and the source region can be selected independently of margins to compensate for alignment and / or size errors between two structures defined in two independent lithography processes.

[0055] The Fig. 2A and Fig. 2B show a method for manufacturing a semiconductor device from a silicon carbide substrate 700 using two cross sections through a portion of the silicon carbide substrate 700.

[0056] The silicon carbide substrate 700 may comprise or consist of a SiC crystal. The polytype of the SiC crystal may be, for example, 15R or a hexagonal polytype, e.g., 2H, 4H, or 6H. In addition to the main components of silicon and carbon, the silicon carbide substrate 700 may comprise dopant atoms, for example, nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al), and / or gallium (Ga). In addition, the silicon carbide substrate 700 may comprise impurities, for example, oxygen, hydrogen, and / or carbon.

[0057] The silicon carbide substrate 700 may form an elliptical, in particular a circular, flat disk having a main surface 701 on the front side and a back side surface 702 on the back side of the disk, wherein the back side surface 702 and the main surface 701 are aligned parallel or approximately parallel to each other.

[0058] The main surface 701 can be planar or ribbed. In the case of a ribbed main surface, a median plane through the ribbed main surface is considered the main surface 701.

[0059] A surface normal 704 to the main surface 701 defines a vertical direction. Directions orthogonal to the surface normal 704 are lateral and horizontal directions. A diameter of the silicon carbide substrate 700 can correspond to an industry standard for semiconductor wafers, for example, 2 inches (51 mm), 3 inches (76 mm), 4 inches (100 mm), 125 mm, or 200 mm.

[0060] The silicon carbide substrate 700 may, for example, comprise a heavily doped base substrate and an epitaxial layer grown on the base substrate, wherein the epitaxial layer may comprise a plurality of differently doped sublayers and doped regions. The doped regions may be formed in portions of one or more of the sublayers. A mask 740 is formed on the silicon carbide substrate 700.

[0061] Fig. 2A shows the mask 740 formed on the main surface 701 of the silicon carbide substrate 700 with mask openings 741. The mask openings 741 may be formed in a strip-like manner, wherein a length of the mask openings 741 in a direction orthogonal to the cross-sectional plane is greater than a width w1 of the mask openings parallel to the cross-sectional plane. Adjacent mask openings 741 may be formed at the same center-to-center pitch p1 from one another. Trenches 750 and source regions 110 are formed on the basis of the mask 740 with the mask openings 741.

[0062] The formation of the trenches 750 includes an etching process that accurately transfers the structure of the mask 740 into the silicon carbide substrate 700. The mask 740 acts as an etch mask, and the trenches 750 are formed directly below the mask openings 741. The formation of the source regions 110 includes the introduction of dopant atoms through the mask openings 741, the mask 740 acting as an implantation mask, and a heat treatment to activate the introduced dopant atoms. The trenches 750 can be formed before or after the dopant atoms are introduced to form the source regions 110.

[0063] Between the introduction of the dopant atoms for the source regions 110 and the formation of the trenches 750 or between the introduction of the trenches 750 and the introduction of the dopant atoms for the source regions 110, the mask openings 741 can be reduced in size and / or enlarged.

[0064] For example, the mask openings 741 can be reduced in size by depositing an auxiliary layer with a layer thickness that is less than half the width w1 of the mask openings 741, or enlarged by isotropic recessing of the mask structure 740.

[0065] The Fig. 2B shows the trenches 750 extending from the first main surface 701 of the silicon carbide substrate 700 into the silicon carbide substrate 700. The source regions 110 extend along one sidewall or along both sidewalls of the trenches 750 from the main surface 701 into the silicon carbide substrate 700. Gate electrode structures can be formed in the trenches 750.

[0066] A lateral extension w2 of the source regions 110 can be selected to be comparatively small. A small lateral extension w2 of the source regions 110 enables smaller distances between adjacent trenches 750, smaller center-to-center distances between adjacent transistor cells, and ultimately a larger overall channel width in a SiC semiconductor device of a given size.

[0067] The described method is applicable to a wide variety of cell concepts for SiC semiconductor devices with electrically parallel-connected transistor cells whose gate electrodes are formed in trenches. For example, SiC TMOSFETs (SiC trench MOSFETs).

[0068] The Fig. 3A-3G show an embodiment with gate electrode structures that, in addition to a conductive gate electrode, have at least one further conductive connection structure. The conductive connection structure can be electrically connected or electrically coupled to a doped shielding region below the gate electrode structure and to a front-side metallization on the front side of the silicon carbide substrate.

[0069] The Fig. Figure 3A shows a silicon carbide substrate 700 based on a hexagonal SiC crystal type, e.g. 4H-SiC, and whose <0001> The grid direction is tilted by an angular deviation α (offset angle) against the surface normal 704 to the main surface 701. The angular deviation α can be between 2° and 8°, for example, about 4°.

[0070] The cross-sectional planes of the Fig. 3A-3G are chosen so that the <0001> Lattice direction in a plane that is oriented orthogonal to the cross-sectional plane and orthogonal to the main surface 701, is tilted by the angular deviation α against the surface normal 704. The <11-20> lattice direction is tilted in the plane that is oriented orthogonal to the cross-sectional plane and orthogonal to the main surface 701, by the angular deviation α against a surface normal to the cross-sectional plane. The <1-100> lattice direction runs parallel to the cross-sectional plane and parallel to the skin surface 701. For further properties of the silicon carbide substrate 700, please refer to the description of Fig. 2A and Fig. 2B.

[0071] The silicon carbide substrate 700 may include a base substrate 705 and an epitaxial layer 707. The base substrate 705 may be heavily doped, for example, heavily n-doped. The base substrate 705 may be a wafer or an epitaxial layer. In the case of a wafer, the base substrate 705 may be a silicon carbide disk that has been separated from a single-crystal silicon carbide crystal, for example, by sawing or by a wafer cleaving process. In the case of an epitaxial layer, the base substrate 705 may have been epitaxially grown on a growth surface of the wafer. The wafer may subsequently remain on the base substrate 705 or be at least partially, in particular completely, removed from the base substrate 705 (and the epitaxial layer 707 that may be present).In the case of complete removal of the wafer, the silicon carbide substrate 700 consists exclusively of epitaxially grown layers, in particular exclusively of the base substrate 705 and the epitaxial layer 707. However, unlike what is shown in the figures, the silicon carbide substrate 700 can also be free of a base substrate 705.

[0072] The epitaxial layer 707 may be formed by an epitaxial process on a process surface of the base substrate 705. The epitaxial layer 707 may include a drift layer structure 730, which may have the same conductivity type as the base substrate 705 or the conductivity type complementary to the conductivity type of the base substrate 705.

[0073] The drift layer structure 730 may include a lightly doped drift layer 731 and a current distribution layer 737, wherein the drift layer 731 is formed between the backside surface 702 (e.g., the base substrate 705) and the current distribution layer 737. The drift layer 731 and the current distribution layer 737 have the same conductivity type. An average dopant concentration in the current distribution layer 737 is higher than in the drift layer 731. For example, the average dopant concentration in the current distribution layer 737 may be at least twice the average dopant concentration in the drift layer 731.

[0074] Unlike in the Fig. However, as shown in Figures 3A-3G, the drift layer structure 730 may also be free of a current distribution layer 737. For example, in this case, the drift layer structure 730 comprises only the drift layer 731.

[0075] On one side of the drift layer structure 730 opposite the base substrate 705, a body structure 720 can be formed, which has a conductivity type opposite to the conductivity type of the drift layer structure 730. The body structure 720 can be grown on the drift layer structure 730, for example, by epitaxy or by introducing dopant atoms into a previously grown upper section of the epitaxial layer 707. The body structure 720 can form a continuous layer or comprise a plurality of laterally separated body wells. The lateral extent of the body well is comparatively large compared to the width of the trenches formed subsequently.

[0076] Heavily doped contact wells 729 of the conductivity type of the body structure 720 can be formed along sections of the main surface 701 between the main surface 701 and the body structure 720. The sections of the main surface 701 with the contact wells 729 can correspond to transistor cell regions of finalized SiC semiconductor components. A further section of the main surface 701 laterally separates the sections with the contact wells 729 from one another. The further section can comprise edge termination regions of the finalized semiconductor components and a kerf region, wherein structures for lateral field reduction can be formed in the edge termination regions.

[0077] According to the illustrated embodiments, the body structure 720 is p-conducting and the drift layer structure 730 is n-conducting. According to other embodiments, the body structure 720 may be n-conducting and the drift layer structure 730 may be p-conducting.

[0078] A mask 740 is formed on the main surface 701 by a photolithographic process. Dopant atoms of the conductivity type of the drift layer 731 are introduced into the silicon carbide substrate 700 through mask openings 741 of the mask 740. The introduction of the dopant atoms can comprise an ion beam implantation process with different acceleration energies.

[0079] Fig. 3B shows mask 740 with mask openings 741. Mask 740 may comprise a single layer of one material or two or more sublayers of different materials. According to one embodiment, mask 740 comprises carbon, e.g., graphite, silicon oxide, and / or silicon nitride.

[0080] The dopant atoms introduced through the mask openings 741 form implantation regions 710, which extend below the mask openings 741 from the main surface 701 into the body structure 720. In the implantation regions 710, the introduced dopant atoms overcompensate the doping of the body structure 720 and / or the contact wells 729 of the Fig. 3A. Portions of the contact wells 729, which are shielded against implantation by the mask 740, form body contact regions 129. A conformal auxiliary layer 780 is deposited, for example, by a CVD (chemical vapor deposition) process.

[0081] According to Fig. 3C, the auxiliary layer 780 covers the mask 740, portions of the main surface 701 in the mask openings 741, and sidewalls of the mask 740 with a uniform or at least approximately uniform layer thickness. The layer thickness d1 of the auxiliary layer 780 is less than half the width w1 (d1 < w1 / 2) of the mask openings 741 before the deposition of the auxiliary layer 780. The auxiliary layer 780 may comprise carbon, silicon oxide, polysilicon, amorphous silicon, and / or silicon nitride. The mask 740 and the auxiliary layer 780 may be formed from different materials, from the same material, or from the same materials.

[0082] With the auxiliary layer 780 lying on the silicon carbide substrate 707 and a suitable material for the auxiliary layer 780, a heat treatment can activate the dopant atoms introduced into the implantation regions 710, whereby the dopant atoms can be incorporated into lattice sites in the crystal lattice of the SiC crystal and any implantation damage in the crystal lattice can be at least largely healed. The activation of the dopant atoms can also occur at a later time.

[0083] An anisotropic etching process, for example, a chemical-physical dry etching process, can remove material from the first auxiliary layer 780 from above. The removal of the auxiliary layer 780 is terminated after exposing the first main surface 701 in the mask openings 741 and before the material of the auxiliary layer 780 is completely removed.

[0084] Fig. 3D shows auxiliary structures 781 formed from remaining sections of the auxiliary layer 780 on side walls of the mask openings 741. The layer thickness of the auxiliary structures 781 can correspond to the layer thickness d1 of the auxiliary layer 780 of the Fig. 3C. The auxiliary structures 781 reduce the width of the mask openings 741 symmetrically to a central longitudinal axis of the mask openings 741. A width w3 of the mask openings 741 after formation of the auxiliary structures 781 is, for example, 200 nm to 3000 nm or 400 nm to 1500 nm smaller than the width w1 of the mask openings 741 before formation of the auxiliary structures 781. Each mask opening 741 is reduced to a central portion of the respective mask opening 741 before formation of the auxiliary structures 781.

[0085] Using an anisotropic etching process, e.g., a chemical-physical dry etching process, trenches 750 are formed, which may extend below the first mask openings 741 from a plane spanned by the main surface 701 through the implantation regions 710 and the body structure 720 into the drift layer structure 730.

[0086] Dopant atoms of the conductivity type of the body structures 720 can be introduced into the drift layer structure 730, e.g., into the drift layer 731, through the bottom of the trenches 750. Before introducing the dopant atoms through the bottom of the trenches 750, a first sacrificial layer can be formed, which covers at least sidewalls of the trenches 750. After introducing the dopant atoms, a second sacrificial layer can be formed after removing the first sacrificial layer or in addition to the first sacrificial layer.

[0087] With a second sacrificial layer in place, heat treatment can activate the dopant atoms introduced through the bottom of the trenches 750, whereby the dopant atoms can be incorporated into lattice sites in the crystal lattice of the SiC crystal, and any implantation damage in the crystal lattice can be healed. The heat treatment can be performed at a minimum of 800°C and a maximum of 2200°C or a maximum of 1900°C. Simultaneously with the dopant atoms introduced through the bottom of the trenches, the dopant atoms in the implantation regions 710 can also be activated.

[0088] Fig. 3E shows the trenches 750 after the removal of all aforementioned sacrificial layers. The trenches 750 may have vertical sidewalls that run parallel to (1-100) lattice planes. The trenches 750 are formed below central portions of the mask openings 741 prior to the formation of the auxiliary structures 781. The dopant atoms introduced through the bottom of the trenches 750 and activated form shielding regions 140, each of which extends from the trench bottom into the drift layer structure 730.

[0089] The implantation areas 710 (see Fig. 3D) introduced and activated dopant atoms form in the Fig. 3E, which each extend from the main surface 701 along sidewalls of the trenches 750 into the silicon carbide substrate 700. The lateral width w2 of the source regions 110 can correspond to the layer thickness of the auxiliary structures 781 or can exceed the layer thickness of the auxiliary structures 781 in a defined manner due to under-irradiation of the mask and / or scattering of the implanted ions on substrate atoms, depending on the level of the implantation energy. The lateral width w2 of the source regions 110 can ultimately be determined via the layer thickness d1 of the auxiliary layer 780 (cf. Fig. 3C) can be adjusted precisely.

[0090] Sections of the body structure 720 (cf. Fig. 3D) between the trenches 750 form in the Fig. 3E illustrated body regions 120. Sections of the current distribution layer 737 (cf. Fig. 3D) between the trenches 750 form in the Fig. 3E shows electricity distribution areas 137.

[0091] A field dielectric 159 may be formed in the trenches 750, which is formed in a lower portion of the trenches 750 on the sidewalls of the trenches 750. Forming the field dielectric 159 may include thermal oxidation and / or the deposition of one or more dielectric layers. A conductive interconnect structure 157 may be formed in the lower portion of the trenches 750. Forming the conductive interconnect structure 157 may include the deposition of highly doped polycrystalline silicon and / or the formation of one or more metallic layers.

[0092] An isolation dielectric 156 may be formed on the interconnect structure 157. Forming the isolation dielectric 156 may include thermally oxidizing an upper portion of the interconnect structure 157 and / or depositing one or more dielectric layers.

[0093] A gate dielectric 151 may be formed in an upper portion of the trenches 750 between the main surface 701 and the isolation dielectric 156. Forming the gate dielectric 151 may include thermal oxidation and / or the deposition of one or more dielectric layers. A conductive gate electrode 155 may be formed in the upper portion of the trenches 750. Forming the conductive gate electrode 155 may include the deposition of highly doped polycrystalline silicon and / or the formation of one or more metallic layers. An upper edge of the gate electrode 155 may be retracted below a plane spanned by the main surface 701.

[0094] An interlayer dielectric layer 200 may be deposited that fills a space between the plane spanned by the main surface 701 and the gate electrode 155.

[0095] Fig. 3F shows in trenches 750 of the Fig. 3E illustrates gate electrode structures 150 having a gate electrode 155 and a conductive interconnect structure 157 directly adjacent to the shielding region 140 formed beneath the gate electrode structure 150. A field dielectric 159 separates the conductive interconnect structure 157 and the current distribution regions 137. A gate dielectric 151 separates the gate electrode 155 and the body regions 120. An isolation dielectric 156 separates the gate electrode 155 and the conductive interconnect structure 157.

[0096] The electrical breakdown strength of the field dielectric 159 is higher than that of the gate dielectric 151. For example, the layer thickness th2 of the field dielectric 159 is greater than the layer thickness th1 of the gate dielectric 151. The interlayer dielectric layer 200 may comprise a single layer of one dielectric material or two or more sublayers of different dielectric materials.

[0097] The mask 740, the auxiliary structures 781, and portions of the interlayer dielectric layer 200 above the main surface 701 are removed. The removal occurs, in particular, before the application of a front-side metallization 790.

[0098] Unlike in the Fig. 3E and Fig. As shown in Figure 3F, the mask 740 and / or the auxiliary structure 781 may be at least partially thinned or completely removed prior to the formation of a gate electrode structure and / or a shielding region 140. The removal may include a polishing process that exposes portions of the main surface 701 between the gate electrode structures 150. One or more metal-containing layers may be deposited onto the main surface 701.

[0099] Polishing and / or over-etching cleaning may attack the materials of the interlayer dielectric 210 and the sections of the main surface 701 slightly differently. This may result in a step between the sections of the main surface 701 and the sections of the interlayer dielectric layer 200. An upper edge of the interlayer dielectric 210 may therefore be flush with the main surface 701 or be formed a few nanometers below the main surface 701. A distance between the upper edge of the interlayer dielectric 210 and a plane spanned by the main surface 701 may, for example, correspond to a maximum of 20% or a maximum of 10% of the thickness of the interlayer dielectric 210.

[0100] The Fig. 3G shows a front-side metallization 790 formed from the metal-containing layers, which rests with a bottom surface alternately on sections of the main surface 701 and on sections of an interlayer dielectric 210, wherein the interlayer dielectric 210 is formed from remaining sections of the interlayer dielectric layer 200 of the Fig. 3F is formed. The front-side metallization 790 and the source regions 110 form first ohmic contacts. The front-side metallization 790 and the body contact regions 129 form second ohmic contacts.

[0101] The Fig. 4A and Fig. 4B relate to an embodiment comprising a self-aligned implantation of dopants to form body contact regions 129.

[0102] A drift layer structure 730 and a body structure 720 are formed in a silicon carbide substrate 700 as described above, with the body structure 720 extending from the main surface 701 to the drift layer structure 730. As described above, a mask 740, implantation regions 710, auxiliary structures 781, and trenches 750 are formed. Dopant atoms of the doping type of the body structure 120 are implanted into the drift layer structure 130 through the bottom of the trenches 750.

[0103] The silicon carbide substrate 700 of the Fig. 4A differs from the silicon carbide substrate 700 of Fig. 3E at least by the missing body contact area 129. The mask 740 and the auxiliary structures 781 are made of different materials.

[0104] The mask 740 is removed selectively with respect to the auxiliary structures 781, exposing at least a portion of the main surface 701 between two adjacent auxiliary structures 781. The dopant atoms of the conductivity type of the body structure 120 are implanted into exposed portions of the silicon carbide substrate 700. A sacrificial layer may be deposited covering exposed portions of the main surface 701. A heat treatment may activate the implanted dopant atoms, and the sacrificial layer may largely suppress the evaporation of silicon atoms.

[0105] The Fig. 4B shows a complementary mask 760 formed from the auxiliary structures 781. The complementary mask 760 completely covers a portion of the main surface 701 through which dopant atoms were introduced to form the source regions 110. Complementary mask openings 761 in the complementary mask 760 completely expose those portions of the main surface 701 that are covered during the introduction of dopant atoms to form source regions 110.

[0106] The implantation areas 710 of the Fig. 4A introduced and activated dopant atoms form source regions 110. The dopant atoms introduced and activated through the complementary mask openings 761 through portions of the main surface 701 form body contact regions 129.

[0107] The relative positions of the body contact regions 129 and the source regions 110 are determined by the same lithography process. The body contact regions 129 and the source regions 110 are self-aligned to one another. Neither the formation of the body contact regions 129 nor the formation of the source regions 110 requires overcompensation for a high counter-doping. The source regions 110 and the body contact regions 129 can have a low ohmic resistance and / or form low-loss ohmic contacts with a load electrode.

[0108] When introducing the dopants through the complementary mask openings 761, the bottom of the trenches 750 can be covered. Alternatively, when introducing the dopants through the complementary mask openings 761, the dopants can also be introduced through the bottom of the trenches 750 and increase the dopant concentration along the bottom of the trenches 750. The dopant atoms introduced through the bottom of the trenches 750 and activated form shielding regions 140, each of which extends from the bottom of the trenches 750 into the drift layer structure 730. The dopant atoms additionally introduced during the implantation to form the body contact regions 129 can contribute to the formation of a shielding contact region 149 that directly borders the trench bottom and has a higher dopant concentration than the shielding region 140. The shielding contact region 149 can improve the outflow of charge carriers from the shielding region 140 to a load electrode.

[0109] During the introduction of the dopants by ion implantation, an auxiliary layer may be present on the walls of the trenches 750, which prevents or at least significantly reduces the penetration of dopants into the sidewalls of the trenches 750. This auxiliary layer is in the Fig. 4A or 4B not shown.

[0110] The Fig. 5A-5F show an embodiment in which dopant atoms are introduced to form source regions after the formation of trenches for gate electrode structures.

[0111] The Fig. Figure 5A shows a silicon carbide substrate 700 based on a hexagonal SiC crystal type, e.g. 4H-SiC, and whose <0001> Grid direction is tilted by an angular deviation α against the surface normal 704 to the main surface 701.

[0112] The cross-sectional planes of the Fig. 5A-5F are chosen so that the <0001> Lattice direction in the cross-sectional plane is tilted by the angular deviation α against the surface normal 704. The <11-20> lattice direction is tilted in the cross-sectional plane by the angular deviation α against the main surface 701. The <1-100> lattice direction is orthogonal to the cross-sectional plane and parallel to the skin surface 701. For further properties of the silicon carbide substrate 700, please refer to the description of the Fig. 2A and Fig. 3A is referred to.

[0113] A mask 740 with mask openings 741 is formed on the main surface 701. A directed, chemical-physical dry etching process, e.g., ion beam etching, transfers the structure of the mask 740 dimensionally accurate into the silicon carbide substrate 700, with trenches 750 being formed in the silicon carbide substrate 700 below the mask openings 741. Dopant atoms of the conductivity type of the body structure 720 are introduced through the bottom of the trenches 750.

[0114] As in Fig. 5B, when the dopants are introduced through the trench bottom, a sacrificial layer 261 may cover the bottom and sidewalls of the trenches 750, as shown in the left trench 750. According to another embodiment, the sacrificial layer 261 may be formed only on the sidewalls of the trenches 750, so that the silicon carbide substrate 700 is exposed at the trench bottom, as shown in the right trench 750.

[0115] The sidewalls of the trenches 750 may be tilted to the vertical so that at least one sidewall is aligned parallel to (11-20) lattice planes. Gate electrode structures 150 are formed in the trenches 750. Details of the gate electrode structures 150 and their fabrication are described above with reference to Fig. 3F described.

[0116] Fig. 5C shows gate electrode structures 150 formed in the trenches 750, including conductive interconnect structure 157, field dielectric 159, isolation dielectric 156, gate dielectric 151, and gate electrode 155. The formation of the gate electrode structures 150 may include sub-processes that result in the sidewalls of the mask openings 741 moving away from the sidewalls of the gate electrode structures 150 in the lateral direction.

[0117] The formation of the gate electrode 155 comprises forming a gate electrode material back below the main surface 701. A distance d2 between a plane spanned by the main surface 701 and an upper edge of the gate electrode 155 is, for example, at least the thickness th1 of the gate dielectric 151 or at least twice the thickness th1 of the gate dielectric 151. For example, the distance d2 is at least 10 nm and at most 500 nm or at least 30 nm and at most 300 nm.

[0118] Dopant atoms are introduced into the silicon carbide substrate 700 through the mask openings 741 to form source regions. The gate electrode 155 delimits a vertical extent of an implantation region 110 introduced by the dopant atoms. The mask 740 delimits a lateral extent of the implantation region 110.

[0119] In at least some of the embodiments described here, the introduction of the dopants may comprise an implantation with an ion beam that forms an angle β unequal to 0° with the surface normal 704. In other words, the ion beam 105 may be inclined relative to the surface normal 704. For example, the magnitude of the angle β is at least 8°. Alternatively, the magnitude of the angle β may be less than 8°. Typically, the magnitude of the angle β is at least 8° and at most 70°, in particular at least 20° and at most 50°.

[0120] It is possible, for example, that in a first step at least a first implantation region and / or a first part of the implantation regions is implanted with a first ion beam 105 and in a second step at least a second implantation region and / or a second part of the implantation regions is implanted with a second ion beam 106. The first implantation region and the second implantation region can be formed on opposite sidewalls of the trench. For example, the first ion beam 105 forms a positive angle +β with the surface normal 704 in the cross-sectional plane, and the second ion beam 106 forms a negative angle -β with the surface normal 704 in the cross-sectional plane, or vice versa. The first and second ion beams differ, for example, only in that they each form a different angle with the surface normal 704.Alternatively, it is possible for different implantation energies and / or implantation doses to be used for the first ion beam and the second ion beam. For example, the first implantation region may have a different dopant concentration and / or a different size than the second implantation region.

[0121] Each implantation region may result from a plurality of implantations, wherein the mask openings 741 may be enlarged or reduced in size prior to each implantation. According to one embodiment, the introduction of the dopants comprises at least one implantation with an ion beam 105 that is inclined at an angle between 8° and 70° or between 20° and 50° relative to the surface normal 704.

[0122] According to the Fig. In the embodiment illustrated in Figure 5D, the introduction of dopant atoms to form source regions may comprise two symmetrical implantations, the ion beams 105, 106 of which impinge on the main surface 701 in the cross-sectional plane at a positive angle +β and at a negative angle -β to the surface normal 704. The magnitude of the angle β is, for example, between 8° and 70° or between 20° and 50°.

[0123] The implanted dopant atoms form implantation regions 710 in the silicon substrate 700, the vertical extent of which depends on the distance d2 and the lateral extent of which depends on a distance between the sidewalls of the gate electrode structures 150 and the sidewalls of the mask opening 741.

[0124] As in Fig. 5E, after introduction of the dopant atoms to form source regions, an interlayer dielectric layer 200 can be formed as described with reference to Fig. 3F and the dopant atoms are activated, wherein from the implantation regions 710 of the Fig. 5D source regions 110. The process can be described as with reference to Fig. 3G described.

[0125] The Fig. 5F shows a semiconductor device 500, for example, from the method of Fig. 5A-5E and may comprise a SiC semiconductor body 100 formed from a portion of the silicon carbide substrate 700 of the Fig. 5E. A first load electrode 310 lies alternately on portions of a first surface 101 of the SiC semiconductor body 100 and on portions of an interlayer dielectric 210 as described with reference to Fig. 3G. An upper edge of the interlayer dielectric 210 may lie in the plane spanned by the first surface 701 or may be recessed by a few nanometers relative to the first surface 701.

[0126] The Fig. 6 to 8 illustrate examples of the Fig. 5D described implantation process.

[0127] In Fig. 6, an implantation auxiliary layer 269 is applied to the gate electrode 155 at the time of implantation. With increasing thickness of the implantation auxiliary layer 269, the penetration depth of the ions decreases. The thickness of the implantation auxiliary layer 269 can be used to adjust the lateral width of the implantation regions 710 independently of a minimum acceleration energy of the ions. The implantation auxiliary layer 269 can be a sacrificial layer that is removed again after implantation, the interlayer dielectric layer 200 can be Fig. 5E, or a partial layer of the interlayer dielectric layer 200 according to Fig. 5E form.

[0128] In Fig. 7, the sidewalls of the mask openings 741 are retracted by a distance r1 from the sidewalls of the gate electrode structures 150 at the time of implantation. The distance r1 may be solely a side effect of the formation of the gate electrode structures 150 or may be adjusted by an additional isotropic etch-back process.

[0129] In Fig. 8, at the time of implantation, auxiliary spacer structures 783 with a thickness r2 are formed along the side walls of the mask openings 741. The thickness r2 can be selected such that the auxiliary spacer structures 783 have a Fig. 7, at least partially compensate, just completely compensate, or overcompensate for the temporary enlargement of the mask opening 741 described above. According to one embodiment, the implantation can be carried out only on one side, so that no implantation region 710 and ultimately no source region 110 is formed along a sidewall, for example, the sidewall with low charge carrier mobility. The said sidewall is then free of a source region 110. For example, the said sidewall is completely covered by the body region 120 in the region of the gate electrode structure 150 and / or in the region of the gate electrode 155.

[0130] Fig. 9A to 9D show a semiconductor device 500, which, for example, consists of a Fig. 1, 2A-2B, 3A-3G, 4A-4B, 5A-5F and 6-8.

[0131] Semiconductor device 500 includes a SiC semiconductor body 100. According to other embodiments, a semiconductor body may be formed from another wide-bandgap semiconductor material. Semiconductor device 500 may be an IGFET, an IGBT, or an MCD (MOS controlled diode). The semiconductor material may be, for example, crystalline silicon carbide with a hexagonal crystal lattice, for example, 2H-SiC, 6H-SiC, or 4H-SiC.

[0132] A first surface 101 on a front side of the SiC semiconductor body 100 can be coplanar with a main lattice plane of the SiC crystal, wherein the first surface 101 is planar. According to another embodiment, the orientation of the first surface 101 is inclined relative to a main lattice plane by an angular deviation α, wherein an absolute value of the angular deviation can be at least 2° and at most 8°, for example approximately 4°. The first surface 101 can then be planar or ribbed. In the case of a ribbed first surface 101, the first surface 101 can have parallel first surface sections and parallel second surface sections. The first surface sections are offset from one another and inclined relative to a horizontal center plane by the angular deviation α.The second surface sections extend obliquely to the first surface sections and connect the first surface sections so that a cross-sectional line of the first surface forms a sawtooth line.

[0133] Directions parallel to the planar first surface 101 or to a midplane of a ribbed first surface 101 are horizontal and lateral directions. A normal 104 to a planar first surface 101 or to the midplane of a ribbed first surface 101 defines a vertical direction. <0001> Grid direction is in a plane orthogonal to the cross-sectional plane of the Fig. 9B is tilted by the angular deviation α. ​​The <1-100> grating direction runs in the cross-sectional plane and parallel to the first surface 101.

[0134] On the back side of the SiC semiconductor body 100, a second surface 102 extends parallel to the first surface 101. A distance between the first surface 101 on the front side and the second surface on the back side correlates with the nominal dielectric strength of the semiconductor device 500. A total thickness of the SiC semiconductor body 100 between the first and second surfaces 101, 102 can be in the range of several hundred nm to several hundred µm.

[0135] On the front side, transistor cells TC are formed along the first surface 101. A drift structure 130 is formed between the transistor cells TC and the second surface 102. The drift structure 130 can have a heavily doped base section 139 and a lightly doped drift zone 131. The base section 139 directly borders the second surface 102. The drift zone 131 is formed between the transistor cells TC and the base section 139. Along the second surface 102, the dopant concentration in the base section 139 is sufficiently high to form an ohmic contact with a metal.

[0136] If the semiconductor device 500 is an IGFET or an MCD, the base section 139 and the drift zone 131 have the same conductivity type. If the semiconductor device 500 is a reverse-blocking IGBT, the base section 139 and the drift zone 131 have complementary conductivity types. If the semiconductor device 500 is a reverse-conducting IGBT, the base section 139 can include zones of both conductivity types, each extending from the drift zone 131 to the second surface 102.

[0137] The drift zone 131 may be formed in an epitaxial layer. An average dopant concentration in the drift zone 131 may be in a range of 1E15 cm -3 up to 5E16 cm -3 The drift structure may have further doped regions, for example field stop zones, barrier zones of the conductivity type of drift zone 131, and / or counter-doped regions.

[0138] In the illustrated embodiment, the drift structure 130 has current distribution regions 137 that directly adjoin the drift zone 131 and are formed between the drift zone 131 and the first surface 101. An average dopant concentration in the current distribution regions 137 is at least 150% of an average dopant concentration in the drift zone 131 or, for example, is at least twice as high as in the drift zone 131. However, the drift structure 130 can also be free of current distribution regions 137. In this case, it is possible for the drift zone 131 to directly adjoin the body regions 120.

[0139] The drift zone 131 can be directly adjacent to the base section 139 or to a buffer layer, wherein the buffer layer and the drift zone 131 form a unipolar junction. A vertical extension of the buffer layer can be approximately 1 µm. An average dopant concentration in the buffer layer can be in a range of 3E17 cm-3 up to 1E18 cm -3 The buffer layer can reduce mechanical stresses in the semiconductor body 100, contribute to reducing the defect density in the semiconductor body, and / or can contribute to forming a desired electric field pattern in the drift structure 130.

[0140] The transistor cells TC are formed along gate electrode structures 150 that extend from the first surface 101 into the SiC semiconductor body 100 and into the drift structure 130. Portions of the SiC semiconductor body 100 between adjacent gate electrode structures 150 form semiconductor mesas 170.

[0141] A longitudinal extension of the gate electrode structures 150 along a first horizontal direction perpendicular to the cross-sectional plane of the Fig. 9B is larger than a width of the gate electrode structures 150 along a second horizontal direction in the cross-sectional plane of the Fig. 9B. The gate electrode structures 150 may, for example, be formed as long strips extending from one side of a transistor cell region to the opposite side, wherein the length of the gate electrode structures 150 may be up to several hundred µm or several mm.

[0142] The gate electrode structures 150 may each be formed at equal distances from one another, wherein a center-to-center distance between adjacent gate electrode structures 150 may be in a range from 0.4 µm to 20 µm, for example from 1 µm to 5 µm.

[0143] A vertical extension of the gate electrode structures 150 may be in a range from 300 nm to 5 µm, for example in a range from 500 nm to 2 µm.

[0144] In the illustrated embodiment, the sidewalls on the long sides of the gate electrode structures 150 are aligned vertically to the first surface 101. According to other embodiments with a different orientation of the long axis of the gate electrode structures 150 relative to the crystal axes, the sidewalls can be inclined to the vertical such that an angle between one of the sidewalls and the normal 104 is equal to the angular deviation α or deviates from it by no more than ± 1°, wherein at least one long sidewall of the gate electrode structures 150 lies in a main lattice plane with high charge carrier mobility. In general, at least one long sidewall of the gate electrode structures 150 can lie in one of the lattice planes (11-20), (-1-120), (1-100), and / or (-1100).

[0145] In a semiconductor mesa 170, source regions 110 may be formed along the sidewalls of the adjacent gate electrode structures 150, extending from the first surface 101 into the semiconductor body 100. A body region 120 is formed in each semiconductor mesa 170, separating the source regions 110 from a current distribution region 137 formed at least partially in the semiconductor mesa 170. The body region 120 may each adjoin both adjacent gate electrode structures 150.

[0146] The body regions 120 and the current distribution regions 137 form first pn junctions pn1. The body regions 120 and the source regions 110 form second pn junctions pn2. The source regions 110 form first ohmic contacts with a first load electrode 310 on the front side of the SiC semiconductor body 100. The body regions 120 may include body contact regions 129 that extend from the first surface 101 into the SiC semiconductor body 100 between the source regions 110 of a semiconductor mesa 170.

[0147] Shielding regions 140 may be formed along the bottom of the gate electrode structures 150, which directly adjoin the bottom of the gate electrode structures 150. The shielding regions 140 form third pn junctions pn3 with the drift structure 130, for example with the drift zone 131. The shielding regions 140 may lie entirely within a vertical projection of the gate electrode structures 150 or may extend laterally beyond the sidewalls of the gate electrode structures 150. An average dopant concentration in the shielding regions 140 may be in a range of 1E17 cm -3 up to 2E19 cm -3 lie, for example in a range of 8E17 cm -3 up to 8E18 cm -3 .

[0148] The gate electrode structures 150 include a conductive gate electrode 155. The gate electrode 155 may, for example, comprise heavily doped polycrystalline silicon and / or a metal-containing layer. The gate electrode 155 may be connected to a gate metallization, wherein the gate metallization may form a gate terminal or be connected to a gate terminal.

[0149] A gate dielectric 151 separates the gate electrode 155 from the body regions 120. The gate dielectric 151 may comprise or consist of a semiconductor dielectric. The semiconductor dielectric may, for example, be a thermally grown or deposited semiconductor oxide, for example a silicon oxide, a semiconductor nitride, for example deposited or thermally formed silicon nitride, and / or a semiconductor oxynitride, for example a silicon oxynitride. The gate dielectric 151 may also be made of another deposited dielectric material or of any combination of the aforementioned materials. According to one embodiment, the gate dielectric 151 comprises a silicon oxide that is densified and / or partially nitrided after deposition. The materials and thickness th1 of the gate dielectric 151 may be selected such that a voltage in a range from 1 to 8V is established as the threshold voltage for the transistor cells TC.

[0150] The gate electrode structures 150 further comprise a conductive connection structure 157, which forms a low-resistance electrical contact with the shielding regions 140. The conductive connection structure 157 may, for example, comprise heavily doped polycrystalline silicon and / or a metal-containing layer, e.g., a silicide. The connection structure 157 is connected to a potential or network node whose electrical potential, during operation of the component, is different from the potential of the gate terminal and the potential at the second load terminal L2. For example, the connection structure 157 is connected to the first load terminal L1, to an auxiliary terminal of the semiconductor component 500, or to an internal network node.

[0151] An isolation dielectric 156 separates gate electrode 155 and interconnect structure 157. A field dielectric 159 separates interconnect structure 157 in the lateral direction from drift structure 130. Field dielectric 159 may be formed along the sidewalls of gate electrode structures 150. A layer thickness th2 of field dielectric 159 may be greater than a layer thickness th1 of gate dielectric 151. For example, layer thickness th2 of field dielectric 159 is at least 120%, for example at least 150%, of the layer thickness th1 of gate dielectric 151. Isolation dielectric 156 and field dielectric 159 may have the same configuration and be formed from the same materials or from different materials.For example, the isolation dielectric 156 and / or the field dielectric 159 may comprise deposited silicon oxide, thermally formed silicon oxide, silicon nitride, silicon oxynitride, and / or another deposited dielectric material.

[0152] An interlayer dielectric 210 is formed between a plane spanned by the first surface 101 and the gate electrode 155. A layer thickness th3 of the interlayer dielectric 210 is, for example, at least 25 nm, or at least 50 nm, or at least 200 nm.

[0153] The source regions 110 and a load electrode 310 on the front side of the SiC semiconductor body 100 form first ohmic contacts along the first surface 101 of the SiC semiconductor body 100. The body contact regions 129 and the load electrode 310 form second ohmic contacts. The base portion 139 and a second load electrode 320 on the back side of the SiC semiconductor body 100 form an ohmic contact along the second surface 102.

[0154] The load electrode 310 has a bottom surface 312 that alternately rests on portions of the first surface 101 and on portions of the interlayer dielectric 210.

[0155] The first load electrode 310 may form a first load terminal L1 or be electrically connected to a first load terminal L1. The first load terminal L1 may be the anode terminal of an MCD, the source terminal of an IGFET, or the emitter terminal of an IGBT. The second load electrode 320 may form a second load terminal L2 or be electrically connected to a second load terminal L2. The second load terminal L2 may be the cathode terminal of an MCD, the drain terminal of an IGFET, or the collector terminal of an IGBT.

[0156] In the off-state of the semiconductor device 500, depletion zones extending laterally from the third pn junctions pn3 into the current distribution regions 137 can shield the gate dielectric 151 from the high potential of the second load electrode 320, so that the electric field strength in the gate dielectric 151 does not exceed 3.5 MV / cm or 3 MV / cm.

[0157] In the event of an avalanche breakdown, the conductive connection structure 157 efficiently conducts charge carriers, for example, holes from an n-doped drift zone 131, which pass through the third pn junction, to the first load electrode 310. The avalanche current is conducted past the body regions 120 and cannot contribute to driving a parasitic bipolar transistor formed by the source regions 110, the body regions 120, and the drift structure 130.

[0158] Fig. 9C and Fig. 9D each show a plan view of end sections 169 of two gate electrode structures 150. In the end section 169, the connecting structure 157 is drawn to the first surface 101. A first opening 221 in the interlayer dielectric 210 exposes the gate electrode 155. A second opening 222 in the interlayer dielectric 210 exposes the connecting structure 157. Contacts (not shown) extend through the opening 221, 222 from the first load electrode 310 of the Fig. 9B up to the connection structure 157 and / or up to the gate electrode 155. A mesa width mw is smaller than a trench width mg.

[0159] As in Fig. 9D, the gate electrode structures 150 may have a first width ww1 in a central section 168 and a second width ww2 in an end section 169, wherein the second width ww2 is greater than the first width ww1, wherein even with a very small first width ww1, the contacting of the gate electrode 155 and the connecting structure 157 is lithographically relaxed.

[0160] The Fig. 10A-10G relate to an embodiment with gate electrode structures whose only conductive structure forms a gate electrode.

[0161] On the main surface 701 of a silicon carbide substrate 700 having a drift layer structure 730 and a body structure 720 as described above, a complementary mask 760 having complementary mask openings 761 is formed.

[0162] Fig. 10A shows the complementary mask 760 on the main surface 701 of the silicon carbide substrate 700. The complementary mask 760 may comprise a single layer of a single material or two or more sublayers of different materials. According to one embodiment, the complementary mask 760 comprises silicon oxide, silicon nitride, and / or carbon, e.g., graphite. Dopant atoms are implanted through the complementary mask openings 761. The implantation may comprise multiple subimplantations at different acceleration energies. The dopant atoms may be of a conductivity type corresponding to the conductivity type of the body structure 720.

[0163] Fig. 10B shows implantation structures 240 in portions of the silicon carbide substrate 700 in a vertical projection of the complementary mask openings 761. Each implantation structure 240 may include a first sub-region 241 and a second sub-region 242. The first sub-region 241 may adjoin the main surface 701. The second sub-region 242 may extend deeper into the silicon carbide substrate 700, starting from the body layer 720.

[0164] An auxiliary material 743, which can be etched with high selectivity against the complementary mask 760, is deposited, wherein the auxiliary material fills the complementary mask openings 761. Auxiliary material 743 deposited outside the complementary mask openings 761 can be removed. Removing the auxiliary material deposited outside the complementary mask openings 761 can, for example, comprise chemical-mechanical polishing.

[0165] Fig. 10C shows the auxiliary material 743 filling the complementary mask openings 761. The complementary mask 760 is removed selectively with respect to the auxiliary material 743. Dopants of the conductivity type of the drift layer structure 730 are introduced through the resulting openings.

[0166] Fig. 10D shows a diagram of the auxiliary material 743 of Fig. 3C formed mask 740 with mask openings 741. The dopant atoms introduced through the mask openings 741 form implantation regions 710 below the mask openings 741, which adjoin the main surface 701 and are each formed between two adjacent first subregions 241.

[0167] An auxiliary layer 780 is deposited, the layer thickness d1 of which is less than half the width w1 of the original mask openings 741. A heat treatment can activate the implanted dopants and / or heal crystal defects in the silicon carbide crystal. The overlying auxiliary layer 780 can thereby largely suppress the evaporation of silicon from the silicon carbide substrate 700.

[0168] Fig. 10E shows the auxiliary layer 780 lining the mask openings 741 and covering the mask 740. The auxiliary layer 780 may comprise, for example, silicon oxide, silicon nitride, or carbon. The material introduced into the implantation regions 710 of the Fig. 10D introduced and activated dopant atoms form source regions 110. The dopant atoms introduced and activated through the complementary mask openings 761 in the first subregions 241 form body contact regions 129. The dopant atoms introduced and activated through the complementary mask openings 761 in the second subregions 241 form shielding regions 140. Instead of the auxiliary layer 780, a sacrificial layer can first be applied, which is removed after the heat treatment and replaced by the auxiliary layer 780.

[0169] A directed etch, for example, an ion beam etching process, can remove material of the first auxiliary layer 780 from above. The removal of the auxiliary layer 780 can be terminated after the first main surface 701 is exposed in the mask openings 741 and before the auxiliary layer 780 is completely removed. Remaining sections of the auxiliary layer 780 form auxiliary structures 781 along the sidewalls of the mask openings 741. A subsequent etching process transfers the mask opening 741 dimensionally accurate into the silicon carbide substrate 700, using the mask 740 and the auxiliary structures 781 as an etching mask.

[0170] Fig. 10F shows trenches 750, the lateral extent of which is defined by the mask openings 741, wherein the mask opening 741 is reduced by the auxiliary structures 781 compared to the introduction of the dopant atoms through the mask openings 741. A layer thickness d1 of the auxiliary layer 780 of Fig. 3E defines the lateral width of the source regions 110. A vertical extent v1 of the trenches 750 may be smaller than a distance v2 between the main surface 701 and a lower edge of the shielding regions 140.

[0171] A gate dielectric 151 may be formed in the trenches 750. Forming the gate dielectric 151 may include thermal oxidation and / or the deposition of one or more dielectric layers. A conductive gate electrode 155 may be formed in the trenches 750 lined with the gate dielectric 151. Forming the conductive gate electrode 155 may include the deposition of highly doped polycrystalline silicon and / or the deposition of one or more metallic layers.

[0172] The mask 740 and the auxiliary structures 781 may be removed. An interlayer dielectric 210 may be formed between a plane spanned by the main surface 701 and the gate electrode 155. Forming the interlayer dielectric 210 may include depositing one or more dielectric layers and / or oxidizing the gate electrode material. One or more metal-containing layers are deposited onto the interlayer dielectric 210 and the main surface 701.

[0173] Fig. 10G shows a semiconductor device 500 which, after a separation process (dicing), is produced from the process of Fig. 10A to 10F. A semiconductor body 100 of the semiconductor device 500 may be formed from a part of the silicon carbide substrate 700 of the Fig. 10F. A part of the drift structure layer 730 of the Fig. 10F forms a drift structure 130.

[0174] A first load electrode 310 formed from the deposited metallic layers rests with a bottom surface 312 alternately on sections of the first surface 701 and sections of the interlayer dielectric 210. The first load electrode 310 contacts the source regions 110 and the body contact regions 129 directly, i.e., without forming contact structures. Neither the formation of the source regions 110 nor that of the body contact regions 129 involves counterdoping an already heavily doped region. The body contact regions 129 form a sufficiently good ohmic contact with the first load electrode 310 to reliably dissipate an avalanche current and / or ensure low-loss operation of the body diode. Further details of the semiconductor component 500 can be found in the description of the Fig. 9A and Fig. 9B.

Claims

[1] A method of manufacturing a semiconductor device, the method comprising: Providing a silicon carbide substrate (700) and a mask (740) on a main surface (701) of the silicon carbide substrate (700), wherein a mask opening (741) in the mask (740) exposes a first portion of the main surface (701); Forming a trench (750) in the silicon carbide substrate (700), the trench (750) being formed under the mask opening (741); Forming a source region (110) in the silicon carbide substrate (700), wherein the formation of the source region (110) comprises introducing first dopant atoms through the mask opening (741); and Forming a shielding region (140), wherein forming the shielding region comprises introducing second dopant atoms through a bottom of the trench (750), wherein the first dopant atoms and the second dopant atoms have complementary doping types. [2] Method according to the preceding claim, wherein the first dopant atoms are introduced after the formation of the trench (750). [3] Method according to the preceding claim, further comprising: Forming a gate electrode (155) in the trench (750) before introducing the first dopant atoms. [4] Method according to one of the preceding claims, further comprising: Forming, after forming the trench (750) and before introducing the first dopant atoms, auxiliary spacer structures (783) on side walls of the mask opening (741). [5] The method of claim 1, wherein the trench (750) is formed after the introduction of the first dopant atoms. [6] Method according to the preceding claim, wherein after the introduction of the first dopant atoms and before the formation of the trench (750), the mask opening (741) is reduced in size. [7] Method according to one of the two preceding claims, further comprising: Forming auxiliary structures (781) on side walls of the mask opening (741) after introducing the first dopant atoms and before forming the trench (750). [8] Method according to one of the three preceding claims, further comprising: Forming a gate electrode structure (150) in the trench (750). [9] Method according to one of the preceding claims, further comprising: Forming a complementary mask (760) on the main surface (701), wherein the complementary mask (760) covers the first portion of the main surface (701) and has a complementary mask opening (761), and the complementary mask opening (761) exposes a second portion of the main surface (701), Introducing second dopant atoms into the silicon carbide substrate (700) through the complementary mask opening (761), wherein the first dopant atoms and the second dopant atoms have complementary doping types, and Forming the mask (740), wherein the formation of the mask (740) comprises filling the complementary mask opening (761) with an auxiliary material (743) and removing the complementary mask (760) selectively with respect to the auxiliary material. [10] Method according to one of the preceding claims, further comprising: Removing the mask (740) and / or the complementary mask (760) and applying a metal layer (730) to the main surface (701). [11] Semiconductor device, comprising: a SiC semiconductor body (100); strip-shaped gate electrode structures (150) extending from a first surface (101) of the SiC semiconductor body (100) into the SiC semiconductor body (100), wherein the gate electrode structures (150) each have a gate electrode (155) and an interlayer dielectric (210), wherein the interlayer dielectric (210) is formed between the first surface (101) and the gate electrode (155), wherein the gate electrode structure (150) each have a conductive connection structure (157) and a separation dielectric (156), wherein in each case the connection structure (157) adjoins the SiC semiconductor body (100) along a bottom of the gate electrode structure (150) and the separation dielectric (156) is arranged between the gate electrode (155) and the connection structure (157); Source regions (110) with a lateral extent (w2) transverse to a longitudinal extent of the gate electrode structures (150), wherein the source regions (110) extend along sidewalls of adjacent gate electrode structures (150) from the first surface (101) into the SiC semiconductor body (100); Body contact regions (129) extending between adjacent source regions (110) from the first surface (101) into the SiC semiconductor body (100); and Shielding regions (140) each formed in the SiC semiconductor body (100) along the bottom of the gate electrode structure (150) and adjacent to the connecting structure (157). [12] Semiconductor device according to the preceding claim, further comprising: a first load electrode (310) having a bottom surface (312), the bottom surface (312) alternately adjacent to portions of the first surface (101) and to portions of the interlayer dielectric (210). [13] Semiconductor component according to one of the two preceding claims, wherein the gate electrode structures (150) each have a longitudinal extent in a first lateral direction (191), two end sections (169) along the longitudinal extent and a central section (168) between the two end sections (169), wherein orthogonal to the longitudinal extent the central section (168) has a first width (ww1) and at least one of the end sections (169) has a second width (ww2), and the second width (ww2) is greater than the first width (ww1). [14] Semiconductor component according to one of the three preceding claims, wherein each gate electrode structure (150) has a trench width (wg), and wherein a portion of the SiC semiconductor body (100) between adjacent gate electrode structures (150) forms a SiC mesa (170) with a mesa width (wm), and the mesa width (wm) is smaller than the trench width (wg).

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