METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT

Abstract

A method for producing a semiconductor device, comprising: Providing a silicon carbide substrate (700), wherein the silicon carbide substrate (700) has a trench (750), the trench (750) extending from a main surface (701) of the silicon carbide substrate (700) into the silicon carbide substrate (700) and having a trench width (wg) at a trench bottom (751); Forming a shielding region (140) in the silicon carbide substrate (700), wherein the shielding region (140) extends along the trench bottom (751), in at least one doping level (105) which runs parallel to the trench bottom (751), a dopant concentration in the shielding region (740) deviates over a lateral first width (w1) by no more than 10% from a maximum value of the dopant concentration in the doping level (105), and the first width (w1) is smaller than the trench width (wg) and is at least 30% of the trench width (wg), wherein the formation of the shielding region (140) comprises: Forming an implantation mask (740), wherein the implantation mask (740) is formed thinner at the trench bottom (751) than at side walls (752) of the trench (750), and introducing dopant atoms through the trench bottom (751); or Forming an implantation mask (740), wherein the implantation mask (740) has a first implantation mask opening (7411) with a third width (w3) at the trench bottom (751), the third width (w3) being greater than the first width (w1), and introducing dopant atoms through the first implantation mask opening (7411).

Description

TECHNICAL FIELD

[0001] The present application relates to semiconductor components with a SiC semiconductor body, in particular semiconductor switches with low on-resistance and high dielectric strength, as well as methods for producing semiconductor components. BACKGROUND

[0002] Power semiconductor components carry a comparatively high load current with high dielectric strength. In power semiconductor components with a vertical structure, the load current flows between two opposing main surfaces of a semiconductor body. The current-carrying capacity can be adjusted by the horizontal extent of the semiconductor body, and the dielectric strength can be adjusted by the vertical extent of a drift zone formed in the semiconductor body. In power semiconductor switches such as MOSFETs (metal oxide semiconductor field-effect transistors) and IGBTs (insulated gate bipolar transistors), a gate electrode capacitively couples into the body regions via a gate dielectric and switches the load current, for example, by temporarily forming an inversion channel in the body regions.In semiconductor bodies made of a material with an intrinsically high breakdown field strength, such as silicon carbide (SiC), the gate dielectric is exposed to a strong electric field in the blocking case, so that the breakdown strength of the gate dielectric can specify up to which voltage the dielectric strength of the semiconductor switch can be adjusted by the vertical extension of the drift zone.

[0003] The document US 2014 / 0 167 151 A1 describes a SiC MOSFET with a stepped trench gate. A floating p+ region is formed beneath the trench gate, which is insulated from the gate electrode by the gate dielectric. The lateral extent of the floating region is larger than the lateral extent of the trench gate at the trench bottom and narrower than the lateral extent of the trench gate at the level of the channel. The document US 2018 / 0 277 637 A1 describes the formation of a p-doped shielding region of a SiC MOSFET with a trench gate electrode by introducing dopant atoms through the bottom of a gate trench.

[0004] The general aim is to further improve the breakdown strength of semiconductor components without compromising on-resistance.

[0005] The problem underlying the application is solved by the method according to the main claim. Advantageous further developments arise from the dependent claims.

[0006] Further features and advantages of the disclosed subject matter will become apparent to the person skilled in the art from the following detailed description and from the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings provide a more in-depth understanding of embodiments of a semiconductor device and a method for manufacturing a semiconductor device, are incorporated in and constitute a part of this disclosure. The drawings merely illustrate embodiments and, together with the description, serve to explain the principles thereof. The semiconductor device and method described herein are therefore not limited to these by the description of the embodiments. Other embodiments and intended advantages will become apparent from an understanding of the following detailed description, as well as from combinations of the embodiments described below, even if not explicitly described. The elements and structures shown in the drawings are not necessarily drawn to scale with respect to one another.Like reference symbols refer to like or corresponding elements and structures. Fig. 1 is a simplified schematic flow diagram illustrating a method of manufacturing a semiconductor device according to one embodiment. Fig. 2A-2D schematically show vertical cross-sectional views of a silicon carbide substrate and a lateral dopant distribution of a shielding region in a doping plane to illustrate a method for manufacturing a SiC semiconductor device according to an embodiment. Fig. 3A-3L show schematic vertical cross-sectional views of a silicon carbide substrate for illustrating a method according to an embodiment in which dopant atoms are introduced into gate trenches by means of an implantation mask to form shielding regions. Fig. 4A-4B show schematic vertical cross-sectional views of a silicon carbide substrate for illustrating a method according to an embodiment in which dopant atoms are introduced into gate trenches by means of implantation masks to form shielding regions and JFET subregions. Fig. 5A-5B show a horizontal and a vertical cross section through a SiC semiconductor device. Fig. 6-8 each show a vertical cross-section through a SiC semiconductor device. Fig. 9A-9B illustrate the electric field in a SiC semiconductor device and in a comparison device using vertical cross-sections. DETAILED DESCRIPTION

[0008] In the following detailed description, reference is made to the accompanying drawings, which form a part of the disclosure and in which, for illustrative purposes, specific embodiments of a method for manufacturing a semiconductor device are shown. The existence of further embodiments is self-evident. Likewise, it is self-evident that structural and / or logical changes may be made to the embodiments without departing from the scope of the claims. The description of the embodiments is not limiting in this respect. In particular, features of embodiments described below may be combined with features of other described embodiments, unless the context indicates otherwise.

[0009] The terms "have," "contain," "comprise," "have," and the like are open-ended terms that, on the one hand, indicate the presence of the elements or characteristics in question, but, on the other hand, do not exclude the presence of further elements or characteristics. The indefinite and definite articles include both the plural and the singular, unless the context clearly indicates otherwise.

[0010] A safe operating area (SOA) defines the environmental and operating conditions under which fail-safe operation of a semiconductor device can be expected. Typically, the safe operating area is defined by specifying maximum values ​​for environmental and operating conditions in a semiconductor device datasheet, e.g., maximum continuous load current, maximum pulsed load current, maximum gate voltage, maximum reverse bias voltage, and others.

[0011] The term or expression "electrically connected" describes an ohmic, e.g., low-ohmic, connection between the electrically connected elements, for example, a direct contact between the elements in question or a connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" implies that one or more intermediate elements suitable for signal transmission may be present between the "electrically coupled" elements, e.g., elements that can be controlled to temporarily establish a low-ohmic connection in a first state and a high-ohmic decoupling in a second state.

[0012] In the following, the phrase "forming a contact" is to be understood as meaning that, during operation of a semiconductor component within the SOA between two structures that form a contact, at least one type of charge carrier can transfer from one structure to the other. In other words, there is contact between the two structures. Typically, the structures are directly adjacent to one another. An area in which the structures form the contact, e.g., where they are adjacent to one another, is also referred to below as a "contact area."

[0013] An ohmic contact, for example, refers to a junction between two structures with low electrical resistance and no rectifying effect. An ohmic contact can be formed, for example, between a metal structure and a sufficiently highly doped semiconductor structure. An ohmic contact region refers to the contact area, e.g., the contact surface, of an ohmic contact.

[0014] A Schottky junction is defined below as a junction with a rectifying effect between a semiconductor material and a metal structure, where, for example, the doping of the semiconductor material and the work function of the metal structure are selected such that, in equilibrium, a depletion zone forms in the semiconductor material along the interface. A Schottky junction region refers to the contact area, e.g., the contact surface of a Schottky junction.

[0015] Some figures represent relative dopant concentrations by indicating "-" or "+" next to the doping type. For example, the designation "n-" indicates a dopant concentration that is lower than the dopant concentration of an "n"-doped region, while an "n+"-doped region has a higher dopant concentration than the "n"-doped region. The indication of the relative dopant concentration does not imply that doped regions with the same relative dopant concentration must have the same absolute dopant concentration, unless otherwise stated. Accordingly, two different "n"-doped regions can have the same or different absolute dopant concentrations.

[0016] If a range of values ​​is defined for a physical quantity by specifying one or two limit values, the terms "from" and "to" or "less" and "more" include the respective limit value. A specification of the type "from ... to" is therefore understood as "from at least ... to at most." Similarly, a specification of the type "less ..." ("more ...") is understood as "at most ..." ("at least ...").

[0017] The abbreviation IGFET (insulated gate field effect transistor) refers to voltage-controlled semiconductor switches and includes not only MOSFETs (metal oxide semiconductor FETs) but also FETs whose gate electrode has doped semiconductor material and / or whose gate dielectric does not have an oxide or does not consist exclusively of an oxide.

[0018] Two adjacent doped regions with the same doping type (conductivity type) and different dopant concentrations form a unipolar junction along a junction surface, e.g., an n / n+ or a p / p+ junction. At the unipolar junction, a dopant profile perpendicular to the junction exhibits a step or inflection point where the dopant profile transitions from a concave to a convex profile or from a convex to a concave profile.

[0019] One embodiment relates to a method for manufacturing a semiconductor device. The method comprises providing a silicon carbide substrate, wherein the silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate and having a trench width at the trench bottom. A shielding region is formed in the silicon carbide substrate, wherein the shielding region may extend along the trench bottom.

[0020] The wording that the shielding region "extends" along the trench floor does not restrict a main extension direction of the shielding region. Rather, this can be interpreted to mean that the shielding region runs along the trench floor and / or that a total lateral width of the shielding region corresponds to at least 80% of a trench width. It is possible for the main extension direction of the shielding region to run along a vertical direction. For example, the shielding region can extend vertically through a large portion, e.g., at least 60%, of a drift zone of the semiconductor component to be fabricated.

[0021] In at least one doping level that runs approximately parallel to the trench floor, a dopant concentration in the shielding region deviates over a lateral first width by no more than ±10% from a maximum value of the dopant concentration in the shielding region in the doping level. Typically, the dopant concentration in the shielding region in the doping level deviates over a lateral first width by no more than ±5% or by no more than ±1% from a maximum value of the dopant concentration in the shielding region in the doping level. In other words, at least one horizontal dopant distribution of the shielding region has a plateau with the first width, wherein within the plateau the dopant concentration fluctuates by a maximum of ±10%, e.g., by a maximum of ±5% or by a maximum of ±1%. The region of the shielding region over the lateral first width can be a central section of the shielding region.

[0022] The trench floor may have a flat section in a ground plane. The ground plane may be parallel to the main surface, or the ground plane and the main surface may form an angle between 0° and 10°, e.g., an angle between 0° and 5°. The doping plane may be parallel to the ground plane, or the ground plane and the doping plane may form an angle between 0° and 10°, e.g., an angle between 0° and 5°.

[0023] The first width is smaller than the trench width. For example, the first width can be at least 50 nm or at least 150 nm and / or at least 2% or at least 5% smaller than the trench width. For example, the first width can be a maximum of 99%, a maximum of 95%, or a maximum of 90% of the trench width. The first width is at least 30% of the trench width.

[0024] Outside the central section, the dopant concentration in the shielding region can drop steeply in the lateral direction, so that the shielding region cannot protrude laterally beyond the gate electrode structure, or can only do so to a very small extent. For example, the total lateral width of the shielding region deviates from the trench width by a maximum of ±20% or by a maximum of ±10%. The shielding region does not reduce, or only slightly reduces, a cross-section of a current distribution region that may laterally border the gate electrode structure.

[0025] According to one embodiment, the doping plane can connect laterally adjacent local maximum values ​​of vertical dopant distributions in the shielding region. A distance between the trench floor and the doping plane can correspond to a penetration depth of the dopant atoms into the silicon carbide substrate, where the penetration depth (projected range) depends on the kinetic energy of the dopant atoms and indicates the average range of the dopant atoms from the irradiated surface. For example, the distance can be in a range from 20 nm to 500 nm, typically in a range from 50 nm to 300 nm.

[0026] According to this embodiment, for example, the maximum dopant concentration in the shielding region may have a dopant plateau over the lateral first width, in which the dopant concentration fluctuates by a maximum of ±10%, eg by a maximum of ±5% or by a maximum of ±1% of the maximum value in the shielding region.

[0027] According to one embodiment, a field dielectric may be formed in the trench, wherein the field dielectric has an opening with a lateral second width at the trench bottom. The second width may be smaller than the first width. The first and second widths may be defined along the same lateral direction.

[0028] Edges of the field dielectric toward the opening can be completely shielded by at least part of the central portion of the shielding region. Sections of the field dielectric toward the opening can therefore be effectively shielded from a backside electrode potential. High electric field strengths in sections of the field dielectric directly adjacent to the opening can be avoided.

[0029] According to one embodiment, the field dielectric along a sidewall of the trench may have a sidewall section with a first layer thickness th1 and the opening may have a second width w2, for which the following may apply: w2<(wg−2*th1), where wg equals the trench width. In other words: The second width is smaller than the difference between the trench width and twice the first layer thickness. This can result in edges of the field dielectric toward the opening being effectively shielded by a section of the shielding region where the dopant concentration does not drop.

[0030] The sidewall section of the field dielectric can extend to the trench floor. It is thus possible for a part of the sidewall section to cover the trench floor and / or terminate at the trench floor. The field dielectric can have two, for example, identically formed, sidewall sections, with each sidewall section extending along one of the sidewalls of the field dielectric.

[0031] It is possible for a bottom section of the field dielectric to extend laterally along the trench floor, starting from the sidewall section. The bottom section can be assigned to the sidewall section, i.e., directly connected to it. In the case of multiple sidewall sections, each sidewall section can be assigned a bottom section, with the bottom section extending along the trench floor, starting from the sidewall section assigned to it. The field dielectric can, for example, have two sidewall sections and two bottom sections.

[0032] The sidewall section, together with its associated bottom section, can be L-shaped. A portion of the field dielectric extending along the trench bottom can be formed from the bottom section and the part of the sidewall section that covers the trench bottom. The bottom section can be arranged between the side section and the opening in the trench bottom. For example, a distance between the opening and the sidewall section can be bridged by means of the bottom section.

[0033] The soil section may have a lateral soil width along the trench floor. Perpendicular to the soil width, the soil section may have a second layer thickness. The soil width may at least partially, in particular completely, compensate for the difference between the second width of the opening and the trench width and twice the first layer thickness. The soil width may correspond to half the difference between the trench width and the second width, minus the first layer thickness: wb=1 / 2*(wg−w2)−th1, where wb is the soil width of the soil section. In other words, the sum of the soil width and the first layer thickness can be half the difference between the trench width and the second width.

[0034] The respective factor 2 and conversely the factor 1 / 2 in the above-described relations of the trench width, the second width, the first layer thickness and (optionally) the bottom width can be based on the fact that the field dielectric can have two sidewall sections, wherein the sidewall sections can be formed on opposite sidewalls of the trench.

[0035] The two sidewall sections of a trench can be designed differently. Regardless of the number of sidewall sections in a trench, the sidewall sections of different trenches can be designed differently. If the trench has multiple sidewall sections, the sidewall sections of a trench can be designed identically or differently.

[0036] For example, two sidewall sections may have different first layer thicknesses, wherein for each of the first layer thicknesses the above relation to the difference between the trench width and the second width may be fulfilled independently.

[0037] Each sidewall section can be assigned a base section. The base sections of different sidewall sections can have different or identical base widths. In the first case, it is possible for the sum of the first layer thickness of the sidewall section and the base width of the base section assigned to the sidewall section to remain the same for different side sections (and thus also different base sections). A thicker sidewall section can therefore, for example, be compensated for by a narrower base section and vice versa. In the second case, in which different base sections have identical base widths, it is possible for the sum of the first layer thickness of the sidewall section and the base width of the base section assigned to the sidewall section to be different for different side sections.For example, in this case the opening is not centered with respect to the trench.

[0038] A central section of the shielding region, in which the dopant concentration is uniformly high, can extend laterally beyond the opening in the field dielectric. An edge of the field dielectric toward the opening can be completely covered by the central section of the shielding region. An edge between a conductive structure, which can border the shielding region in the area of ​​the opening in the field dielectric, the shielding region, and the field dielectric can be effectively shielded against a drain potential. The central section of the shielding region can reduce the maximum electric field strength in the field dielectric and / or the probability of breakdown through the field dielectric.

[0039] Forming the shielding region comprises forming an implantation mask, wherein the implantation mask is formed thinner at the trench bottom than at sidewalls of the trench and wherein the dopant atoms are introduced through the trench bottom and / or through the implantation mask at the trench bottom.

[0040] For example, forming the implantation mask may involve thermal oxide growth, with the thermal oxide growing at a slower rate at the trench bottom than at the sidewalls. The shielding region may be formed without an additional lithography process.

[0041] The implantation mask can largely prevent the scattering of dopant atoms through the sidewalls of the trench during the introduction of dopant atoms for the shielding region. For example, dopant atoms scattered into a body region can influence a threshold voltage for the formation of an inversion channel in the body region. Dopant atoms scattered into a current distribution region can increase the electrical resistance of the current distribution region and thus the on-resistance of a semiconductor component. The implantation mask can prevent the exposure of such doped regions to dopant atoms, whose quantity and precise location in the silicon carbide substrate would be subject to significant fluctuations. The implantation mask can also be used to precisely adjust the initial width in the shielding region, for example, in conjunction with the implantation energy used.

[0042] Alternatively, forming the shielding region comprises forming an implantation mask, wherein the implantation mask has an implantation mask opening with a third width at the trench bottom, and the dopant atoms are introduced through the implantation mask opening. The third width is larger than the first width, wherein the first width can be precisely adjusted via the third width and the implantation process parameters.

[0043] The introduction of the dopant atoms may comprise one or more ion implantation processes, wherein each ion implantation process may comprise multiple implantations at the same acceleration energy and at different implantation angles, and wherein the ion implantation processes differ with respect to the acceleration energies used. Each implantation process may comprise implantations at at least two different implantation angles, each of which may be symmetrical to a center plane of the trench.

[0044] According to an embodiment in which the doping level connects laterally adjacent local maximum values ​​of vertical dopant distributions in the shielding region, it is possible for the first width to deviate by no more than ±10% from a difference between the third width and twice the average distance of the doping level from the trench floor. The average distance between the trench floor and the doping level can correspond to the average penetration depth of dopant ions during ion implantation. The third width and the penetration depth allow the first width and thus the lateral extent of the uniformly and highly doped central section of the shielding region below the trench floor to be precisely adjusted and aligned with the opening in the field dielectric.

[0045] According to one embodiment, forming the implantation mask may include forming an implantation mask layer on sidewalls and at the trench bottom of the trench and removing a portion of the implantation mask layer at the trench bottom, wherein a remaining portion of the implantation mask layer may form the implantation mask.

[0046] The formation of the implantation mask can, in particular, comprise an anisotropic etching of a conformal implantation mask layer, wherein the first width can be precisely adjusted via the layer thickness of the conformal implantation mask layer and the width of the trench. A conformal layer covers a structured substrate with a uniform layer thickness that is largely independent of the alignment of subsections of the substrate to one another. The layer thickness of a conformal layer can exhibit slight fluctuations that are small compared to an average layer thickness of the conformal layer (for example, at most ±10% of the average layer thickness). A conformal layer can, for example, be formed by a thin-film deposition process, e.g., CVD (chemical vapor deposition).

[0047] According to one embodiment, the introduction of dopant atoms may comprise implantations at at least two different acceleration energies, wherein the width of the implantation mask opening may be changed between the implantations.

[0048] In particular, an implantation with higher acceleration energy can be performed with a smaller width of the implantation mask opening and an implantation with lower acceleration energy with a larger width of the implantation mask opening.

[0049] Implantations with higher acceleration energy can form a vertically extended JFET (junction field effect transistor) structure. Implantations with lower acceleration energy can be designed so that the opening of the field dielectric is sufficiently spaced from the outer lateral edge of the shielding region.

[0050] According to one embodiment, the implantation mask can be removed before forming the field dielectric. The field dielectric and implantation mask can thus be formed independently of each other and selected according to the respective requirements.

[0051] According to one embodiment, forming the field dielectric may comprise forming a field dielectric layer, wherein the field dielectric layer lines the trench and a portion of the field dielectric layer is removed at the trench bottom.

[0052] According to one embodiment, removing the portion of the field dielectric layer may comprise forming an etch mask on the field dielectric layer, wherein the etch mask may have an etch mask opening with the second width above the trench bottom. The second width can be precisely adjusted via the layer thickness of the etch mask.

[0053] The etching mask can, for example, be a layer, in particular a conformal layer, that covers, for example completely covers, the sidewall portions of the field dielectric and a bottom portion of the field dielectric to be created at the trench bottom. The layer thickness of the etching mask can correspond to the bottom width of the bottom portion.

[0054] According to one embodiment, a conductive connection structure may be formed in the trench, wherein the connection structure and the shielding region may form a contact.

[0055] The interconnect structure can be formed with an electrically conductive material, such as a metal or a semiconductor (e.g., a highly doped or degenerate semiconductor, such as polycrystalline silicon). The interconnect structure can contain multiple layers, with directly adjacent layers made of different materials.

[0056] The contact between the connecting structure and the shielding region can be an ohmic contact, which enables the discharge of charge carriers from the shielding region via the connecting structure to a load electrode.

[0057] A semiconductor component may comprise a SiC semiconductor body and a gate electrode structure. The gate electrode structure may extend from a first surface of the SiC semiconductor body into the SiC semiconductor body and may comprise a conductive connection structure. The gate electrode structure has a structure width at a bottom. A shielding region may be formed in the SiC semiconductor body along the bottom. A contact, e.g., an ohmic contact or a contact with a non-linear characteristic, e.g., a Schottky contact, may be formed between the conductive connection structure and the shielding region.

[0058] The shielding region may have a central section with a first width. In at least one doping level, which runs approximately parallel to the trench floor, a dopant concentration in the central section deviates from a maximum value in the doping level by no more than ±10%, typically by no more than ±5% or by no more than ±1%. The first width is smaller than the structure width and amounts to at least 30% of the structure width.

[0059] Such semiconductor components may have been manufactured using embodiments of the method described here. This means that all features described in connection with embodiments of the method may be disclosed correspondingly for the semiconductor component, and vice versa. For example, the bottom of the gate electrode structure may emerge from the trench bottom of a manufacturing process. The SiC semiconductor body may emerge from the silicon carbide substrate. The structure width may correspond to the trench width.

[0060] The first width of the central portion can be adjusted via the width of an opening in an implantation mask used in a method for manufacturing the semiconductor device for introducing dopant atoms through a trench bottom of a trench for forming the shielding region, wherein the gate electrode structure has been formed in the trench.

[0061] Outside the central section, the dopant concentration in the shielding region can drop sharply in the lateral direction, so that the shielding region cannot extend laterally beyond the gate electrode structure, or can only extend laterally to a very small extent. The shielding region does not reduce, or only slightly reduces, the cross-section of a current distribution region that may laterally border the gate electrode structure.

[0062] During the introduction of dopant atoms to form the shielding region, the scattering of dopant atoms through sidewalls of a trench in which the gate electrode structure is formed into doped regions laterally adjacent to the gate electrode structure can be suppressed.

[0063] The doping level can connect local maximum values ​​of vertical dopant distributions in the shielding region. A mean distance between the trench floor and the doping level can correspond to a penetration depth of the dopant atoms into the silicon carbide substrate. According to this embodiment, the maximum dopant concentration in the shielding region can have a dopant plateau across the lateral first width, in which the dopant concentration fluctuates by a maximum of ±10%, e.g., by a maximum of ±5%, or by a maximum of ±1% of the maximum value in the dopant level.

[0064] The first width may be smaller than a difference between the feature width and twice the average distance between the doping level and the ground, for example, equal to or smaller than a difference between the feature width and two and a half times or three times the average distance between the doping level and the ground. Accordingly, the formation of the shielding region may comprise an ion implantation, in which an implantation mask covers the sidewalls of the trench and at least partially prevents the introduction of dopant ions at undesired locations.For example, when forming the shielding region after forming a trench for the gate electrode and before forming the gate electrode in the trench, the penetration of dopants through a trench sidewall and through an outer portion of the trench bottom into a body region or into a portion of a drift zone or a current distribution region adjoining the body region towards the drain side can be reduced or completely avoided.

[0065] The gate electrode structure may include a field dielectric. The field dielectric may include a sidewall portion with a first layer thickness th1 along a sidewall of the gate electrode structure. The interconnect structure may have a second width w2 at the bottom, which may be smaller than the difference between the structure width w0 of the gate electrode structure at the bottom and twice the first layer thickness: w2<(w0-2*th1).

[0066] The contact between the connecting structure and the shielding region can be formed entirely by the central portion of the shielding region and / or by an end region of the connecting structure at the bottom. In this case, a contact region between the connecting structure and the shielding region can extend entirely along the shielding region and / or the end region of the connecting structure.

[0067] The central section of the shielding region shields the contact area and sections of the field dielectric directly adjacent to the contact area from a potential of a backside electrode. These sections of the field dielectric can be, for example, the bottom sections. High electric field strengths in sections of the field dielectric directly adjacent to the contact area can be avoided. Laterally retracting the contact area relative to the outer edges of the shielding region can reduce the maximum electric field strength in the field dielectric when the semiconductor device is operated in an SOA, lower the probability of a breakdown of the field dielectric, and increase the reliability of the semiconductor device.

[0068] The field dielectric can have a bottom section along the bottom with a second layer thickness that is equal to or smaller than the first layer thickness. The bottom section can be formed in an outer section of the bottom between a part of the connecting structure and the shielding region. It is possible for the shielding region, in particular its central region, to laterally overlap with the field dielectric, in particular its bottom section. The bottom section can retract the contact region between the connecting structure and the shielding region from a lateral outer edge of the central section of the shielding region, wherein the electric field occurring in sections of the field dielectric along the contact region can be reduced. The second layer thickness of the field dielectric can vary over the distance; for example, the layer thickness can decrease towards the connecting structure.

[0069] A JFET subregion can be formed in the SiC semiconductor body. The JFET subregion and the shielding region can form a unipolar junction. The shielding region is formed between the gate electrode structure and the JFET subregion. At the unipolar junction, the JFET subregion has a fourth lateral width that is smaller than the first width.

[0070] By laterally retracting the JFET sub-region, JFET sub-regions with a comparatively large vertical extent can be realized without reducing the cross-section of a current distribution region, which may laterally border the JFET sub-region, or reducing it more than to a small extent.

[0071] The gate electrode structure may comprise a gate electrode and an isolation dielectric, wherein the gate electrode is formed between the first surface and the interconnect structure, and wherein the isolation dielectric is formed between the gate electrode and the interconnect structure.

[0072] In at least one embodiment of a method and / or a semiconductor device described herein, at least one of the following features (if applicable) may apply: (i) A bottom portion of the field dielectric may extend from the sidewall portion along the bottom and / or along the trench bottom. (ii) The bottom portion may be disposed between the side wall portion and the opening in the trench bottom. (iii) The difference between the bottom width of the bottom section and the first layer thickness of the sidewall section may be equal to half the difference between the trench width and the second width. (iv) The side wall portion of the field dielectric may be L-shaped together with the bottom portion of the field dielectric. (v) The sidewall portion of the field dielectric may be formed integrally with the bottom portion of the field dielectric. (vi) The shielding region, for example its central portion, may laterally overlap with the field dielectric, for example its bottom portion. (vii) The bottom portion may partially cover the central portion of the shielding region. (viii) The connecting structure and the shielding area may be directly adjacent to each other.

[0073] According to Fig. 1, a method for producing a semiconductor component comprises providing a silicon carbide substrate (902), wherein the silicon carbide substrate has a trench, and the trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate (904), wherein the shielding region extends along the trench bottom. In at least one doping plane that runs approximately parallel to the trench bottom, a dopant concentration in the shielding region deviates over a lateral first width by no more than 10%, by no more than 5%, or by no more than 1% from a maximum value of the dopant concentration in the doping plane. The first width is smaller than the trench width and amounts to at least 30% of the trench width.

[0074] The Fig. 2A to 2D relate to a method for manufacturing a semiconductor device from a silicon carbide substrate 700.

[0075] The silicon carbide substrate 700 may comprise or consist of a SiC crystal. The polytype of the SiC crystal may be, for example, 15R or a hexagonal polytype, e.g., 2H, 4H, or 6H. In addition to the main components of silicon and carbon, the silicon carbide substrate 700 may comprise dopant atoms, for example, nitrogen (N), phosphorus (P), beryllium (Be), boron (B), aluminum (Al), and / or gallium (Ga). In addition, the silicon carbide substrate 700 may comprise impurities, for example, oxygen, hydrogen, fluorine, and / or bromine.

[0076] The silicon carbide substrate 700 may form a so-called semiconductor wafer, i.e. an approximately circular, flat disk with a main surface 701 on the front side and a back surface 702 on the back side of the disk, wherein the back surface 702 and the main surface 701 are aligned parallel to each other.

[0077] The main surface 701 can be planar or ribbed. In the case of a ribbed main surface, a median plane through the ribbed main surface is considered the main surface 701.

[0078] A surface normal 704 to the main surface 701 defines a vertical direction. Directions orthogonal to the surface normal 704 are lateral and horizontal directions. A diameter of the silicon carbide substrate 700 can correspond to an industry standard for semiconductor wafers, for example, 2 inches (51 mm), 3 inches (76 mm), 4 inches (100 mm), 125 mm, or 200 mm.

[0079] The silicon carbide substrate 700 may, for example, comprise a heavily doped base substrate and an epitaxial layer grown on the base substrate, wherein the epitaxial layer may comprise a plurality of differently doped sublayers and doped regions. The doped regions may be formed in portions of one or more of the sublayers.

[0080] Trenches 750 are formed in the silicon carbide substrate 700, extending from the main surface 701 into the silicon carbide substrate 700.

[0081] Fig. 2A shows trenches 750 with a trench bottom 751 and with sidewalls 752 that connect the first main surface 701 to the trench bottom 751. The sidewalls 752 can be vertically aligned or vertically inclined. The trenches 750 can be formed in stripes, wherein a length of the trenches 750 in a direction orthogonal to the cross-sectional plane is greater than a trench width wg of the trenches 750 parallel to the cross-sectional plane. Adjacent trenches 750 can be formed at the same center-to-center pitch p1 from one another.

[0082] A shielding region 140 is formed under each trench 750 and a field dielectric 159 with an opening 158 at the trench bottom 751 is formed in each trench 750.

[0083] The Fig. 2B and Fig. 2C show shielding regions 140, each of which extends vertically from the trench bottom 751 into the silicon carbide substrate 700 and can be formed symmetrically to a central axis of the trenches 750. The shielding regions 140 and a drift structure formed in the silicon carbide substrate 700 can form pn junctions. The shielding regions 140 each have a central section 145 with a first width w1. In a dopant plane 105 parallel or approximately parallel to the trench bottom 751, the dopant concentration within the central section 145 deviates by a maximum of 10%, or by a maximum of 5%, or by a maximum of 1%, from a maximum value in the central section 145 in the dopant plane 105.

[0084] Outside of the central section 145, the dopant concentration in the shielding region 140 can decrease significantly in the lateral direction. The first width w1 is smaller than the trench width wg and smaller than a total lateral width w11 of the shielding region 140 in the plane of the trench bottom 751. The total width w11 of the shielding region 140 can be less than or equal to the trench width wg. The total width w11 of the shielding region 140 can assume a value in a range from 500 nm to 3 µm.

[0085] The field dielectric 159 covers the sidewalls 752 and an outer portion of the trench bottom 751 at least in a lower portion of the trenches 750. The opening 158, which may be formed symmetrically to a central axis of the trench 750, exposes a central portion of the trench bottom 751. The opening 158 has a second width w2 that is smaller than the first width w1. A conductive connection structure 157 formed in the trench 750 directly adjoins the shielding region 140 in the region of the opening 158.

[0086] According to Fig. 2C, the field dielectric 159 may include at least one sidewall portion 1593 formed along one of the sidewalls 752 of the trench 750. The sidewall portion 1593 has a first layer thickness th1 and, in a portion of the trench bottom 751, directly adjoins the trench bottom 751 starting from the sidewall 752 up to a distance corresponding to the first layer thickness th1. The field dielectric 159 may include two sidewall portions 1593 formed on two opposing sidewalls 752 of the trench 750, wherein the two sidewall portions 1593 may have different first layer thicknesses th1 or the same first layer thickness th1.

[0087] The field dielectric 159 may include at least one bottom section 1592, which may extend laterally along the trench bottom 751 starting from one of the sidewall sections 1593, wherein the bottom section 1593 may be directly connected to the sidewall section 1593. The bottom section 1592 extends over a bottom width wb from an edge of the opening 158 to the sidewall section 1593 and has a second layer thickness th2, which may be equal to, greater than, or smaller than the first layer thickness th1. The lateral bottom width wb may assume a value in a range from 30 nm to 400 nm, for example, in a range from 100 nm to 300 nm.

[0088] The sidewall portion 1593 and the bottom portion 1592 may be integral, i.e., forming connected portions of a one-piece structure. The bottom portion 1592 and the sidewall portion 1593 may be made of the same material or materials. In a vertical cross-section transverse to the trench 750, the sidewall portion 1593 and the bottom portion 1592 together may have an L-shaped cross-sectional area.

[0089] The field dielectric 159 may have two bottom sections 1592, wherein the two bottom sections 1592 may have different second layer thicknesses th2 or the same second layer thickness th2. The bottom sections 1592 may be formed asymmetrically or symmetrically to the opening 158.

[0090] A total base width of all base sections 1592 in a trench 750 with the trench width wg is obtained by subtracting the first layer thicknesses th1 of the sidewall sections 1593 and the second width w2 of the opening 158 from the trench width wg. For symmetrically formed sidewall sections 1593 with the same first layer thickness th1 and a symmetrical opening 158, the base width wb of an individual base section 1592 is obtained by subtracting the first layer thickness th1 from half the difference between the trench width wg and the second width w2: wb=1 / 2*(wg−w2)−th1,

[0091] A distance Δw between an outer edge of the central portion 145 of the shielding region 140 and the opening 158 in the field dielectric 159 is at least 25 nm and at most 300 nm, for example at least 75 nm.

[0092] The formation of the shielding region 140 can include ion implantations at one or more acceleration voltages for dopant ions. The average range of the implanted dopant ions in the silicon carbide substrate 700 defines a penetration depth. A vertical dopant distribution in the shielding region 140 can be described by a Gaussian distribution or by the superposition of two or more Gaussian distributions. The distance of a local or global maximum of the vertical dopant distribution from the trench floor 751 corresponds to a penetration depth predetermined by the acceleration voltage of an implantation.

[0093] A dopant level 105 can connect, at a distance from the trench bottom 751, locations of laterally adjacent local maxima of the vertical dopant distributions in the shielding region 140, e.g., the locations of the absolute maxima in the shielding region 140 or the locations of such local maxima resulting from the same implantation.

[0094] Fig. Figure 2D shows a lateral dopant distribution in the dopant plane 105 of the Fig. 2C. Over the total lateral width w11 of the shielding region 140, the doping type implanted into the shielding region 140 can predominate. Over a first lateral width w1, the dopant concentration deviates by no more than 10% from the maximum dopant concentration in the doping level 105.

[0095] The lateral first width w1 is smaller than the total lateral width w11 and can be equal to or smaller than the difference between the trench width wg and twice the penetration depth d3, e.g. equal to or smaller than the difference between the trench width wg and two and a half times or three times the penetration depth.

[0096] The relatively highly and uniformly doped central portion 145 of the shielding region 140 effectively shields an edge between field dielectric 159, interconnect structure 157 and shielding region 140 against the potential of a load electrode located on a back side of the silicon carbide substrate facing away from the main surface 701.

[0097] The Fig. 3A-3L show an embodiment with gate electrode structures comprising, in addition to a conductive gate electrode, a conductive connection structure that may be electrically connected or electrically coupled to a doped shielding region below the gate electrode structure and to a front side metallization on the front side of the silicon carbide substrate.

[0098] The Fig. Figure 3A shows a silicon carbide substrate 700 based on a hexagonal SiC crystal type, e.g. 4H-SiC, and whose <0001> The grid direction is tilted by an angular deviation α (offset angle) against the surface normal 704 to the main surface 701. The angular deviation α can be between 2° and 8°, for example, about 4°.

[0099] The cross-sectional planes of the Fig. 3A-3L are chosen so that the <0001> Grid direction in a plane that is oriented orthogonal to the cross-sectional plane and orthogonal to the main surface 701, is tilted by the angular deviation α against the surface normal 704. The <11-20> grid direction is tilted in the plane that is oriented orthogonal to the cross-sectional plane and orthogonal to the main surface 701, by the angular deviation α against a surface normal to the cross-sectional plane. The <1-100> grid direction runs parallel to the cross-sectional plane and parallel to the skin surface 701. In the Fig. In the embodiments shown in Figures 2A-2C, 3A-3L, 4A-4B, 5A-5B, 6, and 8, the <1-100> lattice direction is perpendicular to a main extension direction of the trenches and / or gate electrode structures. However, it is alternatively possible for the <11-20> lattice direction to be perpendicular to a main extension direction of the trenches and / or gate electrode structures (cf., for example, Fig. 7). For further properties of the silicon carbide substrate 700, please refer to the description of Fig. 2A to 2C.

[0100] The silicon carbide substrate 700 may include a base substrate 705 and / or an epitaxial layer 707. The base substrate 705 may be a silicon carbide wafer separated from a single-crystal silicon carbide crystal, for example, by sawing or a wafer cleaving process. The base substrate 705 may be heavily doped, for example, heavily n-doped. However, the silicon carbide substrate 700 may also be free of a base substrate 705, for example, because the base substrate was removed from the epitaxial layer 707 after it was grown.

[0101] The epitaxial layer 707 may be formed by an epitaxial process on a process surface of the base substrate 705. The epitaxial layer 707 may include a drift layer structure 730, which may have the same conductivity type as the base substrate 705 or the conductivity type complementary to the conductivity type of the base substrate 705.

[0102] The drift layer structure 730 may include a lightly doped drift layer 731 and an optional current distribution layer 737, wherein the drift layer 731 may be formed between the base substrate 705 and the current distribution layer 737. The drift layer 731 and the optional current distribution layer 737 have the same conductivity type. An average dopant concentration in the optional current distribution layer 737 is higher than in the drift layer 731. For example, the average dopant concentration in the optional current distribution layer 737 may be at least twice the average dopant concentration in the drift layer 731.

[0103] On one side of the drift layer structure 730 opposite the base substrate 705, a body structure 720 can be formed, which has a conductivity type opposite to the conductivity type of the drift layer structure 730. The body structure 720 can be grown on the drift layer structure 730, for example, by epitaxy or by introducing dopant atoms into a previously grown upper section of the epitaxial layer 707. The body structure 720 can form a continuous layer or comprise a plurality of laterally separated body wells. The lateral extent of the body well can be comparatively large compared to the width of the trenches formed subsequently.

[0104] Heavily doped source wells 711 of the conductivity type of the drift layer 731 may be formed along portions of the main surface 701 between the main surface 701 and the body structure 720. The portions of the main surface 701 with the source wells 711 may correspond to transistor cell regions of finalized SiC semiconductor devices. A further portion of the main surface 701 may laterally separate the portions with the source wells 111 from one another. The further portion may comprise a kerf and edge termination regions of the finalized semiconductor devices, wherein structures for lateral field reduction may be formed in the edge termination regions.

[0105] According to the illustrated embodiments, the body structure 720 is p-conducting and the drift layer structure 730 is n-conducting. According to other embodiments, the body structure 720 may be n-conducting and the drift layer structure 730 may be p-conducting.

[0106] A trench mask 790 with mask openings 791 is formed on the main surface 701 by a photolithographic process. Using an anisotropic etching process, e.g., a chemical-physical dry etching process, the structure of the trench mask 790 is transferred dimensionally accurate into the silicon carbide substrate 700, forming trenches 750 that can extend below the mask openings 791 from a plane spanned by the main surface 701 through the source structures 111 and the body structures 720 into the drift layer structure 730.

[0107] Fig. 3B shows the trench mask 790 with the mask openings 791. The trench mask 790 may comprise a single layer of one material or two or more sublayers of different materials. According to one embodiment, the trench mask 790 comprises carbon, e.g., graphite, silicon, silicon oxide, and / or silicon nitride.

[0108] The trenches 750 may be formed in stripes, wherein a length of the trenches 750 in a direction orthogonal to the cross-sectional plane is greater than a trench width wg of the trenches 750 parallel to the cross-sectional plane. Adjacent trenches 750 may be formed at a center-to-center distance from one another, wherein the center-to-center distance of adjacent trenches 750 along the silicon carbide substrate may be the same or may vary. Sections of the body structure 720 of the Fig. 3A between the trenches 750 form body regions 120. Sections of the source wells 711 of the Fig. 3A, source structures 111 form between the trenches 750. The trench bottom 751 may have a section parallel to the main surface 701. Sidewalls 752 of the trenches 750 may be oriented vertically and / or parallel to (1-100) lattice planes with comparatively high charge carrier mobility. Transitions between the sidewalls 752 and the trench bottom 751 may be rounded.

[0109] An implantation mask 740 is formed, which shields the sidewalls 752 against the introduction of dopant atoms and allows implantation through at least a portion of the trench bottom 751. For example, the formation of an implantation mask 740 includes thermal oxidation and / or the deposition and patterning of a mask layer.

[0110] Fig. 3C shows an implantation mask 740 covering the trench bottom 751 with a layer thickness d1 and the sidewalls 752 with a layer thickness d2, wherein the layer thickness d1 at the trench bottom may be smaller than the layer thickness d2 at the sidewalls. According to other embodiments, an implantation mask 740 may be formed that selectively covers only the sidewalls 752 and exposes the trench bottom 751. This may be viewed as an implantation mask 740 with a vanishing layer thickness d1 at the trench bottom 751, as shown in the right half of Fig. 3D. Such an implantation mask can be produced, for example, by isotropic etching of the implantation mask 740 of the Fig. 3C by removing the implantation mask 740 of the Fig. 3C from above (spacer etching) or by depositing a conformal implantation mask layer followed by spacer etching.

[0111] With the implantation mask 740 in place, dopant atoms are introduced through the trench bottom 751. The introduction of the dopant atoms can comprise multiple implantations at different implantation energies, wherein the opening of the implantation mask 740 at the trench bottom 751 can be changed between the different implantations.

[0112] The implantation mask 740 prevents the scattering of dopant atoms through the sidewalls 752 into the body regions 120 and into the current distribution layer 737.

[0113] The section of the trench bottom 751 through which dopant atoms are introduced has a lateral third width w3. According to the embodiments of the Fig. 3D, the third width w3 may correspond to the lateral distance between the two sections of the implantation mask 740 at the opposite side walls 752 at the trench bottom 751, wherein the two sections of the implantation mask 740 define a mask opening between them. The third width w3 of the mask opening of the implantation mask 740, and / or the width of a thinned section of the implantation mask 740 at the trench bottom 751 as well as the penetration depth of the implanted dopant atoms define a lateral first width w1 of a central section of the shielding regions 140. In the central section of the shielding region 145, in a doping plane 105 which runs parallel or approximately parallel to the trench bottom 751 at a distance from the trench bottom 751, a dopant concentration deviates by no more than 10%, by no more than 5% or by no more than 1% from a maximum value in the doping plane 105 in the central section 145.

[0114] Fig. 3D shows the shielding regions 140, each extending from the trench bottom 751 into the silicon carbide substrate 700. Portions of the current distribution layer 737 of the Fig. 3C between the trenches 750 and between the shielding regions 140 form current distribution regions 137. A central section 145 of the shielding regions 140 has a first width w1 that is smaller than the trench width wg. A heat treatment, which can be performed at at least 800°C and at most 2200°C or at most 1900°C, can activate the dopant atoms introduced into the shielding regions 140 and heal implant damage. During the heat treatment, the implantation mask 740 can be in place or replaced by a sacrificial mask made of a temperature-resistant material. The implantation mask 740 is removed.

[0115] Fig. 3E shows the trenches 750 as well as the shielding regions 140 below the trenches 750 after removing the implantation mask 740 of the Fig. 3D.

[0116] A field dielectric layer 259 may be formed in the trenches 750, covering the sidewalls 752 and the trench bottom 751. Forming the field dielectric layer 259 may include thermal oxidation and / or the deposition of one or more dielectric layers.

[0117] The Fig. 3F shows a field dielectric layer 259 covering the sidewalls 752 and the trench bottom 751 with a uniform layer thickness. According to another embodiment, the layer thickness of the field dielectric layer 259 may be smaller at the trench bottom 751 than at the sidewalls 752.

[0118] A conformal etch mask layer 260 may be formed covering the field dielectric layer 259. The layer thickness of the etch mask layer 260 is selected such that the etch mask layer 260 does not completely fill the trenches 750. Forming the etch mask layer 260 may comprise depositing one or more layers.

[0119] Fig. 3G shows a conformal etch mask layer 260 covering portions of the field dielectric layer 259 in the trenches 750 and the trench mask 790 with a uniform layer thickness. The layer thickness may correspond to a later bottom width of a bottom portion of the field dielectric. The material of the etch mask layer may be silicon oxide, silicon nitride, carbon, polycrystalline silicon, and / or amorphous silicon. The etch mask layer 260 and the field dielectric layer 259 may be formed from different materials. An anisotropic etching process, for example, a chemical-physical dry etching process, may remove material of the etch mask layer 260 from above. The removal of the etch mask layer 260 is terminated after exposing a portion of the field dielectric layer 259 at the trench bottom 751 and before the complete removal of the material of the etch mask layer 260.

[0120] Fig. 3H shows remaining portions of the etch mask layer 260 of the Fig. 3G, which has an etch mask opening 761 in a central portion of the trench 750. A width of the etch mask opening 761 defines a second width w2.

[0121] With the etching mask 760 in place, a portion of the field dielectric layer 259 exposed through the etching mask opening 761 is removed. The etching mask 760 is then removed.

[0122] Fig. 3I shows the field dielectric layer 259 after etching, with an opening 158 exposing a central portion of the trench bottom 751. The opening 158 has the second width w2, which is smaller than the first width w1 of a central portion 145 of the shielding region 140. Highly doped polycrystalline silicon and / or one or more metallic layers are deposited, filling the trenches 750.

[0123] Fig. 3J shows a first doped semiconductor material 257 filling the trenches 750. The first doped semiconductor material 257 is recessed in the trenches 750 to below a lower edge of the body regions 120. The recessed first semiconductor material 257 forms a conductive interconnect structure 157. An isolation dielectric 156 is formed on the interconnect structure 157. Forming the isolation dielectric 156 may include thermally oxidizing an upper portion of the interconnect structure 157 and / or depositing one or more dielectric layers.

[0124] In the upper portion of trench 750, after the first doped semiconductor material 257 has been regenerated, an upper portion of field dielectric layer 259 is removed, and a gate dielectric 151 is formed. Forming gate dielectric 151 may include thermal oxidation and / or the deposition of one or more dielectric layers.

[0125] Fig. 3K shows a conductive connection structure 157 in the lower portion of the trenches 750. A portion of the field dielectric layer 259 of the Fig. 3J in the lower section of trench 750 forms a field dielectric 159. The conductive interconnect structure 157 directly adjoins the shielding region 140. The shielding region 140 and the interconnect structure 157 form an ohmic contact. The interconnect structure 157 may comprise a metal structure, for example, a silicide at the interface with the shielding region 140. An isolation dielectric 156 covers the interconnect structure 157.

[0126] A second doped semiconductor material is deposited. Portions of the second doped semiconductor material outside the trenches 750 are removed.

[0127] Fig. 3L shows a gate electrode 155 formed by the second deposited doped semiconductor material in the upper portions of the trenches 750.

[0128] The Fig. 4A-4B relate to embodiments that provide multiple implantations through the trench bottom 751, wherein the implantations utilize implantation masks having implantation mask openings of different sizes.

[0129] In the trenches 750 according to the Fig. 3B, a first implantation mask 7401 having a first implantation mask opening 7411 with a third width w3 is formed at the trench bottom 751, for example, by a spacer etch of a conformal mask layer. Dopant atoms for shielding regions 140 are introduced through the first implantation mask opening 7411.

[0130] The Fig. 4A shows the shielding regions 140 beneath the trenches 750. A second implantation mask 7402 having a second implantation mask opening 7412 with a fourth width w4 is formed in the trenches 750 at the trench bottom 751, wherein the fourth width w4 is smaller than the third width w3. The formation of the second implantation mask 7402 may, for example, comprise a spacer etch of a further conformal mask layer, wherein the second mask layer may be formed over the first implantation mask 7401 or wherein the first implantation mask 7401 may have been previously removed. Dopant atoms may be introduced through the second implantation mask opening 7412 to form JFET subregions 148.

[0131] The Fig. 4B shows the JFET subregions 148, which each form a unipolar junction with the shielding regions 140 and may extend from the shielding regions 140 further into the drift zone layer 731. According to other embodiments, the dopant atoms for the JFET subregions 148 may be introduced first, and the dopant atoms for the shielding regions 140 may be introduced later.

[0132] A narrower implantation mask opening for implantations with high acceleration energy and penetration depth makes it possible to form JFET subregions 148 with a comparatively large vertical extent, which do not reduce the lateral cross-sectional area of ​​the current distribution regions 137 through lateral scattering. The relatively thick second implantation mask 7402 prevents the scattering of dopant atoms through the sidewalls of the trench 750 into the body regions 120 and the current distribution regions 137, even at high acceleration energies.

[0133] A wider implantation mask opening for implantations with low acceleration energy and shallow penetration depth enables the formation of an effective shielding region 140 for critical subregions of the field dielectric 159 at the bottom 152 of the gate electrode structure 150.

[0134] The Fig. 5A-5B and 6-8 show semiconductor devices 500, which, for example, consist of a Fig. 1, 2A-2B, 3A-3L and 4A-4B.

[0135] In Fig. 5A-5B, a semiconductor device 500 includes a SiC semiconductor body 100. According to other embodiments, a semiconductor body may be provided with a different wide-bandgap semiconductor material. The semiconductor device 500 may be an IGFET, an IGBT, or an MCD (MOS controlled diode). The semiconductor material may be, for example, crystalline silicon carbide with a hexagonal crystal lattice, for example, 2H-SiC, 6H-SiC, or 4H-SiC.

[0136] A first surface 101 on a front side of the SiC semiconductor body 100 can be coplanar with a main lattice plane of the SiC crystal, wherein the first surface 101 is planar. According to another embodiment, the orientation of the first surface 101 is inclined relative to a main lattice plane by an angular deviation α, wherein an absolute value of the angular deviation can be at least 2° and at most 8°, for example approximately 4°. The first surface 101 can then be planar or ribbed. In the case of a ribbed first surface 101, the first surface 101 can have parallel first surface sections and parallel second surface sections. The first surface sections are offset from one another and inclined relative to a horizontal center plane by the angular deviation α.The second surface sections extend obliquely to the first surface sections and connect the first surface sections so that a cross-sectional line of the first surface forms a sawtooth line.

[0137] Directions parallel to the planar first surface 101 or to a midplane of a ribbed first surface 101 are horizontal and lateral directions. A normal 104 to a planar first surface 101 or to the midplane of a ribbed first surface 101 defines a vertical direction. <0001> Grid direction is in a plane orthogonal to the cross-sectional plane of the Fig. 5B is tilted by the angular deviation α. ​​The <1-100> grating direction runs in the cross-sectional plane and parallel to the first surface 101.

[0138] On the back side of the SiC semiconductor body 100, a second surface 102 extends parallel to the first surface 101. A total thickness of the SiC semiconductor body 100 between the first and second surfaces 101, 102 can be in the range of several hundred nm to several hundred µm.

[0139] On the front side, transistor cells TC are formed along the first surface 101. A drift structure 130 is formed between the transistor cells TC and the second surface 102. The drift structure 130 can have a heavily doped base section 139 and a lightly doped drift zone 131. The base section 139 directly borders the second surface 102. The drift zone 131 is formed between the transistor cells TC and the base section 139. Along the second surface 102, the dopant concentration in the base section 139 is sufficiently high to form an ohmic contact with a metal.

[0140] If the semiconductor device 500 is an IGFET or an MCD, the base section 139 and the drift zone 131 have the same conductivity type. If the semiconductor device 500 is a reverse-blocking IGBT, the base section 139 and the drift zone 131 have complementary conductivity types. If the semiconductor device 500 is a reverse-conducting IGBT, the base section 139 can include zones of both conductivity types, each extending from the drift zone 131 to the second surface 102.

[0141] The drift zone 131 may be formed in an epitaxial layer. An average dopant concentration in the drift zone 131 may be in a range of 1E15 cm -3 up to 5E16 cm -3 The drift structure 130 may have further doped regions, for example field stop zones, barrier zones of the conductivity type of the drift zone 131 and / or counter-doped regions.

[0142] In the illustrated embodiment, the drift structure 130 has current distribution regions 137, which directly adjoin the drift zone 131 and can be formed between the drift zone 131 and the first surface 101. An average dopant concentration in the current distribution regions 137 is at least 150% of an average dopant concentration in the drift zone 131 or is, for example, at least twice as high as in the drift zone 131. However, the drift structure 130 can also be free of current distribution regions 137. In this case, it is possible for the drift zone 131 to directly adjoin the body regions 120.

[0143] The drift zone 131 can be directly adjacent to the base section 139 or to a buffer layer, wherein the buffer layer and the drift zone 131 form a unipolar junction. A vertical extension of the buffer layer can be approximately 1 µm. An average dopant concentration in the buffer layer can be in a range of 3E17 cm -3 up to 1E18 cm -3 The buffer layer can reduce mechanical stresses in the semiconductor body 100, contribute to reducing the defect density in the semiconductor body, and / or can contribute to forming a desired electric field pattern in the drift structure 130.

[0144] The transistor cells TC are formed along gate electrode structures 150 that extend from the first surface 101 into the SiC semiconductor body 100 and into the drift structure 130. Portions of the SiC semiconductor body 100 between adjacent gate electrode structures 150 form semiconductor mesas 170.

[0145] A longitudinal extension of the gate electrode structures 150 along a first horizontal direction perpendicular to the cross-sectional plane of the Fig. 5B is larger than a width of the gate electrode structures 150 along a second horizontal direction in the cross-sectional plane of the Fig. 5B. The gate electrode structures 150 may, for example, be formed as long strips extending from one side of a transistor cell region to the opposite side, wherein the length of the gate electrode structures 150 may be up to several hundred µm or several mm.

[0146] The gate electrode structures 150 can each be formed at equal distances from one another, wherein a center-to-center distance between adjacent gate electrode structures 150 can be in a range from 1 µm to 10 µm, for example, from 2 µm to 5 µm. A vertical extension of the gate electrode structures 150 can be in a range from 300 nm to 5 µm, for example, in a range from 500 nm to 2 µm.

[0147] In the illustrated embodiment, the side walls on the long sides of the gate electrode structures 150 are aligned vertically to the first surface 101. According to other embodiments with a different orientation of the long axis of the gate electrode structures 150 to the grid axes, the side walls can be inclined to the vertical such that an angle between one of the side walls and the normal 104 is equal to the angular deviation α or deviates from this by no more than ± 1° (cf., for example, Fig. 7), wherein at least one longitudinal sidewall of the gate electrode structures 150 lies in a main lattice plane with high charge carrier mobility. Generally, at least one longitudinal sidewall of the gate electrode structures 150 can lie in one of the lattice planes (11-20), (-1-120), (1-100), and / or (-1100).

[0148] In a semiconductor mesa 170, source regions 110 may be formed along the sidewalls of the adjacent gate electrode structures 150, extending from the first surface 101 into the semiconductor body 100. A body region 120 is formed in each semiconductor mesa 170, separating the source regions 110 from a current distribution region 137 formed at least partially in the semiconductor mesa 170. The body region 120 may each adjoin both adjacent gate electrode structures 150.

[0149] The body regions 120 and the current distribution regions 137 form first pn junctions pn1. The body regions 120 and the source regions 110 form second pn junctions pn2.

[0150] The gate electrode structures 150 include a conductive gate electrode 155. The gate electrode 155 may, for example, comprise heavily doped polycrystalline silicon and / or a metal-containing layer. The gate electrode 155 may be connected to a gate metallization, wherein the gate metallization may form a gate terminal or be connected to a gate terminal.

[0151] A gate dielectric 151 separates the gate electrode 155 from the body regions 120. The gate dielectric 151 may comprise or consist of a semiconductor dielectric. The semiconductor dielectric may, for example, be a thermally grown or deposited semiconductor oxide, for example a silicon oxide, a semiconductor nitride, for example deposited or thermally formed silicon nitride, and / or a semiconductor oxynitride, for example a silicon oxynitride. The gate dielectric 151 may also comprise another deposited dielectric material or any combination of the aforementioned materials.

[0152] According to one embodiment, the gate dielectric 151 comprises a silicon oxide that is densified and / or partially nitrided after deposition. The materials and thickness th0 of the gate dielectric 151 can be selected such that a voltage in a range of 1 to 8 V is established as the threshold voltage for the transistor cells TC.

[0153] An interlayer dielectric 210 may separate the gate electrode 155 from a first load electrode 310. Contact structures 315 may extend from the first load electrode 310 through openings in the interlayer dielectric 210 to or into the SiC semiconductor body 100. The contact structures 315 form a low-resistance electrical connection between the source regions 110, the body regions 120, and the first load electrode 310 on the device front side. The base portion 139 and a second load electrode 320 on the back side of the SiC semiconductor body 100 form an ohmic contact along the second surface 102 on the device back side.

[0154] The gate electrode structures 150 further comprise a conductive connection structure 157. The conductive connection structure 157 may, for example, comprise heavily doped polycrystalline silicon and / or a metal-containing layer, e.g., a silicide. The connection structure 157 is connected to a potential or network node whose electrical potential, during operation of the component, is different from the potential of the gate terminal and the potential at the second load terminal L2. For example, the connection structure 157 is connected to the first load terminal L1, to an auxiliary terminal of the semiconductor component 500, or to an internal network node.

[0155] An isolation dielectric 156 separates gate electrode 155 and interconnect structure 157. The isolation dielectric 156 may comprise deposited silicon oxide, thermally formed silicon oxide, silicon nitride, silicon oxynitride, and / or another deposited dielectric material.

[0156] A field dielectric 159 separates the interconnect structure 157 from the drift structure 130 in the lateral direction. The field dielectric 159 may comprise deposited silicon oxide, thermally formed silicon oxide, silicon nitride, silicon oxynitride, and / or another deposited dielectric material.

[0157] The field dielectric 159 may include a sidewall portion 1593 formed along a sidewall of the gate electrode structure 150 and separating the connection structure 157 from the current distribution regions 137. A first layer thickness th1 of the sidewall portion 1593 may be greater than a thickness th0 of the gate dielectric 151. For example, the first layer thickness th1 of the sidewall portion 1593 of the field dielectric 159 may be at least 120%, for example, at least 150%, of the thickness th0 of the gate dielectric 151.

[0158] The field dielectric 159 may have a bottom portion 1592 with a second layer thickness th2, wherein the second layer thickness th2 may be equal to or less than the first layer thickness th1. The bottom portion 1592 may be formed in an outer portion of the bottom 152 between the connection structure 157 and the shielding region 140 and may have a central opening 158.

[0159] The bottom section 1592 and the side wall section 1593 can be directly connected to one another. For example, the bottom section 1592 and the side wall section 1593 are formed integrally with one another, i.e., manufactured as a single part. For example, the bottom section 1592 and the side wall section 1593 are made of the same material or materials. The bottom section 1592 can have a bottom width wb.

[0160] Shielding regions 140 may be formed along the bottom of the gate electrode structures 150 and directly adjoin the gate electrode structures 150. The shielding regions 140 form pn junctions with the drift structure 130, for example with the drift zone 131. An average dopant concentration in the shielding regions 140 may be in a range of 1E17 cm -3 up to 2E19 cm -3 lie, for example in a range of 8E17 cm -3 up to 8E18 cm -3 .

[0161] The shielding region 140 has a central section 145 with a first width w1 along the bottom 152 of the gate electrode structure 150. In the central section 145, the dopant concentration in the shielding region 140 deviates in a dopant plane parallel or approximately parallel to the bottom 152 by no more than 10%, e.g., by no more than 5% or by no more than 1%, from a maximum value that the dopant concentration has in the dopant plane. The central section 145 can be formed symmetrically to a central axis of the gate electrode structure 150. Outside the central section 145, the dopant concentration in the shielding region 140 drops steeply in the lateral direction. The first width w1 is smaller than a structure width w0 of the gate electrode structure 150, wherein the structure width w0 corresponds to the lateral extent of the bottom 152.The shielding region 140 may be located entirely within a vertical projection of the gate electrode structures 150, such that the lateral cross-sectional area of ​​the current distribution regions 137 is not reduced by the shielding region 140.

[0162] In a contact region OC with a second width w2, the connecting structure 157 of a gate electrode structure 150 and the shielding region 140 adjacent to the gate electrode structure 150 form an ohmic contact. The second width w2 can be smaller than the difference between the structure width w0 and twice the first layer thickness th1 of the sidewall section 1593 of the field dielectric 159. Thus, the central section 145 of the shielding region 140 completely covers both the contact region OC and those sections of the field dielectric 159 that directly adjoin the contact region OC, reducing the maximum electric field strength in the bottom section 1592 of the field dielectric 159.

[0163] The contact area OC may be laterally delimited by the bottom portions 1592. The bottom portions 1592 may directly border the central portion 145 of the shielding region 140. For example, the bottom portions 1592 may cover areas of the central portion 145 of the shielding region 140 in the vertical direction and / or laterally overlap with the central portion 145 of the shielding region 140.

[0164] In particular, the contact area OC does not extend to the transitions between the side walls and the base. Due to the reduced opening at the base through which the connecting structure 157 contacts the shielding region 140, the contact area OC is retracted.

[0165] The first load electrode 310 may form a first load terminal L1 or be electrically connected to a first load terminal L1. The first load terminal L1 may be the anode terminal of an MCD, the source terminal of an IGFET, or the emitter terminal of an IGBT. The second load electrode 320 may form a second load terminal L2 or be electrically connected to a second load terminal L2. The second load terminal L2 may be the cathode terminal of an MCD, the drain terminal of an IGFET, or the collector terminal of an IGBT.

[0166] In the event of an avalanche breakdown, the conductive connection structure 157 efficiently conducts charge carriers, for example, holes from an n-doped drift zone 131, which pass through the pn junction between shielding region 140 and drift structure 130, to the first load electrode 310. The avalanche current is conducted past the body regions 120 and cannot contribute to driving a parasitic bipolar transistor, which can be formed from the source regions 110, the body regions 120, and the drift structure 130.

[0167] In the semiconductor device 500 of the Fig. 6, the second layer thickness th2 of the bottom portion 1592 of the field dielectric 159 is smaller than the first layer thickness th1 of the sidewall portion 1593. For example, the second layer thickness th2 is approximately one-third of the first layer thickness th1. The shielding regions 140 form unipolar junctions jn with JFET subregions 148 that extend from the shielding regions 140 into the drift structure 130. A lateral width w5 of the JFET subregions 148 along the unipolar junction jn may be smaller than the first width w1.

[0168] The dopant atoms for the JFET subregions 148 and the dopant atoms for the shielding regions 140 can be introduced via implantations that utilize implantation mask openings of varying widths. A narrower implantation mask opening for implantations with high acceleration energy and penetration depth enables the formation of JFET subregions 148 with a comparatively large vertical extent that does not reduce the lateral cross-sectional area of ​​the current distribution regions 137. A wider implantation mask opening for implantations with low acceleration energy and shallow penetration depth enables the formation of an effective shielding region 140 for critical subregions of the field dielectric 159 at the bottom 152 of the gate electrode structure 150.

[0169] The Fig. 7 shows an embodiment in which each sidewall of the gate electrode structures 150 lies in a (11-20) lattice plane. The gate electrode structures 150 extend along the <1-100> lattice direction, which is orthogonal to the cross-sectional plane and parallel to the first surface 101. The sidewall of the gate electrode structures 150 can be formed obliquely, i.e., an angle between one of the sidewalls and the surface normal 104 of the first surface 101 is not equal to zero.

[0170] The shielding regions 140 can be formed along the entire longitudinal extent of a gate electrode structure 150 or only in sections. Alternatively or additionally, complete gate electrode structures 150 can be provided without the shielding region 140. If the shielding region 140 is missing, the connecting structure 157 and the drift structure 130, for example, the connecting structure 157 and sections of the current distribution regions 137, can form Schottky contacts in Schottky contact regions SC. A lateral extent w6 of the Schottky contact regions SC can correspond to the second width w2 of the contact regions OC or can be selected independently of the second width w2.

[0171] The Schottky contacts have a lower threshold voltage than a body diode comprising the first pn junctions pn1. In the reverse-biased state of the semiconductor component 500, a unipolar charge carrier current flows via the Schottky contacts and the connecting structure 157 to the first load electrode 310. When the semiconductor component 500 is operated in the SOA, a bipolar current through the drift structure 130 can be avoided and, for example, degradation of the SiC crystal promoted by a bipolar current can be prevented. At the same time, the voltage drop during a current flow in the reverse-biased state of the semiconductor component 500 is reduced, at least at current values ​​that are not too high. At high current values, however, the pn junction also begins to conduct and, due to the bipolar injection, reduces a further voltage increase.

[0172] Fig. 8 shows gate electrode structures 150 with rounded transitions between the sidewalls and the bottom 152. The structure width w0 at the bottom 152 is measured in a plane in which the curvature begins, starting from the first surface 101.

[0173] The Fig. 9A shows the field dielectric 159 of a semiconductor device 500 according to Fig. 8 effective electric field. The Fig.Figure 9B shows the electric field effective in the field dielectric 159 of a comparison component at the same blocking voltage. In the comparison component, the first width w1 is approximately equal to the second width w2, so that the ohmic contact area OC is too wide to be adequately shielded by the shielding region 140 at high blocking voltage. Critical field strengths are reached in the end sections of the field dielectric 159. If, however, the outer edge of the contact area OC is laterally retracted sufficiently far from the outer edge of the shielding region 140, the electric field in the field dielectric 159 remains uncritical.

Claims

[1] A method for producing a semiconductor device, comprising: Providing a silicon carbide substrate (700), wherein the silicon carbide substrate (700) has a trench (750), the trench (750) extending from a main surface (701) of the silicon carbide substrate (700) into the silicon carbide substrate (700) and having a trench width (wg) at a trench bottom (751); Forming a shielding region (140) in the silicon carbide substrate (700), wherein the shielding region (140) extends along the trench bottom (751), in at least one doping level (105) which runs parallel to the trench bottom (751), a dopant concentration in the shielding region (740) deviates over a lateral first width (w1) by no more than 10% from a maximum value of the dopant concentration in the doping level (105), and the first width (w1) is smaller than the trench width (wg) and is at least 30% of the trench width (wg), wherein the formation of the shielding region (140) comprises: Forming an implantation mask (740), wherein the implantation mask (740) is formed thinner at the trench bottom (751) than at side walls (752) of the trench (750), and introducing dopant atoms through the trench bottom (751); or Forming an implantation mask (740), wherein the implantation mask (740) has a first implantation mask opening (7411) with a third width (w3) at the trench bottom (751), the third width (w3) being greater than the first width (w1), and introducing dopant atoms through the first implantation mask opening (7411). [2] Method according to the preceding claim, further comprising: Forming a field dielectric (159) in the trench (750), wherein the field dielectric (159) has an opening (158) with a second width (w2) at the trench bottom (751), and the second width (w2) is smaller than the first width (w1). [3] Method according to the preceding claim, wherein the field dielectric (159) has a sidewall portion (1593) with a first layer thickness (th1) along a sidewall (752) of the trench (750), the opening (158) has a second width (w2), and wherein the second width (w2) is smaller than a difference of the trench width (wg) and twice the first layer thickness (th1). [4] Method according to one of the preceding claims, wherein the doping level (105) connects laterally adjacent local maximum values ​​of vertical dopant distributions in the shielding region (740) and the first width (w1) deviates by no more than ±10% from a difference between the third width (w3) and twice a distance (d3) of the doping level (105) from the trench bottom (751). [5] The method of any preceding claim, wherein forming the implantation mask (740) comprises: Forming an implantation mask layer on sidewalls (752) and on the trench bottom (751) of the trench (750); and Removing a portion of the implantation mask layer at the trench bottom (751), wherein a remaining portion of the implantation mask layer forms the implantation mask (740). [6] Method according to one of the preceding claims, wherein the introduction of dopant atoms comprises implantations at at least two different acceleration energies and the width of the first implantation mask opening (7411) is changed between the implantations. [7] A method according to any one of the preceding claims, wherein the implantation mask (740) is removed prior to forming a field dielectric (159). [8] A method according to the preceding claim, wherein forming the field dielectric (159) comprises: Forming a field dielectric layer (259), wherein the field dielectric layer (259) lines the trench (750), and Removing a section of the field dielectric layer (259) at the trench bottom (751). [9] The method of the preceding claim, wherein removing the portion of the field dielectric layer (259) comprises: Forming an etching mask (760) on the field dielectric layer (259), wherein the etching mask (760) has an etching mask opening (761) with the second width (w2) above the trench bottom (751), and Removing the portion of the field dielectric layer (259) below the etch mask opening (761). [10] Method according to one of the preceding claims, further comprising: Forming a conductive connection structure (157) in the trench (750), wherein a contact is formed between the connection structure (157) and the shielding region (140).

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