Semiconductor device and method for its manufacture

Abstract

Semiconductor device comprising: a semiconductor substrate (10); a gate electrode (34) above the semiconductor substrate (10); a channel zone (30) between the semiconductor substrate (10) and the gate electrode (34); a pair of source / drain zones (40) adjacent to two opposite sides of the channel zone (30) in a channel longitudinal direction; a threshold voltage setting zone (16) adjacent to two opposite sides of the channel zone (30) in a channel width direction, wherein the threshold voltage setting zone (16) and the channel zone (30) have the same doping type; and an isolation structure (20) in the semiconductor substrate (10), wherein the threshold voltage setting zone (16) is located in a side wall and a bottom of the isolation structure (20).

Description

BACKGROUNDIn semiconductor devices such as field effect transistors (FETs), there is a problem of flicker noise. It is believed that flicker noise is caused by trapping and releasing charge carriers. Flicker noise mitigation may be an important issue for both low frequency analog circuits and high power digital circuits, and therefore reducing flicker noise is desirable. The prior art relating to the subject matter of the invention can be found, for example, in the publication U.S. Pat. No. 6,562,697 B1.The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are set forth in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the art, various elements are not drawn to scale. Indeed, the dimensions of the various elements may be arbitrarily increased or decreased to aid in the description. FIG. 1 is a flow chart illustrating a method of manufacturing a semiconductor device according to various aspects of one or more embodiments of the present disclosure. FIGS. 2, 2A, 2B, 3, 3A, 3B, 4, 4A, 4B, 5, 5A, 5B, 6, 6A, 11B, 12B, 9B, 9B, 9, 9, 9A, 9B, 10, 10A, 10B, 11, 11A, 11B, 12, 12A, FIGS. 12B and 13 are schematic views of one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. FIG. 14 is a diagram illustrating a doping profile of a threshold voltage adjustment zone and a channel zone.DETAILED DESCRIPTIONIn the following disclosure, many different embodiments or examples for the realization of different features of the subject matter of the invention are presented. Specific examples of components and arrangements will be described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. In addition, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and convenience in explanation and, as such, does not determine a relationship between the various embodiments and / or configurations described.In one or more embodiments of the present disclosure, a semiconductor device is provided that includes a threshold voltage adjustment zone for locally adjusting the threshold voltage. The threshold voltage adjustment zone is disposed adjacent to a channel zone in a channel width direction. In some embodiments, the threshold voltage adjustment zone has the same doping type as the channel zone, but a higher doping concentration. The threshold voltage adjustment zone having a higher doping concentration may help to decrease the drain current due to defects in the vicinity of the channel zone and thus increase the threshold voltage of an edge zone of the channel zone in the vicinity of the threshold voltage adjustment zone. Thus, the flicker noise problem can be alleviated. The threshold voltage adjustment zone is configured not to affect the threshold voltage of the channel away from the threshold voltage adjustment zone, and therefore the semiconductor device can be turned on by a predetermined threshold voltage. In some embodiments, the threshold voltage adjustment zone is formed in the sidewall of the trench using the sacrificial pad layer as a mask for patterning the trench, and thus an additional mask may not be required. The threshold voltage adjustment zone may be a doped liner zone in the sidewall of the trench and thereby the layout region is not substantially affected.FIG. 1 is a flow chart illustrating a method of manufacturing a semiconductor device according to various aspects of one or more embodiments of the present disclosure. The method 100 begins with operation 110 where a semiconductor substrate is received. The method 100 continues with operation 120, where a channel zone in the substrate. The method 100 proceeds to operation 130, where a threshold voltage of the channel zone is locally adjusted to make a first threshold voltage of an edge zone of the channel zone higher than a second threshold voltage of a central zone of the channel zone. The method 100 continues with operation 140, where a gate electrode is formed over the semiconductor substrate. The method 100 proceeds to operation 150 where a pair of source / drain regions in the semiconductor substrate.The method 100 is merely an example and is not intended to limit the present disclosure beyond what is expressly set forth in the claims. Additional operations may be provided before, during, and after the method 100, and some operations described may be replaced, omitted, or moved for other embodiments of the method.FIGS. 2, 2A, 2B, 3, 3A, 3B, 4, 4A, 4B, 5, 5A, 5B, 6, 6A, 11B, 12B, 9B, 9B, 9, 9, 9A, 9B, 10, 10A, 10B, 11, 11A, 11B, 12, 12A, FIGS. 12B and 13 are schematic views of one of various operations of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. Reference is now made to FIGS. 2, 2A and 2B. FIG. 2 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 2A is a schematic cross-sectional view taken along line A-A of FIG. 2, and FIG. 2B is a schematic cross-sectional view taken along line B-B of FIG. 2 A semiconductor substrate 10 is received. In some embodiments, the material of the semiconductor substrate 10 may include an elemental semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, or indium arsenide; or combinations thereof.Reference is now made to FIGS. 3, 3A and 3B. FIG. 3 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 3A is a schematic cross-sectional view taken along line A-A of FIG. 3, and FIG. 3B is a schematic cross-sectional view taken along line B-B of FIG. 3. In some embodiments, the sacrificial pad layer 12 is configured to define a position of a trench to be formed, and is subsequently removed. The sacrificial pad layer 12 may be single-layered or multi-layered. For example, the sacrificial pad layer 12 may include a pad oxide layer 12A (e.g., a silicon oxide layer) and a pad nitride layer 12B (e.g., a silicon nitride layer) stacked on the pad oxide layer 12A. In some embodiments, the pad oxide layer 12A is thinner than the pad nitride layer 12B. For example, the thickness of the pad oxide layer 12A is substantially in a range from about 50 angstroms to about 200 angstroms, and the thickness of the pad nitride layer 12B is in a range from about 1000 angstroms to about 2000 angstroms, without limitation. Next, the sacrificial pad layer 12 is patterned to expose a portion of the semiconductor substrate 10. For example, the sacrificial pad layer 12 may be patterned by photolithography techniques using a photoresist layer along with a hard mask layer. The semiconductor substrate 10 exposed by the patterned sacrificial pad layer 12 is then recessed to form one or more trenches 10T. In some embodiments, trench 10T is configured to accommodate an isolation structure, e.g., shallow trench isolation (STI). For example, the semiconductor substrate 10 exposed by the patterned sacrificial pad layer 12 may be removed by etching techniques. In some embodiments, the depth of the trench 10T is less than the thickness of the semiconductor substrate 10, such that the trench 10T does not penetrate the semiconductor substrate 10.Reference is now made to FIGS. 4, 4A and 4B. FIG. 4 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 4A is a schematic cross-sectional view taken along line A-A of FIG. 4, and FIG. 4B is a schematic cross-sectional view taken along line B-B of FIG. 4. In some embodiments, a lining insulation layer 14 may be formed on the sidewall and the bottom of the trench 10T. In some embodiments, the lining insulation layer 14 may include a lining oxide layer, e.g., a silicon oxide layer. For example, the lining insulation layer 14 may be formed by thermal oxidation, but is not limited thereto. In some embodiments, a annealing process may be performed at a temperature of about 1000° C. to about 1200° C. for about 1 hour to 5 hours, without being limited thereto. In some embodiments, the thickness of the lining insulation layer 14 is substantially in a range from about 50 angstroms to about 200 angstroms, but is not limited thereto.Reference is now made to FIGS. 5, 5A and 5B. FIG. 5 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 5A is a schematic cross-sectional view taken along line A-A of FIG. 5, and FIG. 5B is a schematic cross-sectional view taken along line B-B of FIG. 5. In some embodiments, the threshold voltage adjustment zone 16 may include a doped zone. The doping type of the threshold voltage adjustment zone 16 may be selected based on the types of the semiconductor device to be manufactured. When the semiconductor device is an N-type FET, e.g., an NMOS, the dopants of the threshold voltage adjustment zone 16 may be P-type dopants, such as indium or the like. When the semiconductor device is a P-type FET, e.g., a PMOS, the dopants of the threshold voltage adjustment zone 16 may be N-type dopants, such as arsenic, antimony, or the like. In some embodiments, the threshold voltage adjustment zone 16 may be formed by ion implantation, but is not limited thereto. In some alternative embodiments, the threshold voltage adjustment zone 16 may be formed by other suitable doping techniques. In some embodiments, the ion implantation is performed at an inclination angle (shown by the arrows) so that the threshold voltage adjustment region 16 may be formed in the sidewall of the trench 10T. In some embodiments, the angle of inclination is in a range from about 15° to about 40°, but is not limited thereto. For example, the inclination angle of the ion implantation may be modified based on the size of the opening and the depth of the trench 10T. In some embodiments, the dosage of ion implantation is substantially in a range from 5*10 12 atoms / cm 2 to 5*10 13 atoms / cm 2, but is not limited thereto. For example, the dose of ion implantation may be modified based on the doping concentration of the threshold voltage adjustment zone 16. In some embodiments, the thickness of the threshold voltage adjustment zone 16 in a direction substantially perpendicular to the sidewall of the trench 10T is in a range from 0.02 micrometers to 0.1 micrometers, but is not limited thereto. In some embodiments, the energy of ion implantation is substantially in a range from 20 keV to 50 keV, but is not limited thereto. For example, the energy of ion implantation may be modified based on the target thickness of the threshold voltage adjustment zone 16. In some embodiments, a anneal process may be performed after the ion implantation to diffuse the dopants. In some embodiments, the annealing process is performed for about 5 seconds to 30 seconds at a temperature in a range from about 900° C. to 1100° C., but is not limited thereto.Reference is now made to FIGS. 6, 6A and 6B. FIG. 6 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 6A is a schematic cross-sectional view taken along line A-A of FIG. 6, and FIG. 6B is a schematic cross-sectional view taken along line B-B of FIG. 6, and an isolation structure 20, e.g., shallow trench isolation (STI), is formed in the trench 10T. In some embodiments, isolation structure 20 is formed by depositing an oxide layer, e.g., a silicon oxide layer, over sacrificial pad layer 12 and in trench 10T. The oxide layer may then be partially removed, e.g., by chemical mechanical polishing (CMP).Reference is now made to FIGS. 7, 7A and 7B. FIG. 7 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 7A is a schematic cross-sectional view taken along line A-A of FIG. 7 and FIG. 7B is a schematic cross-sectional view taken along line B-B of FIG. 7. In some embodiments, the isolation structure 20 may be partially recessed, e.g., by etching, such that the isolation structure 20 is recessed with respect to the pad nitride layer 12B.Reference is now made to FIGS. 8, 8A and 8B. FIG. 8 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 8A is a schematic cross-sectional view taken along line A-A of FIG. 8, and FIG. 8B is a schematic cross-sectional view taken along line B-B of FIG. 8, In some embodiments, the pad nitride layer 12B is removed by, for example, etching. In some embodiments, one or more ion implantations may be performed after the pad nitride layer 12B is removed to form one or more wells in the semiconductor substrate 10. For example, a P-type doped well and an N-type doped well may be formed at different locations of the semiconductor substrate 10 and configured as the wells for different types of semiconductor devices, e.g., PMOS and NMOS. In some embodiments, a anneal process may be performed after the ion implantation.Reference is now made to FIGS. 9, 9A and 9B. FIG. 9 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 9A is a schematic cross-sectional view taken along line A-A of FIG. 9, and FIG. 9B is a schematic cross-sectional view taken along line B-B of FIG. 9. the pad oxide layer 12A is then removed, e.g., by etching. In some embodiments, along with the pad oxide layer 12A, a portion of the isolation structure 20 may be removed. In some embodiments, a sacrificial layer, e.g., a sacrificial oxide layer (not shown), may be formed over the semiconductor substrate 10. Subsequently, the sacrificial layer may be removed from the semiconductor substrate 10. In some embodiments, the sacrificial layer may be configured to repair and modify the surface state of the semiconductor substrate 10.Reference is now made to FIGS. 10, 10A and 10B. FIG. 10 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 10A is a schematic cross-sectional view taken along line A-A of FIG. 10, and FIG. 10B is a schematic cross-sectional view taken along line B-B of FIG. 10. For example, the channel region 30 may be formed by ion implantation. The threshold voltage adjustment zone 16 is disposed on two opposite sides of the channel zone 30 in a channel width direction W. In some embodiments, the threshold voltage adjustment zone 16 is disposed between the isolation structure 20 and the channel zone 30. In some embodiments, the threshold voltage adjustment zone 16 and the channel zone 30 have the same doping type. For example, when an N-type FET is to be formed, the threshold voltage adjustment zone 16 and the channel zone 30 are P-type ones; when a P-type FET is to be formed, the threshold voltage adjustment zone 16 and the channel zone 30 are N-type ones.In some embodiments, the dopant concentration of the threshold voltage adjustment zone 16 is higher than the dopant concentration of the channel zone 30, for example, a ratio of the dopant concentration of the threshold voltage adjustment zone to the dopant concentration of the channel zone is substantially in a range from about 1.1 to about 2.0, but is not limited thereto. In some embodiments, the threshold voltage adjustment zone 16 adjoins an edge zone 30E of the channel zone 30 in the channel width direction. Thanks to the threshold voltage adjustment zone 16, a first threshold voltage at the edge zone 30E is higher than a second threshold voltage in the central zone 30C. The threshold voltage adjustment zone 16 helps increase the threshold voltage and decrease the drain current at the edge zone 30E, and thus can inhibit flicker noise generated due to defects near the channel zone 30. For example, defects often occur at the corner of the isolation structure 20. The threshold voltage adjustment zone 16 disposed between the isolation structure 20 and the channel zone 30 may help mitigate flicker noise generated due to the defects of the isolation structure 20.Reference is now made to FIG. 14. FIG. 14 is a graph illustrating a doping profile of a threshold voltage adjustment zone and a channel zone, where curve C 1 represents a doping profile of a channel zone without a threshold voltage adjustment zone of a comparative embodiment and curve C 2 represents a doping profile of a channel zone with a threshold voltage adjustment zone of some embodiments of the present disclosure. As shown in FIG. 14, the higher doping concentration threshold voltage adjustment zone 16 is configured to increase the threshold voltage of the edge zone 30E of the channel zone 30, while the doping concentrations of the channel zone 30 are substantially the same with and without the threshold voltage adjustment zone 16. Therefore, the threshold voltage of the central zone 30C of the channel zone 30 remains substantially unaffected when the threshold voltage adjustment zone 16 is integrated.In some embodiments, a ratio of the first threshold voltage at the edge zone 30E to the second threshold voltage in the central zone 30C is substantially in the range of about 1.1 to about 1.5. In some embodiments, the current density at the edge zone 30E of the channel zone 30 is about two to five times lower than the current density at the central zone 30C of the channel zone 30. In some embodiments, a ratio of the width of the edge region 30E to a width of the channel region in the channel width direction W is substantially in a range from about 0.02 to about 0.1. for example, for an analog MOS having a channel width of about 1 micrometer or more, the width of the edge region 30E is substantially in a range from about 0.02 micrometers to about 0.1 micrometers.In some embodiments, a gate insulator 32, e.g., a silicon oxide layer, is formed over the semiconductor substrate 10.Reference is now made to FIGS. 11, 11A and 11B. FIG. 11 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 11A is a schematic cross-sectional view taken along line A-A of FIG. 11, and FIG. 11B is a schematic cross-sectional view taken along line B-B of FIG. 11 A gate electrode 34 is formed over the gate insulator 32. In some embodiments, the gate electrode 34 may include a polycrystalline gate electrode or the like.Reference is now made to FIGS. 12, 12A and 12B. FIG. 12 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. FIG. 3A is a schematic cross-sectional view taken along line A-A of FIG. 12 and FIG. 12B is a schematic cross-sectional view taken along line B-B of FIG. 12 In some embodiments, a pair of lightly doped zones 36 may be formed on two opposite sides of the channel zone 30 in a channel length direction L. For example, the lightly doped regions 36 are formed by ion implantation. In some embodiments, spacers 38 are formed on two opposing sidewalls of the gate electrode 34. The spacer 38 may comprise a single layer spacer, e.g., a silicon oxide spacer. In some other embodiments, the spacer 38 may include a multi-layer spacer, e.g., a stack of a silicon oxide spacer and a silicon nitride spacer. In some embodiments, a pair of source / drain regions may be formed on two opposite sides of the channel region 30 in the channel length direction L to form a semiconductor device 1. For example, the source / drain regions 40 are formed by ion implantation. In some embodiments, the doping type of the lightly doped regions 36 and the source / drain regions 40 is complementary to that of the channel region 30 and the threshold voltage adjustment region 16.Reference is now made to FIG. 13. FIG. 13 is a schematic top view of one of various operations of manufacturing a semiconductor device according to some embodiments of the present disclosure. In some embodiments, at least one inter-layer dielectric (ILD) 42 may be formed over the semiconductor device 1. In some embodiments, a plurality of vias 44 may be formed that electrically connect the source / drain regions 40 and / or the gate electrode 34, respectively. In some embodiments, a back end of line (BEOL) metallization operation may be performed to establish electrical routing. In some embodiments, the BEOL metallization 46 may include at least one inter metal dielectric (IMD) 48 and one or more conductive layers, such as a bottom metal layer 50 and a top metal layer 52.In an integrated circuit (IC) having various types of semiconductor devices formed thereon, the threshold voltage adjustment zone 16 may be formed in some semiconductor devices, while the threshold voltage adjustment zone 16 is not integrated in other semiconductor devices. For example, the threshold voltage adjustment zone 16 may be incorporated into low frequency analog devices and high power digital devices that have the flicker noise problem, while the threshold voltage adjustment zone 16 is not incorporated into other semiconductor devices. In some embodiments, the threshold voltage adjustment zones 16 of different types of semiconductor devices may have different doping concentrations.In some embodiments of the present disclosure, the semiconductor device includes a threshold voltage adjustment zone adjacent to a channel zone in a channel width direction. The threshold voltage adjustment zone has the same type of doping as the channel zone, but a higher doping concentration. The higher doping concentration threshold voltage adjustment zone may help reduce the drain current from the STI corner due to defects and thus increase the threshold voltage of an edge zone of the channel zone near the threshold voltage adjustment zone. Thus, the flicker noise problem can be alleviated. The threshold voltage adjustment zone is configured not to affect the threshold voltage of the channel away from the threshold voltage adjustment zone, and thus the semiconductor device can be turned on by a predetermined threshold voltage. In some embodiments, the threshold voltage adjustment zone is formed in the sidewall of the trench using the sacrificial pad layer as a mask for patterning the trench, and thus an additional mask may not be required. The threshold voltage adjustment zone may be a doped liner zone in the sidewall of the trench and thereby the layout region is not substantially affected.In an exemplary aspect, a semiconductor device includes a semiconductor substrate, a gate electrode, a pair of source / drain regions, and a threshold voltage adjustment region. The gate electrode is located over the semiconductor substrate. The channel region is located between the semiconductor substrate and the gate electrode. The source / drain regions are located adjacent to two opposite sides of the channel region in a channel length direction. The threshold voltage adjustment zone is located adjacent to two opposite sides of the channel zone in a channel width direction, wherein the threshold voltage adjustment zone and the channel zone have the same doping type.In another exemplary aspect, a semiconductor device includes a semiconductor substrate, a gate electrode, a channel region, and a pair of source / drain electrodes. The gate electrode is located over the semiconductor substrate. The channel region is located between the semiconductor substrate and the gate electrode, the channel region including a central region and an edge region adjacent to the central region in a channel width direction. The source / drain regions are located in a channel length direction adjacent two opposite sides of the channel region, wherein a first threshold voltage of the semiconductor device at the edge region is higher than a second threshold voltage of the semiconductor device in the central region.In yet another exemplary aspect, a method of manufacturing a semiconductor device is provided. A semiconductor substrate is received. A channel region is formed in the semiconductor substrate. A threshold voltage of the channel zone is locally set so that a first threshold voltage of an edge zone of the channel zone is made higher than a second threshold voltage of a central zone of the channel zone. A gate electrode is formed over the semiconductor substrate. A pair of source / drain regions are formed in the semiconductor substrate.

Claims

A semiconductor device comprising: a semiconductor substrate (10); a gate electrode (34) over the semiconductor substrate (10); a channel region (30) between the semiconductor substrate (10) and the gate electrode (34); a pair of source / drain regions (40) adjacent to two opposite sides of the channel region (30) in a channel length direction; a threshold voltage setting region (16) adjacent to two opposite sides of the channel region (30) in a channel width direction, wherein the threshold voltage setting region (16) and the channel region (30) have the same doping type; and an isolation structure (20) in the semiconductor substrate (10), wherein the threshold voltage setting region (16) is located in a sidewall and a bottom of the isolation structure (20).The semiconductor device of claim 1, wherein the isolation structure (20) comprises shallow trench isolation, STI, in a trench of the semiconductor substrate (10).The semiconductor device according to any one of the preceding claims, wherein a doping concentration of the threshold voltage adjustment zone (16) is higher than a doping concentration of the channel zone (30).The semiconductor device according to claim 3, wherein a ratio of the doping concentration of the threshold voltage adjustment zone (16) to the doping concentration of the channel zone (30) is substantially in a range of about 1.1 to about 2.0.The semiconductor device according to claim 3 or 4, wherein the channel region (30) comprises an edge region near the threshold voltage adjustment region (16) and a central region away from the threshold voltage adjustment region (16), and a first threshold voltage at the edge region is higher than a second threshold voltage in the central region.The semiconductor device according to claim 5, wherein a ratio of the first threshold voltage to the second threshold voltage is substantially in a range of 1.1 to 1.5.The semiconductor device according to claim 5 or 6, wherein a ratio of a width of the edge region to a width of the channel region (30) in the channel width direction is substantially in a range of about 0.02 to about 0.1.A semiconductor device comprising: a semiconductor substrate (10); a gate electrode (34) over the semiconductor substrate (10); a channel region (30) between the semiconductor substrate (10) and the gate electrode (34), the channel region (30) comprising a central region (30C) and an edge region (30E) adjacent to the central region (30C) in a channel width direction; a pair of source / drain regions (40) adjacent to two opposite sides of the channel region (30) in a channel length direction, wherein a first threshold voltage of the semiconductor device at the edge region (30E) is higher than a second threshold voltage of the semiconductor device at the central region (30C); and a threshold voltage setting zone (16) adjacent to the edge zone (30E) of the channel zone (30) in the channel width direction, wherein a depth of the threshold voltage setting zone (16) is greater than a depth of the pair of source / drain zones (40).The semiconductor device according to claim 8, wherein a ratio of the first threshold voltage to the second threshold voltage is substantially in a range of 1.2 to 1.4.The semiconductor device according to claim 8 or 9, wherein a ratio of a width of the edge region (30E) to a width of the channel region (30) is substantially in a range of about 0.02 to about 0.1.The semiconductor device of any one of claims 8 to 10, further comprising shallow trench isolation, STI, in a trench (10T) of the semiconductor substrate (10).The semiconductor device of claim 11, wherein the threshold voltage adjustment zone (16) is located in a sidewall of the STI.A method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate (10); forming a channel region (30) in the semiconductor substrate (10); forming a threshold voltage adjustment region (16) in a sidewall and a bottom of an isolation structure (20) such that a threshold voltage of the channel region (30) is locally adjusted such that a first threshold voltage of an edge region (30E) of the channel region (30) is made higher than a second threshold voltage of a central region (30C) of the channel region (30); forming a gate electrode (34) over the semiconductor substrate (10); and forming a pair of source / drain regions (40) in the semiconductor substrate (10).The method according to claim 13, wherein the threshold voltage adjustment zone (16) is formed in the semiconductor substrate (10) and in proximity to two opposite sides of the channel zone (30) in a channel width direction.The method of claim 14, wherein the threshold voltage adjustment zone (16) and the channel zone (30) have the same doping type, and a doping concentration of the threshold voltage adjustment zone (16) is higher than a doping concentration of the channel zone (30).The method of claim 14 or 15, further comprising: recessing the semiconductor substrate (10) to form a trench (10T); performing ion implantation to form the threshold voltage adjustment zone (16) in a sidewall of the trench (10T); and forming trench isolation in the trench, wherein the isolation structure (20) is the trench isolation.The method of claim 16, wherein the ion implantation is performed at an inclination angle.

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