USING A FEEDBACK DELAY LINE WITH A TIME-TO-DIGITAL CONVERTER

Abstract

A method for performing a time-to-digital conversion, comprising: Receiving an input pulse (PIN) indicating time information; Feeding back a representation of the input pulse (PIN) in at least one delay line (807, 1007, 1115, 1117, 1207, 1405) using a feedback signal based on a delay line output signal of the at least one delay line (807, 1007, 1115, 1117, 1207, 1405); Generating an output pulse corresponding to the input pulse (PIN) based at least in part on the delay line output signal of the at least one delay line (807, 1007, 1115, 1117, 1207, 1405); and Supplying the output pulse N times to an integrator coupled to the delay line (807, 1007, 1115, 1117, 1207, 1405), where N is an integer greater than one.

Description

GENERAL STATE OF THE ARTField of InventionThe present disclosure relates to time-to-digital converters (TDC) and improvements in the resolution of TDCs.Description of Related ArtA time-to-digital converter (TDC) converts the "time information" between two indicated events into a digital number with respect to a given time base. For example, referring to FIG. 1A, the time information Δt represents the elapsed time between EVENT 1 and EVENT 2. As shown in FIG. 1B, the "time information" Δt in a phase-lock loop (PLL) indicates the phase difference between the rising edges of the reference clock (CLKREF) and the feedback clock (CLKFB). Referring to FIG. 1C, the input pulse width indicates the "time information" in time-of-flight measurements. Therefore, the two events correspond to the rising and falling edges of the input pulse.The native resolution (T LSB) of the TDC is determined by the smallest measure of the time base, which represents the smallest unit of time that can be quantified in the system. FIG. 1A illustrates the smallest T LSB, where LSB refers to the least significant bit. There are different types of time bases with different degrees of stability and resolution. The time base may be, for example, the period of the system clock T CLK. With T CLK as a time base, high stability but poor resolution is obtained. Note that a higher frequency system clock can be used for better resolution at the expense of greater power dissipation. In another example, the time base T GATE, provides high resolution, but poor accuracy, based on the gate delay of a standard digital cell such as an inverter or buffer, as T GATE may be sensitive to process, voltage, and temperature (PVT) variations. In another example, a voltage / current time base (T REF= C REF V REF / I REF) provides mean resolution and mean accuracy. Note that the idea here is to obtain a "time reference" using impedances (resistor / capacitor) and a voltage reference (band gap).Traditionally, in PLLs, phase delay information is stored between a feedback clock (CLKFB) and a reference clock (CLKREF) in voltage mode using a phase detector followed by a charge pump and a capacitor. FIG. 2 illustrates the basic idea. The pulses output from the phase detector 201 control the current sources 203 and 205 to charge / discharge the capacitor C using a fixed current I REF, and the polarity of the charge setting is determined according to whether CLKFB CLKREF leads or lags. If the phase difference between CLKREF and CLKFB is Δt, the voltage across the capacitor is given by thus the capacitor stores the time information (phase delay) as charge. FIG. 3 illustrates a timing diagram associated with the traditional voltage mode approach shown in FIG. 2. A reset mechanism, not shown, is provided to discharge the capacitance between phase comparisons.Where TDCs are used to convert the time information to digital, TDCs often use 2-stage, a coarse TDC, and a fine TDC. The coarse TDC typically operates with a time base T CLK. set by a system clock. Fine TDC is often based on a delay line using N elements with a unit delay of T GATE. The delay line may be synchronized to a period of time base T CLK. The overall resolution is determined by the fine TDC. Improvements in the resolution of TDC are desired to achieve more precise TDC.DE 10 2008 015 791 A1 describes a time delay circuit which comprises a delay line having a first delay circuit and at least one second delay circuit connected downstream thereof. An interpolation circuit is used to generate intermediate signals derived from successive delayed signals in the delay line.SUMMARY OF EMBODIMENTS OF THE INVENTIONThe present invention relates to a method according to claim 1 and an apparatus according to claim 9. Claims 2 to 8 relate to particularly advantageous implementations of the method according to claim 1. Claims 10 to 20 relate to particularly advantageous implementations of the apparatus according to claim 9.Embodiments disclosed herein improve the resolution of time-to-digital converters (TDCs) by using a gain stage at the input of the TDC. The gain stage uses a "time amplifier" which provides a known fixed PVT invariant gain in the time domain. In embodiments, time domain gain is achieved by repetitive addition using a delay line to return time information provided over a pulse, which makes the total gain PVT invariant.In one embodiment, a method for performing time-to-digital conversion includes: receiving an input pulse indicative of time information; and feeding back a representation of the input pulse in at least one delay line using a feedback signal based on a delay line output signal of the at least one delay line. An output pulse corresponding to the input pulse is generated based at least in part on the delay line output signal of the at least one delay line. The output pulse is provided N times to an integrating time-to-digital converter, where N is an integer greater than one.In another embodiment, an apparatus includes a delay line and input logic coupled to receive an input pulse and coupled to an output of the delay line, the input logic to provide a delay line input signal to the delay line. An integrating time-to-digital converter is coupled to the delay line to receive N pulse output signals, each pulse-out signal corresponding to the input pulse, thereby generating a digital representation of the input pulse multiplied by a gain of N, where N is an integer greater than one.In another embodiment, an apparatus includes a delay line that provides a delay line output signal. A rising edge detector detects a rising edge of an input pulse and provides a rising edge pulse. An end-of-fall detector detects a falling edge of the input pulse and generates an end-of-fall pulse. A first logic circuit logically combines the rising edge pulse, the falling edge pulse, and a feedback signal based on the delay line output signal. A second logic circuit receives an enable signal and an output pulse based on the delay line output signal and passes the output pulse when the enable signal is set.BRIEF DESCRIPTION OF THE DRAWINGSThe present invention can be better understood and its numerous objects, features and advantages can be made apparent to those skilled in the art by referring to the accompanying drawings. FIG. 1A illustrates time information between two events. FIG. 1B illustrates the time information corresponding to a phase difference in a PLL. FIG. 1C illustrates time information related to a time of flight measurement. FIG. 2 illustrates how phase delay information between a feedback clock (CLKFB) and a reference clock (CLKREF) is stored in a voltage mode PLL using a phase detector followed by a charge pump and a capacitor. FIG. 3 illustrates a timing diagram associated with the traditional voltage mode approach shown in FIG. 2. FIG. 4A illustrates a high-level block diagram of an embodiment with a gain stage before fine TDC to improve the effective resolution of the TDC. FIG. 4B illustrates another high level block diagram with an amplification stage to improve the effective resolution of the TDC. FIG. 5 illustrates a high level conceptual block diagram of an amplification stage. FIG. 6 illustrates a time amplifier circuit using a time-to-voltage converter or charge pump followed by a voltage amplifier followed by a voltage-to-time converter. FIG. 7 illustrates a conceptual block diagram of a time amplifier circuit based on time information stored in the system and repeatedly provided to a fine integrating TDC to achieve the desired gain. FIG. 8 illustrates how the timing information may be saved as pulses circulating in a delay line. FIG. 9 illustrates a timing diagram associated with feedback pulses in a delay line. FIG. 10 illustrates an embodiment of a feedback delay line circuit having a single delay line for storing information that may be used as a time-gain circuit when used in conjunction with an integrator. FIG. 11 illustrates an embodiment of a feedback delay line circuit that circulates pulses in two delay lines to store time information and desensitizes the circuit for delay mismatches between rising and falling edges in the delay lines using edge detection circuits. FIG. 12 illustrates an embodiment of a feedback delay line circuit that stores time information and mitigate delay mismatch between the two delay lines shown in FIG. 11 using a single delay line to circulate both the rising edge and falling edge pulses. FIG. 13 illustrates an embodiment of a feedback delay line circuit that stores timing information with additional control to provide different delays for rising and falling pulses, if desired. FIG. 14 illustrates an embodiment of a fine integrating TDC that may be used in conjunction with a feedback delay line circuit to provide time gain and increased effective resolution. FIG. 15 illustrates a high level block diagram of a TDC with a coarse TDC and a fine TDC.The use of the same reference symbols in different drawings indicates similar or identical elements.DETAILED DESCRIPTIONThe effective resolution (T LSB,eff) of the TDC can be improved by adding a gain at the input of the fine TDC before its quantization. As shown in FIG. 4A, a gain stage 401 multiplies a pulse 403 having a pulse width T PW and supplies the pulse having the gain to an N-bit fine TDC 405. The digital value provided by TDC 405 is then right shifted 407 to provide a digital average having N+M bits. Thus, at a native resolution of and a gain of 2 M the effective resolution can be determined as follows:FIG. 4B illustrates an equivalent view of achieving improved resolution of fine TDC.Note that the idea described in FIGS. 4A and 4B requires a "time amplifier", such as shown in FIG. 5. The time amplifier 501 accepts an input pulse 503 having the width T PW and generates an output 505 having a pulse width "G×T PW ". Referring to FIG. 6, a time amplifier circuit may be realized with a time-to-voltage converter (TVC) 601 or a charge pump followed by a voltage amplifier (G) 603 followed by a voltage-to-voltage converter (VTC) 605. Note that the linearity and PVT sensitivity of the TVC, voltage amplifier, and VTC affect the overall performance of such a time amplifier. The three operations involved, however, cause a significant PVT variation in overall gain. Embodiments described herein avoid the time to voltage conversion and vice versa shown in FIG. 6 and the significant PVT variation.To avoid the lack of the time-amplifier circuit shown in Figure 6, Figure 7 illustrates a conceptual block diagram of a time-amplifier circuit based on time / phase information in pulse 701 in the system being stored in a time slot 703 and using a fine integrating TDC 705 to achieve the required gain. With the "stored" information, the same input is applied "N times" to fine TDC 705. The fine TDC operates in "integrating mode" where it accumulates the inputs prior to quantization. The integrated input is finally quantized. Since quantization occurs after the input is accumulated "N" times, the system is equivalent to analog gain of "N" followed by the quantizer. For the fine integrating TDC 705, the final output is given by the "first difference" of two successive samples determined in block 707. This allows the errors at the input to be shaped in the first order frequency range (20 dB / decade). Therefore, it is possible to reduce the errors "in-band" by low-pass filtering the digital output. Note that the approach illustrated in FIG. 7 requires a mechanism for "storing" information in the time domain, as further described herein.The traditional approach of storing time information as charge, as illustrated in FIG. 2, works very well in technologies that supply a large supply voltage VDD, and for devices with large channel lengths, to realize near-ideal current sources for charging the capacitor. However, scaling the circuit to short channel nodes is not trivial. Capacitor stray losses in short channel technologies limit the "storage time" (t ret) of the voltage, which limits the maximum time constant that can be achieved in the system. For example, the traditional approach cannot be used to design digital PLLs that process phase information at low reference update rates (such as 1 pps / 1 Hz) required in network synchronization. In addition, using longer devices and capacitors requires significant area on the chip - which is costly in short channel process nodes. Advanced process technologies provide high precision in the time domain at small intrinsic gate delays due to reduced parasitics and shorter channel lengths, resulting in a large transconductance g m.To store the time information, the embodiments described herein enhance the high precision available in the time domain to "keep the phase information "memorized" as a pulse circulating in a delay line loop. Figures 8 and 9 illustrate how the memory information can be provided and backed up as pulses circulating in a delay line rather than being used to turn on a current source as shown in Figure 2. The XOR gate 801 generates a pulse 803 (shown as P IN in FIG. 9 ) having a width Δt when the rising edges of CLKIN and CLKREF occur at different times. CLKIN may be, for example, CLKFB of FIG. 2. Although the pulse may represent time information related to a phase difference between clock signals in a PLL, the pulse may more generally represent any time information between two events. OR gate 805 receives pulse 803 and provides the pulse to delay line 807. The delay line is formed by buffers or inverters, for example. Delay line 807 couples its output back to OR gate 805 to recirculate the pulses.Referring to FIG. 9, the first pulse enters the delay line at 901 and exits the delay line at 903 as P OUT. The output pulse is fed back as P FB and reenters the delay line at 905. This in turn results in a pulse out at 907. The pulse is fed back until a reset signal 809 (FIG. 8 ) is set to reset the delay line, for example, to force all stages of the delay line to output a high or low voltage or an appropriate reset condition. Note the assumption that the maximum pulse width of Δt is smaller than the delay T DL. shown in FIG. 9.FIG. 10 shows an embodiment 1000 similar to the embodiment shown in FIG. 8. A conventional phase frequency detector 1001 provides an UP pulse 1003 and a down (DN) pulse 1004 which are logically combined in an OR gate 1005. OR gate 1005 supplies input pulse P IN to a single delay line 1007 having a delay (T DL). Delay line 1007 provides its output back to OR gate 1005 to form a closed loop system which returns the pulses. The S-R latch 1011 generates the sign of Δt based on the UP and DN pulses. A reset signal (RST) 1008 initializes the system and prepares the system for a next measurement. The delay line provides the output signal to an AND gate 1009 which drives the pulses from the delay line 1007. For example, for a gain value of 5, enable signal EN provided by control logic not shown is set high to allow five pulses through AND gate 1009, and then set false to disable the pulses if not required. The phase information from the PFD 1001 is maintained as pulse P OUT. Note that the approach of FIG. 10 includes the smallest amount of hardware compared to embodiments described later, but is sensitive to mismatch between propagation of rising and falling edges in the delay line.FIG. 11 illustrates an embodiment 1100 that desensitizes the circuit to delay mismatches between rising and falling edges in the delay line. Embodiment 1100 uses edge detectors 1103 and 1101 on the input pulse (P IN), to generate two pulses corresponding to their rising (P R) and falling (P F) edges, respectively. OR gates 1105 and 1107 receive the rising and falling edge pulses, respectively, and feed the T DL1 and T DL2 pulses into two separate delay lines 1115 and 1117. Thus, the pulses circulating in the two delay lines with rising and falling edges represent the input pulse. The second input of each of the OR gates 1105 and 1107 is connected to the output of the corresponding delay line to form a closed loop system which returns the rising and falling edge pulses. Corresponding reset operations, not shown, are provided to initialize the system. After initialization, the loop will regenerate the pulses over time. An SR latch 1119 receives the output of the delay lines 1115 and 1117 and reproduces the pulse supplied to the delay lines through the OR gate 1109. The "EN" signal for the output pulse (P OUT), generated by a control block not shown passes the number of pulses corresponding to the desired gain and turns off the pulses if not required. The time information (phase difference in the embodiment of FIG. 11 ) is preserved as the pulse width of P IN and P OUT. Embodiment 1100 is sensitive to delay mismatch between the two delay lines and calibration may be used to correct any mismatch and ensure that T DL1 and T DL2 are equal.FIG. 12 illustrates another embodiment 1200 that mitigate delay mismatch between the two delay lines shown in embodiment 1100 using a single delay line 1207 to circulate both the rising edge and falling edge pulses. The embodiment illustrated in FIG. 12 uses edge detectors 1201 and 1203 on the input pulse (P IN), to generate two pulses corresponding to its rising (P R) and falling (P F) edges, respectively. The OR gate 1205 receives the rising edge pulse and the falling edge pulse, and supplies the pulses with a delay (T DL) to the single delay line 1207. The third input of OR gate 1205 is connected to the output of delay line 1207 to form a closed loop system which returns the pulses. Corresponding reset operations, not shown, are provided to initialize the system. After initialization, the loop will regenerate the pulses over time. A divide by two or a flip flop 1209 receives the output of the delay line and reproduces the input pulse based on the pulses having the rising and falling edges. A control block, not shown, generates the "EN" signal to AND gate 1211, which provides the output pulse (P OUT) to provide a corresponding number of pulses corresponding to a desired gain and to shut down the pulses if not required. The time (phase) information is preserved as the pulse width of P IN and P OUT.FIG. 13 illustrates an embodiment similar to that of FIG. 12 with additional control to provide various delays for odd (rising) and even (falling) pulses. In certain cases, the pulse circulating through the delay line loop may decrease or even disappear due to asymmetric rising and falling edges. Fig. 13 includes edge detection circuits 1301 and 1302, similar in operation to Fig. 12, and also includes a monostable multivibrator (also referred to herein as a mono shot or one shot). The monostable multivibrator 1351 in the feedback path regenerates a pulse having the same pulse width every time the pulse is fed back in the loop. Thus, the feedback signal of the delay line may come indirectly from the delay line in the form of the mono-shot pulse or directly from the output of the delay line, as shown in FIG. 8, 10, 11 or 12, for example. The use of the one-shot ensures that the pulse width does not become too small (≈0) or too large (≈T DL) due to any systematic errors in the loop. The mono shot affects both the rising edge pulse and the falling edge pulse in the same manner. The mono shot "extends" the pulses (both rising and falling edge pulses) by delaying one of the edges of the individual pulses. In other words, the mono shot ensures that the pulse width of each of the two pulses is restored to a constant value ("T monoshot "). The actual information between two successive rising (or falling) edges of the pulses is not affected by the mono shot. Thus, in various embodiments described herein, a representation of the input pulse is fed back using a feedback signal based on a delay line output signal, for example, by providing the delay line output signal itself or a mono shot pulse based on the delay line output signal through an OR gate to the input of the delay line.The embodiment of FIG. 13 also includes an optional fast delay path 1353 and slow delay path 1355 formed, for example, by buffers that can be used to adjust the pulse width. A multiplexer 1357 selects one of the fast delay path and the slow delay path based on a selection signal from a control logic. The control logic 1359 determines whether to increase the pulse width or decrease the pulse width. For example, the control logic may increase the pulse width by delaying the falling edge pulse in the slow path 1355, while the rising edge pulse uses the fast path 1353. Alternatively, the control logic may decrease the pulse width by utilizing the slow path for the rising edge pulse and the fast path for the falling edge pulse. The control logic determines whether it is rising or falling based on whether an edge is odd or even.The control logic 1359 that selects the fast or slow path may be configured to "modulate" the pulse width in the loop. The actual operation depends on how the user desires the pulse width to change with time. Note that with this approach, by providing different delays in the feedback path, the phase delay information can be made greater / smaller or monotonically increasing / decreasing. This can be used for noise shaping in a sigma-delta loop.For example, if the user desires the pulse width to increase monotonically, the control logic selects the "fast" path for the rising edge pulse and the "slow" path for the falling edge pulse. For this embodiment, the control logic has a flip-flop, not shown, which is clocked by the output of the div-by-2 1358 to control the select line 1360 to the multiplexer 1357. Such control is useful in pulse width modulation systems. Note that an extension of this control with a DTC (Time to Digital Converter) may also be used to generate a SAR (Successive Approximation Register) TDC. In another embodiment, the control logic uses a pseudo-random bit sequence (PRBS) to randomize the selection of the fast / slow path, which helps mitigate spurious signals arising from deterministic edges of the pulse for a given input.FIG. 14 illustrates an embodiment of a fine integrating TDC 1400 using three delay line elements 1402. The pulse 1401 supplied by the pulse feedback amplifying circuit controls a switch 1403. When the pulse 1401 is set, the switch closes and current is provided to the delay line 1405 causing a pulse to circulate in the delay line for the duration of the pulse 1401. The circuit shown in FIG. 14 is also known as a gated ring oscillator (GRO). Here, the ring oscillator continues to oscillate as long as the switch (1403) is closed by the pulse 1401, and solidifies / stops when the switch is opened when the pulse is L. The number of pulses through the delay line 1405 is detected in the counter 1407. When the pulse 1401 is turned off, the thermometer-to-binary (T2B) decoder 1409 provides the value of each stage of the delay line as a value X. Thus, the determined value is 3A+X for each pulse 1401.The multiplication by 3 can be understood as follows. Assuming that the number of times the GRO has a "polarity change" is "A", then the "effective" number of delay units that were skewed during the time that the switch (1403) was set is 3*A+X. Here, the expression 3*A corresponds to the total delay of "3" unit cells having "A" times a polarity change. To provide gain, the pulse-feedback gain circuit, examples of which are shown in Figures 8, 10 and 11-13, provides N times the pulse 1401, resulting in a gain of N or N(3A+X).In embodiments, the initial state of the delay line may be arbitrary. That is, the GRO can start from any initial state (as long as it is recorded as the initial state). Starting from an arbitrary state works because in embodiments the "final" output is taken as the difference between the final and initial states (1st difference). See, for example, 707 in FIG. 7, note that this barrel shifting operation provides first order mismatch shaping for the delay mismatch between units. The capacitors 1406 in the delay line 1405 ensure that the next pulse 1401 to be integrated starts with the delay line 1405 in the same state as it has ceased. It is assumed here that the next pulse arrives from the feedback delay line before the capacitors have discharged significantly. The key is that the state of the GRO is "frozen" between the N returns. Thus, the GRO sees "virtually" a pulse having N times the input pulse width. The number of delay units 1403 is usually selected to minimize the polarity change frequency so that the number of polarity changes (A) can be accurately detected using digital circuitry including the counter and the thermometer-to-binary encoder. The numeral "3" shown in Fig. 14 is illustrative. As mentioned above, the internal state of the GRO is frozen between the transformations - in other words, the partial residue on the capacitors of the unit cells is assumed to be "held" before the next pulse arrives from the feedback. This ensures that the GRO operates as an integrating TDC, the integration being used to provide gain.Figure 15 shows a high level block diagram of a TDC using a coarse TDC 1501 and a fine TDC 1503 providing improved effective resolution using feedback of input pulses as described above. The coarse TDC may be, for example, an asynchronous counter. Fine TDC 1503 includes one of the feedback delay lines described above in connection with an integrating delay line, for example, described in FIG. 14. In the example of FIG. 15, the coarse TDC provides N coarse bits, for example 24 bits, and the fine TDC provides M bits, for example 8 fine bits.Thus, various aspects have been described with respect to improving the resolution of TDCs. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. Other variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope of the invention as set forth in the following claims.

Claims

A method of performing time-to-digital conversion, comprising: receiving an input pulse (PIN) indicative of time information; feeding back a representation of the input pulse (PIN) in at least one delay line (807, 1007, 1115, 1117, 1207, 1405) using a feedback signal based on a delay line output signal of the at least one delay line (807, 1007, 1115, 1117, 1207, 1405); generating an output pulse corresponding to the input pulse (PIN) based at least in part on the delay line output signal of the at least one delay line (807, 1007, 1115, 1117, 1207, 1405); and supplying the output pulse to an integrator coupled to the delay line (807, 1007, 1115, 1117, 1207, 1405) N times, where N is an integer greater than one.The method of claim 1, wherein the feeding back the representation of the input pulse (PIN) in the at least one delay line (807, 1007, 1115, 1117, 1207, 1405) further comprises: logically combining, in a logic circuit, a first input signal to the logic circuit with the feedback signal to generate a delay line input signal; and supplying the delay line input signal to the delay line (807, 1007, 1115, 1117, 1207, 1405).The method of any of claims 1 to 2, further comprising selectively providing the output pulse to the integrator N times according to an enable signal (EN).The method of any of claims 1 to 2, further comprising: determining a polarity of the input pulse (PIN); and providing a sign signal indicative of the polarity.The method of claim 1, comprising: detecting a rising edge of the input pulse (PIN) and generating a rising edge pulse (P R); detecting a falling edge of the input pulse (PIN), and generating a falling edge pulse (P F); logically combining the feedback signal based on the delay line output signal and at least the rising edge pulse (P R), to generate a delay line input signal; and supplying the delay line input signal to an input of the at least one delay line (807, 1007, 1115, 1117, 1207, 1405).The method of claim 5, further comprising selecting a first delay path or a second delay path in a feedback path coupled between an output of the delay line (807, 1007, 1115, 1117, 1207, 1405) providing the delay line output signal and the input of the at least one delay line (807, 1007, 1115, 1117, 1207, 1405).The method of claim 5 or 6, further comprising logically combining the feedback signal based on the delay line output signal, the rising edge pulse (P R) and the falling edge pulse (P F), to generate the delay line input signal.The method of claim 7, further comprising dividing the delay line output signal by two to generate the output pulse.An apparatus comprising: a delay line (807, 1007, 1115, 1117, 1207, 1405); input logic coupled to receive an input pulse (PIN) and coupled to an output of the delay line (807, 1007, 1115, 1117, 1207, 1405), the input logic to provide a delay line input signal to the delay line (807, 1007, 1115, 1117, 1207, 1405); and an integrating time-to-digital converter coupled to the delay line (807, 1007, 1115, 1117, 1207, 1405) for receiving N pulse-off signals, each pulse-off signal corresponding to the input pulse (PIN), to thereby generate a digital representation of the input pulse (PIN) multiplied by a gain of N, where N is an integer greater than one.The apparatus of claim 9, wherein the input logic comprises an OR gate (805, 1005, 1105, 1107, 1109, 1205) to logically combine at least one input signal to the OR gate (805, 1005, 1105, 1107, 1109, 1205) with a feedback signal corresponding to the output of the delay line (807, 1007, 1115, 1117, 1207, 1405) to generate the delay line input signal.The apparatus of claim 9 or 10, further comprising: a first delay path and a second delay path in a feedback path between the output of the delay line (807, 1007, 1115, 1117, 1207, 1405) and the input logic; and a selector circuit for selecting the first or second delay path.The apparatus of claim 10, further comprising: a monostable multivibrator circuit coupled to the output of the delay line (807, 1007, 1115, 1117, 1207, 1405) to generate the feedback signal.The apparatus of any of claims 9 to 12, further comprising: output logic coupled to the output of the delay line (807, 1007, 1115, 1117, 1207, 1405) to provide a pulse-off signal according to an enable signal (EN).The apparatus of any of claims 9 to 13, further comprising: sign logic for determining a polarity of the input pulse (PIN) and providing a sign indication.The apparatus of claim 9, wherein the input logic further comprises: - a rising edge detector (1103, 1201) for detecting a rising edge of the input pulse (PIN) and providing a rising edge pulse (P R); - a falling edge detector (1101, 1203) for detecting a falling edge of the input pulse (PIN) and generating a falling edge pulse (P F); and logic circuitry for logically combining a feedback signal based on the output of the delay line (807, 1007, 1115, 1117, 1207, 1405), the rising edge pulse (P R) and the falling edge pulse (P F), to generate the delay line input signal.The apparatus of claim 15, further comprising a divide-by-two circuit for dividing the output of the delay line (807, 1007, 1115, 1117, 1207, 1405) by two to generate the pulse-off signal.The apparatus of claim 16, further comprising a drive circuit for selectively passing the pulse-off signal N times according to an enable signal (EN) to thereby effectively deliver the input pulse (PIN) N times to the integrating time-to-digital converter.The apparatus of claim 9, further comprising: a second delay line (1117); a rising edge detector (1103) for detecting a rising edge of the input pulse (PIN) and providing a rising edge pulse (P R); a falling edge detector (1101) for detecting a falling edge of the input pulse (PIN) and generating a falling edge pulse (P F), a first logic circuit (1105) for logically combining an output of the delay line (1115) and the rising edge pulse (P R), to generate the delay line input signal; a second logic circuit (1107) for logically combining an output of the second delay line (1117) and the falling edge pulse (P F), to generate a second delay line input signal; and a logic circuit for combining the output of the delay line (1115) and the output of the second delay line (1117) to generate the pulse-off signal supplied to the integrating time-to-digital converter.The apparatus of claim 9, wherein the delay line (1207) provides a delay line output signal; wherein the input logic comprises: - a rising edge detector (1201, 1301) for detecting a rising edge of the input pulse (PIN) and providing a rising edge pulse (P R), - a falling edge detector (1203, 1303) for detecting a falling edge of the input pulse (PIN) and generating a falling edge pulse (P F), and - a first logic circuit (1205) for logically combining the rising edge pulse (P R), the falling edge pulse (P F) and a feedback signal based on the delay line output signal and for supplying the delay line input signal to the delay line (1207); and wherein the apparatus comprises a second logic circuit (1211) coupled to receive an enable signal (EN) and an output pulse based on the delay line output signal and to pass the output pulse when the enable signal (EN) is set.The apparatus of claim 19, comprising: a divide-by-two circuit (1209) coupled to receive the delay line output signal and provide the output pulse to the second logic circuit (1211).

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