Semiconductor device

Abstract

A semiconductor device (100) having the following features: “n” pairs of pn transition structures, where n is an integer ≥ 2, where the i-th pair, with i ∈ {1, ..., n}, has two pn transition structures of the i-th type, where the two pn transition structures of the i-th type are connected in anti-serial order, where the pn transition structure of type i-th is designed such that it has an i-th transition step factor m i to demonstrate where at least one first pair of the n pairs of pn transition structures is designed to have a first transition step factor m1, with m1 ∉ {0,00, 0,50} and m1 < 0,50, and a second pair of the n pairs of pn transition structures is designed to have a second transition step factor m2, with m2 ∉ {0,00, 0,50} and m2 > 0,50, and wherein the transition step factors m1, m2 of the first and second pair of the n pairs of pn junction structures are set such that they result in the generation of a noisy third harmonic signal of the semiconductor device with a signal power level (PH3) that is at least 10 dB lower than a reference signal power level (PH3) of the noisy third harmonic signal obtained for a reference case where the first and second transition step factors m1, m2 are equal to 0.25.

Description

Technical area

[0001] Embodiments relate to a semiconductor device having at least two pairs of anti-serially connected pn junction structures (also referred to herein as diode structures) with adjusted junction step factors (also referred to as diode power law exponent) to provide at least reduced or minimal generation of spurious odd harmonics, for example third harmonics.

[0002] Further embodiments relate to a semiconductor device having at least two anti-serially connected pn junction structures with adjusted junction step factors, wherein one of the two pn junction structures has a "composite" diode structure in order to adapt and maintain a desired TVS (transient voltage suppressor) behavior of the semiconductor device with respect to breakdown voltage and to provide at least reduced or minimal generation of spurious odd harmonics, for example third harmonics. background

[0003] Discrete ESD (electrostatic discharge) and TVS (transient voltage suppressor) devices generally exhibit nonlinear electrical characteristics that cause harmonic distortion of RF (radio frequency) signals present on signal lines, such as printed circuit board (PCB) lines connected to the ESD protection device or TVS device. This harmonic generation produces spurious and unwanted harmonic signals that can interfere with other functions or functional blocks of an electronic system if those functions or functional blocks use frequency bands that are an integer multiple of the distorted RF signal.

[0004] For example, the third harmonic (H3) frequency of certain frequency bands in the range between 800 and 900 MHz used in mobile communications standards interferes with RF signals in the 2.4 GHz WiFi band, i.e. in the frequency range between 2.412 and 2.472 GHz.

[0005] To avoid such unwanted interference between the frequency bands described above as examples, electronic devices such as TVS devices should reduce the generation of harmonics to a sufficiently low level.

[0006] For example, in known implementations, the generation of even-numbered harmonics is minimized by utilizing a strictly symmetric design and highly symmetrical behavior of the electronic device for positive and negative half-waves of the RF signal. By ensuring symmetry, even-numbered harmonics can be efficiently suppressed, but the generation of odd-numbered harmonics is not achieved or sufficiently suppressed by this approach.

[0007] Regarding minimal generation of odd harmonics, for example the third harmonic (H3), it has long been assumed in the prior art that low capacitance and flat capacitance / voltage (CV) behavior of an electronic device leads to low generation of harmonics, including the third harmonic.

[0008] However, recent research by the applicant has shown that, considering the comparison of harmonic generation of electronic devices with different capacitance values ​​and CV characteristics, the above approach is not sufficient for suppressing the generation of odd harmonics.

[0009] Semiconductor devices for suppressing harmonics are described, for example, in the documents US 2008 / 0 290 465 A1, US 2016 / 0 329 918 A1 and US 2018 / 0 083 473 A1.

[0010] In general, there is a need in the art for an approach to implementing semiconductor devices, for example, discrete ESD protection devices or TVS devices, with reduced or minimal generation of odd harmonics, e.g., the third harmonic.

[0011] In general, there is a need in the art for an approach to implementing semiconductor devices, for example, discrete ESD protection devices or TVS devices, that also have a reduced or tuned breakdown voltage. Brief description

[0012] According to one embodiment, a semiconductor device according to the invention comprises “n” pairs of pn-junction structures, where n is an integer ≥ 2, wherein the i-th pair, with i ∈ {1,... n}, comprises two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are connected anti-serially, wherein the pn-junction structure of the i-th type is arranged to have an i-th junction step factor m i to show, wherein at least a first pair of the n pairs of pn junction structures is arranged to have a first junction step factor m1, with m1 ∉ {0.00, 0.50} and m1 < 0.50, and a second pair of the n pairs of pn junction structures is arranged to have a second junction step factor m2, with m2 ∉ {0.00, 0.50} and m2 > 0.50, and wherein the junction step factors m1, m2 of the first and second pair of the n pairs of pn junction structures are adjusted to result in the generation of a spurious third harmonic signal of the semiconductor device with a signal power level (PH3) that is at least 10 dB lower than a (for example simulated) reference signal power level (PH3) of the spurious third harmonic signal, which is obtained for a (for example simulated) reference case where the first and second transition step factors m1, m2 are 0.25.

[0013] In a commonly used model of a pn junction structure, the i-th junction step factor m i based on a voltage-dependent capacitance characteristic C i (V i ) of a depletion region of the i-th type pn junction structure for a reverse bias voltage V i which can be applied to the pn junction structure of the i-th type, with Ci(Vi)=Cj0i(ViVji+1)mi; where C J0i denotes an i-th zero-bias capacitance and V Ji is called an i-th transition voltage potential.

[0014] The generation of spurious odd harmonics, for example for the reference case, can be determined by simulations using a standard circuit simulation tool such as the Advanced Design System (ADS) from Keysight Technologies, for example by a harmonic balance analysis, which is well known in the art.

[0015] According to a further embodiment, a semiconductor device according to the invention comprises “n” pairs of pn-junction structures, where n is an integer ≥ 2, where the i-th pair, with i ∈ {1, ..., n}, comprises two pn-junction structures of the i-th type, where the two pn-junction structures of the i-th type are connected anti-serially, where the pn-junction structure of the i-th type is arranged to have an i-th junction step factor m i to show, where the first to n-th transition step factor m1 to m n within a tolerance range of ±0.05 satisfy the following ellipse equation: ∑i=1n(mi−0.25ai)2=1, with ∑i=1n(1ai)2=16, wherein at least a first pair of the n pairs of pn junction structures is arranged to have a first junction step factor m1, with m1 ∉ {0.00, 0.50} and m1 < 0.50, and a second pair of the n pairs of pn junction structures is arranged to have a second junction step factor m2, with m2 ∉ {0, 00, 0.50} and m2 > 0.50, and wherein the parameters a i based on a zero-bias capacitance C J0i and a transition voltage potential V Ji the pn junction structure of the i-th type.

[0016] The tolerance range of ± 0.05 specifies a range for each of the transition step factors. In the present context, the step factors m1 to m n considered that within this tolerance range they satisfy the ellipse equation if the ellipse occupies the volume defined by the tolerance range near a specific point (m1 to m n) in the n-dimensional space (coordinate system) of the step factor. For illustrative purposes, in the two-dimensional case of two pairs of pn junction structures with step factors m1 and m2, the volume defined by the tolerance ranges is a circle with a diameter of 0.10 and the specific point (m1, m2) at its center. This effectively defines a width range of 0.10 around the ellipse, in which possible combinations of step factors m1 to m n can be found.

[0017] In this, the i-th transition step factor m i , the zero-bias junction capacitance C J0i and the transition potential V Ji the pn junction structure of the i-th type can also be described by the above-mentioned formula (A1).

[0018] Thus, embodiments relate to a semiconductor device comprising at least two pairs of anti-serially connected pn junction structures, with junction step factors adjusted for each of the at least two pairs to provide at least reduced or minimal generation of spurious odd harmonics, for example the third harmonic.

[0019] According to a further embodiment, a semiconductor device comprises a composite pn junction structure in a semiconductor substrate, wherein the composite pn junction structure is arranged to have a predetermined first junction step factor m1, with m1 > 0.50, wherein the composite pn junction structure comprises a first partial pn junction structure and a second partial pn junction structure, wherein the first partial pn junction structure is arranged to have a predetermined first partial junction step factor m 11 and wherein the second partial pn junction structure is arranged to have a predetermined second partial junction step factor m 12 wherein the predetermined first partial transition step factor m 11 of the predetermined second partial transition step factor m 12 is different, with m 11 ≠ m 12, and wherein at least one of the predetermined first and second partial transition step factors m 11 , m 12 is greater than 0.5, with m 11 and / or m 12 > 0.5, and wherein the predetermined first junction step factor m1 of the composite pn junction structure is based on a predetermined combination of the first and second partial junction step factors m 11 , m 12 based.

[0020] Thus, embodiments relate to a semiconductor device comprising at least two pairs of anti-serially connected pn junction structures with adjusted junction step factors, wherein at least one of the at least two pairs of pn junction structures is a pair of anti-serially connected composite pn junction structures (also referred to herein as a composite diode structure) in order to adapt and maintain a desired TVS (transient voltage suppressor) behavior of the semiconductor device with respect to a breakdown voltage and to provide at least reduced or minimal generation of spurious odd harmonics, for example third harmonics. Short description of the drawings

[0021] Embodiments of the present concept are described herein with reference to the accompanying drawings and figures, wherein: Fig. 1a-d show exemplary schematic circuit diagrams of a semiconductor device with n pairs of anti-serially connected pn junction structures according to an embodiment, Fig. 2 shows an exemplary circuit block diagram for testing the semiconductor device, Fig. 3a, Fig. 3b show schematic power distributions of RF signals according to an embodiment, Fig. 4a shows the graphical representation (graph of the function) of the cancellation lines of the third harmonic signal of the semiconductor device as a function of the first and second transition step factors m1, m2 according to an embodiment, Fig. 4b shows an enlarged view of Fig. 4a, Fig. Figure 4c shows a further graphical representation of the function graphs for which the third harmonic generation PH3 of the semiconductor device can be optimally suppressed, Fig. Figure 4d shows an enlarged view of the graphical representation of Fig. 4c, Fig. Figure 4e shows a graphical representation of the parameters a1, a2 (= radii r1, r2) of the ellipse at which the third harmonic generation of the semiconductor device can be optimally suppressed, Fig. Figure 4f shows a graphical representation of the cancellation lines of the third harmonic PH3 of the semiconductor device as a function of the first and second transition step factors m1, m2 in view of the influence of non-equal values ​​for the first and second transition voltage potential V J1 , V J2 , Fig. 4g-j show the simulated spurious third harmonic PH3 of the semiconductor device with equal first and second bias junction capacitance C J01 = C J02 at different input power levels of the fundamental frequency signal, Fig. Figure 5a shows a schematic cross-sectional view of the semiconductor device of Fig. 1a, Fig. Figure 5b shows a schematic simulated representation of an exemplary doping profile of pn junction structures of the semiconductor device of Fig. 5a, Fig. 6a shows a schematic cross-sectional view of a semiconductor device according to an embodiment, Fig. Figure 6b shows a schematic plan view of the semiconductor device of Fig. 6a, Fig. 7a, Fig. 7b show exemplary schematic circuit diagrams of a semiconductor device with n pairs of anti-serially connected pn junction structures according to an embodiment, Fig. Figure 8a shows a schematic simulated representation of the resulting transition step factor m1 as a function of the doping concentration, based on different implantation doses for the doping profiles of Fig. 5b, Fig. Figure 8b shows a schematic simulated representation of the resulting breakdown voltage as a function of the doping concentration, based on different implantation doses for the doping profiles of Fig. 5b, Fig. Figure 8c shows the resulting combined junction step factor of the composite pn-junction structure of the first type as a function of the area ratio between the areas of the first and second partial pn-junction structures, based on two adjusted partial junction step factors m 11 , m 12 for two of the Fig. Doping profiles shown in Figure 5b, Fig. 9a shows a schematic cross-sectional view of another exemplary implementation of the semiconductor device, Fig. Figure 9b shows a schematic simulated representation of different exemplary doping profiles of the composite pn junction structure of the semiconductor device of Fig. 9a, Fig. Figure 9c shows a schematic plan view through the semiconductor device of Fig. 9a in the plane through the composite pn junction structure of the first type, showing the “active” areas of the first and second partial anode regions of the pn junction structure of the first type, and Fig. 9d-f show schematic cross-sectional views of further exemplary implementations of the semiconductor device.

[0022] Before embodiments of the present invention are explained in more detail with reference to the drawings, it is pointed out that in the figures and the application, identical elements and elements with the same functionality and / or the same technical or physical effect are generally provided with the same reference numerals or identified by the same name, so that the description of these elements and the functionality thereof, as illustrated in the various embodiments, are interchangeable or can be applied interchangeably in the various embodiments. Detailed description of illustrative embodiments

[0023] In the following description, embodiments of the invention are discussed in detail, with it being understood that the invention offers many applicable concepts that may be embodied in a variety of semiconductor device concepts. The specific embodiments discussed merely illustrate specific ways of making and using the invention and do not limit the scope of the invention. In the following description of embodiments, the same or similar elements having the same function are assigned the same reference numerals or name, and a description of such elements is not repeated for each embodiment. Furthermore, features of the different embodiments described below may be combined with one another unless expressly stated otherwise.

[0024] It should be understood that when an element is described as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is described as "directly" connected, "connected," or "coupled" to another element, there are no intermediate elements. Other terms used to describe the relationship between elements should be constructed in a similar manner (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.).

[0025] The abbreviation CV or C(V) used here stands for capacitance versus voltage (capacitance / voltage). The terms C(V) characteristics, C(V) properties, and C(V) behavior may be used synonymously in this document.

[0026] The Fig. 1a-d show various schematic circuit diagrams of a semiconductor device 100 with "n" pairs 102, 104 (....) of anti-serially connected pn junction structures J1, J2, J3, J4 (....), which can be adapted on the basis of the present concept as described below to have a reduced, e.g., greatly reduced, or even minimized generation of a spurious odd harmonic, e.g., a third harmonic.

[0027] More specifically, the semiconductor device 100 comprises "n" pairs 102, 104 (...) of pn-junction structures J1, J2 and J3, J4 (...), where n is an integer ≥ 2, wherein the i-th pair, with i ∈ {1, ..., n}, comprises two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are connected anti-serially. The pn-junction structure of the i-th type is arranged to have an i-th junction step factor m i(m1, m2, ...), an i-th zero-bias junction capacitance C J0i and an i-th junction voltage potential V Ji and the following capacity behavior C i (V i ) based on a reverse bias voltage V i , which can be applied to the pn junction structure of the i-th type, with Ci(Vi)=CJ0i(ViVJi+1)mi;

[0028] The C(V) characteristics described by the above equation also hold for small forward bias voltages. In other words, the expression also holds for a range of applied voltages where the reverse bias voltage is negative, i.e., the applied voltage is a forward bias. In this application, the phrase "pn junction (or diode structure) with a step factor m i“ is used to express that the C(V) characteristics of the pn junction or diode structure are given by the above equation, with a step factor or power law exponent m i can be described.

[0029] According to one embodiment, at least a first pair 102 of the n pairs 102, 104 (...) of pn junction structures J1, J2 and J3, J4 (...) is arranged to have a first junction step factor m1, with m1 ∉ {0.00, 0.50}, and a second pair 104 of the n pairs 102, 104 (...) of pn junction structures J1, J2 and J3, J4 (...) is arranged to have a second junction step factor m2, with m2 ∉ {0.00, 0.50}, and wherein the first pair 102 of the pn junction structures J1, J2 is arranged to have the first junction step factor m1, with m1 < 0.50, and wherein the junction step factors m1, m2 of the first and second Pair 102, 104 (...) of the n pairs of pn junction structures J1, J2 and J3, J4 (...) are adjusted to result in a generation of a spurious third harmonic signal of the semiconductor device 100 having a signal power level PH3 that is at least 10 dB lower, preferably at least 15 dB lower, and more preferably at least 20 dB lower than a (e.g., simulated) reference signal power level PH3 of the spurious third harmonic signal obtained for a (e.g., simulated) reference case in which the first and second junction step factors m1, m2 are each 0.25. In order to facilitate the manufacture of the pn junction structure, it may be preferable for m1 to be 0.48.

[0030] According to the invention, the second pair 104 of the pn junction structures J3, J4 has the second junction step factor m2, with m2 > 0.50, preferably m2 ≥ 0.52.

[0031] In the reference case, a reference signal power level PH3' of the spurious third harmonic signal of the semiconductor device 100 is simulated and calculated by setting the reference value of the transition step factors m1, m2 (...), ie, all the transition step factors m1, m2, (...) set above and between 0.00 and 0.50 from the reference value m i = 0.25.

[0032] According to the above-defined embodiment, the transition step factors m1, m2 (...) of the n pairs 102, 104 (...) of the pn junction structures J1, J2 and J3, J4 (...) are set to provide an at least reduced signal power level of the spurious third harmonic signal PH3, compared to the, e.g., simulated, reference signal power level PH3' of the spurious third harmonic signal of the semiconductor device 100 obtained in the reference case in which the transition step factors m1, m2 (...) are set to a reference value of 0.25. The following evaluations regarding the Fig. 2a-i will show, for example, that a simulation with a circuit simulation tool, which will be described in more detail below, related to the reference signal power level PH3' of the semiconductor device 100, in which the transition step factors m1, m2 (...) are set to the reference value 0.25, refers to a (theoretical) local maximum of the reference signal power level PH3' of the spurious third harmonic signal of the semiconductor device 100.

[0033] According to a further embodiment, the semiconductor device 100 comprises "n" pairs 102, 104 (...) of pn-junction structures J1, J2 and J3, J4 (...), where n is an integer ≥ 2, wherein the i-th pair, with i ∈ {1, ..., n}, comprises two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are connected anti-serially. The pn-junction structure of the i-th type is arranged to have an i-th junction step factor m i, an i-th zero-bias junction capacitance C J0i and an i-th junction voltage potential V Ji and the following capacity behavior C i (V i ) based on a reverse bias voltage V i which can be applied to the pn junction structure of the i-th type, with Ci(Vi)=CJ0i(ViVJi+1)mi; and where the first to n-th transition step factor m1 to m n within a tolerance range of ±0.05 satisfy the following ellipse equation: ∑i=1n(mi−0.25ai)2=1, with ∑i=1n(1ai)=16, wherein at least a first pair of the n pairs of pn junction structures is arranged to have a first junction step factor m1, with m1 ∉ {0.00, 0.50}, where m1 < 0.50, and a second pair of the n pairs of pn junction structures is arranged to have a second junction step factor m2, with m2 ∉ {0.00, 0.50}, and wherein the first to n-th parameters “a1 to a n “ of the zero-bias capacitances C J0i and the transition voltage potentials V Ji of the pn junction structures. In order to facilitate the fabrication of the pn junction structure, it may be preferable for m1 ≤ 0.45.

[0034] The second pair 104 of the pn junction structures J3, J4 has the second junction step factor m2, with m2 > 0.50, preferably m2 ≥ 0.52.

[0035] As stated above, the first to n-th transition stage factors m1 to m nwithin a tolerance range of ±0.05 the specified (n-dimensional) ellipse equation. The tolerance range of ±0.05 (or ±0.03) may, for example, take into account unavoidable semiconductor manufacturing tolerances of the semiconductor device 100. The tolerance range of ±0.05 (or ±0.03) may, for example, further take into account a (possibly occurring) difference between the trajectory of the theoretical optimal suppression of spurious third harmonics and the trajectory of the actual (for example, input power-dependent) optimum suppression at different input power levels of the semiconductor device 100. This will be explained below with reference to the Fig. 4g-j described in more detail.

[0036] In the following, schematic diagrams of some possible implementations of the semiconductor device 100 according to the present concept are presented with reference to the Fig. 1a-d.

[0037] As in Fig. 1a, the semiconductor device 100 may comprise n = 2 pairs 102, 104 of anti-serially connected pn-junction structures J1, J2, J3, J4, wherein the first pair 102 of the pn-junction structures comprises the pn-junction structures of the first type J1, J2 with the first step factor m1, the first junction voltage potential V J1 and the first zero-bias capacitance C J01 wherein the second pair of pn junction structures 104 comprises the pn junction structures of the second type J3, J4 with the second step factor m2, the second junction voltage potential V J2 and the second zero-bias capacitance C J02 As in Fig. As shown in Figure 1a, the pn junction structures J1, J2 of the first pair 102 and the pn junction structures J3, J4 of the second pair 104 are each connected anti-serially, wherein the (at least) two pairs 102, 104 of pn junction structures J1-J4 are connected between the first and second terminals 107, 108.

[0038] Fig. Fig. 1b shows a further exemplary schematic circuit diagram of the semiconductor device 100 with two (n = 2) pairs 102, 104 of pn junction structures J1, J2, J3, J4, wherein the first pair 102 comprises the pn junction structures of the first type J1, J2 with the first step factor m1, the first junction voltage potential V J1 and the first zero-bias capacitance C J01 and the second pair 104 comprises the pn junction structures of the second type J3, J4 with the second step factor m2, the second junction voltage potential V J2 and the second zero-bias capacitance C J02 As in Fig. 1b, the pn-junction structures J1, J2 of the first pair 102 are connected anti-serially and the pn-junction structures J3, J4 of the second pair 104 are connected anti-serially, wherein the (at least) two pairs 102, 104 of pn-junction structures J1-J4 are connected between the first and second terminals 107, 108. The arrangement of the two pairs 102, 104 of the pn-junction structures J1, J2 and J3, J4, as shown in Fig. 1b, differs when compared with the semiconductor device 100 of Fig. 1a merely by a reversed direction of the respective pn junction structures J1-J4.

[0039] Fig. Fig. 1c shows a further schematic circuit diagram of the semiconductor device 100 with n = 2 pairs 102, 104 of pn junction structures J1, J2, J3, J4, wherein in Fig. 1c the first pair 102 the pn-junction structures of the first type J1, J2 with the first step factor m1, the first junction voltage potential V J1and the first zero-bias capacitance C J01 wherein the second pair 104 comprises the pn junction structures of the second type J3, J4 with the second step factor m2, the second junction voltage potential V J2 and the second zero-bias capacitance C J02 As in Fig. 1c, the pn-junction structures J1, J2 of the first pair 102 and the pn-junction structures J3, J4 of the second pair 104 are each connected anti-serially, wherein the (at least) two pairs 102, 104 of pn-junction structures J1-J4 are connected between the first and second terminals 107, 108. The arrangement of the two pairs 102, 104 of the pn-junction structures J1-J4, as shown in Fig. 1c, differs when compared with the semiconductor device 100 of Fig. 1a only with regard to the order of arrangement of the respective pn junction structures J1-J4.

[0040] Fig. 1d shows another schematic circuit diagram of the semiconductor device 100 with n = 3 pairs 102, 104, 106 of anti-serially connected pn junction structures J1, J2 and J3, J4 and J5, J6. As in Fig. As shown in Figure 1d, the first pair 102 comprises the two pn junction structures of the first type J1, J2 with the first step factor m1, the first junction voltage potential V J1 and the first zero-bias capacitance C J01 the second pair 104 has the pn junction structures of the second type J3, J4 with the second step factor m2, the second junction voltage potential V J2 and the second zero-bias capacitance C J02 and wherein the third pair 106 comprises, for example, the pn junction structures of the third type J5, J6 with the third step factor m3, the third junction voltage potential V J3 and the third zero-bias capacitance C J03 As in Fig. As shown in Figure 1d, the pn junction structures J1, J2 of the first pair 102, the pn junction structures J3, J4 of the second pair 104 and the pn junction structures J5, J6 of the third pair 104 are each connected anti-serially, the three pairs 102, 104, 106 of pn junction structures J1-J6 being connected between the first and second terminals 107, 108.

[0041] The above-described schematic circuit diagrams of the semiconductor devices 100 show that the semiconductor device 100 can have a plurality of pairs 102, 104, 106 of pn junction structures J1-J6, wherein the two associated pn junction structures of the respective pair are arranged or connected anti-serially between the first and second terminals 107, 108, wherein the order of the respective pn junction structures does not influence the resulting reduction in third harmonic generation of the semiconductor device, so that the different pn junction structures of the n pairs can be arranged anti-serially as desired between the first and second terminals 107, 108.

[0042] The generation of spurious odd harmonics, for example, in the reference case, can be determined by simulations using a standard circuit simulation tool such as Keysight Technologies' Advanced Design System (ADS), for example, using harmonic balance analysis, which is well known in the art. The simulation results can be compared to a measurement of the generation of spurious harmonics of a semiconductor device under test and thus compared to the harmonic generation of the reference case to determine a power level of the measured spurious third harmonic of the device under test relative to the power level of the spurious third harmonic determined by simulation for the reference case.Model parameters for simulating the reference case other than the step factor, such as the zero-bias junction capacitance and the junction potential, can be obtained from measurements of the device under comparison using methods well known in the art.

[0043] A possible circuit setup for measuring or simulating the generation of harmonics of a semiconductor device under test is shown in the block diagram of Fig. 2. It depicts a transmission line consisting of two parts, TL1 201 and TL2 202, in which the semiconductor device 200 under test (illustrated as four diode structures J1 to J4) is connected to ground in a shunt configuration. An RF signal is supplied at a fundamental frequency f0 from an RF source PORT1 211 and coupled into TL1 201 at a depicted left end of the transmission line TL1 201 by a circulator CIR1 203.

[0044] The RF signal is routed to the semiconductor device under test 200 (J1 to J4), where, due to nonlinearities in the electrical properties of the semiconductor device under test 200, harmonic signals in integer multiples of the fundamental frequency (overtones) are generated. The generated harmonic signals are transmitted from the semiconductor device under test 200 via TL2 202 to the termination Term2 212 and via TL1 201, the circulator CIR1 203, and the transmission line TL3 204 to the termination Term3 213. Using a spectrum analyzer (not shown), the RF power distribution of the harmonic signals can be determined at either the position of the termination Term2 212 or the termination Term3 213.

[0045] By sweeping the power of the applied RF signal at the fundamental frequency, the input power dependence of the harmonic generation can be determined.

[0046] The sensitivity of the determination of a generated harmonic signal can be further increased, for example, by adding additional filters or diplexers (not shown) to filter out the signal at the fundamental frequency f0.

[0047] Typical spectra of the generated RF signal and the harmonic signals are shown in Fig. 3a and 3b are shown schematically. Fig. Figure 3a illustrates the spectrum of the RF signal as supplied by the RF source PORT1 211. This signal is supplied in such a way that it only includes the fundamental frequency f0 (1, harmonic, x=1). Fig. Figure 3b shows the spectrum of the signal arriving at termination Term2 212, for example. The signal power at the fundamental frequency is reduced compared to the incident signal, as in Fig. 3a, (1) by impedance mismatch caused by the semiconductor device under test 200 in shunt configuration, and (2) by partial conversion of the electrical signal at the fundamental frequency into the harmonics, shown here for simplicity for the second through fourth harmonics. The spectrum further shows that the signal, for example in the termination Term2 212, also has power contributions at integer amounts of the fundamental frequency, such as the second harmonic power PH2 at 2 times f0 (2 x f0, x=2), third harmonic power PH3 at 3 times f0 (3 x f0, x=3), and so on. In general, the power contribution of the harmonics decreases with the order of the harmonics.

[0048] The following evaluations provide a comprehensive explanation of the present concept in the form of the described implementations and embodiments of the semiconductor device 100 with properly adjusted transition step factors m i(m1, m2 ....) according to the Fig. 1a-d. In particular, the following discussion regarding the Fig. 4a - j to the technical and mathematical analysis in the field of semiconductor devices, for example in the field of discrete ESD protection devices or TVS devices, by the applicant and to the resulting technical findings and conclusions for a correct setting of the transition step factors m i the n pairs of pn junction structures of the semiconductor device 100.

[0049] Assuming that the "capacitance / voltage C(V) characteristics" of a pn junction structure (or simply a pn junction) are the main factor for the generation of odd harmonics of the semiconductor device 100, the third harmonic generation can be substantially completely canceled or at least greatly reduced in case of a proper adjustment of the C(V) characteristics of the individual pn junction structures, which may comprise at least two pairs 102, 104 (....) of anti-serially connected pn junction structures J1, J2, J3, J4 (....).

[0050] More specifically, in the case of a compound or stack of, for example, four anti-serially connected pn-junction structures J1-J4 (i.e., two pairs of pn-junction structures), the third harmonic generation can be canceled or at least minimized by selecting a suitable combination of C(V) behavior of the different pn-junction structures J1-J4 in the four-pn-junction structure stack, for example, by appropriately choosing the (first and second) n-junction step factors m1, m2 according to the equations and formulas for the transition step factors m given below. i and the parameters a1, a2, which depend on the zero-bias capacitances C J01 , C J02 and the transition voltage V J1 , V J2 the two pairs 102, 104 depend on pn junction structures.

[0051] The C(V) behavior of a pn junction, which is denoted by “i” in this specification to indicate the “i-th” type, can be generally described by the following expression: Ci(V)=Cj0i(VVji+1)mi

[0052] In many cases, this expression provides an accurate description of the C(V) characteristics of pn junction structures. The parameters have the following meaning: C j0 is the capacitance at 0V bias, V ji is the built-in voltage and mi is the junction step factor. V represents the reverse bias voltage across the i-th pn junction. As can be seen from expression (A1), the junction step factor m is i a key parameter for controlling the C(V) behavior of the pn junction structure and thus of the semiconductor device 100. The junction step factor m i can be adjusted by the doping profile of the respective pn junction structure J1-J4 (....).

[0053] Some examples of the transition step factor m: - m = 0.5 represents (1.) the behavior of an abrupt pn junction with uniform dopants (= doping concentrations) in the n- and p-region, or (2.) a one-sided junction with a very abrupt pn junction between a highly doped region and a uniformly doped less doped region. It can be difficult or expensive to realize this type of idealized junction with conventional semiconductor technologies. - m = 0.33 represents the behavior of a linearly stepped junction. In this case, the dopant concentration around the junction varies linearly with depth. This type of pn junction is very common in conventional semiconductor technology as a result of the diffusion of a p- and an n-doped region. - In the case of m > 0.5, the term hyper-abrupt transition is used. This can be considered a one-sided transition in which the less doped region does not have a constant doping profile, but rather a doping concentration that decreases with distance from the metallurgical transition.

[0054] The following discusses in general terms the mathematical derivation of the optimal C(V) parameters for suppressing third harmonic generation of the semiconductor device 100. The following derivation can describe the C(V) characteristics sufficiently well for low input powers P IN of the input RF signal, e.g., not more than 20 dBm, but may be less accurate for higher input powers.

[0055] In the following equations (1) to (38) and in the corresponding Fig. 4a to 4j correspond to the radii r i the parameters described so far a ithe described ellipse equation, i.e. r i = a i . In general, in this document, the radii as described and / or illustrated herein correspond to the parameters a i as described and / or illustrated herein, ie r i = a i .

[0056] The capacitance / voltage behavior of two different pn junctions is expressed by the following equations. These equations can be successfully used to describe the depletion capacitance behavior under reverse and forward bias conditions within a wide range of doping profiles: C1(V)=CJ0,1(VVJ1+1)m1 C2(V)=CJ0.2(VVJ2+1)m2 where V is the applied reverse bias voltage, C J0i is the zero-bias junction capacitance, V Jjis the junction voltage or junction potential (equal to or closely related to the built-in voltage, sometimes referred to as “effective built-in voltage”) and where m i is the step factor (also called the “diode power law exponent”).

[0057] The equations for capacitance / voltage behavior can be extended to a Taylor series: C1(V)=K10+K11V+K12V2+... C2(V)=K20+K21V+K22V2+...

[0058] By integrating the C l (V) expressions from 0 V to a certain voltage V ij the total charge Q ij In the case of a series circuit of two pairs of antiserial pn junctions, the following must be applied to find the charge on each pn junction, taking into account that for each pair of junctions, one junction is reverse biased and one junction is forward biased. Q11(V11)=∫0V11C1(V)dV Q12(V12)=−∫0V12C1(V)dV Q21(V21)=∫0V21C2(V)dV Q22(V22)=−∫0V22C2(V)dV

[0059] Applying the integration of a capacitance / voltage relationship C(V) to the series expansions yields the following expressions: Q11=K10V11+K11V1122+K12V1133+... Q12=K10V12−K11V1222+K12V1233+... Q21=K20V21+K21V2122+K22V2133+... Q22=K20V22−K21V2222+K22V2233+...

[0060] In a series-connected configuration of capacitors, the charge on all capacitors is the same: Q11=Q12=Q21=Q22=Q

[0061] By series inversion, the charge versus voltage (equations (9)-(12)) can be reversed to voltage versus charge. V11=Q24K107[24K106+12K104K11Q+K102Q2(−8K10K12+12K112) +5K11Q3(4K10K12−3K112)]+ V12=Q24K107[24K106−12K104K11Q+K102Q2(−8K10K12+12K112) +5K11Q3(−4K10K12+3K112)]+ V21=Q24K207[24K206+12K204K21Q+K202Q2(−8K20K22+12K212) +5K21Q3(4K20K22−3K212)]+ V22=Q24K207[24K206−12K204K21Q+K202Q2(−8K20K22+12K212) +5K21Q3(−4K20K22−3K212)]+

[0062] The total voltage V across the two pairs of anti-serial connected pn junctions is: V=V11+V12+V21+V22

[0063] By summing equations (14)-(17), the total voltage V across the series-connected pn junctions as a function of the charge Q is: V=2(1K20+1K10)Q+(K112K105+K212K205−2K123K104−2K223K204)Q3+

[0064] By series inversion of equation (19), the charge Q as a function of the total voltage V across the series-connected pn junction is as follows: Q=K10K202(K10+K20)V+K105(2K20K22−3K212)+K205(2K10K12−3K112)48K10K20(K10+K20)4V3+

[0065] The capacitance / voltage characteristics of the series junction can be calculated by differentiating the Q(V) expression (Eq. 20). C=dQdV C=K10K202(K10+K20)+K105(2K20K22−3K212)+K205(2K10K12−3K112)16K10K20(K10+K20)4V2+

[0066] The coefficients in this resulting series for the C(V) behavior are defined as follows: C=κ0+κ1V+κ2V2

[0067] The coefficient of the quadratic term K2V 2 determines the generation of the third harmonic. This coefficient K2 is: κ2=K105(2K20K22−3K212)+K205(2K10K12−3K112)16K10K20(K10+K20)4

[0068] Now the coefficients K 10 , K 11 , K 12 , K 20 , K 21 , K 22the series expansion of the individual pn junctions is replaced by the respective Taylor coefficients resulting from a Taylor expansion of the C(V) behavior (equations (1) and (2)). After this replacement, the coefficient K2 of the quadratic term becomes: κ2=−18(1CJ0.1+1CJ0.2)4[1CJ0.13VJ12(m12−12m1)+1CJ0.23VJ22(m22−12m2)]

[0069] In a series expansion of the C(V) behavior, the quadratic term is responsible for generating the third harmonic. If the quadratic term is zero, the third harmonic is completely canceled. κ2=0

[0070] This expression (Eq. 25) for K2 = 0 can be transformed into the following form, which describes an ellipse in the plane m1, m2: (m1−m0,1)2r12+(m2−m0,2)2r22=1 where (m 0,1 , m 0,2 ) is the center of the ellipse and r1 and r1 are the radii in the direction of m1 and m2 respectively.

[0071] Equation (25) under the condition expressed by equation (26) is transformed into the form of equation (27) and thus yields: (m1−14)2(CJ0.13VJ12+CJ0.23VJ224CJ0.232VJ2)2+(m1−14)2(CJ0.13VJ12+CJ0.23VJ224CJ0.132VJ1)2=1 from which it can be concluded that the third harmonic generation is cancelled when the step factors m1 and m2 are on the ellipse centered at (14,14), with radii r1 and r2, as described by the following equations: r1=14(CJ0,1CJ0,2)3(VJ1VJ2)2+1 r2=14(CJ0,2CJ0,1)3(VJ2VJ1)2+1

[0072] From equations (29) and (30), it can be concluded that the shape of the ellipse into which the combinations of the step factors m1 and m2 fall depends on the ratio of the zero-bias capacitances and the junction potentials of both junction pairs. The zero-bias capacitance can vary over a wide range by adjusting the doping profile of the pn junction and / or the physical design (layout) of the pn junction. On the other hand, the variation range of the junction potential is considerably smaller, since this parameter relates to the built-in voltage of the pn junction. A typical variation range of V J for a silicon pn junction is approximately 0.6 to 0.9 V. If a specific breakdown voltage must be provided by a pn junction, the influence on V J very limited and cannot be considered as a useful parameter for designing the device behavior.

[0073] The Fig. 4a-j, as described below, show the influence of the device parameters, ie the zero-bias junction capacitances C J01 , C J02 , and the transition voltage potentials V J1 , V J2 on the relationship between the first to n-th (here: second) transition stage factor m1 to m n (here: m1 and m2).

[0074] Fig. 4a shows the graphical representation (graph of function) of the cancellation lines of the third harmonic signal PH3 of the semiconductor device 100 as a function of the first and second transition step factors m1, m2 according to an embodiment.

[0075] Based on the above mathematical derivation of the optimal C(V) parameters, the ellipses of Fig. 4a, into which the combinations of the step factors m1, m2 fall, indicate a cancellation of the third harmonic signal PH3 of the semiconductor device 100. Therefore, these ellipses are also called cancellation lines in the present context. The shape of the ellipses depends on the ratio of the zero-bias capacitances C J01 , C J02 and the transition voltage potentials V J1 , V J2 of the two pairs 102, 104 of the pn junction structures J1-J4 of the semiconductor device 100.

[0076] More precisely, Fig. 4a the combinations of the transition step factors m1, m2 at which the third harmonic PH3 generated by the semiconductor device 100 (for example with two pairs 102, 104 of pn junction structures J1, J2 and J3, J3) is zero or at least almost zero, wherein the ratio of the zero-bias capacitances C J01 , C J02The shape (=eccentricity) of the ellipse is determined by determining the parameter a1 and the parameter a2, as given in equations (29) and (30) above. As mentioned above, the parameters a i the radii r i of equations (1) to (31) above and the radii r i , as they are in the Fig. 4a to 4j are shown, that is r i = a i . The other parameters that influence the parameters a1, a2 of the ellipses, for example the first and second transition voltage potential V J1 , V J2 , for example, during the calculation of the curves (function graphs) of Fig. 4a are set to the same values.

[0077] Fig. 4b shows an enlarged view of Fig. 4a. From Fig. 4a and Fig. 4b it is evident that all ellipses have crossing points for (1.) m1 = m2 = 0; (2.) m1 = m2 = 0.5; (3.) m1 = 0 and m2 = 0.5; and (4.) m1 = 0.5 and m2 = 0, ie for m i ∈ {0.00, 0.50}.

[0078] Fig. Figure 4c shows a further graphical representation of the function graphs for which the third harmonic generation PH3 of the semiconductor device 100 is theoretically completely suppressed. More specifically, Fig. 4c the step factor m2 of the second pair 104 of pn junction structures J3, J4, for which the third harmonic generation PH3 is completely suppressed, as a function of the ratio of the first and second zero-bias capacitance C R = C J01 / C J02 The step factor m1 of the first pair 102 of pn-junction structures J1, J2 is a parameter of this representation (function graph). During the calculation of these curves of Fig. 4c are the first and second transition voltage potential VJ1 , V J2 set to the same values, with V R = V J01 / V J02 = 1.

[0079] Fig. Figure 4d shows an enlarged view of the graphical representation of Fig. 4c.

[0080] Fig. Figure 4e shows a graphical representation of the parameters a1, a2 (radii r1, r2) of the ellipse, in which the third harmonic PH3 generation of the semiconductor device 100 is at least theoretically completely suppressed, as a function of the ratio C R the first and second zero-bias capacitance C J01 / C J02 . During the calculation of these curves, the first and second transition voltage potential V J1 , V J2 set to the same values, with V R = V J01 / V J02 = 1.

[0081] The relatively large dependence of the first parameter a1 (first radius r1) of the ellipse on the ratio C Rthe first and second bias capacitance C J01 / C J02 reflects the increasing eccentricity of the ellipse, as in Fig. 4a regarding the increasing ratio C R the first and second zero-bias capacitance C R = C J01 / C J02 is shown.

[0082] Fig. Figure 4f shows a graphical representation of the cancellation lines of the third harmonic PH3 of the semiconductor device 100 as a function of the first and second transition step factors m1, m2 in view of the influence of non-equal values ​​on the first and second transition voltage potential V J1 , V J2 , i.e. for V R = V J01 / V J02 ≠ 1. More precisely, Fig. 4f the influence of non-equal values ​​for the first and second transition voltage potential V J1 , V J2, to the combinations of the step factors m1, m2 that lead to a complete suppression of the third harmonic PH3 generation of the semiconductor device 100. In the case of Fig. 4f are the first and second zero-bias capacitances C J01 , C J02 set to the same values, with C J01 = C J02 . The junction voltage potential V J2 of the second pair 104 of pn junction structures J3, J4 is set to a fixed value V J2 = 0.8.

[0083] The Fig. 4g-j show graphical representations of the respective third harmonic power levels PH3 for the semiconductor device 100 as a function of the first and second transition step factors m1, m2 as a result of a simulation using, for example, the method as described above with reference to Fig. 2 and Fig. 3. In addition, the Fig. 4g-j shows the theoretical cancellation line (= the path of the theoretical optimal suppression of the third harmonic PH3 for low input power levels P IN ). More specifically, the Fig. 4g-j the simulated spurious third harmonic PH3 of the semiconductor device 100 with equal first and second zero-bias junction capacitance C J01 = C J02 at different input power levels P IN ( Fig. 4g P IN = -10 dBm; Fig. 4h P IN = 0 dBm and Fig. 4i P IN = +10 dBm) of the fundamental frequency RF signal (for example, using the circuit simulation tool described above). The trajectory of the theoretical optimal PH3 rejection according to the derivation described above (also referred to herein as the cancellation line) is represented by curve "A" ("grey" curve). At lower input power levels P INthe minimum third harmonic PH3 of the circuit simulation and the theoretical derivative (curve “A”) are in close agreement, with increasing input power levels P IN the deviation of the minimum third harmonic PH3, resulting from the circuit simulation and from the theoretical optimal suppression (curve “A”), is somewhat more pronounced, but remains moderate for the input powers investigated and up to 20 dBm.

[0084] It can be seen that the irregular features of the isolines in the Fig. 4g-j, and even the appearance of separated isoline regions near the cancellation line in the contour plots are due to the algorithm used to generate the contour plots from a simulation data set in which the simulation data are available only for a finite number of simulated m1, m2 combinations located in a regular rectangular mesh.

[0085] The change of the optimal transition step factor with input power is also Fig. 4j, which shows the simulated PH3 power level depending on the transition step factor m2 for different input powers P IN (-10 dBm, 0 dBm, 10 dBm and 20 dBm). The transition step factor m1 is kept fixed at m1 = 0.25, where C J01 =C j02 The power levels are normalized to the local maximum at m1=m2=0.25 (reference case) to facilitate comparison of the results. Therefore, it can be pointed out that the suppression of the generation of the spurious third harmonic can be optimized for an expected predetermined input power level. For this purpose, it may also be possible to deliberately deviate from curve "A", which is suitable for small input power levels P INanalytically derived, and to arrange the pn junction structures with respective junction step factors designed to reduce the generation of the spurious third harmonic with respect to the reference case by a desired amount for a predetermined input level P IN to suppress, using the results from the simulation described above by the circuit simulation tool.

[0086] Furthermore, it may only be necessary to reproduce the optimal transition step factors to a certain degree of accuracy depending on the desired suppression level. For example, if the power level of the spurious third harmonic is to be suppressed by 10 dB compared to the reference case, a deviation of ±0.05 for the transition step factors m2 may be acceptable. To achieve a higher suppression level, a smaller deviation of ±0.03 or even ±0.02 may be desirable. Similar considerations apply to the transition step factor m1, or more generally, m i .

[0087] The relationship between the simulated PH3 values ​​and the optimum value (curve “A”) also applies to non-equal zero-bias capacitances C J0,1 , C J0,2 , which lead to an increasing eccentricity of the ellipses, as with respect to Fig. 4a is described.

[0088] In the following, the mathematical derivation of the optimal C(V) parameters for suppressing third harmonic generation is extended to three (n = 3) pairs 102, 104, 106 of anti-serially connected pn junction structures J1, J2 and J3, J4 and J5, J6 and further generalized for n pairs.

[0089] Using the same steps as described above, the conditions under which third-harmonic generation is canceled for three pairs of anti-series connected pn junctions can be determined. In this case, the quadratic coefficient of the series expansion of the C(V) behavior is as follows: κ2=−18(r1=1CJ0.3+1CJ0.2+1CJ0.1)4[1CJ0.13VJ12(m12−12m1) +1CJ0.23VJ22(m22−12m2)+1CJ0.33VJ32(m32−12m3)]=0 which can be further simplified as follows: 1CJ0.13VJ12(m1−14)2+1CJ0.23VJ22(m2−14)2+1CJ0.33VJ32(m3−14)2=116(1CJ0.13VJ12+1CJ0.23VJ22+1CJ0.33VJ32+)

[0090] This is a three-dimensional ellipsoid with the following general shape: (m1−m0.1)2r12+(m2−m0.2)2r22+(m3−m0.3)2r32=1 with the center m0,i=14 for i ∈ {1, ..., n} and the radii: r1=14(CJ0,1CJ0,2)3(VJ1VJ2)2+(CJ0,1CJ0,3)3(VJ1VJ2)2+1 r2=14(CJ0,2CJ0,1)3(VJ2VJ1)2+(CJ0,2CJ0,3)3(VJ2VJ3)2+1 r3=14(CJ0,3CJ0,1)3(VJ3VJ1)2+(CJ0,3CJ0,2)3(VJ3VJ2)2+1

[0091] Generalization for pn junction pairs: All combinations of m i , with i ∈ {1,...,n}, lying on the following n-dimensional ellipsoid, lead to a cancellation of the third harmonic. ∑i=1n(mi−14ri)2=1 where the radii of the ellipsoid r i with i ∈ {1, ..., n} are defined as: ri=14∑j=1n(CJ0,iCJ0,j)3(VJiVJj)2

[0092] In the following, different aspects of the present concept of the semiconductor device 100, as can be derived from the above evaluations, are described in detail, wherein the semiconductor device 100 comprises n (at least two) pairs 102, 104 (...) of anti-serially connected pn junction structures J1, J2, J3, J4 (...) with set junction step factors m1 to m n for providing at least reduced or minimal generation of a disturbing odd harmonic, for example a third harmonic, for a predetermined input power level P IN.

[0093] As can be seen from the above evaluations for the semiconductor device 100 with n pairs 102, 104 (...) of anti-serially connected pn junction structures J1, J2 and J3, J4 (...) with set junction step factors m1 to m n is derivable, each of the first to n-th parameters “a1 to a n“ on the n zero-bias capacitances C J0,1 -C J0,n and on the n junction voltage potentials V J1 -V Jn the n pairs of pn junction structures.

[0094] As can be deduced from the above evaluations for the semiconductor device 100, the first to n-th parameters “a1 to a n “ the following equation: ai=14∑j=1n(CJ0,iCJ0,j)3(VJiVJj)2.

[0095] Based on the above evaluations for the semiconductor device 100 and with reference to the Fig. 4g-j show the simulated plots of the respective third harmonic power levels PH3 for the semiconductor device 100 as a function of the first and second transition step factors m1, m2 and the theoretical cancellation lines together with the general derivation above that the values ​​for the first to “n-th” transition step factors m1 to m ncan be adjusted to result in a third-order crossover point IP3 of at least 50 dBm, 55 dBm, or even 60 dBm. For example, a third-order crossover point IP3 of 50 dBm corresponds to a PH3 power level of -70 dBm at 10 dBm input power. Here, one of the crossover step factors, for example, m1, can be set to m1 < 0.50, preferably m1 ≤ 0.48, the latter being advantageous from a manufacturing standpoint, as already mentioned above.

[0096] According to an embodiment of the semiconductor device 100, at least two of the first to n-th transition step factors m1 to m n different. More specifically, the n" pairs of pn junctions comprise at least a first pair 102 with a pn junction of the first type with step factor m1 and a second pair 104 with a pn junction of the second type with step factor m2.

[0097] According to one embodiment of the semiconductor device 100, for Cj01 = Cj02, and Vj1 = Vj2, pn junction structures of the first type J1, J2 are arranged to have a first junction step factor m1 = 0.33 ± 0.10, and the pn junction structures of the second type J3, J4 are arranged to have a second junction step factor m2, with m2 = 0.59 ± 0.03. The latter may represent a transition with a nearly linear gradient.

[0098] Based on the above evaluations for some embodiments of the semiconductor device 100, with i ∈ {1, 2}, the parameters a1 and a2 (= radii r1, r2) of the ellipse equation correspond to the following equations: a1=14(CJ0,1CJ0,2)3(VJ1VJ2)2+1 and a2=14(CJ0,2CJ0,1)3(VJ2VJ1)2+1.

[0099] According to a further embodiment, the pn junction structures J1, J2 and J3, J4 of the first and second types / pairs 102, 104 are arranged to have a ratio of the zero-bias capacitances C J0-1 , C J0-2 that meets the following condition: 14 <CJ0,1CJ0,2<4.

[0100] According to a further embodiment, the i-th type pn junction structure forms an i-th type diode structure with an anode region and a cathode region. Furthermore, the semiconductor device 100 may include a first connection terminal 107 and a second connection terminal 108, with the "n" pairs 102, 104 (...) of pn junction structures J1-J4 (...) connected between the first and second terminals 107, 108.

[0101] According to a further embodiment, the "n" pairs 102, 104 (...) of pn junction structures J1-J4 (...) are arranged in a stacked configuration in a semiconductor substrate. According to a further embodiment, differently doped semiconductor regions of the pn junction structures extend vertically into the semiconductor substrate with respect to a main surface region of the semiconductor substrate, wherein the main portion of the surface of the metallurgical pn junction is a planar pn junction extending parallel to a main surface region of the semiconductor substrate. According to a further embodiment, the two pn junction structures of the i-th pair can be arranged together in a stacked configuration in the semiconductor substrate.According to a further embodiment, one of the two pn junction structures of the first pair can be arranged in the semiconductor substrate in a stacked configuration with one of the two pn junction structures of the second pair. According to a further embodiment, the stacked configuration can comprise an npn structure with a floating base region in the semiconductor substrate.

[0102] Fig. 5a shows a schematic cross-sectional view of the semiconductor device 100 according to an embodiment, which may include, for example, the four anti-serially connected pn junction structures J1, J2, J3, J4 according to an embodiment (see, for example, Fig. 1a), wherein the first stack or the first pair 102 comprises the pn junction structures of the first type J1, J2 (i = 1), and wherein the second stack or the second pair 104 comprises the pn junction structures of the second type J3, J4 (i = 2).

[0103] As in Fig. 5a, the semiconductor device 100 comprises the semiconductor substrate 120 having a first main surface portion 120a and a second main surface portion 120b on opposite main sides of the semiconductor substrate 120.

[0104] The following exemplary description of the different layers and regions of the semiconductor substrate 120 extends substantially from the second main surface portion 120b to the first main surface portion 120a of the semiconductor substrate 120. The different regions and structures in the semiconductor substrate 120 may, for example, be formed during the so-called FEOL (front end of line) process stage.

[0105] The semiconductor substrate 120 may include a low-resistance n-type substrate 120-1. A p-type semiconductor layer 120-2 is arranged on the n-type substrate 120-1. The p-type semiconductor layer 120-2 (e.g., p-epi layer 120-2) may be epitaxially deposited on the n-type substrate 120-1. The p-type semiconductor layer 120-2 includes a buried p-type semiconductor layer 120-3 (p-buried layer 120-3). The buried p-type semiconductor layer 120-3 may be formed, for example, in the form of a blanket implantation (unmasked implantation) of a p-type dopant in the semiconductor layer 120-2.

[0106] Another p-type layer 120-4 (e.g., p-epi layer 120-4) is arranged on the p-type layer 120-2 with the buried p-type layer 120-3. The p-type semiconductor layer 120-4 can be epitaxially deposited on the p-type layer 120-2. Alternatively, the layer 120-4 can also be implemented as an i-type layer (i.e., an intrinsic and not intentionally doped layer).

[0107] A p-type well region 120-5 (p-well 120-5) may be arranged in the second epitaxial layer 120-4. The p-type well region 120-5 may be formed after performing a LOCOS oxidation of the main surface area 120a of the p-type layer 120-4 of the semiconductor substrate 120 and by performing a blanket implantation step. Based on this approach, no lithographic resist mask would be required on the surface area 120a of the p-type layer 120-4, but a self-aligned implantation process could be performed due to the LOCOS oxidation on the surface 120a. A LOCOS process (LOCOS = LOCal Oxidation of Silicon) is a microfabrication process in which silicon dioxide is formed in selected areas on a silicon wafer, i.e.the semiconductor substrate 120, with the Si-SiO 2 interface at a lower point or level than the rest of the silicon main surface area 120a. Of course, a p-well 102-5 can also be formed using a lithographic process that is well known in the art.

[0108] As in Fig. 5a, the pn junction structures J1, J3 and the pn junction structures J2, J4 may be arranged in separate semiconductor areas 122, 124 of the semiconductor substrate 120, wherein the separate areas 122, 124 may be achieved by means of so-called deep isolation trenches 130 that laterally delimit and / or laterally surround the semiconductor regions 122, 124 with the pn junction structures J1, J3 and J2, J4. The deep isolation trenches 130 may, for example, be formed in the semiconductor substrate 120 by means of RIE process steps (RIE = reactive ion etching), wherein the resulting trenches 130 are filled with an oxide material 134, e.g. B. a SiO2 liner, using a trench liner oxidation process and can be filled using a semiconductor material 132, e.g. polysilicon.

[0109] The semiconductor device 100 further includes highly doped n-type contact regions 120-7 in the form of implantation regions adjacent to the surface of the p-type well 120-5. An n-type contact region 120-7 may also be considered simply as a shallow n-type region 120-7 or as an emitter region in some embodiments. The n-type contact regions 120-7 may be formed using an n-contact implantation process step, e.g., using a blanket implantation, which may be self-aligned using the LOCOS process (described above), thus eliminating the need for a lithographic resist mask.

[0110] As a further (e.g., final) process step of the FEOL process for processing the semiconductor substrate 120, an oxide material 128 may be deposited on the first main surface 120a of the semiconductor substrate 120. The semiconductor device 100 may further comprise a contact and metallization layer stack 140 (BEOL stack, BEOL = back end of line) on the first main surface 120a of the semiconductor substrate 120 to form interconnections 110 (e.g., contact plugs or vias) and interconnect layers 107, 108 for the semiconductor device(s) 100 and optionally for further circuit elements (not included in Fig. 5a) in the semiconductor substrate 120. The contact structures and (patterned) metallization layers of the metallization stack 140 may be formed using BEOL process steps. Finally, the semiconductor devices 100 may be packaged and separated (singulated) if a plurality of semiconductor devices 100 are manufactured in the semiconductor substrate 120, e.g., a semiconductor wafer 120. One example is a chip-size packaging process, which includes, for example, forming electrodes (or pads) as the top layer of the metallization stack 140 and a singulation process.

[0111] As in Fig. As shown in Figure 5a, the n-type contact region 120-7 (= cathode region) and the p-type well region 120-5 (= anode region) form the first-type pn junction structure J1 and J2, respectively, in the different semiconductor substrate areas 122 and 124. Furthermore, the buried p-type layer 120-3 (= anode region) and the n-type substrate 120-1 (= cathode region) form the second-type pn junction structures J3 and J4, respectively, in the separate semiconductor regions 122, 124 of the semiconductor substrate 120.

[0112] Fig. 5b shows a schematic calculated representation of an exemplary doping profile of the semiconductor device 100 of Fig. 5a, where different doping concentrations in the p-type well 120-5 can be achieved by different implantation doses, which are labeled “36” to “42”. The representation of Fig. 5b further includes an exemplary indication of the approximate extent of the different layers and / or regions of the semiconductor substrate 120 of Fig. 5a. The metallurgical junction between n-type region 120-7 and p-type region 120-5 falls within the downward slope of the p-type implant profile of region 120-5. With a sufficiently steep slope of the n-type implant of n-type region 120-7, the C(V) properties of the pn junction formed by regions 120-5 and 120-7 can exhibit a hyper-abrupt character and thus exhibit a step factor m1 > 0.5.

[0113] Fig. 6a shows a schematic cross-sectional view of the semiconductor device 100 along the section line ABCD in the schematic plan view through the semiconductor device 100 of Fig. 6b. The semiconductor device 100 comprises, for example, the four anti-serially connected pn junction structures J1, J2, J3, J4 according to one embodiment (see, for example, Fig. 1a). The pn junction structures J1, J3 (vertical device 1) may comprise a first npn structure with a first floating base region in the semiconductor substrate 120, wherein the pn junction structures J2, J4 may comprise a second npn structure with a second floating base region in the semiconductor substrate 120. The floating base regions are each formed by the p-type portions between the n-type substrate 120 and the n-type contact region 120-7, e.g., by p-type regions 120-2 to 120-5.

[0114] As regards Fig. 5a-b, with respect to the first and second pair 102, 104 of pn junction structures J1, J2 and J3, J4 connected in anti-series, the first type pn junction structures J1 and J2 may have (substantially) the same layout and doping profile and have the step factor m1, wherein the second type pn junction structures J3 and J4 may also have (substantially) the same layout and doping profile and have the second junction step factor m2.

[0115] According to one embodiment, the semiconductor device forms, for example, a discrete ESD device (ESD = electrostatic discharge) with a TVS functionality.

[0116] According to further embodiments, the semiconductor device 100 may comprise n (at least two) pairs of anti-serially connected pn junction structures 102, 104 (...) with adjusted junction step factors m1, m2 ... m nwherein (at least) one of the n pairs 102, 104 (...) of the pn junction structures J1-J4 (...) comprises a "composite" diode structure to adapt and maintain a desired breakdown voltage behavior of the device 100 and to provide at least reduced or minimal generation of spurious odd harmonics, for example, third harmonics. The device 100 can be used, for example, for TVS (Transient Voltage Suppressor) devices.

[0117] Fig. Fig. 7a shows a schematic diagram of the semiconductor device 100 with n = 2 pairs 102, 104 of anti-serially connected pn-junction structures, wherein (at least) one pair 102 of the at least two pairs 102, 104 of pn-junction structures is arranged to have a junction type described herein as a compound pn-junction structure (compound diode structure) and described with reference to Fig. 7b is described in more detail below.

[0118] Fig. 7b shows only the first pair 102 of the Fig. 7a, which is formed as a pair of two composite pn junction structures 102-1, 102-2. The first composite pn junction structure 102-1 has a first partial pn junction structure J 11 and a second partial pn junction structure J 12and the second composite pn junction structure 102-2 has a first partial pn junction structure J 21 and a second partial pn junction structure J 22 That is, the first pair 102 of Fig. 7a and Fig. 7b is formed by a pair of anti-serially connected composite pn junction structures 102-1, 102-2, each of which comprises a parallel circuit of a first partial pn junction structure J 11 , J 21 and a second partial pn junction structure J 12 , J 22 The first partial pn junction structures J 11 , J 21 have a first partial transition step factor m 11 , a first partial transition voltage potential V J11 and a first partial zero-bias capacitance C J011 where the second partial pn junction structures J 12 , J 22 a second partial transition step factor m12 , a second partial transition voltage potential V J12 and a second partial zero-bias capacitance C J012 which differ, for example, from the first partial transition step factor m 11 , the first partial transition voltage potential V J11 and the first partial zero-bias capacitance C J011 Based on a combination of the first and second partial transition step factor m 11 , m 12 This results in a first effective junction step factor m1 of the respective composite pn junction structure 102-1 and 102-2. This means that the composite pn junction structures 102-1 and 102-2 behave like pn junction structures with an effective junction step factor m1, an effective junction potential V J1 and an effective zero-bias junction capacitance C J01This effective behavior of the composite pn-junction structure 102-1 as a simple pn-junction structure is shown in Fig. 7b by corresponding the composite pn junction structure 102-1 to the pn junction structure J1 and the composite pn junction structure 102-2 to the pn junction structure J2. Accordingly, the voltage-dependent capacitance characteristics of the composite pn junction structures can in many cases be satisfactorily described or modeled by the above expression A1, where m i is taken as the effective (combined) transition step factor, and similarly for the transition potential V Ji and the zero-bias junction capacitance C J0i .

[0119] In other words, the semiconductor device 100 as shown in Fig. 7a and Fig. 7b, according to one embodiment, a first parallel circuit 102-1 of the first partial pn junction structure J 11 and the second partial pn junction structure J 12 and a second parallel circuit 102-2 of the first partial pn junction structure J 21 and the second partial pn junction structure J 22 wherein the first and second parallel circuits 102-1, 102-2 are connected in anti-serial. The anti-serial first and second parallel circuits 102-1, 102-2 form the first pair 102 of the pn junction structures J1, J2, which is connected in series with the second pair 104 of the pn junction structures J3, J4, as shown in Fig. 7a is specified.

[0120] That is, according to embodiments of the semiconductor device 100, at least one pair 102 of the n pairs 102, 104 (...) of pn junction structures J1-J4 (...) may be arranged to form a composite pn junction structure 102, as shown in Fig. 7b, with a first partial pn junction structure J 11 , J 21 and a second partial pn junction structure J 12 , J 22 , which are connected in parallel, with the first partial pn-junction structures J 11 , J 21 a first partial transition step factor m 11 and wherein the second partial pn junction structures J 12 , J 22 a second partial transition step factor m 12 which differs from the first partial transition step factor m 11The resulting effective junction step factor m1 of the composite pn junction structure 120 is based on a combination of the first and second partial junction step factors m 11 , m 12 .

[0121] In order to better understand the present concept in the form of the described implementations and embodiments of the semiconductor device 100 according to Fig. 7a and Fig. 7b, the following comments refer to the Fig. 8a-c refer to the exemplary technical analysis in the field of semiconductor devices, for example in the field of discrete ESD protection devices or TVS devices, by the applicant and the resulting technical findings and conclusions.

[0122] As in Fig. As shown in Figure 7a, the semiconductor device 100 can be realized with the resulting junction step factors m1, m2 of the first 102 and second pair 104 of pn junction structures with a high degree of freedom. In particular, a pn junction structure with a high degree of freedom of breakdown voltage tuning with a step factor m≥0.5 can be realized as a composite pn junction structure and used for the semiconductor device 100 of some embodiments.

[0123] With conventional semiconductor technologies, it is difficult to realize hyper-abrupt junctions with low breakdown voltages below 25 V or even below 16 V or 12 V with a controllable step factor m ≥ 0.5. Some embodiments provide the semiconductor device 100 with both desired properties, i.e., with a low breakdown voltage and a controllable step factor of at least 0.5. This is due to the fact that conventionally used process steps in semiconductor technology, such as implantation and diffusion, result in dopant profiles that exhibit some stepping in a narrow region around the metallurgical junction. The space charge region, which determines the capacitance / voltage behavior and the breakdown voltage of a pn junction, extends around the metallurgical junction.At a low breakdown voltage, doping concentrations are high and the extent of the space-charge region is small. As the breakdown voltage increases, the doping concentration on one or both sides of the metallurgical junction decreases, and the width of the space-charge region increases. Due to the inevitable stepping near the metallurgical junction, low breakdown voltage junctions in practice see a more or less stepped profile instead of the desired abrupt or hyper-abrupt doping profile. Therefore, the combination of low breakdown voltage and a step factor m ≥ 0.5 is difficult to realize with semiconductor processes conventionally used in the mass production of semiconductor devices and circuits.

[0124] In summary, higher doping levels lead to a less extended space charge region (= depletion region) and thus to a lower breakdown voltage V bd Furthermore, a resulting linearly stepped transition behavior leads to a lower step factor m.

[0125] A high or higher step factor m ≥ 0.5 requires a more (or hyper-)abrupt doping profile. At a lower doping level on one side of a metallurgical junction, the depletion layer extends further into this less doped region. Therefore, the depletion layer is not confined to a narrow area around the metallurgical junction, as is the case with higher doping levels, where the doping profile typically exhibits a more or less linear step. Since the depletion region extends beyond this stepped region near the metallurgical junction in the case of a lower doping level, the C(V) characteristics of a less doped junction can be more easily adapted to a step factor m ≥ 0.5. At the same time, a lower doping level leads to a higher breakdown voltage V bd .

[0126] Therefore, the combination of low breakdown voltage and a step factor m ≥ 0.5 is difficult to achieve with conventional technology.

[0127] To overcome this limitation, the embodiments as in Fig. 7a and Fig. 7b, introduces a concept to obtain a junction (pn junction structure) with both desired properties, i.e., a predetermined low breakdown voltage of not more than 25 V and a predetermined step factor above 0.5, by dividing the junction into two areas, i.e., partial pn junction structures, which together form a composite pn junction structure: (1) an active area with a higher well implantation dose, which becomes part of the pn junction J 11 , J 21 with a low predetermined breakdown voltage and a step factor m 11 < 0.5, and (2) another active area with a lower well implantation dose, which becomes part of the pn junction J 12 , J 22 with a breakdown voltage higher than the predetermined one and a step factor m 12 > 0.5 leads.

[0128] The overall behavior of this composite pn-junction 102-1 or 102-2 shows a breakdown voltage determined by the higher well doping, and the step factor of the capacitance / voltage characteristics is determined by the parallel connection in the two branches of the first and second partial pn-junction structure J 11 , J 12 or J 21 , J 22 certainly.

[0129] By setting (1) the step factors m 11 , m 12 in the two regions of the first and second partial pn junction structure J 11 , J 12 and J 21 , J 22(by well implantation dose and energy as well as by further diffusion steps) and by adjusting (2) the area ratio of the two regions of the first and second partial pn junction structure J 11 , J 12 and J 21 , J 22 With different well implantation, the resulting effective step factor m1 of the resulting composite junction structure 102-1, 102-2 can be set to a target value that is close to the value that results in minimized third harmonic (H3) generation. In some embodiments, a zero-bias capacitance (C J0 ) by J 11 and J 21 (as well as by J 12 or J 22,) be arranged to be equal, from the perspective of forming a symmetrical device 100 for further suppressing the generation of even (e.g., second) harmonics. Similar considerations apply to the junction voltage potentials (V J0 ) of the partial pn junction structures J 11 and J 21 (as well as J 12 or J 22 ) as well as for the area ratios of the partial pn junction structures in each of the composite structures 102-1 and 102-2 forming the pair 102 of composite pn junction structures. The concept described above realizes a pair of composite pn junctions 102-1 and 102-2 in which the breakdown voltage and net step factor can be controlled over a much wider range of parameters through technology and physical design or layout adjustments.

[0130] Fig. Figure 8a shows a schematic simulated representation of the resulting junction step factor m1 as a function of the doping concentration, based on different implantation doses. More specifically, the simulated capacitance / voltage characteristics of the pn junction between a shallow contact region with high n-doping and the p-doped well region are shown in Fig. 8a for the doping profiles shown in Fig. 5b (described in more detail above) for the semiconductor region 120-4, which has regions 120-7 and 120-5 (see, for example, Fig. 5a), where like numbers (36-42) denote corresponding doping profiles. This figure shows that with low implantation doses for the p-well, hyper-abrupt transitions with m > 0.5 can be obtained.

[0131] Fig. Figure 8b shows a schematic simulated representation of the resulting breakdown voltage as a function of the doping concentration, based on different implantation doses and doping profiles, as shown by the same numbers as in Fig. 8a and Fig. 5b. However, as explained above, the breakdown voltage of the junction with the lowest p-well doses and highest step factors tends to have high breakdown voltages, as shown in Fig. 8b. In the case of this simulation example, it is shown that if a step factor between 0.5 and 0.6 is required for minimum third-harmonic generation, the junction would have a breakdown voltage of 40 V or higher without using a composite pn junction structure as explained above.

[0132] Fig. Figure 8c shows the resulting combined junction step factor m1 of the composite pn junction structure 102-1 (or 102-2) as a function of the area ratio between the active areas of the first and second partial pn junction structure J 11 and J 12 (or J 21 and J 22 ) of the composite pn junction structure 102-1 (102-2), based on two adjusted partial junction step factors m 11 (by J 11 or J 21 ) and m 12 (by J 12 or J 22 ). The doping profiles of the first and second partial pn-junction structures in this case correspond to the numbers 37 and 41, which are shown in Fig. 5b (see also corresponding figures in Fig. 8a and Fig. 8b). As discussed above, the junction breakdown voltage with the lowest p-well doses and highest step factors tends to exhibit high breakdown voltages, as shown in Fig. 8b. The relative area contribution can be easily controlled by the physical design (layout) of the device.

[0133] More generally, the composite junction 102-1 described above can be described as 120-i, which is placed as the pn junction structure of the i-th type. Therefore, according to one embodiment, the first partial pn junction structure is arranged to have a first partial junction step factor m i1 > 0.5, and wherein the second partial pn junction structure is arranged to have a second partial junction step factor m i2 < m i1 to have, for example, m i1 between 0.30 and 0.5.

[0134] According to one embodiment, the first and second partial pn junction structures J 11 , J 21 , and J 12 , J 22arranged in a semiconductor substrate, wherein the combination is proportional to an area ratio between an active area parallel to a first main surface of the semiconductor substrate of the first and second partial pn junction structure J 11 and J 12 the composite pn junction structure 102-1 and J 21 and J 22 of the composite pn junction structure 102-2. According to one embodiment, the first and second partial pn junction structures J 11 , J 12 the first composite pn junction structure 102-1 and the first and second partial pn junction structures J 21 , J 22The second composite pn junction structure 102-2 may be arranged together in a laterally isolated common region of the semiconductor substrate. According to one embodiment, the first and second partial pn junction structures extend vertically into the semiconductor substrate in a depth direction relative to a first main surface of the semiconductor substrate.

[0135] Fig. 9a and Fig. 9d show schematic cross-sectional views of further exemplary implementations of the semiconductor device 100 having a pair of composite pn junction structures. Fig. Figure 9b shows a schematic simulated representation of the different exemplary doping profiles, which are also shown in Fig. 5b and are now for the semiconductor device of Fig. 9a can be used. Fig. Figure 9c shows a schematic plan view through the semiconductor device of Fig. 9a in-plane through the composite type pn junction structures showing, for example, the “active” areas of the first and second partial anode regions 120-5, 120-6 of the composite pn junction structures J1 and J2.

[0136] In the figures and the application, identical elements and elements with the same functionality and / or the same technical or physical effect are provided with the same reference numerals or identified with the same name. Thus, in the following description of the embodiments of the semiconductor device 100 in the Fig. 9a and Fig. 9d a focus on the respective differences and adaptations between the different implementations of the semiconductor device 100 compared, for example, to the embodiments of the semiconductor device 100 in the Fig. 5a-b and Fig. 6a-b.

[0137] The Fig. 9a and Fig. 9d show different cross-sectional views of the semiconductor device 100, which comprises, for example, the two pairs of anti-serially connected pn junction structures J1, J2 (= first pair 102) and J3, J4 (= second pair 104) according to an embodiment, wherein the first pair 102 comprises the composite pn junction structures 102-1, 102-2 and wherein the second pair 104 comprises the pn junction structures J3, J4 (see, for example, Fig. 7a) to set and maintain, for example, a desired TVS (transient voltage suppressor) behavior of the semiconductor device 100 with respect to a breakdown voltage and transition step factors thereof.

[0138] The first composite pn-junction structure 102-1 has the first partial pn-junction structure J 11 with the first partial transition step factor m 11 and the second partial pn junction structure J 12with the second partial transition step factor m 12 The second composite pn junction structure 102-2 has the third partial pn junction structure J 21 (essentially the same structure as J 11 , also with respect to the zero-bias capacitance C J0 and the transition potential V J0 ), which also determines the partial transition step factor m 11 and the partial pn junction structure J 22 on (essentially the same structure as J 12 , also with respect to the zero-bias capacitance C J0 and the transition potential V J0 ), which determines the partial transition step factor m 12 The resulting transition step factor m1 of the first and second composite pn junction structures 102-1, 102-2 is based on a combination of the first and second partial transition step factors m 11 , m 12 .

[0139] As in Fig. As shown in Figure 9a, the first composite pn junction structure 102-1 may be implemented using two different implantation areas 120-5, 120-6 in the substrate region 122. Thus, the n-type contact region 120-7 in the substrate region 122 is embedded in the adjacent implantation areas 120-5, 120-6. The second composite pn junction structure 102-2 may be implemented using two different implantation areas 120-5, 120-6 in the substrate region 124. Thus, the further n-type contact region 120-7 in the substrate region 124 is embedded in the further adjacent implantation areas 120-5, 120-6.

[0140] As in Fig. As shown in Figure 9a, the partial pn junction structures J 11 , J 12 in the semiconductor surface 122 of the semiconductor substrate 120 (as adjacent partial pn junction structures J 11 , J 12), whereby the partial pn junction structures J 21 , J 22 in the further semiconductor area 124 of the semiconductor substrate 120 (as adjacent partial pn junction structures J 21 , J 22 ). The separated areas 122, 124 can be achieved by means of so-called deep isolation trenches 130, which laterally delimit and / or laterally surround the semiconductor regions 122, 124. Furthermore, the buried p-type layer 120-3 (= anode region) and the low-resistance n-type substrate 121 (= cathode region) form the second-type pn junction structures J3 and J4, respectively, in the separated semiconductor regions 122, 124 of the semiconductor substrate 120.

[0141] Fig. 9b shows a schematic simulated representation of different exemplary doping profiles for the semiconductor device 100 of Fig. 9a. The different doping concentrations of the implantation areas 120-5, 120-6 in the p-type layer 120-4 can be achieved using different implantation doses, which is Fig. 9b with "36" to "42". The illustration also includes an indication of the approximate extensions of the different layers and / or regions of the semiconductor substrate 120. As in Fig. As shown in Figure 9a, the first composite pn junction structure 102-1 with the first and second partial pn junction (diode) structures J 11 , J 12 two p-type well regions 120-5, 120-6. A doping concentration profile of the p-well 120-5 (A), for example, leads to the first partial transition step factor m 11 . A doping concentration profile of the p-well 120-6 (B), which may be lower than the doping concentration of the p-well 120-5 (A), leads to the second partial transition step factor m 12, e.g. with m 12 > m 11 . Based on the first and second partial transition step factor m 11 , m 12 an effective net step factor m1 of the composite transition 102-1 can be achieved.

[0142] Since higher doping levels lead to a less extended space charge region (= depletion region) and thus to a lower breakdown voltage V bd , a resulting more linearly stepped junction behavior leads to a lower step factor m. A high or higher step factor m requires a more (or hyper-) abrupt doping profile. However, there are practical difficulties in generating “ideal” abrupt profiles. Therefore, to form a pn junction structure with a step factor m ≥ 0.50, a broader space charge region with a lower doping level may be required. A lower doping level leads to a high or higher breakdown voltage Vbd .

[0143] The above evaluations regarding the schematic simulated representation of different exemplary doping profiles are correspondingly applicable to the second composite pn junction structure 102-2 of the first pair of pn junction structures 102 and the resulting effective net step factor m1.

[0144] Fig. 9c shows a schematic top view of a possible layout of the semiconductor device 100 of Fig. 9a, which shows the expansion of the "active" areas of the first partial anode region 120-5 (with the higher p-well doping implant) and the second partial anode region 120-6 (with the lower p-well doping implant) of the composite-type pn junction structure 102-1 and 102-2. The exemplary area ratio is approximately 40% of the first partial anode region 120-5 and 60% of the second partial anode region 120-6.

[0145] By optimizing the layout, the ratio of the areas defined by the lower and higher dopant concentration of the p-well regions 120-6, 120-5 can be adjusted to achieve the (optimal) target value of the junction step factor m1 > 0.5, e.g., m1 ∼ 0.55, while maintaining a breakdown voltage of no more than 25 V.

[0146] As in Fig. As shown in Figure 9d, the first pair of partial pn junction structures J 11 , J 12 be arranged in the semiconductor area 122 of the semiconductor substrate 120, wherein the second pair of partial pn junction structures J 21 , J 22 can be arranged in the further semiconductor area 124 of the semiconductor substrate 120. The separated areas 122, 124 can be achieved by means of so-called deep isolation trenches 130, which laterally delimit and / or laterally surround the semiconductor regions 122, 124.

[0147] As in Fig. As shown in Figure 9d, a p-type well region 120-5 (p-well 120-5) is arranged in the second p-type epitaxial layer 120-4 in the semiconductor regions 122 and 124, wherein the p-type well 120-5 only partially surrounds the highly doped n-type contact regions 120-7 in the p-type layer 120-4 of the semiconductor substrate 120. Thus, in the semiconductor region 122, the highly doped n-type contact regions 120-7 and the second p-type epitaxial layer 120-4 form the first partial pn junction structure J 11 , where the p-type well region 120-5 and highly doped n-type contact region 120-7 form the second partial pn junction structure J 12 form (as adjacent partial pn junction structures J 11 , J 12 ). Accordingly, in the semiconductor region 124, the highly doped n-type contact regions 120-7 and the second epitaxial p-type layer 120-4 form the third partial pn junction structure J 21, where the p-type well region 120-5 and the highly doped n-type contact region 120-7 form the fourth partial pn junction structure J 22 form (as adjacent partial pn junction structures J 21 , J 22 ). Thus, the first and third partial pn junction structures J 12 , J 21 For example, it does not have a p-type well region. As mentioned above, layer 120-4 can also be realized by an i-type layer (i.e., an intrinsic and not intentionally doped layer).

[0148] Alternatively, a doping profile in layer 120-4 may be adjusted to provide a predetermined step factor m 12 in a partial pn junction structure J11 or J12 by gradually adjusting the doping level during the epitaxial growth of layer 120-4. In other words, a hyper-abrupt transition behavior in partial pn junctions J 11 and J 12be realized by creating a depth dependence of the doping level in the epitaxial layer by controlling the gas flow of dopant source gas during epitaxial layer growth

[0149] Furthermore, the buried p-type layer 120-3 (= anode region) and the n-type substrate 121 (= cathode region) form the second type pn junction structures J3 and J4, respectively, in the separated semiconductor regions 122, 124 of the semiconductor substrate 120.

[0150] The p-type well region 120-5 (p-well 120-5) may be arranged in the second p-type epitaxial layer 120-4 by forming the required doping profile in the p-type semiconductor layer 120-4, for example, during epitaxial growth or by performing an implantation step.

[0151] Fig. 9e shows a configuration of a composite pn junction structure 102-1 according to another embodiment. The composite pn junction structure 102-1 includes a pn junction between an n+ region 120-7 and a p-well region 120-5 and another adjacent voltage-dependent capacitance, which in this embodiment may be formed by an inversion charge layer 120-8 at an interface 135 between an oxide layer and a bulk or epi layer 120-4 of semiconductor material. The bulk semiconductor material or epi layer 120-4 may, for example, be p-doped or intrinsically (i.e., not intentionally doped). One electrode (corresponding to the cathode) of this voltage-dependent capacitance is formed by the inversion charge layer 120-8, which is caused by the presence of fixed oxide charges 136 at or near the semiconductor / oxide interface 135.Directly adjacent to the inversion charge layer 120-8, the volume of the semiconductor material is depleted with respect to mobile charges, as indicated by the depletion region 120-9 in . Fig. 9e, and the unused semiconductor material below the depleted zone forms the other electrode (corresponding to the anode) of the voltage-dependent capacitance. The depletion zone is shown in Fig. 9e by dashed lines 137, which schematically represent the boundaries of the depletion layer.

[0152] In some embodiments, the doping profile of the p-well 120-5 near the edges and the semiconductor / oxide interfaces 135 is adjusted such that an inversion charge layer 120-8 is also present in this region and an electrical connection is established between the n+ region 120-7 and the surrounding inversion charge layer 120-8.

[0153] The characteristics of the voltage-dependent capacitance formed due to the electron inversion charge layer 120-8 can be determined according to the above formula (A1), which defines a step factor, a zero-bias capacitance, and a junction potential also for this type of voltage-dependent capacitance. In this regard, the voltage-dependent capacitance formed due to the presence of the inversion charge layer 120-8, as described above, is also referred to as a partial pn junction structure J 11 , J 12 / J 21 , J 22 considered in the context of the composite pn junction structure 102-1, 102-2.

[0154] The effective step factor of the composite pn junction structure 102-1 according to this embodiment is a combination of the step factor of the pn junction and the step factor of the voltage-dependent capacitance formed due to the presence of the electron inversion charge layer 120-8. The relative contribution of both step factors can be adjusted by (1) the doping profiles of the respective regions defining the pn junction and the voltage-dependent capacitance 120-8 and (2) the relative areas of the pn junction and the voltage-dependent capacitance 120-8.

[0155] The voltage-dependent capacitance 120-8 may be surrounded by a channel stop region 120-10, which prevents regions outside the intended region in which the voltage-dependent capacitance 120-8 is formed from contributing to the voltage-dependent capacitance.

[0156] The breakdown voltage V bdof such a structure is determined by the pn junction structure between the n+ region and the p-well region.

[0157] Fig. Figure 9f shows yet another embodiment of the composite pn junction structure. The voltage-dependent capacitance of the embodiment shown in Fig. 9e is shown in Fig. 9f through an inversion layer 120-8 v formed on the vertical side walls of a deep isolation trench structure 130. The other features are those related to Fig. 9e are similar and are not repeated here.

[0158] Also described as part of the present disclosure is a method for manufacturing a semiconductor device comprising at least a first pair of pn junction structures of a first type and a second pair of pn junction structures of a second type. The method may include a design step of determining a first step factor for the pn junction structures of the first type and a second step factor of the pn junction structure of the second type, wherein the first step factor is different from the second step factor and wherein the first step factor is less than 0.50 and the second step factor is greater than 0.50, the step factors being determined to suppress generation of spurious third harmonics by the semiconductor device.

[0159] Examples of the present disclosure may provide a semiconductor device having the following features: “n” pairs of pn-junction structures, where n is an integer ≥ 2, where the i-th pair, with i ∈ {1, ..., n}, comprises two pn-junction structures of the i-th type, where the two pn-junction structures of the i-th type are connected anti-serially, wherein the pn junction structure of the i-th type is arranged to have an i-th junction step factor m i to show, wherein at least a first pair of the n pairs of pn junction structures is arranged to have a first junction step factor m1, with m1 ∉ {0.00, 0.50} and m1 < 0.50, and a second pair of the n pairs of pn junction structures is arranged to have a second junction step factor m2, with m2 ∉ {0.00, 0.50}, and wherein the transition step factors m1, m2 of the first and second pair of the n pairs of pn junction structures are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device having a signal power level (PH3) that is at least 10 dB lower than a reference signal power level (PH3) of the spurious third harmonic signal obtained for a reference case in which the first and second transition step factors m1, m2 are 0.25.

[0160] According to an example, the first to n-th transition stage factors m1 to m n within a tolerance range of ±0.05 the following ellipse equation: ∑i=1n(mi−0.25ai)2=1, with ∑i=1n(1ai)2=16, where the parameters a i based on a zero-bias capacitance C J0i and a transition voltage potential V Ji the pn junction structure of the i-th type.

[0161] Further examples may provide a semiconductor device having the following features: “n” pairs of pn-junction structures, where n is an integer ≥ 2, where the i-th pair, with i ∈ {1, ..., n}, comprises two pn-junction structures of the i-th type, where the two pn-junction structures of the i-th type are connected anti-serially, wherein the pn junction structure of the i-th type is arranged to have an i-th junction step factor m i to show, where the first to n-th transition step factor m1 to m n within a tolerance range of ±0.05 satisfy the following ellipse equation: ∑i=1n(mi−0.25ai)2=1, with ∑i=1n(1ai)2=16, wherein at least a first pair of the n pairs of pn junction structures is arranged to have a first junction step factor m1, with m1 ∉ {0.00, 0.50} and m1 < 0.50, and a second pair of the n pairs of pn junction structures is arranged to have a second junction step factor m2, with m2 ∉ {0, 00, 0.50}, wherein the parameters a i based on a zero-bias capacitance C J0i and a transition voltage potential V Ji the pn junction structure of the i-th type.

[0162] According to an exemplary embodiment, the first pair of the n pairs of pn junction structures is arranged to have the first junction step factor m1, where m1 ≤ 0.48.

[0163] According to the invention, the second pair of the n pairs of pn junction structures is arranged to have the second junction step factor m2, with m2 > 0.50.

[0164] According to an exemplary embodiment, each of the first to n-th parameters “a1 to a n “ based on the zero-bias capacitances C J0,1 -C J0,ni and on the n junction voltage potentials V J1 -V Jn the n pairs of pn junction structures.

[0165] According to an exemplary embodiment, the first to n-th parameters “a1 to a n “ the following equation: ai=14∑j=1n(CJ0,iCJ0,j)3(VJiVJi)2.

[0166] According to an exemplary embodiment, the values ​​for the first to “n-th” transition step factors are m1 to m n adjusted so that they lead to a third-order intersection point IP3 of at least 50dBm.

[0167] According to an exemplary embodiment, for n = 2, the pn junction structures of the first and second types are arranged to have a ratio of the zero-bias capacitances C J0-1 , C J0-2 that meets the following condition: 14 <CJ0,1CJ0,2<4.

[0168] According to an exemplary embodiment, the i-th type pn junction structure forms an i-th type diode structure having an anode region and a cathode region.

[0169] According to an exemplary embodiment, the semiconductor device may further comprise a first connection terminal and a second connection terminal, wherein the “n” pairs of pn junction structures are connected between the first and second terminals.

[0170] According to an exemplary embodiment, the “n” pairs of pn junction structures are arranged in a stacked configuration in a semiconductor substrate.

[0171] According to an exemplary embodiment, differently doped semiconductor regions of the pn junction structures extend vertically into the semiconductor substrate with respect to a main surface region of the semiconductor substrate, and wherein the main portion of the surface of the metallurgical pn junction is a planar pn junction extending parallel to a main surface region of the semiconductor substrate.

[0172] According to an exemplary embodiment, the two pn junction structures of the i-th pair are arranged together in a stacked configuration in the semiconductor substrate.

[0173] According to an exemplary embodiment, one of the two pn junction structures of a first pair of the n pairs of pn junction structures is arranged in the semiconductor substrate in a stacked configuration with one of the two pn junction structures of a second pair of the n pairs of pn junction structures.

[0174] According to an exemplary embodiment, the stacked configuration comprises an npn structure with a floating base region in the semiconductor substrate.

[0175] According to an exemplary embodiment, at least one pair of the n pairs of pn junction structures is arranged as a pair of two composite pn junction structures, each of which has a first partial pn junction structure and a second partial pn junction structure, wherein the first partial pn junction structure has a first partial junction step factor m i1and wherein the second partial pn junction structure has a second partial junction step factor m i2 which is determined by the first partial transition step factor m i1 is different, where the transition step factor m i the composite pn junction structure on a combination of the first and second partial junction step factor m i1 , m i2 based.

[0176] According to an exemplary embodiment, the first and second partial pn junction structures are arranged in a semiconductor substrate, wherein the combination depends proportionally on an area ratio between an active area parallel to a first main surface area of ​​the semiconductor substrate of the first and second partial pn junction structures.

[0177] According to an exemplary embodiment, the first and second partial pn junction structures of the first type pn junction structure and the first and second partial pn junction structures of the second type pn junction structure are arranged together in a laterally isolated common region of the semiconductor substrate.

[0178] According to an exemplary embodiment, the first partial pn junction structure is arranged to have a first partial junction step factor m i1 > 0.50, and wherein the second partial pn junction structure is arranged to have a second partial junction step factor m i2 between 0.30 and 0.5.

[0179] According to an exemplary embodiment, the first and second partial pn junction structures extend vertically into the semiconductor substrate in a depth direction with respect to a first main surface area of ​​the semiconductor substrate.

[0180] Although some aspects have been described in the context of a device, it is understood that such a description can also be considered a description of corresponding features of a method. Although some aspects have been described as features in the context of a method, it is understood that such a description can also be considered a description of corresponding features related to the functionality of a device.

[0181] In the foregoing Detailed Description, it will be appreciated that various features have been grouped into examples for the convenience of disclosure. This manner of disclosure should not be interpreted as reflecting an intent that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims demonstrate, inventive subject matter may lie in fewer than all of the features of a single disclosed example. Therefore, the following claims are hereby incorporated into the Detailed Description, with each claim being capable of standing on its own as a separate example.While each claim may stand alone as a separate example, it should be noted that while a dependent claim in the claims may refer to a particular combination with one or more other claims, other examples may include a combination of the dependent claim with the subject matter of any other dependent claim, or a combination of each feature with other dependent or independent claims. Such combinations are suggested herein unless it is stated that a particular combination is not intended. List of reference symbols 32 - 42 different implantation doses 100 semiconductor devices 102 first pairs of pn junction structures 102-1, 102-2 first, second parallel circuit / compound pn junction structures 104 second pair of pn junction structures 106 third pair of pn junction structures 107 first connection 108 second connection 110 intermediate connections 120 semiconductor substrate 120a, 120b first, second main surface section 120-1 n-type substrate 120-2 p-type semiconductor layer 120-3 buried p-type semiconductor layer 120-4 p-type semiconductor layer 120-5 p-type well region 120-6 p-type well region 120-7 n-type contact region 120-8 inversion charge layer 120-9 Impoverishment region 120-10 Canal Stop Region 122 separate semiconductor regions 124 separate semiconductor regions 130 deep isolation trenches 132 semiconductor fillers 134 Liner oxide 135 Semiconductor / Oxide Interface 136 fixed oxide charges 137 Limits of the impoverishment zone a1, a2 shape parameters (= radii r1, r2) of the ellipse (A), (B) higher, weaker p-well doping concentration C J01 , C J02 first, second zero-bias capacitances C J011 , C J012 first, second partial zero-bias capacitances J1, J2 pn junction structures of the first type J3, J4 pn junction structures of the second type J 11 , J 21 partial pn junction structures of the first type J 12 , J 22 partial pn junction structures of the second type m1, m2 first, second transition step factor m 11 , m 12 partial transition step factor S1, S2 first, second series circuit V bd Breakdown voltage V J1 , V J2 first, second transition voltage potential V J11 , V J12first, second partial transition voltage potential PH3 Signal power level of the disturbing third harmonic

Claims

[1] A semiconductor device (100) comprising: “n” pairs of pn-junction structures, where n is an integer ≥ 2, where the i-th pair, with i ∈ {1, ..., n}, comprises two pn-junction structures of the i-th type, where the two pn-junction structures of the i-th type are connected anti-serially, wherein the pn junction structure of the i-th type is designed to have an i-th junction step factor m i to show, wherein at least a first pair of the n pairs of pn junction structures is designed to have a first junction step factor m1, with m1 ∉ {0.00, 0.50} and m1 < 0.50, and a second pair of the n pairs of pn junction structures is designed to have a second junction step factor m2, with m2 ∉ {0.00, 0.50} and m2 > 0.50, and wherein the transition step factors m1, m2 of the first and second pair of the n pairs of pn junction structures are adjusted to result in a generation of a spurious third harmonic signal of the semiconductor device having a signal power level (PH3) that is at least 10 dB lower than a reference signal power level (PH3) of the spurious third harmonic signal obtained for a reference case in which the first and second transition step factors m1, m2 are equal to 0.

25. [2] A semiconductor device according to claim 1, wherein the first to n-th transition step factors m1 to m n within a tolerance range of ± 0.05 satisfy the following ellipse equation: ∑i=1n(mi−0.25ai)2=1, with ∑i=1n(1ai)2=16, where the parameters a i based on a zero-bias capacitance C J0,i and a transition voltage potential V Jithe pn junction structure of the i-th type. [3] A semiconductor device having the following features: “n” pairs of pn-junction structures, where n is an integer ≥ 2, where the i-th pair, with i ∈ {1, ..., n}, comprises two pn-junction structures of the i-th type, where the two pn-junction structures of the i-th type are connected anti-serially, wherein the pn junction structure of the i-th type is arranged to have an i-th junction step factor m i to show, where the first to n-th transition step factors m1 to m n within a tolerance range of ± 0.05 satisfy the following ellipse equation: ∑i=1n(mi−0.25ai)2=1, with ∑i=1n(1ai)2=16, wherein at least a first pair of the n pairs of pn junction structures is designed to have a first junction step factor m1, with m1 ∉ {0.00, 0.50} and m1 < 0.50, and a second pair of the n pairs of pn junction structures is designed to have a second junction step factor m2, with m2 ∉ {0, 00, 0.50} and m2 > 0.50, wherein the parameters a i based on a zero-bias capacitance C J0,i and a transition voltage potential V Ji the pn junction structure of the i-th type. [4] A semiconductor device according to claim 2 or 3, wherein each of the first to n-th parameters a1 to a n based on the zero-bias capacitances C J0,1 -C J0,ni and on the n-junction voltage potentials V J1 -V Jn of the n pairs of pn junction structures. [5] A semiconductor device according to any one of claims 2 to 4, wherein the first to n-th parameters a1 to a n satisfy the following equation: ai=14∑j=1n(CJ0,iCJ0,j)3(VJiVJi)2. [6] A semiconductor device according to any one of the preceding claims, wherein the first pair of the n pairs of pn junction structures is configured to have the first junction step factor m1, where m1 ≤ 0.

48. [7] A semiconductor device according to any one of the preceding claims, wherein the values for the first to n-th transition step factors are m1 to m n are adjusted to result in a third-order intersection point IP3 of at least 50 dBm. [8] A semiconductor device according to any one of claims 2 to 7, wherein for n = 2, the pn junction structures of the first and second types are configured to have a ratio of the zero-bias capacitances C J0,1 , C J0,2that meets the following condition: 14 <CJ0,1CJ0,2<4. [9] A semiconductor device according to any preceding claim, wherein the i-th type pn junction structure forms an i-th type diode structure having an anode region and a cathode region. [10] A semiconductor device according to any preceding claim, further comprising a first connection terminal and a second connection terminal, wherein the n pairs of pn junction structures are connected between the first and second terminals. [11] A semiconductor device according to claim 10, wherein the n pairs of pn junction structures are arranged in a stacked configuration in a semiconductor substrate. [12] A semiconductor device according to claim 11, wherein differently doped semiconductor regions of the pn junction structures extend vertically into the semiconductor substrate with respect to a main surface region of the semiconductor substrate, and wherein the main portion of the surface of the metallurgical pn junction is a planar pn junction extending parallel to a main surface region of the semiconductor substrate. [13] A semiconductor device according to claim 12, wherein the two pn junction structures of the i-th pair are arranged together in a stacked configuration in the semiconductor substrate. [14] A semiconductor device according to claim 12, wherein one of the two pn junction structures of a pair of the n pairs of pn junction structures is arranged in the semiconductor substrate in a stacked configuration with one of the two pn junction structures of another pair of the n pairs of pn junction structures. [15] A semiconductor device according to claim 13 or 14, wherein the stacked configuration comprises an npn structure having a floating base region in the semiconductor substrate. [16] A semiconductor device according to any one of the preceding claims, wherein at least one pair of the n pairs of pn junction structures is configured as a pair of two composite pn junction structures, each of which comprises a first partial pn junction structure and a second partial pn junction structure, wherein the first partial pn junction structure has a first partial junction step factor m i1 and wherein the second partial pn junction structure has a second partial junction step factor m i2 which differs from the first partial transition step factor m i1 differs, where the transition step factor m ithe composite pn junction structure on a combination of the first and second partial junction step factor m i1 , m i2 based. [17] A semiconductor device according to claim 16, wherein the first and second partial pn junction structures are arranged in a semiconductor substrate, the combination proportionally depending on an area ratio between an active area parallel to a first main surface region of the semiconductor substrate of the first and second partial pn junction structures. [18] A semiconductor device according to claim 16 or 17, wherein the first and second partial pn junction structures of the first type pn junction structure and the first and second partial pn junction structures of the second type pn junction structure are arranged together in a laterally isolated common region of the semiconductor substrate. [19] A semiconductor device according to any one of claims 16 to 18, wherein the first partial pn junction structure is configured to have a first partial junction step factor m i1 > 0.50, and wherein the second partial pn junction structure is designed to have a second partial junction step factor m i2 between 0.30 and 0.

5. [20] A semiconductor device according to any one of claims 16 to 19, wherein the first and second partial pn junction structures extend vertically into the semiconductor substrate in a depth direction with respect to a first main surface region of the semiconductor substrate.

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