Method for producing a transistor element with reduced lateral electric field

Abstract

Procedure with: Forming an isolation trench (403T) for laterally delimiting an active region containing a channel region along a lateral direction (400L); Forming a doped material (416) in the isolation trench (403T) such that an increased concentration of at least a first and second dopant species is provided laterally adjacent to the channel region; Forming a laterally graded dopant profile in a first edge region and / or a second opposite edge region (460E) of the channel region, wherein forming the laterally graded dopant profile comprises initiating a diffusion of the at least first and second dopant species; and After forming the laterally graded dopant profile, forming a gate electrode structure on the channel region such that the gate electrode structure at least partially overlaps with the first and second edge regions (460E).

Description

BACKGROUND1, AREA OF REVELATION

[0001] In general, the present disclosure relates to semiconductor devices and manufacturing techniques in which transistor elements are formed based on a very thin crystalline semiconductor material. 2. DESCRIPTION OF THE STATE OF THE ART

[0002] Great progress has been made in the field of semiconductor devices, achieved primarily by steadily reducing the critical dimensions of circuit elements in such semiconductor devices. In sophisticated semiconductor devices, a substantial portion of the circuit elements provided therein is based on CMOS technology, which in turn is based on corresponding field-effect transistors comprising a channel region whose conductivity is controlled by a suitable control voltage. The control voltage is typically applied using a suitable electrode structure, typically referred to as a gate electrode structure, comprising an electrode material separated from the semiconductor material of the channel region by a dielectric material.When operating such a field-effect transistor, the current flowing in the channel region from the source region to the drain region can thus be efficiently controlled by applying the control voltage to the gate electrode structure, wherein transistor properties, such as a threshold voltage or onset voltage, the forward current, and the like, depend on various component parameters.

[0003] In general, the continuous reduction of critical dimensions of field-effect transistors, particularly the length of the channel region, contributes to greater overall packaging density, whereby a certain degree of performance gain may be achieved with a reduction in transistor size. On the other hand, the continuous reduction of critical dimensions of field-effect transistors is fraught with major challenges that must be addressed in order not to offset the performance gains generally achieved by reducing critical feature sizes. For example, effective controllability of the channel region of the transistor elements depends significantly on the capacitive coupling of the gate electrode structure to the channel region, and this typically becomes more complex as the channel length of the transistors is reduced.Therefore, the thickness of the gate dielectric material must be appropriately adjusted to provide sufficient capacitive coupling while still ensuring a suitable dielectric strength with respect to the supply voltage and / or control voltage applied when operating the transistor element, if these voltages differ from each other. Therefore, in complex semiconductor devices, different types of gate electrode structures with different types and / or materials with different thicknesses are used to accommodate the overall device requirements, since transistor elements in a complex integrated circuit are typically designed for different purposes.For example, in certain logic paths of a more or less complex control circuit, an increased switching speed of the respective field-effect transistor is of great importance, requiring extremely small gate lengths in conjunction with specially adapted gate electrode structures. To avoid unnecessarily increasing overall power losses, for example, due to static and dynamic leakage currents, attempts are being made to design the corresponding transistors so that operation at moderately low supply voltages, approximately 1 V or even lower, is possible in complex, currently available semiconductor components.

[0004] In other component regions, an increased operating voltage may generally be required, for example, to provide suitable adaptation to signal processing based on external signals and / or based on signals provided by different component regions, which generally operate based on an increased supply voltage. For example, input / output regions of a complex integrated circuit often operate at increased supply voltages compared to an "internal" reduced supply voltage for complex digital circuit regions, with 2.5 to 3.3 V often being used as operating voltages. Due to these significantly different supply voltages and thus also gate voltages, a corresponding adaptation of certain transistor parameters, such as the thickness of the gate dielectric material and the like, must therefore be considered.

[0005] In the further reduction of critical dimensions aimed at improving overall performance, and in particular for providing increased packing density of such integrated circuits, various approaches have been developed, for example with a view to improving overall channel controllability. One promising approach consists in providing essentially completely depleted channel regions with reduced dopant concentration. For this purpose, a very thin semiconductor base material, such as a crystalline silicon material, a crystalline silicon / germanium material, and the like, with a very low dopant concentration or even as an intrinsic material is provided, thereby contributing to a reduction in scattering events and scattering centers typically associated with the incorporation of dopant species.Furthermore, a substantially complete depletion of the channel region can be achieved for a certain transistor state when essentially no conducting channel is required. In such sophisticated planar transistor configurations, the very thin semiconductor base material, which may have an initial thickness of 15 nm and significantly less, can be combined with a suitably designed gate electrode structure to obtain transistor elements with a channel length of approximately 30 nm and less. Furthermore, since the very reduced thickness of the semiconductor material may impose certain limitations on providing highly conducting drain and source regions, such regions are typically fabricated based on a raised drain and source architecture in which a suitably heavily in-situ doped semiconductor material is grown on the initial semiconductor material.

[0006] Although this basic transistor design in complex semiconductor devices can be extremely effective for transistor elements intended for critical signal paths, it is nevertheless evident that further reduction of the overall dimensions can cause severe reliability problems for transistor elements that have the same basic design, whereby an increased supply voltage must be applied in order to be compatible with the overall functional requirements for certain circuit areas, such as I / O (input / output) areas and the like.It has been recognized that corresponding reliability issues, i.e., degradation of device performance and / or premature failure of semiconductor devices, can be linked to high-energy carrier injection (HCI), a phenomenon that occurs at elevated supply voltages, where carriers injected in the source region attain sufficient energy to exceed the potential of the gate dielectric material. This means that, typically on the drain side, a certain amount of charge carriers can enter and potentially penetrate the gate dielectric material, significantly altering the overall transistor characteristics, such as threshold voltage, leakage current behavior, and the like.

[0007] In view of the situation described above, the present disclosure relates to techniques and semiconductor devices in which transistor elements are fabricated on the basis of a thin semiconductor base layer, wherein the effects of one or more of the problems identified above are avoided or at least reduced.

[0008] A field-effect transistor with exponentially increasing dopant concentration is known from US 5 841 170 A, semiconductor devices with regions lightly doped with arsenic and deeply and highly doped with phosphorus from US 2008 / 0 185 665 A1, and a method for sidewall diffusion doping of semiconductor regions with boron from Davari, B. et al.: A variable-size shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS. In: International Electron Devices Meeting, 1988, pp. 92-95. ISSN - 0163-1918. OVERVIEW OF THE INVENTION

[0009] According to the invention, a method according to claim 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The disclosure may be better understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals indicate like elements and in which: Fig. 1A-1C schematically show cross-sectional views of a semiconductor device in an early manufacturing stage, wherein dopant species are incorporated into a thin semiconductor layer based on a suitable masking scheme to obtain a laterally graded dopant profile prior to the formation of a gate electrode structure; Fig. 1D schematically shows a transistor element of a semiconductor device, wherein at least one edge region of a channel region has a laterally graded dopant profile; Fig. Figure 1E schematically shows the qualitative functional behavior of a transistor element with respect to a lateral electric field; Fig. 2A-2E schematically show cross-sectional views of a semiconductor device during an early manufacturing stage in which masked implantation processes based on a varying degree of masking are applied to obtain a laterally graded dopant profile prior to the formation of a gate electrode structure; Fig. 3A-3B schematically show cross-sectional views of a semiconductor device during various manufacturing stages in which at least two different dopant species with different diffusion behavior are incorporated into the semiconductor base material such that a laterally graded dopant profile is obtained in edge regions of a channel region upon initiation of a diffusion process; and Fig. 4A-4B schematically show a cross-sectional view and a top view, respectively, of a semiconductor device in a manufacturing stage in which one or more dopant species are incorporated laterally from an isolation trench provided along a lateral direction of an active region of semiconductor devices.

[0011] While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described in detail herein. DETAILED DESCRIPTION

[0012] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of illustrative embodiments. In other instances, well-known structures and components are shown in block diagram form in order not to unnecessarily obscure the illustrative embodiments. Furthermore, unless otherwise indicated, all numbers referring to amounts, ratios, and numerical properties of ingredients, reaction conditions, etc., used in the specification and claims are to be understood as modified by the term "about" to describe, for example, process ambiguities.

[0013] Various embodiments of the invention are described below. For the sake of clarity, not all features of an actual implementation are described in this application. However, it should be appreciated that in developing such an actual embodiment, numerous implementation-specific decisions must be made to meet the developers' particular goals, such as compatibility with system-related and company-specific constraints that may vary from one implementation to another. Furthermore, it should be appreciated that such a development effort can be complex and time-consuming, but nevertheless represents a routine effort for one of ordinary skill in the art given this disclosure.

[0014] The present disclosure will now be described with reference to the accompanying figures. Various structures, systems, and devices are shown schematically in the drawings for the purpose of illustration and are not intended to obscure the present disclosure with details that are already apparent to those skilled in the art. Nevertheless, the accompanying drawings are a part of the specification and serve to describe and explain illustrative examples of the present disclosure. The terms and expressions used herein should be understood and construed to have the meaning commonly understood by those skilled in the art. No specific definition of a term or expression, that is, a definition that differs from its usual meaning to one skilled in the art, is intended when the term or expression is used consistently herein.If a term or expression is intended to have a special meaning, that is, a meaning different from that understood by a person skilled in the art, such a special definition will be explicitly stated in the description in a defining manner that directly and unambiguously provides the special definition for the term or expression.

[0015] As previously discussed, the high lateral electric field for charge carriers, particularly on the drain side of a transistor element, can pose a reliability problem for transistors operating at elevated supply voltages, such as approximately 2 V and higher, when sophisticated, fully depleted device architectures must be implemented to meet the overall device requirements. In general, providing a fully depleted transistor architecture, particularly based on a SOI (silicon or semiconductor-on-insulator) configuration, can fundamentally lead to improved device performance while simultaneously reducing the effects of specific degradation mechanisms that typically accompany the reduction of device sizes from transistor elements to 30 nm and significantly smaller.For example, this type of fundamental transistor design allows well-established planar transistor architectures to continue to be used while still allowing for further overall size reduction.

[0016] On the other hand, providing a very thin crystalline semiconductor layer, especially when formed on a buried insulating layer, requires the drain and source architecture to have a raised configuration to provide suitable contact areas with low-resistance behavior, essentially preventing significant lateral dopant diffusion in the very thin semiconductor base layer and complicating the development of a corresponding laterally graded dopant profile. Furthermore, the thin semiconductor base material may not allow the use of a high dose during an implantation process or process sequence, since amorphization of the semiconductor base material occurs at significantly lower concentrations compared to semiconductor materials with a thickness of several tens of nm, as typically found in bulk architectures.For these reasons, the present disclosure provides techniques for creating a laterally graded dopant profile at least at an edge region of a channel region of a transistor element based on technical concepts in which the basic transistor configuration, and in particular the thin semiconductor base material above the buried insulating layer, is preserved. Thus, the gradation of the profile may further provide a significantly reduced lateral electric field, in particular on the drain side of the transistor element, significantly improving transistor performance with regard to long-term reliability, since the injection of high-energy charge carriers into and through the gate dielectric material may be significantly reduced.

[0017] According to some illustrative embodiments disclosed herein, the incorporation of one or more dopants with a suitable conductivity type is accomplished in an early manufacturing stage, so that corresponding process parameters for the incorporation of the one or more dopants can be specifically selected to accommodate the requirements of a very thin crystalline semiconductor material layer, without having to consider the presence of raised drain and source regions. In some illustrative embodiments of these approaches, the dopant material is incorporated prior to the actual formation of the gate electrode structure or a part thereof, thereby achieving a high degree of flexibility in selecting a suitable process for incorporating the dopant and / or for corresponding masking schemes, if required to obtain a lateral gradation of the dopant profile.

[0018] For example, prior to the formation of materials of the gate electrode structure, masked implantation processes are performed to incorporate a varying lateral concentration of dopant species. In this way, the gradation of the dopant profile on the drain side of the channel region can be achieved for transistor elements for which the source and drain do not change in function if a corresponding region is always used as a drain region or a source region. In other cases, when a symmetrical lateral dopant profile is desired at the edge regions—that is, at the regions that extend along a transistor width direction and whose dopant profile varies along the transistor length direction—the incorporation of the laterally varying dopant profile can be accomplished based on masked implantation processes for which one or more process parameters are varied.For example, the degree of masking, i.e., at least the size of the corresponding implantation mask along the transistor longitudinal direction, can be varied for two or more implantation processes, so that edge regions receive different amounts of dose, even for otherwise identical process parameters, such as implantation energy, implantation type, and the like. Furthermore, throughout the masked implantation sequence, the process parameters, in particular implantation energy and dose, are adjusted such that the degree of implantation-induced lattice damage is maintained at a level that still allows efficient recrystallization during a subsequent annealing process, even if a template material is not present in deeper device regions due to the presence of the buried insulating layer, for example, when considering an SOI configuration.

[0019] In other examples, in addition to or alternatively to varying the degree of masking, other process parameters are varied, such as the type of dopant, which may have different diffusion coefficients, thereby achieving a different degree of diffusion during a subsequent annealing process. This can also be advantageously applied for generating a laterally varying dopant profile, even if otherwise identical process parameters are used. This means that even if a single mask is used to incorporate at least two different types of dopants of the same conductivity type into unmasked regions of the semiconductor base layer, the different diffusion behavior ultimately leads to a laterally graded profile, thereby contributing to a reduction of the lateral field variation during operation of the corresponding transistor element.In other cases, a varying degree of masking during respective implantation processes may be combined with the incorporation of different types of dopants, at least in some phases of the overall process sequence, thereby providing an additional control mechanism for appropriately adjusting a desired lateral dopant profile.

[0020] In still other cases, in addition to or alternatively to the aforementioned control mechanisms, a lateral dopant profile is obtained based on varying implantation parameters, such as implantation dose and / or implantation energy and / or implantation angle, which are nevertheless generally adapted to the specific configuration of the semiconductor base material.

[0021] In yet other processes as disclosed herein, the previously described processes for incorporating one or more dopants are used at a more advanced manufacturing stage, for example, after the formation of at least a portion of the gate electrode structure and / or a portion of a corresponding patterning mask used to pattern the gate electrode structure. In this case, a substantially self-aligned behavior of the incorporation of the dopant species is achieved for at least one implantation process without adversely affecting substantially the entire gate patterning process.

[0022] In still other processes disclosed herein, the incorporation of one or more dopants is accomplished at least in part on the basis of a suitably positioned diffusion layer, such as a diffusion layer formed in or near respective isolation trenches, so that a desired lateral diffusion of the dopant species into the respective edge regions of a yet-to-be-formed channel region is achieved.

[0023] Fig. 1A schematically shows a cross-sectional view of a semiconductor device 100 in an early manufacturing stage, that is, in a manufacturing stage in which a gate electrode structure of a transistor element has yet to be formed. In the manufacturing stage shown, the semiconductor device 100 comprises a substrate 101, such as a crystalline silicon material or another carrier material, depending on the required overall device configuration. It should be noted that a crystalline semiconductor material is often used as the substrate material 101 to create doped regions, circuit elements, and the like therein, as required in the device 100, in conjunction with complex transistor elements formed on the basis of a crystalline material 104, such as a silicon material, a silicon / germanium material, and the like. In the Fig. In the configuration illustrated in Figure 1A, a SOI architecture is used to form the semiconductor layer 104 on a buried insulating layer 102, which may include silicon dioxide, silicon nitride, and / or other dielectric materials, such as high-dielectric-constant dielectric materials, and the like. It should be noted that the thickness and structure of the buried insulating layer 102 may be adapted, at least locally, to specific device requirements if necessary. As further explained above, in some illustrative embodiments, a thickness 104T of the semiconductor layer 104 may be in a range of 15 nm and smaller, with a final thickness and / or material composition being adjusted during any suitable manufacturing stage, e.g., by removing a portion of an initially provided semiconductor material, by forming epitaxially grown layer regions, and the like.For example, a silicon / germanium material is often manufactured locally in certain component areas to meet the respective component requirements.

[0024] Furthermore, in this manufacturing phase, the semiconductor layer 104 and the buried insulating layer 102 may be laterally delimited by a suitable isolation structure 103, such as a trench isolation, which is constructed from silicon dioxide, silicon nitride or another suitable dielectric material.

[0025] It should be noted that the “lateral” direction herein is to be understood as a direction corresponding to a transistor longitudinal direction (current transport) indicated by 100L, while a direction perpendicular to the transistor longitudinal direction 100L is considered as a transistor width direction (not shown) corresponding to a direction perpendicular to the plane of the drawing of the Fig. 1A corresponds.

[0026] Consequently, the isolation structure 103 extends along the transistor width direction such that a transistor length is determined along this direction, that is, a dimension of the semiconductor layer 104 along the transistor longitudinal direction 100L, wherein the layer is also referred to as an active layer or an active region of a transistor element that is yet to be formed in and on the semiconductor layer 104. It should be noted that in some illustrative embodiments, the isolation structure 103 provides a delimitation of the semiconductor layer 104 only in a lateral direction, that is, the isolation structure 103 extends along the width direction, that is, the direction perpendicular to the plane of the drawing of the Fig. 1A, whereas a corresponding insulation along the longitudinal direction 100L for limiting a width of the semiconductor layer 104 may not yet be provided or may only be provided as a trench that “cuts through” the semiconductor layer 104 without being filled with dielectric material.

[0027] Furthermore, in this manufacturing phase, an implantation mask 105 is provided over the semiconductor layer 104 in an area corresponding to an area that will be covered by a gate electrode structure in a later manufacturing phase. The implantation mask 105 is provided in the form of any suitable material, such as a polymer material, a dielectric material in the form of silicon dioxide, and the like, or in the form of another material that has suitable properties for being patterned based on a lithography process and that acts as an efficient mask material during an implantation process 106.The implantation mask 105 is positioned to define at least one boundary of an edge region 151E of a channel region 151, which represents a region of the semiconductor layer 104 that will subsequently be covered by a gate electrode structure yet to be formed, such that a conductive channel is established therein during operation of a transistor element yet to be formed. A corresponding gate electrode structure may thus have edges 160E, which therefore define a corresponding gate length 160L. By appropriately positioning the implantation mask 105 and defining a corresponding lateral size thereof, a corresponding distance 105L of the implantation mask 105 with respect to the edge 160E is thus defined, whereby the corresponding edge region 151E is exposed during the implantation process 106, while the incorporation of dopant material into the central region 151C of the channel region 151 is reliably prevented.

[0028] The Fig. The semiconductor device 100 shown in Figure 1A may be fabricated based on the following processes. Typically, the substrate material 101 is provided in the form of an upper portion of a suitable carrier substrate, such as a silicon substrate and the like, wherein the buried insulating layer 102 is typically formed at least locally on the substrate material 101 by well-established process techniques, such as oxidation, deposition, and the like. Furthermore, the semiconductor layer 104 in its initial composition and thickness, i.e., thickness 104T, is provided by a suitable technique, for example, by wafer bonding to transfer the layer 104 from a donor substrate to the buried insulating layer 102 and the like.Subsequently, before or after the formation of the isolation structure 103, doped regions (not shown) are created in the substrate material 101 with a structure as required by the overall design criteria. The isolation structure 103 is formed by well-established process techniques in which the semiconductor layer 104 is masked by a suitable material or material system, followed by complex lithography and etching techniques to create trenches extending along the width direction, that is, along the direction perpendicular to the plane of the drawing. Fig. 1A, which have a desired extension along the longitudinal direction 100L. The trenches are then filled with a suitable dielectric material, and excess material is removed using well-established planarization techniques.

[0029] Next, the mask 105 is formed using well-established lithography techniques, wherein the patterning of the implantation mask 105 is accomplished only in a lateral direction if necessary, so that the mask may extend along the width direction over a significant portion of the device 100, while its lateral size is determined during the lithography process in conjunction with a corresponding patterning process, such as a development process, an etch adjustment process, and the like. It should be noted that in some illustrative embodiments, the intended gate length 160L may not substantially correspond to a critical dimension of highly complex transistor elements. Thus, the implantation mask 105 may be provided with a lateral size that is smaller than the gate length 160L and within the capabilities of the corresponding lithography and patterning technique.In other cases, the implantation mask 105 is initially provided with a lateral size, i.e., a dimension along the longitudinal direction 100L, substantially corresponding to the gate length 160L, thereby applying and employing similar patterning strategies as those used in the fabrication of complex gate electrode structures. The ultimately desired reduced length of the implantation mask 105 can then be obtained based on etching processes using well-established etch chemistries, ultimately creating the gap 105L.

[0030] It should be noted that the adjustment of the distance 105L is also referred to as adjustment of the degree of masking of the implantation mask 105 with respect to the implantation process 106.

[0031] Next, the implantation process 106 is performed based on appropriately selected process parameters such that a specific dopant species is incorporated into unmasked areas of the semiconductor layer 104, including the edge region 151E. As previously explained, the implantation process 106 is performed based on a correspondingly low dose and an appropriately selected implantation energy such that a desired relatively low concentration of a specific dopant species is achieved, since a laterally graded dopant profile is to be created in the edge region 151E, with the dopant concentration decreasing towards the central region 151C. For example, if the graded dopant profile is to be created for an N-type transistor yet to be formed, then an N-type dopant species, such as arsenic, phosphorus, and the like, is incorporated during the process 106.Due to the moderately low dose, the corresponding degree of lattice damage remains relatively low, allowing sufficient recrystallization in a later phase.

[0032] It should be noted that suitable process parameters for the implantation process 106 with regard to implantation energy, implantation dose, and selection of a suitable dopant species can be efficiently determined based on simulation calculations and / or experiments. For this purpose, the effect of a corresponding concentration of a dopant species on the electric field generated in the edge region 151E when using a suitable supply voltage for a given transistor architecture is efficiently determined by simulation, and thus, corresponding process parameters can be selected. In other cases, various test implantations are performed with varying parameters, and the results are monitored for several test regions, including the layer 104 and the implantation mask 105. Suitable parameters are then selected by evaluating the corresponding test results.

[0033] It should be noted that in Fig. 1A and in the subsequent drawings, the edge region 151E is typically illustrated as being present at both edges 160E of a yet-to-be-formed gate electrode structure. In this way, a corresponding lateral graded dopant profile is obtained in each of the edge regions 151E regardless of whether a corresponding region is adjacent to a drain region or a source region of a yet-to-be-formed transistor element. Therefore, in such a structure, the function of the drain and source can be changed depending on the respective electrical state of the corresponding transistor element.In other variations (not shown), the implantation mask 105 exposes only one of the edge regions 151e adjacent to a corresponding drain region, which is sufficient for reducing the lateral electric field near the drain region if the function of the drain region and the source region does not change during the entire use of the corresponding transistor element.

[0034] Thus, after the end of the implantation process 106, a relatively low concentration of a dopant 106A is incorporated into exposed regions of the semiconductor layer 104, forming a junction 106J whose lateral position is essentially defined by the implantation mask 105. It should be noted that the junction 106J is not actually a sharp boundary, but that some variability may be present due to the nature of the implantation process 106. Furthermore, the junction 106J can in principle be shifted at a later stage if an appropriate annealing process is employed.

[0035] Fig. 1B schematically shows the semiconductor device 100 in a further advanced manufacturing stage. As shown, a further implantation mask 107 is formed within the region defined by the edges 160E of a yet-to-be-formed gate electrode structure. Consequently, a side surface of the implantation mask 107 may have a distance 107L with respect to the corresponding edge 160E, wherein the distance 107L is smaller compared to the distance 105L of the implantation mask 105 (see Fig. 1A). By acting on the device 100 by means of an implantation process 108, which is carried out on the basis of suitably selected process parameters, a corresponding dopant species 108A is thus incorporated into exposed regions of the semiconductor layer 104, thereby creating a second junction 108J that is laterally offset from the junction 106J, the lateral position of which is determined by the implantation mask 107.

[0036] The implantation mask 107 is fabricated based on well-established lithography and patterning strategies, as explained previously, so that the lateral distance 107L is obtained after the previous implantation mask 105 ( Fig. 1A) has been removed based on well-established cleaning processes.

[0037] With regard to any implantation parameters for the process 108, the same criteria apply as previously explained. That is, in some cases, a suitable implantation energy and dose for the dopant species 108A are selected, for example, based on simulation calculations and / or experiments, wherein the process parameters are typically selected such that the overall effect of the implantation processes 105 ( Fig. 1A) and 108 leads to a desired dopant concentration in unexposed regions of the semiconductor layer 104, thereby forming the junction 108J, which can also be understood as the region in which the concentration changes more or less abruptly to a reduced concentration, represented by the junction 106J. Consequently, a moderately increased dose and thus concentration can be obtained overall compared to the previously performed implantation process. Subsequently, the implantation mask 107 is removed by a suitable cleaning process based on plasma and / or wet chemistry.

[0038] Fig. Figure 1C schematically shows the semiconductor device 100 in a more advanced manufacturing stage. As shown, after removing the implantation mask 107 ( Fig. 1B) a further implantation mask 109 is provided such that it defines a further lateral distance 109L with respect to the edge 160E, wherein the lateral distance 109L is smaller than the lateral distance 107L of the implantation mask 107 of the Fig. 1B. Furthermore, a further implantation process 110 is applied such that a dopant species 110A is introduced into exposed regions of the semiconductor layer 104, thereby creating a further junction 110J defined by the sidewalls of the implantation mask 109. With regard to parameters of the implantation process 110 and techniques for fabricating the implantation mask 109, the same criteria apply as previously explained. That is, process parameters, such as energy and dose, as well as a selection of a suitable species, can be obtained based on simulation calculations and / or experiments, wherein the implantation mask 109 is fabricated in accordance with suitable patterning strategies and lithography techniques such that the desired degree of masking is achieved during the implantation process 110.Therefore, the respective transitions 110J, 108J, 106J represent a gradation of the dopant concentration that decreases toward the central region 151C, which also results in a desired reduction of the lateral electric fields during operation of a yet-to-be-formed gate electrode. On the other hand, the dopant concentration achieved by the combined incorporation of the dopant species 106A, 108A, 110A is selected to provide the required moderate dopant concentration while still maintaining crystal damage at a moderately low level, allowing recrystallization based on a suitable annealing process 111 in a subsequent phase of the overall manufacturing process.

[0039] In some process strategies, a corresponding annealing process is performed before a final implantation process if implantation-induced damage is deemed too high, as significant amorphization of exposed regions of the semiconductor layer 104 is induced in conjunction with a final implantation process. Consequently, crystal damage resulting from one or more previous implantation processes may be annealed, if deemed appropriate, before a next implantation process is performed, thereby achieving improved crystal properties and potentially allowing the use of a higher dose, if necessary.The one or more annealing processes 111 are carried out based on suitable process techniques, such as annealing techniques requiring very short annealing times in the range of nanoseconds to microseconds, if pronounced diffusion is deemed unsuitable. In this case, the respective transitions 106J, 108J, 110J remain as relatively sharp regions where a corresponding, more or less abrupt change in the dopant concentration is observable. In other cases, fast thermal annealing processes with significantly longer process times are used, initiating a certain degree of diffusion leading to more "rounded" and thus more continuous concentration changes, if desired.

[0040] It should further be noted that if two or more annealing processes are to be performed to establish a desired laterally graded dopant profile, the annealing process 111, or one or more of the annealing processes, may be performed at a later manufacturing stage if the modification of the semiconductor layer 104 is compatible with further processing for forming a gate electrode structure. For example, an annealing process may be applied after a corresponding gate electrode structure has been formed and possibly another dopant species has been incorporated to obtain a desired dopant concentration in corresponding drain and source regions.

[0041] Furthermore, in the context of the Fig. 1A-1C, a degree of masking, represented by the distances 105L, 107L, 109L, is applied. That is, the distances decrease starting from the implantation mask 105, so that the implantation with the lowest dose is performed first, followed by an implantation with a slightly increased dose, and so on. Otherwise (not shown), the sequence of the implantation processes 105, 108, 110 is selected in any desired manner, for example, by providing the implantation mask 109 first and the implantation mask 105 last, so that the implantation process 110 is performed as a first implantation process with a moderately high implantation dose.

[0042] Furthermore, the information provided with reference to the Fig. 1A-1C, the corresponding implantation masks 105, 107, 109 are provided as individual masks, which are manufactured on the basis of corresponding individual lithography and patterning processes. In other cases, the degree of masking and thus the lateral size of the implantation mask 105 that is initially provided is increased by depositing a suitable material, such as silicon dioxide and the like, before a next implantation process is carried out. By initially arranging the implantation mask 105 of the Fig. 1A, further masks are thus obtained by deposition processes in a substantially self-aligning manner, without the need for further lithography processes.

[0043] In other examples, as explained below with reference to the Fig. 2A-2E, the size of an initially provided implantation mask is sequentially reduced to achieve different degrees of masking.

[0044] Fig. 1D schematically illustrates the semiconductor device 100 in a more advanced manufacturing stage. As shown, a transistor element 150 is formed according to selected design criteria, in particular, using the semiconductor layer 104 as a semiconductor base layer with a thickness such that a substantially fully depleted transistor configuration is achieved, as previously explained. Furthermore, the transistor element 150 comprises a gate electrode structure 160 with respective gate edges 160E defined, for example, by respective sidewall spacer elements 164 made of silicon nitride, silicon dioxide, and the like, to enclose other sensitive materials of the gate electrode structure 160 and to provide electrical isolation with respect to the drain and source regions 152, 153.The drain and source regions 152, 153 are provided in a raised architecture in which a highly doped crystalline semiconductor material is formed on the semiconductor layer 104 in such a way that a moderately high conductivity is created and thus the production of corresponding contact regions is possible, so that a connection can be made to corresponding contact elements that are still to be produced in a contact level of the semiconductor device 100.

[0045] The gate electrode structure 160 is formed above the channel region 151, which includes the central portion 151C and, in the illustration shown, the two edge regions 151E having the laterally graded dopant profile, as indicated by the junctions 106J, 108J, 110J, and as previously explained. In other examples, the corresponding graded dopant profile is formed only in one edge region, for example, the edge region 151E, which is arranged adjacent to the drain region 152. In order to suitably electrically isolate an electrode material 163 of the gate electrode structure 160 from the channel region 151, a gate dielectric material 161 is provided, for example in the form of silicon oxide, silicon oxynitride, and the like, if a corresponding thickness and the corresponding dielectric constant are suitable to achieve the desired channel controllability.In other cases, the gate dielectric material 161 comprises, instead of or in addition to a standard dielectric material, a high-k dielectric material, which is then provided in combination with an additional metal-containing material for adjusting the threshold voltage and a corresponding barrier layer, collectively indicated as 162. It should be noted that in some illustrative embodiments, the transistor element 150, and in particular the gate electrode structure 160, are designed to operate with a supply voltage of approximately 2.5 V and higher, such as 3.3 V, which are typical supply voltages for transistor elements used in I / O circuitry.It should be noted, however, that the graded dopant profile in one or both edge regions 151E may also be beneficial for other transistor elements operating at lower supply voltages, thereby further improving the overall reliability of such transistor elements.

[0046] The Fig. The transistor element 150 shown in Figure 1D is manufactured based on the following processes. Starting with the component configuration, as shown, for example, in Fig. 1C, or in a component configuration as described below with reference to the Fig. 2A-2E, 3A-3B, and 4A-4B, the gate electrode structure may be formed on the semiconductor layer 104 above the channel region 151 such that it overlaps at least a portion of the edge regions 151E. For this purpose, well-established and elaborate lithography and patterning strategies may be applied, for example, by first forming the dielectric material 161, or at least a portion thereof, followed by the deposition of further required material systems and the electrode material 163, possibly followed by the deposition of a suitable dielectric capping material, such as silicon nitride and the like, which may then be patterned and used as an etch mask for the subsequent patterning of the underlying materials.

[0047] It should be noted that in some examples, as previously mentioned with reference to the Fig. 1A-1C, the edge regions 151E, or at least a region thereof, may already comprise the graded dopant profile in a more or less graded or step-like manner, depending on a sequence of processes previously performed, wherein a substantially crystalline state of the semiconductor layer 104 has also been restored. Furthermore, the gradation of the degree of lateral variation of the dopant profile in the edge regions 151E may be determined based on the number of implantation processes performed during the subsequent process sequence and the respective process parameters used. For example, although three individual implantation processes have been used to obtain the three junctions 106J, 108J, 110J, in other examples, one or two implantation processes or four or more implantation processes may be employed, depending on the required lateral dopant profile.As further explained above, and as will be shown in more detail below, the respective transitions may be "smeared" to obtain a substantially continuously varying dopant profile, depending on the process parameters applied in the one or more annealing processes.

[0048] Although in principle the corresponding annealing process for restoring the crystalline state of the semiconductor layer 104 may be performed after at least a part of the gate electrode structure 160 is formed, in some variations, performing corresponding annealing processes before completing the gate electrode structure 160 offers increased flexibility in applying specific process parameters for the annealing processes with respect to length, temperature, and the like.

[0049] After patterning the gate electrode structure 160, the drain and source regions 152, 153 are formed, for example, by selective epitaxial growth techniques, wherein a suitable dopant species is introduced into the deposition atmosphere to obtain a highly in-situ doped crystalline semiconductor material. Due to the previously incorporated dopant species in layer 104, a high overall dopant concentration is obtained in the drain and source regions 152, 153 from top to bottom, while simultaneously achieving a relatively smooth connection to the laterally graded dopant profile in the edge regions 151E.

[0050] Thereafter, further processing may continue, for example, by removing a cap material from the gate electrode structure 160 and forming contact regions (not shown), such as metal silicide in the form of nickel / platinum silicide and the like, in the drain and source regions 152, 153 and in the gate electrode structure 160, followed by the formation of contact elements (not shown) to connect the various contact regions of the transistor element 150.

[0051] In the previous with reference to Fig. 1D, reference is made to a manufacturing strategy in which the gate electrode structure 160 is provided as a functional structure in an early manufacturing stage, i.e., before the formation of the raised drain and source regions 152, 153 and before the formation of any interlevel dielectric material, which typically encloses the resulting transistor structure and is also used to form contact elements therein. In other strategies, the final functional design of the gate electrode structure 160 is completed in a late manufacturing stage, e.g., by providing at least some material systems that are replaced by the actual materials of the gate electrode structure in a later manufacturing stage, i.e., after the formation of the drain and source regions 152, 153.Also in this case, the laterally graded dopant profile in the edge regions 151E can be produced on the basis of the principles as explained previously or as described in more detail below.

[0052] In any case, by providing the laterally graded dopant profile, as represented by the junctions 106J, 108J, 110J, at least in the edge region 151E on the drain side, an improved behavior is achieved due to the significant reduction of the lateral electric field during operation of the transistor element 150.

[0053] Fig. 1E schematically illustrates the qualitative functional behavior of transistor element 150 with respect to a lateral electric field, i.e., the field prevailing during operation of transistor element 150 along longitudinal direction 100L. As shown, curve A represents a typical qualitative behavior of the lateral electric field for a transistor element having the same structure as transistor 150, but without incorporating the laterally graded dopant profile. Consequently, a pronounced peak is observed near the gate edge 160E adjacent to the drain region 152, thus giving rise to a pronounced degradation caused by energetic charge carriers being imprinted into the gate dielectric material near the corresponding edge 160E, as also previously explained.Consequently, significant reliability problems can be observed at moderately high supply voltages, making such conventional transistor elements less desirable for use in complex semiconductor devices.

[0054] On the other hand, the laterally graded dopant profile, indicated by junctions 106J, 108J, and 110J, can lead to a significantly reduced maximum value of the lateral electric field, as indicated by curve B, thereby significantly reducing the probability of high-energy carriers being imprinted and thus significantly increasing the reliability of transistor element 150. On the other hand, the desired low value of the lateral electric field is still maintained in the central region 151C.

[0055] With reference to the Fig. 2A-2E, further steps will now be described in more detail to obtain the transistor element 150 as previously described with reference to the Fig. 1D and Fig. 1E is explained.

[0056] Fig. 2A schematically shows a cross-sectional view of a semiconductor device 200 having a structure similar to that of the semiconductor device 100 of Fig. 1A. That is, a semiconductor layer 204 is delimited by isolation structures 203 and is optionally vertically separated from a substrate material 201 by a buried insulating layer 202. With regard to these components, the same criteria apply as previously described with reference to Fig. 1A are explained.

[0057] Furthermore, in this manufacturing phase, an implantation mask 209 is provided such that a certain degree of masking of a channel region 251 is defined. The degree of masking may be defined as a lateral distance 209L of the implantation mask 209 from at least one drain-side edge 260E of a gate electrode structure yet to be formed. In this case, however, the implantation mask 209 defines a position of a maximum dopant concentration of a laterally graded dopant profile yet to be formed. For this purpose, an implantation process 210 is applied based on process parameters determined based on simulation calculations and / or experiments in order to introduce a dopant species 210A into exposed regions of the semiconductor layer 204. After the implantation process 210, a corresponding transition 210J is thus created, which is aligned with sidewall surfaces of the implantation mask 209.

[0058] Fig. 2B schematically illustrates the semiconductor device 200 in a more advanced manufacturing stage, in which a material removal process 212 is performed to reduce the dimensions of the implantation mask 209 to obtain a reduced mask 207 and to define a further degree of masking, which is given by the lateral distance 207L with respect to the edge 260E of the yet-to-be-formed gate electrode structure. For this purpose, many well-established resist trimming processes are available and may be employed, thereby obtaining the desired lateral distance 207L with a high degree of process controllability.It should be noted that the initial mask 209 is designed, for example, with respect to its vertical extent, so as to maintain a reliable implantation mask upon further reducing its size during the process 212, possibly during any further processes for further reducing the size of the initial mask 209.

[0059] Fig. 2C schematically illustrates the semiconductor device 200 in a more advanced manufacturing stage, in which a further implantation process 208 is applied based on appropriately selected process parameters, such as dose and energy, thereby introducing a further dopant species 208A into exposed regions of the semiconductor layer 204. Consequently, a further junction 208J is created based on the implantation mask 207. It should also be noted that with regard to any process parameters of the implantation process 208, the same criteria as previously explained may apply.

[0060] Fig. 2D schematically illustrates the semiconductor device 200 being exposed to a further reactive environment 213 configured to reduce the size of the previously formed implantation mask 207, thereby obtaining a further implantation mask 205. The process 213 may be controlled to maintain the desired lateral distance 205L with respect to the gate edge 260E, so that the degree of masking during a subsequent implantation process may be appropriately determined. It should be noted that, as previously explained, the height of the implantation mask 205 may still be sufficient to reliably prevent penetration of dopant species into the central portion of the channel region 251. For this purpose, the initial size of the implantation mask 209 ( Fig. 2A) is suitably selected with respect to the implantation energy used in conjunction with the implantation mask 205.

[0061] Fig. 2E schematically illustrates the semiconductor device 200 when it is subjected to a further implantation process 206, in which a further dopant species 206A is incorporated such that a further junction 206J is created in an edge region 251E of the channel region 251. Regarding process parameters and the type of dopant species used, reference is also made to the previously described steps.

[0062] Consequently, the graded dopant profile indicated by the transitions 206J, 208J, 210J may be established based on a process sequence in which at least some of the implantation masks are obtained by applying a resist trimming process or another well-controllable removal process to a previously used implantation mask.

[0063] It should be noted that in some cases the information provided by reference to the Fig. 2A-2E described process strategy with one or more of the previously mentioned with reference to the Fig. 1A-1C. That is, one or more of the implantation masks produced by lithography are used, while one or more of the implantation masks are obtained based on a trimming process applied to a previously used implantation mask. Although three implantation masks are described above, two or four or more implantation masks may be used. Furthermore, although the corresponding implantation processes described with reference to Fig. 1A-1C and 2A-2E are illustrated as substantially orthogonal implantation processes with respect to the lateral directions of the semiconductor device under consideration, one or more of the implantation processes may be performed as tilted implantation processes, or the implantation angle may be varied during a single implantation process.

[0064] Subsequently, further processing continues in such a way that the data relating to the Fig. 1D, the functional behavior being similar to that described in connection with Fig. 1E is described.

[0065] With reference to Fig. 3A and Fig. 3B further production phases are now described in more detail.

[0066] Fig. 3A schematically shows a cross-sectional view of a semiconductor device 300 comprising a substrate material 301, a buried insulating layer 302, insulation structures 303, and a semiconductor layer 304. With respect to these components, the same criteria apply as previously explained in connection with devices 100 and 200. Furthermore, in this manufacturing phase, an implantation mask 305 may be formed such that a certain degree of masking is provided, as represented by a lateral distance 305L of the mask 305 relative to an edge 360E of a yet-to-be-formed gate electrode structure. In an implantation sequence indicated by individual implantation processes 306, 308, at least two different types of dopants 306A, 308A may be incorporated into exposed regions of the semiconductor layer 304, thereby forming a corresponding junction 306J.Dopant species 306A and 308A represent the same conductivity type but may differ in terms of diffusion properties. For example, arsenic and phosphorus represent N-type dopants, with arsenic having a noticeably lower diffusion coefficient compared to phosphorus. Regarding the selection of suitable implantation energies and doses, appropriate simulations and / or experiments can be performed to obtain the desired penetration depth and concentration while still maintaining crystal damage at an acceptable level.

[0067] Fig. 3B schematically illustrates the semiconductor device 300 during one or more annealing processes 315 designed to restore the crystal structure of the semiconductor layer 304 and initiate a desired degree of diffusion of the dopant species 306A, 308A. In the present example, it is assumed that the diffusion of the dopant species 308A is stronger compared to the diffusion of the species 306A, thereby achieving a greater lateral penetration depth, thus determining the lateral extent of the edge region 351E, and subsequently continuously varying the lateral dopant profile, which decreases toward the central region 351C.It should be noted that suitable process parameters, such as annealing temperature and process time, for the one or more processes 315 may be selected based on experiments and / or calculations, since several annealing techniques are typically known in the art and may be used to adjust the laterally graded dopant profile in the edge region 351E in conjunction with the two or more dopant species 306A, 308A applied in the previously applied process parameters of the respective implantation processes.

[0068] It should be noted that the concept of using two or more different implantation materials with different diffusion behavior is applied in some manufacturing stages in two or more of the implantation processes, which are described with reference to the Fig. 1A-1C and 2A-2E, thereby creating the possibility of achieving a smoother change in the lateral dopant profile, since a more continuous change is created during a corresponding annealing process. For example, the number of implantation masks to be used is reduced by using one or more of the implantation masks in conjunction with two or more implantation processes in which correspondingly different dopant species are incorporated. Thus, for a given number of implantation masks to be used, a more continuous and smoother dopant profile can be achieved, while in other cases the number of implantation masks and thus possibly the number of lithography processes is reduced, while still achieving a desired degree of lateral change in the dopant profile in the corresponding edge region.

[0069] In some manufacturing stages, the implantation mask 305 represents a part of a gate electrode structure or a patterning mask used to pattern underlying gate materials (not shown). In this way, two or more dopants with different diffusion behavior may be introduced in a self-aligned manner with respect to the gate edges 360E, while the gradation or lateral change of the dopant profile in the edge regions 351E is achieved by the different diffusion behavior. It should be noted that in some cases, one or more dopant species may have been incorporated based on techniques described with reference to Fig. 4A and Fig. 4B and / or previously described with reference to components 100 and 200.

[0070] It should be noted that the masking schemes described above can be applied separately to different types of transistor elements, such as N-type transistors and P-type transistors, by appropriately masking corresponding device regions where the incorporation of one or more dopant species is not required. Consequently, the corresponding laterally graded dopant profile can be tailored to a given type of transistor element.

[0071] With reference to Fig. 4A and Fig. 4B, further illustrative embodiments will now be described in more detail.

[0072] Fig. 4A schematically shows a cross-sectional view of a semiconductor device 400 comprising a substrate material 401, a buried insulating layer 402, and a semiconductor layer 404 formed thereon. With respect to these components, the same criteria apply as previously explained with reference to the semiconductor devices 100, 200, and 300. Furthermore, in the manufacturing stage shown, a protective layer 415 composed of silicon nitride and / or silicon dioxide and the like is formed on the semiconductor layer 404, and isolation trenches 403T are formed to define a lateral size along a transistor longitudinal direction 400L of the semiconductor layer 404.

[0073] Furthermore, a doped material 416 is formed in the isolation trench 403T and on the protection layer 415. The doped material 416 is provided in the form of any suitable material incorporating one or more desired dopant species that diffuse laterally into the semiconductor layer 404 upon performing a corresponding annealing process 417. For example, the doped material 416 is made of polysilicon, silicon dioxide, and the like, wherein a corresponding dopant species is incorporated during the corresponding deposition process for the doped material 416 by introducing a suitable dopant species at a high concentration into the deposition atmosphere.

[0074] In principle, the isolation trenches 403T can be formed by applying well-established lithography and patterning techniques such that the layers 415, 404, 402 are etched in accordance with well-established process recipes. Subsequently, the doped material 416 is deposited such that it contains a correspondingly high concentration of one or more dopant species. It should be noted that, as also discussed in connection with Fig. 3A and Fig. 3B, different dopant species with different diffusion behavior may be incorporated into the doped material 416, such as arsenic and phosphorus for N-type transistor elements, while P-type dopant species may be incorporated into the doped material 416 for P-type transistor elements. Therefore, in some illustrative embodiments, the diffusion layer for one type of dopant species may be deposited first and may be removed again over device regions requiring the incorporation of a dopant species with an opposite conductivity type. Thereafter, the corresponding diffusion layer may be deposited, and the one or more annealing processes 417 may be applied if a corresponding set of process parameters is suitable for the diffusion of both dopant types.In other cases, the dopant species of a conductivity type is provided by a corresponding diffusion layer, such as the doped material 416, selectively formed over corresponding device regions, and the parameters of the annealing process 417 are selected such that the desired lateral dopant profile is achieved upon application of a second annealing process or process sequence designed to obtain the desired lateral dopant profile for dopant species incorporated on the basis of a separately deposited diffusion layer. Consequently, in this case as well, the desired lateral dopant profile is obtained in the semiconductor layer 404 for N-type transistor elements and P-type transistor elements, even if these dopant species have very different diffusion behavior.By selecting a suitable dopant type for the different conductivity types and by selecting suitable process parameters for the one or more annealing processes 417, the lateral diffusion is thus controlled to obtain a desired lateral profile extending into the semiconductor layer 404 in order to achieve a corresponding varying dopant profile in the vicinity of a gate edge 460E of a gate electrode structure yet to be formed.

[0075] Fig.4B schematically illustrates a top view of the semiconductor device 400 according to illustrative embodiments, in which the isolation trenches 403T extend along a transistor width direction 400W, thereby defining a length of respective active regions, while a separation along the longitudinal direction 400L of the layer 415 has not yet taken place to thereby define a width of the respective active region. Upon initiating the diffusion of dopant species, as indicated by 406A, undesired dopant incorporation at respective end portions of the active regions along the transistor width direction 400W may be substantially avoided.

[0076] Thus, the present disclosure provides techniques and semiconductor devices in which a laterally graded or varying dopant profile in edge regions of channel regions of transistor elements provides improved reliability by significantly reducing the peak value of the lateral electric field, while still maintaining the fundamentally fully depleted transistor structure fabricated on the basis of a very thin crystalline semiconductor layer.

[0077] The specific embodiments disclosed above are merely illustrative. For example, the aforementioned process steps may be performed in a different order. It should be noted that the use of terms such as "first," "second," "third," or "fourth" to describe various processes or structures in this specification and the following claims is intended only as an abbreviated reference to such steps / structures and does not necessarily imply that such steps / structures are performed / manufactured in that ordered sequence.

Claims

[1] Procedure with: Forming an isolation trench (403T) for laterally delimiting an active region containing a channel region along a lateral direction (400L); Forming a doped material (416) in the isolation trench (403T) such that an increased concentration of at least a first and second dopant species is provided laterally adjacent to the channel region; Forming a laterally graded dopant profile in a first edge region and / or a second opposite edge region (460E) of the channel region, wherein forming the laterally graded dopant profile comprises initiating a diffusion of the at least first and second dopant species; and After forming the laterally graded dopant profile, forming a gate electrode structure on the channel region such that the gate electrode structure at least partially overlaps with the first and second edge regions (460E). [2] The method of claim 1, wherein initiating a diffusion of the at least first and second dopant species comprises an annealing process (417).

Images