INTEGRATED CIRCUIT ELEMENT AND NEGATIVE CAPACITY ENERGY STORAGE ELEMENT

Abstract

Integrated circuit element, comprising the following: a first electrode (101, 301, 501, 601), a second electrode (102, 302, 502, 602) and a first dielectric layer (111, 311, 511, 611) with positive capacitance, which is arranged between the first and the second electrode layer, and a second dielectric layer (106, 312, 512, 612) adjacent to the first dielectric layer (111, 311, 511, 611) comprising a polarizable material, wherein the first dielectric layer (111, 311, 511, 611) is thicker than the second dielectric layer (106, 312, 512, 612).

Description

background

[0001] In the future, increasing amounts of electrical energy will need to be stored efficiently due to a shift towards decentralized generation and consumption. Electrostatic capacitors can achieve very high power densities compared to other storage technologies such as batteries. However, the energy densities of such capacitors are comparatively low. When a voltage is applied to a capacitor (see Fig. 1a, Fig. 1b), energy is stored in the electric field in a dielectric material (105) that separates the two conducting electrodes (101, 102). The main advantages of energy storage in capacitors lie in high energy storage efficiency, temperature and cycle stability, and fast charging and discharging. However, conventional dielectric capacitors cannot compete with the orders of magnitude higher energy storage density (ESD) of, for example, batteries. Electrochemical supercapacitors, which combine the high power density of conventional capacitors with higher energy densities, are ideal for applications where a large amount of electrical energy needs to be stored and released in a short time. Such supercapacitors are currently used, for example, to stabilize the power grid, recover braking energy in electric vehicles, or provide a backup power supply for critical electrical systems.

[0002] In the past, electrostatic energy storage capacitors based on polarizable materials instead of dielectric (DE) materials were proposed to overcome ESD limitations. State-of-the-art energy storage capacitors based on single layers of ferroelectric (FE), antiferroelectric (AFE), and relaxor-like ferroelectric (RFE) materials still have several disadvantages. First, energy is dissipated due to hysteretic switching during charging and discharging, which reduces energy storage efficiency (see Fig. 2a, Fig. 2b, Fig. 2c). Secondly, the breakdown field strength of FE and AFE materials is limited due to their crystalline structure compared to amorphous DE materials with a high electronic band gap.

[0003] Besides energy storage applications, stored energy can also be interpreted as stored information. A well-known concept for stored energy used as information storage in capacitor structures is DRAM (Dynamic Random Access Memory), which utilizes a high or low charge as information storage. This is referred to as a volatile memory structure because the stored data is lost within seconds and must be updated in a timely manner to ensure data retention, primarily due to problems with leakage currents. Another example is NAND flash memory, which uses a floating gate or a charge-trapping layer to store information in a transistor structure.

[0004] Polarizable materials have become significantly more attractive for use in information storage applications. Prominent examples of this type of storage are ferroelectric memory structures such as FeRAM (Ferroelectric Random Access Memory) and FeFET (Ferroelectric Field Effect Transistor) devices.

[0005] Further circuit elements are known from KIM, Yu Jin, [et al.]: Time-Dependent Negative Capacitance Effects in Al2O3 / BaTiO3Bilayers, Nano Lett. 2016, 16, 4375-4381, SI, Mengwei, [et al.]: Steep-slope hysteresis-free negative capacitance MoS2 transistors, Nature Nanotechnology 2017, 13, 24, US 2008 / 0 107 885 A1 and US 2017 / 0 256 552 A1. Brief description

[0006] The invention is based on the objective of providing an improved integrated circuit element and an improved energy storage element.

[0007] According to embodiments, the problem is solved by the subject matter of the independent patent claims.

[0008] The present invention describes a concept for increasing the energy density of capacitors by utilizing a material with differential negative capacitance (NC), which has recently been observed in FE materials. Furthermore, the invention reveals a more general approach to improved electrostatic energy storage densities by technically influencing the nonlinearity of the capacitance of electrostatic devices. The invention disclosed herein overcomes the disadvantages of conventional polarizable materials by utilizing the NC effect, ideally without hysteresis losses and leading to a theoretical efficiency of 100% (see [reference]). Fig. 2d). Furthermore, by storing the energy predominantly in an amorphous DE layer, the breakdown field strength is much higher compared to pure FE or AFE storage capacitors. In addition, leakage current losses can be reduced by improving the morphology of the insulating materials used.

[0009] According to the present invention, the improved electrostatic energy storage density is used by technically influencing the nonlinearity of the capacitance of electrostatic capacitors for energy storage applications as an energy storage element and for data and information storage and processing applications as an integrated circuit element. Brief description of the drawings Fig. 1: (a) Positive capacitor with charge Q, voltage V, electric field E, and displacement field D. (b) Energy stored in a linear positive capacitor at a given voltage V is given by the area above the charge-voltage curve. (c) Combining layers of negative and positive capacitance to create an NC capacitor with improved energy density and no hysteresis (see d). Fig. 2: Comparison of different capacitor designs utilizing polarizable materials. Charge-voltage characteristics of (a) a ferroelectric, (b) an antiferroelectric, (c) a relaxor-like ferroelectric, and (d) the ferroelectric / dielectric capacitor as disclosed herein. Hatched areas represent the energy lost due to hysteresis. Fig. 3: (a) Proposed NC capacitor consisting of a ferroelectric / dielectric stack with a boundary layer charge σ IF , which is the spontaneous polarization P f (a) NC capacitor stabilized at zero voltage. (b) NC capacitor with a positive voltage V1 applied, where the ferroelectric layer is still in the positive capacitance (PC) characteristic. (c) NC capacitor with a higher positive voltage V2 > V1 applied, where the ferroelectric is in the NC characteristic. Due to the NC in the ferroelectric layer, the stored energy (gray area) is significantly increased. Fig. 4: (a) Exemplary NC capacitor structure using a dielectric Ta2O5 and a ferroelectric Hf 0.5 Zr 0.5O2 layer. To measure the stored charge, voltage pulses V are applied to the upper electrode. (b) Measured charges as a function of the applied voltage during charging (filled line, Q) c ) and unloading (outlined symbols, Q d (c) Similarly, the energy densities during charging (filled symbols, W) c ) and unloading (outlined symbols, W a ) as a function of voltage V. (d) Energy storage efficiency as a function of discharged energy density W d . Fig. 5: Various structures for energy storage and storage applications according to the present invention. (a) to (c) planar structure, (d) 3D structure to improve energy storage density, and (e) planar structure combined with a charging and loading element (530). Fig. 6: Illustration of an exemplary implementation of the inventive concept in memory cells. (a) illustrates an exemplary implementation of the inventive concept using a memory cell architecture based on capacitor integration and (b) illustrates an exemplary implementation of the inventive concept using a memory cell architecture based on transistor integration. Detailed description

[0010] The present document describes a new concept for a capacitor element (see Fig. 1c), which uses a stack of insulating layers (111, 106), one of which exhibits differential NC (111), while the others exhibit positive capacitance (PC) (106). Insulators exhibiting differential NC are polarizable materials, e.g., ferroelectric (FE) or antiferroelectric (AFE) materials, whereas conventional dielectric (DE) materials exhibit only PC. Depending on the electrical boundary conditions, NC materials can also be in a PC state. The inventive concept disclosed herein enables a very high electrical energy storage density (ESD) with high efficiency in a capacitor consisting of two electrodes (101, 102) separated by a stack of a polarizable and a dielectric insulating layer (111, 106). When the voltage across the capacitor electrodes is zero, the polarizable layer (111) is in a PC state, resulting in a low overall capacitance of the device.When a specific positive voltage is applied to the electrodes, the polarizable layer (111) enters a normally closed (NC) state, leading to a significant increase in the total capacitance of the component. The increase in total capacitance with increasing voltage, as well as the improved breakdown field strength of the diode layer (106) due to the polarizable layer (111), results in a very high ESD (electrostatic discharge). Fig. 1d).

[0011] Graphically, the stored energy or the storage energy density is identical to the area above the charge-voltage (QV) curve as shown in Fig. 2 shown or in the electric field-electric displacement field (ED) curve. For linear positive components such as capacitors with a linear dielectric relation D = εE, where ε is the permittivity, the capacitance is constant and the stored charge depends linearly on the voltage (Q = CV), as shown in Fig. 1b shown. For materials with negative capacitance (NC), the ratio between Q and V (or D and E) cannot be linear, since such a component could supply infinite amounts of energy.

[0012] Materials exhibiting a differential negative permittivity (dD / dE < 0) or capacitance (dQ / dV < 0) can exist if the negative capacitance (NC) region borders regions with positive capacitance. The simplest way to describe the behavior of materials with negative capacitance (NC) is a third-degree polynomial shifted along the charge axis. Successive combinations of a material with linear capacitance (V = Q / C) with an NC material described by a third-degree polynomial (see Fig. 1d), a third-order polynomial still describes the capacitance of the two materials. An exemplary QV curve of such an NC capacitor with a stack of a polarizable and a dielectric insulating layer is given in Fig. Figure 2d shows under the assumption that such a capacitor exhibits no QV hysteresis. The curve in Fig. 2d explicitly confirms the stable behavior of such a component.

[0013] The invention disclosed herein differs from the prior art in that it has a theoretical efficiency of 100% and can store the majority of the energy or information in the dielectric layer and not in the polarizable layer. This is evident from the schematic QV characteristics in Fig. 2, which highlights the conceptual advantage of using an NC capacitor. While conventional ferroelectrics with significant remanent polarization ( Fig. 2a) due to the large hysteresis, antiferroelectrics exhibit fairly low ESD and efficiency ( Fig. 2b) or relaxor-like ferroelectrics ( Fig. 2c) improved efficiency as well as ESD, because the remanent polarization is much lower at comparable maximum charge. The highest efficiency and ESD are achieved by the new concept for energy or information storage in a capacitor that uses a stack of insulating layers, one of which has a differential negative capacitance (NC), while the others have a positive capacitance (PC). Fig. 2d).

[0014] According to this invention, the improved electrostatic energy storage density achieved by technically influencing the nonlinearity of the capacitance of electrostatic capacitors is used as an energy storage element for energy storage applications. According to this invention, and without limitation, the improved electrostatic energy storage density achieved by technically influencing the nonlinearity of the capacitance of the electrostatic behavior of components with an integrated circuit element is used for data and information storage applications.

[0015] In this embodiment, an energy or information storage element comprises a first electrode, a second electrode, a first dielectric layer with positive capacitance arranged between the first and second electrode layers, and a second dielectric layer adjacent to the first dielectric layer and comprising a polarizable material. Preferably, for some applications, the second dielectric layer comprising the polarizable material is thicker than 3 nm. For the same or other applications, the first dielectric layer is thicker than the second dielectric layer. In this embodiment, the polarizable material is at least partially in a state of differential negative capacitance when a voltage is applied to the electrodes.

[0016] In one embodiment of an energy or information storage device, the polarizable material is a ferroelectric material, and fixed positive or negative charges are located at the interface between the first and second dielectric layers, with a charge density on the order of the remanent polarization of the ferroelectric material. For some ferroelectric materials, the amount of charge located between the first and second dielectric layers is in the range of 5 µC / cm². 2 and 100 µC / cm 2 In another embodiment, the polarizable material is an antiferroelectric or relaxor-like material with no charge or with charges of less than 1 µC / cm². 2 , which are located between the first and second layers.

[0017] In one embodiment, the polarizable material described above is a ferroelectric material and the stack consists of a ferroelectric (312) and a dielectric layer (311) ( Fig. 3a). In the case of the FE / DE stack, fixed or interface charges σ IF (320) is introduced at the interface between the FE and DE layers to stabilize the PC state in the FE layer when the voltage is zero. In this way, depolarization fields in the FE layer are greatly reduced. In the DE layer, the displacement field is zero (D d =0). This fixed charge at the interface between the layers is comparable to the spontaneous polarization P f of the FE layer. The fixed charges can be of positive or negative polarity, depending on the direction of the ferroelectric polarization. For negatively fixed charges, P exhibits fto the interface (320) and in the case of positive fixed charges, P f away from the interface. The amount of fixed charges should correspond to the extent of spontaneous polarization P. fThe fixed charges (320) at the interface of the ferroelectric material (312) with the NC effect and the dielectric material (311) can be achieved, for example, by electrons that are trapped in states of low-energy defects at the interface. In another embodiment, a lattice mismatch between the FE and DE materials introduces these charges. In another embodiment, lattice defects cause free valences of the atoms at the interface, which introduce these free charges. In yet another embodiment, doping the polarizable material with the NC effect or the dielectric material at the interface with a dopant having higher or lower valences compared to the material with the NC effect or the dielectric material introduces these charges.

[0018] The highest ESD can be achieved by precisely matching the NC (non-volatile) capacity of the FE layer with the PC (polycyclic aromatic hydrostatic) capacity of the DE layer. This can be accomplished, for example, by varying the thickness of the FE and DE layers or by using materials with different relative permittivities. Additionally, increasing the thickness of the DE layer relative to the FE layer will further increase the ESD, as the majority of the energy is stored in the DE layer—more than 50% and typically more than 80%.

[0019] In another embodiment, the polarizable material is a stack of an antiferroelectric material, and the stack consists of an antiferroelectric and a dielectric layer. In the case of the AFE / DE stack, no fixed charges should be introduced at the interface between the AFE and DE layers, since the AFE material is always in a PC state without an applied voltage. The highest ESD can be achieved by precisely matching the capacitances of the NC (non-polarizing) of the AFE layer with the PC of the DE layer. This can be done, for example, by varying the thickness of the AFE and DE layers or by using materials with different relative permittivities. Additionally, increasing the thickness of the DE layer relative to the AFE layer will increase the ESD, since most of the energy is stored in the DE layer.

[0020] The novel concept for an energy storage element, which utilizes a stack of insulating layers, one of which exhibits differential negative capacitance (NC) while the others exhibit positive capacitance (PC), can also be used in memory cells for data or information storage. Insulators exhibiting differential NC are polarizable materials, such as ferroelectric (FE) or antiferroelectric (AFE) materials, whereas conventional dielectric (DE) materials exhibit exclusively PC. According to this invention, the majority of the information in the memory cell is stored in the dielectric materials (typically more than 80%). Only a smaller proportion is stored in the polarizable material.

[0021] In this embodiment, an integrated circuit element comprises a first electrode, a second electrode, a first dielectric layer with positive capacitance arranged between the first and second electrodes, and a second dielectric layer adjacent to the first dielectric layer and comprising a polarizable material, wherein the first dielectric layer is thicker than the second dielectric layer. In this embodiment, the polarizable material forming part of the second dielectric layer is at least partially in a state of differential negative capacitance when a voltage is applied to the electrodes.

[0022] In one embodiment of an integrated circuit element, the polarizable material is a ferroelectric material, and fixed positive or negative charges are located at the interface between the first and second dielectric layers, with a charge density on the order of the remanent polarization of the ferroelectric material. In another embodiment, the polarizable material is an antiferroelectric or relaxor-type material, and charges of less than 1 µC / cm² are located between the first and second dielectric layers. 2 .

[0023] One embodiment of an integrated circuit element according to the invention is a capacitor structure, a second embodiment is a transistor structure. Both structures are used for memory and logic components. Therefore, one embodiment of the integrated circuit element is a memory component, another embodiment is a logic component. Furthermore, the integrated circuit element is used as a piezoelectric component, a pyroelectric component, or an energy storage component.

[0024] In one embodiment of the memory element in a memory cell, the polarizable material is a ferroelectric material, and the stack consists of a ferroelectric and a dielectric layer. In the case of the FE / DE stack, fixed charges are introduced at the interface between the FE and DE layers to stabilize the polarization-positive (PC) state in the FE layer when the voltage is zero. This significantly reduces depolarization fields in the FE layer. The maximum amount of stored charge can be achieved by precisely matching the capacitances of the neutral density (NC) of the FE layer with the PC of the DE layer. This can be accomplished, for example, by varying the thickness of the FE and DE layers or by using materials with different relative permittivities.In typical ferroelectric materials such as doped HfO2, the amount of charge located between the first and second dielectric layers is in the range of 5 µC / cm. 2 and 50 µC / cm 2 .

[0025] In another embodiment of the memory cell, the polarizable material is a stack of an antiferroelectric material, and the stack consists of an antiferroelectric and a dielectric layer. In the case of the AFE / DE stack, no fixed charges should be introduced at the interface between the AFE and DE layers, since the AFE material is always in a PC state without an applied voltage. For typical antiferroelectric materials such as ZrO₂ or Si-doped HfO₂, the amount of charge located between the first and second dielectric layers is less than 1 µC / cm². 2The highest amount of stored charge can be achieved by precisely matching the NC (non-volatile) capacitance of the AFE layer with the PC (polycyclic aromatic hydrocarbon) capacitance of the DE layer. This can be accomplished, for example, by varying the thickness of the AFE and DE layers or by using materials with different relative permittivity.

[0026] By applying a positive voltage V1 to a FE / DE capacitor, as described above and in Fig. As shown in 3b, the ferroelectric polarization P increases. f In the positive capacitance characteristic, the charge Q increases only slowly, resulting in a rather small increase in charge Q and thus in stored energy with increasing voltage. Here, the FE layer exhibits its PC characteristic. However, the total capacitance increases with increasing voltage. By further increasing the voltage to V2 > V1, as in Fig. As shown in Figure 3c, the FE material enters the NC region, where a small change in the external voltage leads to a large increase in charge and thus also in the stored energy. The electric field within the dielectric (E d ) is amplified, while the field within the ferroelectric (E f ) is moderate and in this example even changes its sign. Ideally, the NC capacitor should be operated in this range, as the voltage gain effect is reduced at higher voltages, where the ferroelectric material enters its second PC range.

[0027] An example of an embodiment of the NC capacitor is a metal-ferroelectric insulator-metal (MFIM) capacitor, which is a ferroelectric Hf 0.5 Zr 0.5The O2 (HZO) layer and a dielectric layer of Ta2O5 thin films, as described, are used. The metal-ferroelectric-insulator-metal (MFIM) capacitors can be fabricated on substrates such as Si substrates with a native SiO2 layer. The lower electrodes consist of TiN with a thickness in the range of 10 to 100 nm. In a specific embodiment described herein, a thickness of 12 nm is used. TiN can be reactively sputtered in a physical vapor deposition tool at room temperature. Subsequently, Hf 0.5 Zr 0.5O₂ (HZO) layers are grown by atomic layer deposition (ALD) at a temperature between 200 °C and 300 °C. In a specific embodiment described herein, a temperature of 260 °C was used. TEMA-Hf and TEMA-Zr are used as precursors for the ALD growth of the HZO layer. Water or ozone can be used as the oxygen source. Alternating ALD cycles of TEMA-Hf and TEMA-Zr should be applied to achieve a homogeneous distribution of Hf and Zr in the layers. The Ta₂O₅ layer can be fabricated by reactive sputtering of Ta₂O₅ at room temperature after the ALD of HZO. The upper TiN electrodes can be deposited in the same manner as the lower electrodes. After deposition of the upper electrodes, crystallization of the HZO layers is achieved by annealing the samples. Preferably, the annealing is carried out at Ta2O5 for 20 s at 500 °C in a nitrogen atmosphere.The etching of the capacitor can be achieved either by wet etching or plasma-assisted gas etching.

[0028] Fig. Figure 4 shows experimental data for a TiN / HZO / Ta2O5 / TiN capacitor as described above, using pulsed electrical measurement techniques. The integrated charges during charging (filled symbols, Q) c ) and unloading (outlined symbols, Q d ) are as a function of the applied voltage in Fig. 4b shown. By integrating the area above the QV curve, the energy required to charge the capacitor is obtained (filled symbols, W). c ) and the energy recovered during discharge (outlined symbols, W d ) calculates what is in Fig. 4c can be seen. The energy storage efficiency can then be calculated as Efficiency = (WC - Wd) / WC

[0029] When examining efficiency as a function of discharge energy density, as in Fig. As shown in 4d, even at very high densities over 100 J / cm³, energy levels can be achieved. 3 Efficiencies exceeding 95% can be achieved.

[0030] Various structures for energy storage and energy storage applications are provided according to the present invention. Planar structures are typically used, as in Fig. 5a to 5c are shown. In this embodiment, material exhibiting a differential NC effect (512) is located under ( Fig. 5a) or via ( Fig. 5b) arranged in the material exhibiting a PC (511), with both being located between an upper electrode (501) and a lower electrode (502). In this embodiment, the polarizable material exhibiting the differential NC effect is a ferroelectric material (512), and negative charges (520) are located at the interface with the material exhibiting a PC (511). In another embodiment, fixed positive charges are located at the interface instead of negative charges (520).

[0031] Fig. 5c describes an embodiment with an antiferroelectric material that exhibits the differential NC effect (513).

[0032] It is understood that additional layers between the electrodes and the polarizable material exhibiting the differential NC effect, and between the electrodes and the material exhibiting PC, can be used to improve the reliability of the NC capacitor or to reduce charge stasis effects. Furthermore, it is understood that an intermediate layer can be used between the polarizable material exhibiting the differential NC effect and the capacitor, thereby forming multiple layers to improve the polarizability of the material. Additionally, the material exhibiting the PC effect can consist of different materials and / or different layers to improve the reliability or energy density of the NC capacitor, e.g., a stack of two PC layers, one of which has a very high electronic bandgap, while the other PC layer has a very high relative permittivity.

[0033] The materials described herein are most advantageously processed as thin films. To improve energy storage density, 3D structures are used. Fig. Figure 5d shows a 3D structure of such an embodiment in cross-section. From top to bottom, the structure can resemble a circle, an oval, a trench, or any other type of structure. In this embodiment, the material exhibiting the differential NC effect (512) is located below the material exhibiting the PC effect (511). In other embodiments of the 3D structures, the material exhibiting the differential NC effect is located above the material exhibiting the PC effect. Both are situated between an upper electrode (501) and a lower electrode (502). In this embodiment, the polarizable material exhibiting the differential NC effect is a ferroelectric material (512), and negative charges (520) are located at the interface with the material exhibiting a PC effect (511).In another embodiment, which uses a ferroelectric material exhibiting an NC effect, positive charges are present at the interface with the material exhibiting the PC effect. In yet another embodiment, an antiferroelectric layer is used instead of the ferroelectric layer (512), and no charges are present at the interface with the PC layer.

[0034] In Fig. Figure 5e depicts an energy storage cell as an application for charging systems that utilize electrical energy, in combination with a charging and load element used for charging components and recharging the energy storage cell. In this embodiment, the polarizable material exhibiting the differential NC effect is a ferroelectric material (512), and negative charges (520) are located at the interface with the material exhibiting a PC effect (511). The upper electrode (501) and a lower electrode (502) are connected to a charging and load unit (530).

[0035] Fig. 6a and Fig. Figure 6b illustrates two examples of storage application concepts according to the invention based on capacitor and transistor integration. Fig. Figure 6a illustrates a cross-sectional view of an embodiment of an integrated circuit relating to the inventive concept described herein, including a planar one-transistor-one-capacitor (1T-1C) memory cell utilizing a polarizable material exhibiting the differential NC effect and a dielectric material exhibiting PC. The memory cell comprises source / drain regions (640, 645) formed in a bulk substrate support (650), such as a silicon substrate. A gate layer stack (660) is formed on a surface of the support (650), located between the source region (645) and the drain region (650). A bit line (670) is formed on the source region (645), and a word line (665) is formed on the gate layer (660).A storage element according to the inventive concept described herein is coupled to the drain region (640) by a contact (680). In particular, in this embodiment, the polarizable material exhibiting the differential NC effect is a ferroelectric material (612), and negative charges (520) are located at the interface with the material exhibiting a PC effect (611). Thus, the storage element according to the inventive concept described herein is a ferroelectric material (612). Fig. The arrangement shown in 6a is formed.

[0036] Fig. Figure 6b illustrates a cross-sectional view of an embodiment of an integrated circuit relating to the inventive concept described herein, including a planar single-transistor (1T) memory cell in which the memory layer is incorporated into the gate stack. As in the Fig. The structure shown in 6a includes the memory cell of Fig. 6b Source / drain regions (645), (640) formed in a bulk carrier (650), and a bit line (670) formed on the source layer (645). In this embodiment, the polarizable material exhibiting the differential NC effect is a ferroelectric material (612), and negative charges (520) are located at the interface with the material exhibiting a PC effect (611). The material exhibiting a PC effect (611) forms a layer on the surface of a carrier layer (650) extending between the source regions (645) and the drain region (640). A metal electrode (601) is formed on the ferroelectric layer (612), and a word line is formed on a metal electrode (665). In this way, the Fig.The structure shown in Figure 6b is incorporated into the gate stack and is formed by the support layer (650), an insulating layer (620) which partially uses a polarizable material that exhibits the differential NC effect, an insulating layer which uses a dielectric material that exhibits the PC effect (611), and the metal electrode (601).

[0037] The electrodes of the embodiments described herein may comprise one or more suitable conductive metals, including, but not limited to, TiN, TaN, TaCN, WCN, Ru, Re, RuO, Pt, Ir, IrO, Ti, TiAlN, TaAlN, W, WN, C, Si, Ge, SiGe, and NbCN. The electrodes may be a combination of one or more conductive layers. It is understood that one of the electrodes described herein may be a substrate.

[0038] The ferroelectric material and the antiferroelectric material, as the terms are used herein, refer to a material that is at least partially in a ferroelectric state or an antiferroelectric state, and further comprise as principal components oxygen and any element of the group consisting of Hf, Zr, and (Hf, Zr). For example, the ferroelectric material may be any combination of HfO₂, ZrO₂, or any ratio of Hf and Zr in combination with oxygen (e.g., Zr). x Hf 1-xO2, where x < 1) and any combination thereof. Furthermore, the term "principal components" as used herein refers to any suitable number of O and of any element or combinations of Hf, Zr and (Hf, Zr) per volumetric content, e.g., unit cell, which is greater than that of any other components or further additives incorporated in any suitable manner into an oxide layer of ferroelectric material.

[0039] The antiferroelectric material can be of a field-induced ferroelectric type of layer, which Zr a X b O2 comprises, where X is an element of the periodic table with a smaller ionic radius than Zr and a > 0, b > 0. Suitable X elements can be one of Hf, Si, Al, Ge, elements of the second group of the periodic table, and a > 0, b > 0. In addition to this combination, the antiferroelectric material Hfa X b O2, where X is an element of the periodic table with a smaller ionic radius than Hf and a > 0, b > 0. Suitable elements for this combination can be any of the elements in the second group of the periodic table (Zr, Si, Al, Ge), where, as above, a > 0, b < 0.

[0040] Another possibility for the antiferroelectric material is that it is of the field-induced ferroelectric type, consisting of a pure ZrO2 layer or comprising a dielectric material based on ZrO2 or HfO2.

[0041] A third possibility for the antiferroelectric material is that it consists of a relaxor-like ferroelectric material (e.g., BaTiO3 or PbMg). 1 / 3 Note 2 / 3 O3). And a fourth possibility for the antiferroelectric material is that it consists of an antiferroelectric-like material such as PbZrO3.

[0042] The dielectric material with positive capacitance includes SiO2, Al2O3 or rare earth oxides.

[0043] In the MFIM or MIFM structure, the electrode layer can be deposited over a support structure using any suitable process. Some examples of formation processes that can be used to form conductive layers include, but are not limited to, atomic layer deposition (ALD), metal-organic atomic layer deposition (MOALD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), or any other suitable deposition technique that enables the formation of the conductive layers using one or more suitable conductive materials as described above. The conductive layer can be formed with a suitable thickness dimension, for example, in the range of about 2 nm to about 5000 nm. In one embodiment, the thickness range for the conductive layer can be in the range of about 2 nm to about 500 nm or in the range of about 2 nm to about 50 nm.

[0044] In each embodiment, the dielectric layer and the polarizable layer can be formed using any atomic layer deposition (ALD), metal-organic atomic layer deposition (MOALD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), sol-gel, or any other suitable deposition technique that enables the formation of the layer containing the polarizable material as described herein (e.g., oxygen and at least one of Hf and Zr), wherein the growth of each layer can be single-crystalline, polycrystalline, or amorphous with subsequent crystallization by a thermal process. Any suitable number and type of precursors can be used to introduce elements such as Hf and Zr into the layer using any of the techniques described herein.The dielectric layer and the polarizable layer are formed with a suitable thickness, e.g., in the range of approximately 2 nm to approximately 5000 nm. In one embodiment, the thickness range for both layers can be in the range of approximately 2 nm to approximately 500 nm or in a range of approximately 2 nm to approximately 50 nm.

Claims

[1] Integrated circuit element comprising the following: a first electrode (101, 301, 501, 601), a second electrode (102, 302, 502, 602) and a first dielectric layer (111, 311, 511, 611) with positive capacitance, which is arranged between the first and the second electrode layer, and a second dielectric layer (106, 312, 512, 612) adjacent to the first dielectric layer (111, 311, 511, 611) comprising a polarizable material, wherein the first dielectric layer (111, 311, 511, 611) is thicker than the second dielectric layer (106, 312, 512, 612). [2] Integrated circuit element comprising the following: a first electrode (101, 501), a second electrode (102, 502) and a first dielectric layer (111, 511) with positive capacitance, which is arranged between the first and second electrode layers, and a second dielectric layer (106, 513) adjacent to the first dielectric layer (111, 511) comprising a polarizable material, wherein the polarizable material is at least partially in a state of differential negative capacitance and wherein the polarizable material is an antiferroelectric or relaxor-type material. [3] Integrated circuit element suitable for storing energy or information and comprising the following: a first electrode (101, 501, 601), a second electrode (102, 502) and a first dielectric layer (111, 311, 511, 611) with positive capacitance, which is arranged between the first and the second electrode layer, and a second dielectric layer (106, 513) adjacent to the first dielectric layer (111, 311, 511, 611) comprising a polarizable material, wherein the polarizable material is at least partially in a state of differential negative capacitance, and more than 50% of the energy or information stored by the circuit element is stored in the first dielectric layer (111, 311, 511, 611). [4] Integrated circuit element according to claim 3, wherein the polarizable material is a ferroelectric material. [5] Integrated circuit element according to claim 1 or 3, wherein the polarizable material is a ferroelectric material and charges are located at the interface between the first and the second dielectric layer (111, 311, 511, 611; 106, 312, 512, 612). [6] Integrated circuit element according to claim 5, wherein fixed positive or fixed negative charges with a charge density on the order of approximately the remanent polarization of the ferroelectric material are located at the interface between the first and the second dielectric layer (111, 311, 511, 611; 106, 312, 512, 612). [7] Integrated circuit element according to claim 6, wherein charges of between 5 µC / cm are located between the first and the second dielectric layer (111, 311, 511, 611; 106, 312, 512, 612). 2 and 50 µC / cm 2 condition. [8] Integrated circuit element according to claim 1 or 3, wherein the polarizable material is an antiferroelectric or relaxor-type material. [9] Integrated circuit element according to claim 2 or 8, wherein charges of less than 1 µC / cm are located between the first and the second dielectric layer (111, 511; 106, 513). 2 condition. [10] Integrated circuit element according to one of claims 1 to 3, wherein one of the two electrodes (101, 301, 501, 601; 102, 302, 502, 602) is a substrate. [11] Integrated circuit element according to any one of claims 1 to 3, wherein the electrodes (101, 301, 501, 601; 102, 302, 502, 602) comprise TiN, TaN, TaCN, WCN, Ru, Re, RuO, Pt, Ir, IrO, Ti, TiAlN, TaAlN, W, WN, C, Si, Ge, SiGe and NbCN. [12] Integrated circuit element according to any one of claims 1 to 3, wherein the first dielectric layer (111, 311, 511, 611) comprises Al2O3, SiO2 or rare earth oxides. [13] Integrated circuit element according to claim 2, 4, 5 or 8, wherein the ferroelectric or antiferroelectric material comprises oxygen and any one of the group consisting of Hf, Zr and (Hf,Zr) as its main components. [14] Integrated circuit element according to claim 1 or 2, wherein the integrated circuit element is a capacitor or a transistor structure. [15] Integrated switching element according to claim 1 or 2, wherein the integrated circuit element is a memory or logic element. [16] Integrated circuit element according to claim 1 or 2, wherein the integrated circuit element is a piezoelectric component or a pyroelectric component. [17] Integrated circuit element according to claim 1 or 2, wherein the integrated circuit element is an energy storage element. [18] Energy storage element comprising the following: a first electrode (101, 301, 501, 601), a second electrode (102, 302, 502, 602) and a first dielectric layer (111, 311, 511, 611) with positive capacitance, which is arranged between the first and the second electrode layer, and a second dielectric layer (106, 312, 512, 612) adjacent to the first dielectric layer (111, 311, 511, 611) comprising a polarizable material, wherein the first dielectric layer is thicker than the second dielectric layer. [19] Energy storage element comprising the following: a first electrode (101, 501), a second electrode (102, 502) and a first dielectric layer (111, 511) with positive capacitance, which is arranged between the first and second electrode layers, and a second dielectric layer (106, 513) adjacent to the first dielectric layer (111, 511) comprising a polarizable material, wherein the polarizable material is at least partially in a state of differential negative capacitance and wherein the polarizable material is an antiferroelectric or relaxor-type material. [20] Energy storage element comprising the following: a first electrode (101, 501, 601), a second electrode (102, 502) and a first dielectric layer (111, 311, 511, 611) with positive capacitance, which is arranged between the first and the second electrode layer, and a second dielectric layer (106, 513) adjacent to the first dielectric layer (111, 311, 511, 611) comprising a polarizable material, wherein the polarizable material is at least partially in a state of differential negative capacitance and more than 50% of the energy is stored in the first dielectric layer (111, 311, 511, 611). [21] Energy storage element according to claim 18 or 20, wherein the polarizable material is a ferroelectric material and fixed positive or fixed negative charges with a charge density on the order of about the remanent polarization of the ferroelectric material are located at the interface between the first and the second dielectric layer (111, 311, 511, 611; 106, 312, 512, 612). [22] Energy storage element according to claim 18 or 20, wherein the polarizable material is an antiferroelectric or relaxor-type material. [23] Energy storage element according to claim 19 or 22, wherein charges of less than 1 µC / cm are located between the first and the second dielectric layer (111, 511; 106, 513). 2 condition. [24] Energy storage element according to claim 18 or 19, wherein more than 50% of the energy is stored in the first dielectric layer.

Images