INTEGRATED CIRCUIT PACKAGE AND METHOD

Abstract

Device comprising: a first package component (400A, 400B, 400C), comprising: a first integrated circuit die (405); a first encapsulation substance (406) which at least partially surrounds the first integrated circuit die (405); and a redistribution structure (430) on the first encapsulation substance (406) and coupled to the first integrated circuit die (405); a second package component (100A, 100B, 100C) bonded to the first package component (400A, 400B, 400C), the second package component having: an integrated passive device (50A); and a second encapsulation substance (120) which at least partially surrounds the integrated passive device (50A); and a power module (160A, 160B) that is attached to the first package component (400A, 400B, 400C) by the second package component (100A, 100B, 100C), and wherein the power module (160B) is coupled to the second package (100A, 100B, 100C) by means of spring-type contacts (166).

Description

BACKGROUND

[0001] The semiconductor industry has experienced rapid growth thanks to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely due to repeated reductions in the minimum feature size, which allows more components to be integrated into a given area. With the increasing demand for ever-smaller electronic devices, a need has arisen for smaller and more creative techniques for packaging semiconductor die. One example of such packaging systems is package-on-package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on top of a lower semiconductor package to provide a high level of integration and component density.PoP technology generally enables the production of semiconductor devices with improved functionalities and a small footprint on a printed circuit board (PCB).

[0002] US 2016 / 0 329 272 A1 describes examples of a stacked semiconductor device package and related techniques and configurations. US 2002 / 0 012 231 A1 discloses a heat sink comprising one side including a structural element defining a distance between a heat-generating structure and the second side of the heat sink. US 2010 / 0 091 537 A1 discloses an integrated circuit package comprising an interface chip and a separate memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It is noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be exaggerated or reduced as desired to facilitate clarity of discussion. Fig. 1-4, 5A, 5B, 6-15, 16A-16C, 17A-17C, 18A-18E show cross-sectional views of intermediate steps during a process for forming first packages according to some embodiments. Fig. 19-24 show cross-sectional views of intermediate steps during a process for forming a system-on-wafer (SoW) package according to some embodiments. Fig. 25-32 show cross-sectional views of intermediate steps during a process for forming a packaged device according to some embodiments. Fig. 33-38 show top views of packaged devices according to some embodiments. DETAILED DESCRIPTION

[0004] The invention is defined by claim 1, which defines an apparatus, and claim 7, which defines a method. Embodiments of the invention are provided by the dependent claims, the description, and the figures. The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure.For example, in the following description, the formation of a first feature over or on top of a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not automatically dictate a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used in this document for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or in other orientations), and the spatially relative terms used in this document may be interpreted accordingly.

[0006] Although embodiments are described in detail below, a general description of the present disclosure is provided in this document. Fundamentally, the embodiments described in this document provide a package in which integrated passive devices (IPDs) are packaged in a system-on-wafer (SoW) package (e.g., a super-large fan-out wafer-scale package) by stacking IPD packages between a power module (sometimes referred to as a socket) and an integrated fan-out (InFO) structure. SoW packages of the embodiments may include any combination of interconnected functional dies in a package area of ​​10,000 mm 2or larger. For example, the interconnected functional dies within a SoW package can provide each component of a complete electrical system to enable high-performance computing (HPC) (e.g., an accelerator of an artificial intelligence (AI) server, a cloud computing system, an edge computing system, or the like) in a data center application, a server application, or the like. The power modules can be connected to the functional dies of the SoW package through the IPD packages. Each power module can provide power management for a single functional die or multiple functional dies within the SoW package.

[0007] Advantageous features of some or all of the embodiments described in this document may include a shorter distance between IPDs and the functional dies, which may improve the performance of the power distribution network (PDN). Some embodiments may provide for the integration of 3D-stacked IPDs with InFO processes, thus making the use of the embodiments practical. In some embodiments, 3D stacking of IPDs avoids the need to remove ball grid array (BGA) connectors from the socket landscape (e.g., the footprint of a package), enabling improved power handling through an increased area (e.g., more BGA connectors) for power handling.

[0008] Fig. 1 to 16C show cross-sectional views of intermediate steps during a process for forming a first package component 100 according to some embodiments. According to various embodiments, the first package component 100 is an IPD package comprising one or more IPDs arranged between a module (e.g., a module 160 shown in Fig. 17A-17C) and a SoW package (e.g., a SoW package 400 shown in Fig. 24) can be implemented. Fig. 1 shows a first package region 101A and a second package region 101B in which one or more IPDs, for example IPDs 50A, which will be referred to below in Fig. 4 are discussed, can be housed.

[0009] In Fig. 1, a carrier substrate 102 is provided, and a separation layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer, so that multiple packages can be formed simultaneously on the carrier substrate 102.

[0010] The release layer 104 may be formed from a polymer-based material that can be removed along with the support substrate 102 from overlying structures formed in subsequent steps. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesion when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultraviolet (UV) adhesive that loses its adhesion when exposed to UV light. The release layer 104 may be dispensed and cured as a liquid, may be a laminate film laminated to the support substrate 102, or the like. A top surface of the release layer 104 may be leveled and may have a high degree of planarity.

[0011] In Fig. 2, a backside redistribution structure 106 may be formed on the isolation layer 104. In the illustrated embodiment, the backside redistribution structure 106 includes a dielectric layer 108, a metallization structure 110 (sometimes referred to as redistribution layers or redistribution lines), and a dielectric layer 112. The backside redistribution structure 106 is optional. In some embodiments, a dielectric layer without metallization structures is formed on the isolation layer 104 instead of the backside redistribution structure 106.

[0012] The dielectric layer 108 may be formed on the separation layer 104. The bottom surface of the dielectric layer 108 may be in contact with the top surface of the separation layer 104. In some embodiments, the dielectric layer 108 is formed from a polymer, for example, polybenzoxazole (PBO), polyimide, benzocylcobutene (BCB), or the like. In other embodiments, the dielectric layer 108 is formed from: a nitride, for example, silicon nitride; an oxide, for example, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer 108 may be formed by any acceptable coating method, for example, spin coating, chemical vapor deposition (CVD), lamination, the like, or a combination thereof.

[0013] The metallization structure 110 may be formed on the dielectric layer 108. For example, the metallization structure 110 may be formed by first forming a seed layer over the dielectric layer 108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to the metallization structure 110.Patterning creates openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by a permissible ashing or ablation process, for example, a process using an oxygen plasma or the like. Once the photoresist has been removed, exposed portions of the seed layer are removed using a permissible etching process, such as wet or dry etching.The remaining portions of the seed layer and the conductive material form the metallization structure 110.

[0014] The dielectric layer 112 may be formed on the metallization structure 110 and the dielectric layer 108. In some embodiments, the dielectric layer 112 is formed from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. In other embodiments, the dielectric layer 112 is formed from: a nitride, for example, silicon nitride; an oxide, for example, silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 112 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 112 may be patterned to form openings 114 that expose portions of the metallization structure 110.The patterning may be performed by a permissible process, for example, by exposing the dielectric layer 112 if the dielectric layer 112 is a photosensitive material, or by etching, for example, using an anisotropic etchant. In embodiments where the dielectric layer 112 is a photosensitive material, the dielectric layer 112 may be developed after exposure.

[0015] It should be appreciated that the backside redistribution structure 106 may include any number of dielectric layers and metallization structures. If more dielectric layers and metallization structures are to be formed, the steps and processes discussed above may be repeated. The metallization structures may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization structures by forming the seed layer and the conductive material of the metallization structure in an opening of the underlying dielectric layer. The conductive vias may thus interconnect and electrically couple the various conductive lines of the metallization structures.

[0016] In Fig. 3, vias 116 are formed in the openings 114 and extend over a top dielectric layer of the rear redistribution structure 106 (e.g., the dielectric layer 112 in the case of the Fig. 3). For example, the vias 116 may be formed by first forming a seed layer over the backside redistribution structure 106, e.g., on the dielectric layer 112 and portions of the metallization structure 110 exposed through the openings 114. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and exposed for patterning.The pattern of the photoresist corresponds to the vias 116. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an allowable ashing or ablation process, for example, by using a process employing an oxygen plasma or the like.Once the photoresist has been removed, exposed portions of the seed layer are removed using a permissible etching process, such as wet or dry etching. The remaining portions of the seed layer and conductive material form the vias 116.

[0017] In Fig. 4, dies 50 comprising IPDs 50A, discrete passive devices 50B, and active device dies 50C are bonded to the dielectric layer 112 using an adhesive 118. A desired type and number of dies 50 are bonded in each of the first package region 101A and the second package region 101B. In various embodiments, passive devices, such as the IPDs 50A and the discrete passive devices 50B, may occupy an area greater than 50 percent in each of the first package region 101A and the second package region 101B. In the illustrated embodiment, a plurality of dies 50 are bonded adjacent to one another. The IPDs 50A and the active device dies 50C are each described below with reference to Fig. 5A and 5B are described in more detail.

[0018] The discrete passive devices 50B may, for example, include one or more discrete capacitors, inductors, combinations thereof, or the like. When multiple discrete passive devices 50B are disposed in each of the first package region 101A and the second package region 101B, the discrete passive devices 50B may be bonded together in a stacked configuration (as shown) or disposed side by side directly on the backside redistribution structure 106. As shown in Fig. 4, each of the discrete passive devices 50B may include a semiconductor substrate 52B, vias 53B extending through the semiconductor substrate 52B, pads 62B disposed over the semiconductor substrate 52B and the vias 53B, passivation layers 64B disposed on the semiconductor substrate 52B and the pads 62B, and die connectors 66B extending through the passivation layers 64B. The discrete passive devices 50B and the active device dies 50C are optional, and in some embodiments, the discrete passive devices 50B and / or the active device dies 50C may be omitted from the first package region 101A and / or the second package region 101B.

[0019] The IPDs 50A, the discrete passive devices 50B, and the active device dies 50C may have different sizes (e.g., different heights and / or surface areas) or may have the same size (e.g., the same height and / or surface area). The space available for the vias 116 in the first package region 101A and the second package region 101B may be limited, particularly when the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C comprise devices with a large footprint, such as SoCs. The use of the backside redistribution structure 106 enables an improved interconnect arrangement when limited space is available for the vias 116 in the first package region 101A and the second package region 101B.

[0020] The adhesive 118 is on the backsides of the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C and adheres the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C to the backside redistribution structure 106, for example, to the dielectric layer 112. The adhesive 118 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 118 may be applied to the backsides of the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C, or may be applied over the surface of the dielectric layer 112 on the carrier substrate 102.For example, the adhesive 118 may be applied to the backsides of the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C prior to singulation to separate the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C.

[0021] Fig. 5A shows an IPD 50A according to some embodiments. The IPD 50A may include a wide variety of passive devices, such as baluns, couplers, splitters, filters, diplexers, inductors, capacitors, resistors, or the like. In some embodiments, the IPD 50A may be a multilayer ceramic capacitor (MLCC), a coil inductor, a film resistor, or the like. According to some embodiments, no active devices such as transistors or diodes are present in the IPD 50A.

[0022] The IPD 50A may be formed in a wafer, which may include various device regions that are singulated in subsequent steps to form a plurality of the IPDs 50A. The IPD 50A may be processed according to applicable manufacturing processes to form integrated circuits. For example, the IPD 50A may include a semiconductor substrate 52A, such as silicon, doped and undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52A may include: other semiconductor materials, such as germanium; a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used.The semiconductor substrate 52A has an active surface (e.g., the upward-facing surface in . Fig. 5A), sometimes referred to as the front surface, and an inactive surface (e.g. the downward-facing surface in Fig. 5A), sometimes referred to as the back.

[0023] An interlayer dielectric (ILD) 56A is formed over the front surface of the semiconductor substrate 52A. The ILD 56A may include one or more dielectric layers formed from materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0024] An interconnect structure 60A is provided over the ILD 56. The interconnect structure 60A can be used to interconnect various passive devices included in the IPD 50A. The interconnect structure 60A can further define the various passive devices included in the IPD 50A. For example, a region 70A of the interconnect structure 60A can define a resistor, a region 70B of the interconnect structure 60A can define a capacitor, and a region 70C of the interconnect structure 60A can define an inductor. However, each of the regions 70A, 70B, and 70C can define any passive devices of the IPD 50A.

[0025] The interconnect structure 60A may be formed, for example, by metallization structures in dielectric layers on the ILDA 56. The metallization structures include metal lines and vias formed in one or more low-k dielectric layers. The metallization structures of the interconnect structure 60A are electrically coupled to the passive devices of the IPD 50A.

[0026] The IPD 50A further includes pads 62A, for example, aluminum pads, to which external connections are made. The pads 62A are on the front side of the IPD 50A, for example, in and / or on the interconnect structure 60A. One or more passivation films 64A are on the IPD 50A, for example, on portions of the interconnect structure 60A and the pads 62A. Openings extend through the passivation films 64A to the pads 62A. Die connectors 66A, for example, conductive pillars (formed, for example, from a metal such as copper), extend through the openings in the passivation films 64A and are physically and electrically connected to corresponding ones of the pads 62A. The die connectors 66A can be formed, for example, by plating or the like. The die connectors 66A electrically couple the respective passive devices of the IPD 50A to external devices.

[0027] Optionally, solder regions (e.g., solder balls or solder bumps) can be arranged on the pads 62A. The solder balls can be used to perform chip probe tests (CP tests) on the IPD 50A. CP tests can be performed on the IPD 50A to determine whether the IPD 50A is a known good die (KGD). Thus, only IPD 50A that are KGDs are subsequently processed and packaged, and dies that fail the CP tests are not packaged. After the tests, the solder regions can be removed in subsequent processing steps.

[0028] A dielectric layer 68A may be provided on the front side of the IPD 50A, for example, on the passivation films 64A and the die connectors 66A. The dielectric layer 68A laterally encapsulates the die connectors 66A, and the dielectric layer 68A laterally terminates with the IPD 50A. First, the dielectric layer 68A may conceal the die connectors 66A such that a top surface of the dielectric layer 68A is above top surfaces of the die connectors 66A. In some embodiments where solder regions are disposed on the die connectors 66A, the dielectric layer 68A may also conceal the solder regions. Alternatively, the solder regions may be removed prior to forming the dielectric layer 68A.

[0029] The dielectric layer 68A may be: a polymer, for example, PBO, polyimide, BCB, or the like; a nitride, for example, silicon nitride or the like; an oxide, for example, silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof. The dielectric layer 68A may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, during formation of the IPD 50A, the die connectors 66A are exposed through the dielectric layer 68A. In some embodiments, the die connectors 66A remain concealed and are exposed during a subsequent process for packaging the IPD 50A. By exposing the die connectors 66A, any solder regions that may be present on the die connectors 66A can be removed.

[0030] In some embodiments, the IPD 50A may be a stacked device including a plurality of semiconductor substrates 52A. In such embodiments, the IPD 50A includes a plurality of semiconductor substrates 52A interconnected using through-substrate vias (TSVs). Each of the semiconductor substrates 52A may include an interconnect structure 60A.

[0031] Fig. 5B shows an active device die 50C according to some embodiments. The active device die 50C is packaged in subsequent processing to form an integrated circuit package. The active device die 50C may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, or the like), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth memory (HBM) die, or the like), an input / output (I / O) interface die, a power management die (e.g., a power management integrated circuit (PMIC) die, or the like), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die, or the like), a front-end die (e.g.,an analog front-end (AFE) die or the like), the like, or combinations thereof.

[0032] The active device die 50C may be formed in a wafer, which may include various device regions that are singulated in subsequent steps to form a plurality of active device dies. The active device die 50C may be processed according to applicable manufacturing techniques to form integrated circuits. For example, the active device die 50C comprises a semiconductor substrate 52C, for example, silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52C may comprise: other semiconductor materials, for example, germanium; a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 52C has an active surface (e.g., the upward-facing surface in . Fig. 5B), sometimes referred to as the front surface, and an inactive surface (e.g. the downward-facing surface in Fig. 5B), sometimes referred to as the back.

[0033] Devices 54 may be formed on the front side of the semiconductor substrate 52. The devices 54 may be active devices (e.g., transistors, diodes, or the like), capacitors, resistors, or the like. An interlayer dielectric (ILD) 56C is formed over the front side of the semiconductor substrate 52C. The ILD 56C surrounds and may cover the devices 54. The ILD 56C may include one or more dielectric layers formed from materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0034] Conductive plugs 58 extend through the ILD 56C to electrically and physically couple the devices 54. For example, if the devices 54 are transistors, the conductive plugs 58 may couple the gates and source / drain regions of the transistors. The conductive plugs 58 may be formed from tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or combinations thereof. An interconnect structure 60C is provided over the ILD 56C and the conductive plugs 58. The interconnect structure 60C interconnects the devices 54 to form an integrated circuit. The interconnect structure 60C may be formed, for example, by metallization structures in dielectric layers on the ILD 56. The metallization structures include metal lines and vias formed in one or more low-k dielectric layers.The metallization structures of the interconnect structure 60C are electrically coupled to the devices 54 by the conductive plugs 58.

[0035] The active device die 50C further includes pads 62C, for example, aluminum pads, to which external connections are made. The pads 62C are on the active side of the active device die 50C, for example, in and / or on the interconnect structure 60C. One or more passivation films 64C are on the active device die 50C, for example, on portions of the interconnect structure 60C and the pads 62C. Openings extend through the passivation films 64C to the pads 62C. Die connectors 66C, for example, conductive pillars (for example, formed from a metal such as copper), extend through the openings in the passivation films 64C and are physically and electrically coupled to corresponding ones of the pads 62C. The die connectors 66C may be formed, for example, by plating or the like. The die connectors 66C electrically couple the respective integrated circuits of the active device die 50C.

[0036] Optionally, solder regions (e.g., solder balls or solder bumps) may be disposed on pads 62C. The solder balls may be used to perform chip probe tests (CP tests) on active device die 50C. CP tests may be performed on active device die 50C to determine whether active device die 50C is a known good die (KGD). Thus, only active device dies 50C that are KGDs are subsequently processed and packaged, and dies that fail the CP tests are not packaged. After the tests, the solder regions may be removed in subsequent processing steps.

[0037] A dielectric layer 68C may be on the front side of the active device die 50C, for example, on the passivation films 64C and the die connectors 66C. The dielectric layer 68C laterally encapsulates the die connectors 66C, and the dielectric layer 68C laterally coterminates with the active device die 50C. First, the dielectric layer 68C may conceal the die connectors 66C such that a top surface of the dielectric layer 68C is above top surfaces of the die connectors 66C. In some embodiments where solder regions are disposed on the die connectors 66C, the dielectric layer 68C may also conceal the solder regions. Alternatively, the solder regions may be removed prior to forming the dielectric layer 68C.

[0038] The dielectric layer 68C may be: a polymer, for example, PBO, polyimide, BCB, or the like; a nitride, for example, silicon nitride or the like; an oxide, for example, silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof. The dielectric layer 68C may be formed, for example, by spin coating, lamination, CVD, or the like. In some embodiments, during formation of the active device die 50C, the die connectors 66 are exposed through the dielectric layer 68C. In some embodiments, the die connectors 66C remain concealed and are exposed during a subsequent process for packaging the active device die 50C. By exposing the die connectors 66C, any solder regions that may be present on the die connectors 66C can be removed.

[0039] In some embodiments, the active device die 50C is a stacked device including a plurality of semiconductor substrates 52C. For example, the active device die 50C may be a memory device such as a hybrid memory cube (HMC) module, a high-bandwidth memory (HBM) module, or the like, including a plurality of memory dies. In such embodiments, the active device die 50C includes a plurality of semiconductor substrates 52C interconnected using through-substrate vias (TSVs). Each of the semiconductor substrates 52C may include an interconnect structure 60C.

[0040] In Fig. 6, an encapsulant or encapsulant material 120 is formed on and around the dies 50 and the vias 116. Once formed, the encapsulant 120 encapsulates the vias 116, the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C. The encapsulant 120 may be a molding compound, an epoxy, or the like. The encapsulant 120 may be applied by compression molding, transfer molding, or the like and may be formed over the carrier substrate 102 such that the vias 116 and / or the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C are obscured or covered. The encapsulant 120 is further formed in gap regions between the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C.The encapsulating substance 120 can be applied in liquid or semi-liquid form and subsequently cured.

[0041] In Fig. 7, a planarization process is performed on the encapsulant 120 to expose the vias 116 and the die connectors 66A, 66B, 66C. The planarization process may also remove material from the vias 116, the dielectric layers 68A and 68C, and / or the die connectors 66A, 66B, 66C until the die connectors 66A, 66B, 66C and the vias 116 are exposed. Top surfaces of the vias 116, the die connectors 66A, 66B, 66C, the dielectric layers 68A and 68C, and the encapsulant 120 may be level with each other (e.g., coplanar) after the planarization process. The planarization process can be, for example, a chemical mechanical polishing (CMP) process, a grinding process, an etch-back process, or the like.In some embodiments, the planarization process may be omitted, for example, if the vias 116 and / or the die connectors 66A, 66B, 66C are already exposed.

[0042] In Fig. 8 to 11, a front-side redistribution structure 122 (see Fig. 11) is formed over the encapsulant 120, the vias 116, the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C. The front-side redistribution structure 122 includes: dielectric layers 124, 128, 132, and 136; and metallization structures 126, 130, and 134. The metallization structures may also be referred to as redistribution layers or redistribution lines. The Fig. The front-side redistribution structure 122 illustrated in Figure 11 includes three layers of metallization structures and four layers of dielectric layers; however, more or fewer metallization structures and dielectric layers may be incorporated into the front-side redistribution structure 122. If fewer dielectric layers and metallization structures are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization structures are to be formed, the steps and processes discussed below may be repeated.

[0043] In Fig. 8, the dielectric layer 124 is applied to the encapsulant 120, the vias 116, and the die connectors 66A, 66B, and 66C. In some embodiments, the dielectric layer 124 is formed from a photosensitive material, such as PBO, polyimide, BCB, or the like, which can be patterned using a lithography mask. The dielectric layer 124 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 124 is then patterned. The patterning forms openings that expose portions of the vias 116 and the die connectors 66A, 66B, and 66C.The patterning can be performed using a permissible process, for example, by exposing the dielectric layer 124 if the dielectric layer 124 is a photosensitive material, or by etching, for example, using an anisotropic etchant. If the dielectric layer 124 is a photosensitive material, the dielectric layer 124 can be developed after exposure.

[0044] Then, the metallization structure 126 is formed. The metallization structure 126 includes line portions (also referred to as conductive lines) on and extending along the main surface of the dielectric layer 124. The metallization structure 126 further includes via portions (also referred to as conductive vias) extending through the dielectric layer 124 to physically and electrically couple the vias 116 and the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C. For example, the metallization structure 126 may be formed by first forming a seed layer over the dielectric layer 124 and in the openings extending through the dielectric layer 124.In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. Then, a photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to the metallization pattern 126. Patterning forms openings through the photoresist to expose the seed layer. Then, a conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer.The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer forms the metallization structure 126. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by a permissible ashing or ablation process, for example, by using an oxygen plasma or the like. Once the photoresist has been removed, exposed portions of the seed layer are removed using a permissible etching process, such as wet or dry etching.

[0045] In Fig. 9, the dielectric layer 128 is applied to the metallization structure 126 and the dielectric layer 124. The dielectric layer 128 may be formed in a similar manner to the dielectric layer 124 and may be formed from a material similar to the material of the dielectric layer 124.

[0046] Then, the metallization structure 130 is formed. The metallization structure 130 includes conductive lines on and extending along the main surface of the dielectric layer 128. The metallization structure 130 further includes via portions extending through the dielectric layer 128 to physically and electrically couple the metallization structure 126. The metallization structure 130 may be formed in a similar manner to the metallization structure 126 and may be formed from a material similar to the material of the metallization structure 126. In some embodiments, the metallization structure 130 has a different size than the metallization structure 126. For example, the conductive lines and / or vias of the metallization structure 130 may be wider or thicker than the conductive lines and / or vias of the metallization structure 126.Furthermore, the metallization structure 130 may be formed with a larger pitch than the metallization structure 126.

[0047] In Fig. 10, the dielectric layer 132 is applied to the metallization structure 130 and the dielectric layer 128. The dielectric layer 132 may be formed in a similar manner to the dielectric layer 124 and may be formed from a material similar to the material of the dielectric layer 124.

[0048] Then, the metallization structure 134 is formed. The metallization structure 134 has conductive portions on the main surface of the dielectric layer 132 and extending along the dielectric layer 132. The metallization structure 134 further has via portions extending through the dielectric layer 132 to physically and electrically couple the metallization structure 130. The metallization structure 134 may be formed in a similar manner to the metallization structure 126 and may be formed from a material similar to the material of the metallization structure 126. The metallization structure 134 is the uppermost metallization structure of the front-side redistribution structure 122. Thus, all intermediate metallization structures of the front-side redistribution structure 122 (e.g.Metallization structures 126 and 130 are disposed between metallization structure 134 and IPDs 50A, discrete passive devices 50B, and active device dies 50C. In some embodiments, metallization structure 134 has a different size than metallization structures 126 and 130. For example, the conductive lines and / or vias of metallization structure 134 may be wider or thicker than the conductive lines and / or vias of metallization structures 126 and 130. Furthermore, metallization structure 134 may be formed with a larger pitch than metallization structure 130.

[0049] In Fig. 11, the dielectric layer 136 is applied to the metallization structure 134 and the dielectric layer 132. The dielectric layer 136 may be formed in a similar manner to the dielectric layer 124 and may be formed from a material similar to the material of the dielectric layer 124. The dielectric layer 136 is the uppermost dielectric layer of the front-side redistribution structure 122. Thus, all metallization structures of the front-side redistribution structure 122 (e.g., the metallization structures 126, 130, and 134) are arranged between the dielectric layer 136 and the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C. Furthermore, all intermediate dielectric layers of the front-side redistribution structure 122 (e.g.,the dielectric layers 124, 128, 132) are disposed between the dielectric layer 136 and the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C.

[0050] In Fig. 12, UBMs 138 are formed for external connection to the front-side redistribution structure 122. The UBMs 138 have bump portions on and extending along a major surface of the dielectric layer 136 and have via portions extending through the dielectric layer 136 to physically and electrically couple the metallization structure 134. As a result, the UBMs 138 are electrically coupled to the vias 116 and the IPDs 50A, the discrete passive devices 50B, and the active device dies 50C. The UBMs 138 may be formed from the same material as the metallization structure 126. In some embodiments, the UBMs 138 may have a different size than the metallization structures 126, 130, and 134.

[0051] In Fig. 13, conductive interconnects 150 are formed on the UBMs 138. The conductive interconnects 150 may be ball grid array (BGA) interconnects, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using the electroless nickel-electroless palladium-immersion gold (ENEPIG) process, or the like. The conductive interconnects 150 may comprise a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive interconnects 150 are formed by first forming a layer of solder by evaporation, electroplating, printing, solder delivery, ball placement, or the like. Once a layer of solder has been formed on the structure, reflow can be performed to form the material into the desired bump shapes.In another embodiment, the conductive connectors 150 include metal pillars (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed at the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

[0052] In Fig. 14 the structure of Fig. 13 is turned over, placed on a tape 149, and the carrier substrate 102 is separated from the rear-side redistribution structure 106, e.g., the dielectric layer 108, by debonding. According to some embodiments, debonding comprises projecting a light, such as a laser light or UV light, onto the separation layer 104 so that the separation layer 104 is decomposed under the heat of the light and the carrier substrate 102 can be removed. The structure is then turned over and placed on the tape 149.

[0053] Furthermore, in Fig. 14, the front-side redistribution structure 122 may be pre-cut. A cutting device may partially cut into the front-side redistribution structure 122 in a scribe line area between the first package region 101A and the second package region 101B to form recesses (not separately shown) in the front-side redistribution structure 122. In some embodiments, the cutting device for the pre-cutting process is a laser. The pre-cutting process may prevent delamination of the front-side redistribution structure 122 and its layers during the subsequent singulation process (see, e.g., Fig. 16A-16C).

[0054] In Fig. 15, openings 151 are formed through the dielectric layer 108 to expose portions of the metallization structure 110. The openings 151 may be formed, for example, using laser drilling, etching, or the like.

[0055] In Fig. 16A-16C, various external connectors are formed in the openings 151 to form first package components 100 in the first package region 101A and the second package region 101B. In Fig. 16A, conductive interconnects 152 are formed on the metallization structure 110 in the openings 151, thereby forming first package components 100A in the first package region 101A and the second package region 101B. The conductive interconnects 152 may be ball grid array (BGA) interconnects, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using the electroless nickel-electroless palladium-immersion gold (ENEPIG) process, or the like. The conductive interconnects 152 may comprise a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 152 are formed by first forming a layer of solder by commonly used methods such as evaporation, electroplating, printing, solder delivery, ball placement, or the like.Once a layer of solder has been formed on the structure, reflow can be performed to form the material into the desired bump shapes.

[0056] In Fig. 16B, pads 154 are formed on the metallization structure 110 in the openings 151, thereby forming first package components 100B in the first package region 101A and the second package region 101B. The pads 154 are used to couple to conductive connectors 156 and may be referred to as under bump metallurgies (UBMs) 154. In the illustrated embodiment, the pads 154 are formed in the openings 151 through the dielectric layer 108 to the metallization structure 110.

[0057] For example, the pads 154 may be formed by first forming a seed layer over the dielectric layer 108 and in the openings 151 extending through the dielectric layer 108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to the pads 154.Patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the photoresist openings and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, tungsten, aluminum, or the like. In some embodiments, the pads 154 may comprise alloys such as electroless nickel, electroless palladium, immersion gold (ENEPIG), electroless nickel, immersion gold (ENIG), or the like. The combination of the conductive material and underlying portions of the seed layer forms the pads 154. The photoresist and portions of the seed layer on which the conductive material is not formed are removed.The photoresist can be removed by a permissible ashing or ablation process, such as using an oxygen plasma or the like. Once the photoresist has been removed, exposed portions of the seed layer are removed using a permissible etching process, such as wet or dry etching.

[0058] Next, conductive connectors 156 are formed over pads 154. Conductive connectors 156 may be formed in a similar manner to conductive connectors 152 and may be formed from a material similar to that of conductive connectors 152.

[0059] Fig. 16C shows an embodiment in which the pads 154 are formed without conductive connectors being formed over the pads 154, thereby forming first package components 100C in the first package region 101A and the second package region 101B. The pads 154 may be formed from a material and in a manner that meets the requirements described with respect to Fig. 16B are similar.

[0060] In Fig. 17A-17C, modules 160 are bonded to the backside redistribution structure 106. The modules 160 may be power modules, memory modules, voltage regulator modules, integrated passive device (IPD) modules, or the like. In some embodiments, the modules 160 may include flip-chip bonding, wire bonding, or the like. The modules 160 may be chip-scale packages (CSPs), multi-chip modules (MCMs), or the like. According to some embodiments, the modules 160 may be packaged circuit board (PCB) modules that include discrete integrated circuits and passive devices.

[0061] Fig. 17A shows modules 160A connected to the Fig. 16A are bonded to the first package components 100A. As shown in Fig. 17A, the modules 160A may include pads 162 on which conductive connectors 158 are formed. The pads 162 may be formed in a manner similar to the pads 154 and may be formed from a material similar to the material of the pads 154. The conductive connectors 158 may be formed in a manner similar to the conductive connectors 152 and may be formed from a material similar to the material of the conductive connectors 152. The modules 160A may be placed in the first package region 101A and the second package region 101B using a pick and place machine or the like. Once the modules 160A have been placed, the conductive connectors 152 and the conductive connectors 158 may be reflowed to bond the modules 160A to the backside redistribution structure 106.

[0062] An underfill 164 may be formed to fill the gaps between the modules 160A and the backside redistribution structure 106. The underfill 164 may be formed by a capillary flow process after the modules 160A have been attached, or may be formed by a suitable deposition process before the modules 160A are attached.

[0063] Fig. 17B shows the modules 160A connected to the Fig. 16B. Pads 162 may be formed in a manner similar to pads 154 and may be formed from a material similar to the material of pads 154. Modules 160A may be placed in first package region 101A and second package region 101B using a pick-and-place machine or the like. Once modules 160A have been placed, conductive connectors 152 may be reflowed to bond modules 160A to backside redistribution structure 106.

[0064] An underfill 164 may be formed to fill the gaps between the modules 160A and the backside redistribution structure 106. The underfill 164 may be formed by a capillary flow process after the modules 160A have been attached, or may be formed by a suitable deposition process before the modules 160A are attached.

[0065] Fig. 17C shows modules 160B connected to the Fig. 16C are electrically coupled. As shown in Fig. 17C, the modules 160B may include spring-type contacts 166. The modules 160B may be placed over the first package components 100C using a pick-and-place machine or the like such that the spring-type contacts 166 are disposed on the pads 154. The modules 160B may then be secured to the first package components 100C using fasteners such as those described below with respect to Fig. 30 and Fig. 32 discussed fasteners 450 to the first package components 100B. The spring-type contacts 166 may be formed from a material such as copper, a copper alloy, plated beryllium copper (e.g., beryllium copper (BeCu) plated with nickel (Ni) and then gold (Au), combinations thereof, or the like. The spring-type contacts 166 may be formed by a cold forming process or the like. Incorporating the spring-type contacts 166 enables the modules 160B to be mechanically attached to the first package components 100C without requiring a bonding or joining process, and enables the modules 160B to be easily replaced. As in Fig. 17C, in the embodiment where the spring-type contacts 166 are used to attach the modules 160B to the backside redistribution structure 106, underfill material may not be incorporated between the modules 160B and the backside redistribution structure 106.

[0066] In Fig. 18A-18E, the first package components 100 are singulated in the first package region 101A and the second package region 101B, and each of the package components 100, with or without an attached module 160, is inserted into a tray 170. The first package components 100 may be singulated by a singulation process such as sawing, laser drilling, or the like. As shown in Fig. 18A-18E, the first package components 100 include the front-side redistribution structure 122, the encapsulated dies 50, the back-side redistribution structure 106, and any of the conductive connectors 152, the pads 154, and the conductive connectors 156. First packages 200 include the modules 160 bonded to the first package components 100. After the first package components 100 are singulated, each of the first packages 200 is removed from the tape 149 and inserted into a tray 170. The trays 170 may be used to provide protection for the first packages 200 until the first packages 200 are removed during subsequent 3D packaging processes (e.g., the process shown in Fig. 25, which is used to attach the first packages 200 to the SoW package 400. Placing the first packages 200 into the trays 170 can improve the reliability and yield of packages manufactured using the methods of the present application.

[0067] Fig. 18A shows a first package 200A including module 160A bonded to first package component 100A. Module 160A is bonded to first package component 100A by solder connections between conductive connectors 152 and conductive connectors 158. Module 160A is coupled to dies 50 of first package component 100A by pads 162, conductive connectors 158, conductive connectors 152, and backside redistribution structure 106. Fig. 18B shows a first package 200B including module 160A bonded to first package component 100B. Module 160A is bonded to first package component 100B by solder connections between conductive connectors 156 and pads 162. Module 160A is coupled to dies 50 of first package component 100B through pads 162, conductive connectors 156, pads 154, and backside redistribution structure 106. Fig. 18C shows a first package 200C having the module 160B bonded to the first package component 100C. The module 160B is placed on the first package component 100C, with the spring-type contacts 166 disposed on the pads 154. As with respect to Fig. 30, the module 160B may subsequently be fixed to the first package component 100C using a mechanical clamp 450A or the like. The module 160B is coupled to the dies 50 of the first package component 100C through the spring-type contacts 166, the pads 154, and the backside redistribution structure 106. Fig. 18D shows a singulated first package component 100C having pads 154 without a conductive connector thereon and inserted into tray 170 without a module 160 attached to the first package component 100C.

[0068] Fig. 18E shows a first package 200D having a module 160C bonded to the first package component 100B. The module 160C may have conductive pads (not separately shown) flush with a surface thereof. The conductive connectors 156 are bonded to the conductive pads of the module 160C. The module 160C may be bonded using processes similar to the processes used to bond the module 160A to the first package component 100B described above with reference to Fig. 17B, ​​are bonded to the first package component 100B. The module 160C is coupled to the die 50 of the first package component 100B through the conductive connectors 156, the pads 154, and the backside redistribution structure 106.

[0069] Fig. 19 to 24 show cross-sectional views of intermediate steps during a process for forming a system-on-wafer (SoW) package 400A according to some embodiments. In Fig. 19, a carrier substrate 402 is provided, and integrated circuit dies 405 are attached to the carrier substrate 402. A separation layer 404 may be formed on the carrier substrate 402. The carrier substrate 402 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 402 may be a wafer, such that multiple packages can be formed simultaneously on the carrier substrate 402. The separation layer 404 may be removed together with the carrier substrate 402 from the overlying structures formed in subsequent steps. In some embodiments, the separation layer 404 is any suitable adhesive, epoxy, die attach film (DAF), or the like, and is applied over the surface of the carrier substrate 402.

[0070] The integrated circuit dies 405 are attached to the carrier substrate 402 using the isolation layer 404. A desired type and quantity of integrated circuit dies 405 can be attached to the carrier substrate 102. The integrated circuit dies 405 can be the same as or similar to the active device dies 50C. For example, each of the integrated circuit dies 405 may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, or the like), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a high bandwidth memory (HBM) die, or the like), an input / output (I / O) interface die, a power management die (e.g.,a power management integrated circuit (PMIC) die or the like), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die or the like), a front-end die (e.g., an analog front-end (AFE) die or the like), the like, or combinations thereof.

[0071] As in Fig. 19, the integrated circuit dies 405 may include the same components as the active device dies 50C. For example, the integrated circuit dies may include: a semiconductor substrate 52C, a device 54 on the semiconductor substrate 52C, an ILD 56C surrounding the device 54, an interconnect structure 60C over the ILD 56C, pads 62C over the interconnect structure 60C, a passivation film 64C over the interconnect structure 60C and the pads 62C, die connectors 66C coupled to the pads 62C, and a dielectric layer 68C surrounding the die connectors 66C.

[0072] In Fig. 20, an encapsulant 406 is formed over the isolation layer 404, surrounding the integrated circuit dies 405. Once formed, the encapsulant 406 encapsulates the integrated circuit dies 405. The encapsulant 406 may be a molding compound, an epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. The encapsulant 406 may be applied in liquid or semi-liquid form and subsequently cured. In some embodiments, the encapsulant 406 is formed over the carrier substrate 402 such that the integrated circuit dies 405 are concealed or covered, and a planarization process is then performed on the encapsulant 406.The planarization process may planarize the encapsulant 406 and the dielectric layers 68C of the integrated circuit dies and may expose the die connectors 66C of the integrated circuit dies 405. Top surfaces of the encapsulant 406, the die connectors 66C, and the dielectric layers 68 may be flush with each other after the planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP).

[0073] In Fig. 21 to 23, a redistribution structure 430 (see Fig. 23), which includes a fine feature portion 414 and a coarse feature portion 426, is formed over the encapsulant 406 and the integrated circuit dies 405. The redistribution structure 430 includes metallization structures, dielectric layers, and under-bump metallurgy (UBMs). The metallization structures may also be referred to as redistribution layers or redistribution lines. The redistribution structure 430 is illustrated as an example including four layers of metallization structures. More or fewer dielectric layers and metallization structures may be formed in the redistribution structure 430. If fewer dielectric layers and metallization structures are to be formed, steps and processes discussed below may be omitted.If more dielectric layers and metallization structures are to be formed, the steps and processes discussed below may be repeated. The fine feature portion 414 and the coarse feature portion 426 of the redistribution structure 430 include metallization structures and dielectric layers of different sizes.

[0074] In Fig. 21, the fine feature portion 414 of the redistribution structure 430 is formed. The fine feature portion 414 of the redistribution structure 430 includes dielectric layers 408 and 411; and metallization structures 410 and 412. In some embodiments, the dielectric layers 408 and 411 are formed from a same dielectric material and have a same thickness. Similarly, in some embodiments, the conductive features of the metallization structures 410 and 412 are formed from a same conductive material and have a same thickness. In particular, the dielectric layers 408 and 411 have a first thickness T1 that is small, for example, in the range of about 5 µm to about 40 µm, and the conductive features of the metallization structures 410 and 412 have a second thickness T2 that is small, for example, in the range of about 1 µm to about 25 µm.

[0075] As an example of forming the fine feature portion 414 of the redistribution structure 430, the dielectric layer 408 is applied to the encapsulant 406, the dielectric layers 68C, and the die connectors 66C. In some embodiments, the dielectric layer 408 is formed from a photosensitive material such as PBO, polyimide, BCB, or the like, which can be patterned using a lithography mask. The dielectric layer 408 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. Then, the dielectric layer 408 is patterned. The patterning forms openings that expose portions of the die connectors 66C.Patterning may be performed by an acceptable process, for example, by exposing the dielectric layer 408 if the dielectric layer 408 is a photosensitive material, or by etching, for example, using an anisotropic etchant. If the dielectric layer 408 is a photosensitive material, the dielectric layer 408 may be developed after exposure.

[0076] Then, the metallization structure 410 is formed. The metallization structure 410 includes line portions (also referred to as conductive lines or traces) on and extending along the main surface of the dielectric layer 408 and includes via portions (also referred to as conductive vias) extending through the dielectric layer 408 to physically and electrically couple the die connectors 66C of the integrated circuit dies 405. For example, the metallization structure 410 may be formed by forming a seed layer over the dielectric layer 408 and in the openings extending through the dielectric layer 408. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials.In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. Then, a photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to the metallization pattern 410. Patterning forms openings through the photoresist to expose the seed layer. Then, a conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, for example, electroplating or electroless plating, or the like. The conductive material may comprise a metal such as copper, titanium, tungsten, aluminum, or the like.The combination of the conductive material and underlying portions of the seed layer forms the metallization structure 410. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by a permissible ashing or ablation process, for example, by using an oxygen plasma or the like. Once the photoresist has been removed, exposed portions of the seed layer are removed using a permissible etching process, such as wet or dry etching.

[0077] Then, the dielectric layer 411 is applied to the metallization structure 410 and the dielectric layer 408. The dielectric layer 411 may be formed in a similar manner to the dielectric layer 408 and may be formed from a material similar to the material of the dielectric layer 408. Then, the metallization structure 412 is formed. The metallization structure 412 has conductive portions on and extending along the main surface of the dielectric layer 411 and has via portions extending through the dielectric layer 411 to physically and electrically couple the metallization structure 410. The metallization structure 412 may be formed in a similar manner to the metallization structure 410 and may be formed from a material similar to the material of the metallization structure 410.Although the fine feature portion 414 is illustrated as having two dielectric layers and two metallization structures, any number of dielectric layers and metallization structures may be formed in the fine feature portion 414.

[0078] In Fig. 22, the coarse feature portion 426 of the redistribution structure 430 is formed. The coarse feature portion 426 of the redistribution structure 430 includes dielectric layers 416, 420, and 424; and metallization structures 418 and 422. In some embodiments, the dielectric layers 416, 420, and 424 are formed from a same dielectric material and have a same thickness. Similarly, in some embodiments, the conductive features of the metallization structures 418 and 422 are formed from a same conductive material and have a same thickness. In particular, the dielectric layers 416, 420 and 424 have a third thickness T3 that is large, for example, in the range of about 5 µm to about 40 µm, and the conductive features of the metallization structures 418 and 422 have a fourth thickness T4 that is large, for example, in the range of about 1 µm to about 25 µm.In various embodiments, the third thickness T3 may be greater than the first thickness T1 (see . Fig. 21), and the fourth thickness T4 may be greater than the second thickness T2 (see Fig. 21).

[0079] To form the coarse feature portion 426 of the redistribution structure 430, the dielectric layer 416 may be applied to the metallization structure 412 and the dielectric layer 411. The dielectric layer 416 may be formed in a similar manner to the dielectric layer 408 and may be formed from a material similar to the material of the dielectric layer 408. Then, the metallization structure 418 is formed. The metallization structure 418 includes conductive portions on and extending along the main surface of the dielectric layer 416 and includes via portions extending through the dielectric layer 416 to physically and electrically couple the metallization structure 412.The metallization structure 418 may be formed in a similar manner to the metallization structure 410 and may be formed from a material similar to the material of the metallization structure 410.

[0080] Then, the dielectric layer 420 is applied to the metallization structure 418 and the dielectric layer 416. The dielectric layer 420 may be formed in a similar manner to the dielectric layer 408 and may be formed from a material similar to the material of the dielectric layer 408. Then, the metallization structure 422 is formed. The metallization structure 422 includes conductive portions on and extending along the main surface of the dielectric layer 420 and includes via portions extending through the dielectric layer 420 to physically and electrically couple the metallization structure 418. The metallization structure 422 may be formed in a similar manner to the metallization structure 410 and may be formed from a material similar to the material of the metallization structure 410.

[0081] Then, the dielectric layer 424 is applied to the metallization structure 422 and the dielectric layer 420. The dielectric layer 424 may be formed in a similar manner to the dielectric layer 408 and may be formed from a material similar to the material of the dielectric layer 408. Although the coarse feature portion 426 is illustrated as including three dielectric layers and two metallization structures, any number of dielectric layers and metallization structures may be formed in the coarse feature portion 426. In some embodiments, the fine feature portion 414 and the coarse feature portion 426 may each include three dielectric layers and three metallization structures.

[0082] Due to the thickness of the metallization structures incorporated in the coarse feature section 426 and the fine feature section 414, the coarse feature section 426 may have a lower resistance compared to the fine feature section 414. Due to the lower resistance, the coarse feature section 426 may be used to carry power lines. The fine feature section 414 may be used to carry signal lines that do not require the lower resistance. Incorporating both the coarse feature section 426 and the fine feature section 414 allows for power lines and signal lines to be carried while minimizing the thickness of the redistribution structure 430.

[0083] In Fig. 23, UBMs 428 are formed for external connection to the redistribution structure 430. The UBMs 428 have bump portions on and extending along the main surface of the dielectric layer 424 and have via portions extending through the dielectric layer 424 to physically and electrically couple the metallization structure 422. As a result, the UBMs 428 are electrically coupled to the integrated circuit dies 405. The UBMs 428 may be formed in a similar manner and from a similar material as the metallization structure 410. In some embodiments, the UBMs 428 have a different size than the metallization structures 410, 412, 418, and 422.

[0084] In Fig. 24, conductive interconnects 432 are formed on the UBMs 428, forming the SoW package 400A. The conductive interconnects 432 may be ball grid array (BGA) interconnects, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using the electroless nickel-electroless palladium-immersion gold (ENEPIG) process, bumps formed using the electroless nickel-immersion gold (ENIG) process, or the like. The conductive interconnects 432 may comprise a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 432 are formed by first forming a layer of solder or solder paste by evaporation, electroplating, printing, solder delivery, ball placement, or the like.Once a layer of solder has been formed on the structure, reflow can be performed to form the material into the desired bump shapes.

[0085] In Fig. 25, a first package 200A comprising a module 160A bonded to a first package component 100A, and external connectors 434A bonded to the SoW package 400A. In various embodiments, the SoW package 400A may be a super-large fan-out wafer-level package with an area of ​​10,000 mm 2 or larger. The first package 200A may be placed over the SoW package 400A using a pick and place machine or the like. Once the first package 200A has been placed, the conductive connectors 432 and the conductive connectors 150 may be reflowed to bond the first package 200A to the SoW package 400A. Although the Fig. 25 illustrates a first package 200A attached to the SoW package 400A, alternatively or additionally, the first package 200B or the first package 200C may be attached to the SoW package 400A.

[0086] Further, external connectors 434A are attached to the SoW package 400A. The external connectors 434A are electrical and physical interfaces for the SoW package 400A to other SoW packages 400A, other external systems, or the like. For example, if the SoW package 400A is mounted as part of a larger external system, such as a data center, the external connectors 434A can be used to couple the SoW package 400A to the external system. Examples of external connectors 434A include large wire bonds, receptacles for ribbon cables, flexible printed circuits, or the like. The external connectors 434A include pads 438, which may be similar to the UBMs 428. The external connectors 434A may include various components, such as a chassis, the pads 438, and external connection pins, which may include various materials.The external connectors 434A also include conductive connectors 436 on the pads 438, which may be similar to the conductive connectors 432. The pads 438 and the conductive connectors 432 are used for physical and electrical connection to the SoW package 400A. Attaching the external connectors 434A may include placing the external connectors 434A on the SoW package 400A using a pick and place machine or the like and then reflowing the conductive connectors 436 and the conductive connectors 432 to physically and electrically couple the pads 438 and the UBMs 428.

[0087] An underfill 440 may be formed to fill the gaps between the first package 200A and the SoW package 400A. The underfill 440 may be formed by a capillary flow process after the first package 200A has been attached, or may be formed by a suitable deposition process before the first package 200A is attached.

[0088] In Fig. 26, the carrier substrate 402 is separated from the encapsulant 406 and the integrated circuit dies 405 by debonding to form a packaged device 500A. According to some embodiments, debonding includes projecting a light, such as a laser light or a UV light, onto the separation layer 404 so that the separation layer 404 is decomposed under the heat of the light and the carrier substrate 402 can be removed.

[0089] Fig. Figure 27 shows an embodiment in which the first package component 100C is bonded to the SoW package 400A, and not, as in Fig. 25, the first package 200A is bonded to the SoW package. The first package component 100C may be placed over the SoW package 400A using a pick and place machine or the like. Once the first package component 100C has been placed, the conductive connectors 432 and the conductive connectors 150 may be reflowed to bond the first package component 100C to the SoW package 400A. The external connectors 434A, which include the pads 438 and the conductive connectors 436, are formed using the same methods described above with reference to Fig. 25 were also bonded to the SoW package 400A.

[0090] An underfill 440 may be formed to fill the gaps between the first package component 100C and the SoW package 400A. The underfill 440 may be formed by a capillary flow process after the first package component 100C has been attached, or may be formed by a suitable deposition process before the first package component 100C is attached.

[0091] In Fig. 28, the carrier substrate 402 has been separated from the encapsulant 406 and the integrated circuit die 405 by debonding, and screw holes 442 are formed through the SoW package 400A. According to some embodiments, debonding includes projecting a light, such as a laser light or a UV light, onto the separation layer 404 so that the separation layer 404 is decomposed under the heat of the light, and the carrier substrate 402 can be removed. The screw holes 442 may be formed by a drilling process, such as laser drilling, mechanical drilling, or the like. The screw holes 442 may be formed by drilling an outline for the screw holes 442 with the drilling process and then removing the material separated by the outline.

[0092] In Fig. 29, a module 160B having spring-type contacts 166 is placed on the first package component 100C to form a first package 200C. The module 160B may be similar or identical to the module 160B described above with reference to Fig. 17C, and the spring-type contacts 166 may be the same as or similar to the spring-type contacts 166 discussed above with reference to Fig. 17C. The module 160B can be placed over the first package component 100C using a pick-and-place machine or the like.

[0093] In Fig. 30, a mechanical clamp 450A is attached to fix the module 160B to the first package component 100C and the SoW package 400A, thereby forming a packaged device 500B. The mechanical clamp 450A is a rigid mount that may be formed from a high-rigidity material, such as a metal that may include steel, titanium, cobalt, or the like. The mechanical clamp 450A physically engages portions of the module 160B. Using the mechanical clamp 450A to clamp the module 160C to the first package component 100C and the SoW package 400A may reduce any warpage in the packaged device 500B.

[0094] The module 160C is secured between the first package component 100C and the mechanical clamp 450A with screws 452A. The screws 452A are threaded through the screw holes 442 of the SoW package 400 and through corresponding screw holes in the mechanical clamp 450A. Fasteners 454A are threaded onto the screws 452A and tightened to clamp the module 160C between the first package component 100C and the mechanical clamp 450A. The fasteners 454A can be, for example, nuts that can be threaded onto the screws 452A. The fasteners 454A can be tightened onto the screws 452A such that the spring-type contacts 166 are compressed. Once secured, sections of the mechanical clamp 450A are positioned between the module 160C and the external connectors 434A. Fig. 30 may not have an underfill disposed between the module 160B and the first package component 100C, and portions of the module 160B may be separated from the first package component 100C by an opening or gap.

[0095] Fig. 31 shows a packaged device 500C including a first package 200B (including a module 160A bonded to a first package component 100B), a first package 200D (including a module 160C bonded to a first package component 100B), and a SoW package 400B, according to one embodiment. The SoW package 400B may be formed in a similar manner to the SoW package 400A and may be formed from materials similar to the SoW package 400A, but may include two regions where the first packages 200B and 200D are bonded. In various embodiments, the SoW package 400B may be a super-large fan-out wafer-level package having an area of ​​10,000 mm 2 or greater. The first package 200B may be separated from the second package 200D by a distance of about 0.05 mm to about 10 mm, for example, about 0.5 mm.

[0096] The first packages 200B and 200D may be placed over the SoW package 400B using a pick-and-place machine or the like. Once the first packages 200B and 200D have been placed, the conductive connectors 432 and the conductive connectors 150 may be reflowed to bond the first packages 200B and 200D to the SoW package 400B. Although Fig. 31 shows first packages 200B and 200D attached to the SoW package 400B, any combination of the first packages 200A-200D may alternatively or additionally be attached to the SoW package 400B. Underfills 440 may be formed to fill the gaps between the first packages 200B and 200D and the SoW package 400B. The underfills 440 may be formed by capillary flow processes after the first packages 200B and 200D have been attached, or may be formed by a suitable deposition process before the first packages 200B and 200D are attached.

[0097] Further, external connectors 434B are attached to the SoW package 400B. The external connectors 434B are electrical and physical interfaces for the SoW package 400B to other SoW packages 400B, other external systems, or the like. For example, if the SoW package 400B is mounted as part of a larger external system, such as a data center, the external connectors 434B can be used to couple the SoW package 400B to the external system. Examples of external connectors 434B include large wire bonds, receptacles for ribbon cables, flexible printed circuits, or the like. The external connectors 434B include pads 438, which may be similar to the UBMs 428. The external connectors 434B may include various components, such as a chassis, the pads 438, and external connection pins, which may include various materials.The external connectors 434B also include conductive connectors 436 on the pads 438, which may be similar to the conductive connectors 432. The pads 438 and the conductive connectors 432 are used for physical and electrical connection to the SoW package 400B. Attaching the external connectors 434B may include placing the external connectors 434B on the SoW package 400B using a pick and place machine or the like and then reflowing the conductive connectors 436 and the conductive connectors 432 to physically and electrically couple the pads 438 and the UBMs 428.

[0098] A mechanical clamp 450B is attached to secure a thermal module 460 to a backside of the SoW package 400B. The thermal module 460 may be a heat sink, a heat spreader, a cold plate, or the like. The mechanical clamp 450B is a rigid mount that may be formed from a high-stiffness material, such as a metal that may include steel, titanium, cobalt, or the like. The mechanical clamp 450B physically engages portions of the SoW package 400B. Using the mechanical clamp 450B to clamp the thermal module 460 to the SoW package 400B may reduce any warpage in the SoW package 400B.

[0099] The thermal module 460 is attached to the back of the SoW package 400B with screws 452B. The screws 452B are threaded through screw holes 442 formed in the SoW 400B and through corresponding screw holes in the mechanical clamp 450B. Fasteners 454B are screwed onto the screws 452B and tightened to clamp the thermal module 460 to the SoW package 400B, with the SoW package 400B disposed between the mechanical clamp 450B and the thermal module 460. The fasteners 454B can be, for example, nuts that can be screwed onto the screws 452B. Once secured, portions of the mechanical clamp 450B are disposed between the first package 200A and the first package 200B and outside the external connectors 434B.

[0100] Before attaching the thermal module 460 and the SoW package 400B together, a thermal interface material (TIM) 462 may be applied to the backside of the SoW package 400B, physically and thermally coupling the thermal module 460 to the SoW package 400B. In some embodiments, the TIM 462 is formed from a film including indium, a thermal grease, a thermal plate, a phase-change material, combinations thereof, or the like. During attachment, the fasteners 454B are tightened, thereby increasing the mechanical force applied to the SoW package 400B by the thermal module 460 and the mechanical clamp 450A. The fasteners 454B are tightened until the thermal module 460 exerts a desired amount of pressure on the TIM 462.

[0101] Fig. 32 shows a packaged device 500D including modules 160B, first package components 100C, a mechanical clamp 450C, a mechanical clamp 450B, a thermal module 460, and a SoW package 400C. The SoW package 400C may be formed in a manner similar to the SoW package 400A and may be formed from materials similar to the SoW package 400A, but may include two regions where the first package components 100C are bonded. In various embodiments, the SoW package 400C may be a super-large fan-out wafer-level package having an area of ​​10,000 mm 2 or larger.

[0102] Each of the first package components 100C may be placed over the SoW package 400C using a pick-and-place machine or the like. Once the first package components 100C have been placed, the conductive connectors 432 and the conductive connectors 150 may be reflowed to bond the first package components 100C to the SoW package 400C. Although Fig. 32 shows first packages 200B and 200D attached to the SoW package 400B, alternatively or additionally, any combination of the first packages 200A-200D may be attached to the SoW package 400B. Underfills 440 may be formed to fill the gaps between the first package components 100C and the SoW package 400C. The underfills 440 may be formed by capillary flow processes after the first package components 100C have been attached, or may be formed by a suitable deposition process before the first package components 100C are attached.

[0103] Further, external connectors 434B are attached to the SoW package 400C. The external connectors 434B are electrical and physical interfaces for the SoW package 400C to other SoW packages 400C, other external systems, or the like. For example, if the SoW package 400C is mounted as part of a larger external system, such as a data center, the external connectors 434B can be used to couple the SoW package 400C to the external system. Examples of external connectors 434B include large wire bonds, receptacles for ribbon cables, flexible printed circuits, or the like. The external connectors 434B include pads 438, which may be similar to the UBMs 428. The external connectors 434B may include various components, such as a chassis, the pads 438, and external connection pins, which may include various materials.The external connectors 434B also include conductive connectors 436 on the pads 438, which may be similar to the conductive connectors 432. The pads 438 and the conductive connectors 432 are used for physical and electrical connection to the SoW package 400C. Attaching the external connectors 434B may include placing the external connectors 434B on the SoW package 400C using a pick and place machine or the like and then reflowing the conductive connectors 436 and the conductive connectors 432 to physically and electrically couple the pads 438 and the UBMs 428.

[0104] Each of the modules 160B may be placed over the respective first package components 100C using a pick-and-place machine or the like. The mechanical clamp 450C is then attached to fix each of the modules 160B to a respective first package component 100C, thereby forming first packages 200C. The mechanical clamp 450C is a rigid fixture that may be formed from a high-stiffness material, such as a metal that may include steel, titanium, cobalt, or the like. The mechanical clamp 450C physically engages portions of the modules 160B. Using the mechanical clamp 450C to clamp the modules 160B to the first package components 100C and the SoW package 400C may reduce any warpage in the packaged device 500D.

[0105] The module 160B is secured between the first package component 100C and the mechanical clamp 450C with screws 452C. The screws 452C are threaded through the screw holes 442 of the SoW package 400C and through corresponding screw holes in the mechanical clamp 450C. Fasteners 454C are threaded onto the screws 452C and tightened to clamp the module 160B between the first package component 100C and the mechanical clamp 450C. The fasteners 454C can be, for example, nuts that can be threaded onto the screws 452C. The fasteners 454C can be tightened onto the screws 452C such that the spring-type contacts 166 are compressed. Once secured, portions of the mechanical clamp 450C are positioned between the first package components 100C and the external connectors 434B.

[0106] The mechanical clamp 450B is attached to secure the thermal module 460 to a rear side of the SoW package 400C. The mechanical clamp 450C may also secure the thermal module to the rear side of the SoW package 400C. The thermal module 460 may be a heat sink, heat spreader, cold plate, or the like. The mechanical clamp 450B is a rigid mount that may be formed from a high-stiffness material, such as a metal that may include steel, titanium, cobalt, or the like. The mechanical clamp 450B physically engages portions of the SoW package 400C. Using the mechanical clamp 450B to clamp the thermal module 460 to the SoW package 400C may reduce any warpage in the SoW package 400C.

[0107] The thermal module 460 is secured to the rear of the SoW package 400C with screws 452B. The screws 452B are threaded through screw holes 442 formed in the SoW package 400C and through corresponding screw holes in the mechanical clamp 450B. Fasteners 454B are screwed onto the screws 452B and tightened to clamp the thermal module 460 to the SoW package 400C, with the SoW package 400C disposed between the mechanical clamp 450B and the thermal module 460. The fasteners 454B can be, for example, nuts that can be screwed onto the screws 452B. Once secured, portions of the mechanical clamp 450B are disposed outside the external connectors 434B.

[0108] Before attaching the thermal module 460 and the SoW package 400C to each other, a thermal interface material (TIM) 462 may be applied to the backside of the SoW package 400C, physically and thermally coupling the thermal module 460 to the SoW package 400C. In some embodiments, the TIM 462 is formed from a film including indium, thermal grease, a thermal plate, a phase-change material, combinations thereof, or the like. During attachment, the fasteners 454B and 454C are tightened, thereby increasing the mechanical force applied to the SoW package 400C by the thermal module 460 and the mechanical clamps 450B and 450C. The fasteners 454B and 454C are tightened until the thermal module 460 exerts a desired amount of pressure on the TIM 462.

[0109] Fig. 33-38 show top views of SoW packages 400 according to various embodiments. In the Fig. 33-35, the SoW packages 400 have circular shapes. Fig. 33-35 may be intermediate structures that can be sawn, cut, or similarly processed to form the SoW packages 400 shown in Fig. 36-38. The SoW packages 400 include various integrated circuit dies 405, such as compute dies 405A, memory dies 405B, and input / output (I / O) dies 405C. In some embodiments, the compute dies 405A may include central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASCIs), field-programmable gate arrays (FPGAs), or the like. The memory dies 405B may include high-bandwidth memory (HBM) dies, dynamic random access memory (DRAM) dies, hybrid memory cubes (HMCs), or the like.

[0110] At the Fig. 33, a first package 200 is provided over each of the integrated circuit dies 405. The first packages 200 may be any of the first packages 200A-200E discussed above. In the embodiment shown in Fig. 34, each pair of two memory dies 405B shares a first package 200 and each set of four data processing dies 405A shares a first package 200. In the embodiment shown in Fig. In the embodiment illustrated in Figure 35, two of the first packages 200 may be provided for each of the I / O dies 405C, and four first packages 200 may be provided for each of the compute dies 405A. Other configurations are possible, and any number of first packages 200 may be provided for any number of integrated circuit dies 405. The SoW packages 400 further include external connectors 434.

[0111] In the Fig. 36-38, the SoW packages 400 have octagonal shapes. This may allow interconnected SoW packages 400 to be placed closer together. The SoW packages 400 include various integrated circuit dies 405, such as data processing dies 405A, memory dies 405B, and input / output (I / O) dies 405C. In the embodiment shown in Fig. 36, a first package 200 is provided over each of the integrated circuit dies 405. The first packages 200 may be any of the first packages 200A-200E discussed above. In the embodiment shown in Fig. 37, each pair of two memory dies 405B shares a first package 200, and each set of four data processing dies 405A shares a first package 200. In the embodiment shown in Fig.In the embodiment illustrated in Figure 38, two of the first packages 200 may be provided for each of the I / O dies 405C, and four first packages 200 may be provided for each of the compute dies 405A. Other configurations are possible, and any number of first packages 200 may be provided for any number of integrated circuit dies 405. The SoW packages 400 further include external connectors 434.

[0112] Providing packaged devices 500 comprising first package components 100 (having dies 50 disposed therein) disposed between modules 160 and SoW packages 400 reduces the distance between IPDs incorporated into the first package components 100 and functional dies incorporated into the SoW packages 400. This improves the performance of the power distribution network (PDN). Various embodiments discussed above may be applicable to high-performance computing (HPC) (e.g., an accelerator of an artificial intelligence (AI) server, a cloud computing system, an edge computing system, or the like) in data center applications, server applications, or the like.

[0113] Other features and processes may also be incorporated. For example, test structures may be incorporated to support verification testing of the 3D package or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that enables testing of the 3D package or 3DIC, the use of probes and / or probe cards, and the like. Verification tests may be performed on intermediate structures as well as on the final structure. Furthermore, the structures and methods disclosed in this document may be used in conjunction with test methods that include intermediate verification of known good dies to increase yield and reduce costs.

[0114] According to one embodiment, an apparatus comprises: a first package component comprising a first integrated circuit die; a first encapsulant at least partially surrounding the first integrated circuit die; and a redistribution structure on the first encapsulant and coupled to the first integrated circuit die; a second package component bonded to the first package component, the second package component comprising an integrated passive device; and a second encapsulant at least partially surrounding the integrated passive device; and a power module attached to the first package component by the second package component. In one embodiment, the apparatus further comprises electrical connectors coupled to the redistribution structure, the electrical connectors encircling the second package component.In one embodiment, the second package includes non-active devices disposed within the second encapsulant. In one embodiment, the power module is bonded to the second package component via solder connections. In one embodiment, the power module is coupled to the second package via spring-type contacts. In one embodiment, the device further includes a mechanical clamp extending through the first package component, the mechanical clamp in contact with the power module, the mechanical clamp securing the power module to the second package component.In one embodiment, the device further comprises a thermal module attached to the first package component, wherein the second package component is disposed on a first side of the first package component and the second package component is disposed on a second side of the first package component opposite the first side. In one embodiment, the device further comprises a thermal interface material disposed between the thermal module and the first package component, wherein a mechanical clamp attaches the thermal module to the first package component.

[0115] According to another embodiment, a method comprises forming a first package component, wherein forming the first package component comprises: attaching a first integrated passive device to a first redistribution structure; encapsulating the first integrated passive device with an encapsulant; and forming a second redistribution structure over the first integrated passive device and the encapsulant; attaching a power module to the second redistribution structure; and bonding the first redistribution structure to a third redistribution structure of a second package component, the second package component comprising a first integrated circuit die coupled to the third redistribution structure.In one embodiment, the method further comprises singulating the first package component after attaching the power module to the first package component and before bonding the first package component to the second package component. In one embodiment, the power module is attached to the first package component after the first package component has been bonded to the second package component. In one embodiment, attaching the power module to the first package comprises placing the power module over the first package component using a pick and place machine and attaching the power module to the first package component using a mechanical clamp, wherein the mechanical clamp has screws extending through the second package component.In one embodiment, the power module includes spring-type contacts, and the mechanical clamp applies pressure to the spring-type contacts to compress the spring-type contacts. In one embodiment, the method further comprises applying a first underfill material between the power module and the first side of the first package component and applying a second underfill material between the second side of the first package component and the second package component.

[0116] According to yet another embodiment, a device comprises a first package including: a plurality of integrated circuit dies; a plurality of power modules above the first package, each of the power modules disposed directly above the integrated circuit dies in a direction perpendicular to a major surface of the first package; and a plurality of package components disposed between the integrated circuit dies and the power modules, each of the package components comprising an integrated passive device (IPD). In one embodiment, one of the power modules and one of the package components are disposed above each of the integrated circuit dies. In one embodiment, more than one of the power modules and more than one of the package components are disposed above each of the integrated circuit dies.In one embodiment, one of the power modules and one of the package components are arranged over more than one of the integrated circuit dies. In one embodiment, each of the package components comprises: a front-side redistribution structure, wherein the IPD is arranged over the front-side redistribution structure; an encapsulant arranged over the front-side redistribution structure and surrounding the IPD; vias extending through the encapsulant and coupled to the front-side redistribution structure; and a back-side redistribution structure over the vias, the IPD, and the encapsulant, wherein the back-side redistribution structure is coupled to the front-side redistribution structure through the vias. In one embodiment, the first package has an octagonal shape in a top view.

Claims

[1] Device comprising: a first package component (400A, 400B, 400C), comprising: a first integrated circuit die (405); a first encapsulant (406) at least partially surrounding the first integrated circuit die (405); and a redistribution structure (430) on the first encapsulation substance (406) and coupled to the first integrated circuit die (405); a second package component (100A, 100B, 100C) bonded to the first package component (400A, 400B, 400C), the second package component comprising: an integrated passive device (50A); and a second encapsulating substance (120) at least partially surrounding the integrated passive device (50A); and a power module (160A, 160B) attached to the first package component (400A, 400B, 400C) by the second package component (100A, 100B, 100C), and wherein the power module (160B) is coupled to the second package (100A, 100B, 100C) by means of spring-type contacts (166). [2] The apparatus of claim 1, further comprising electrical connectors (434, 434A, 434B) coupled to the redistribution structure (430), the electrical connectors (434, 434A, 434B) encircling the second package component (1004, 100B, 100C). [3] The device of claim 1 or 2, wherein the second package component (100A, 100B, 100C) does not have any active devices disposed in the second encapsulating substance (120). [4] The device of any preceding claim, further comprising a mechanical clamp (450A) extending through the first package component (400A, 400B, 400C), the mechanical clamp (450A) in contact with the power module (160B), the mechanical clamp (450A) securing the power module (160B) to the second package component (400A, 400B, 400C). [5] The device of any preceding claim, further comprising a thermal module (460) attached to the first package component (400B, 400C), wherein the second package component (100A, 100B, 100C) is disposed on a first side of the first package component (400B, 400C), and wherein the thermal module (460) is disposed on a second side of the first package component (400B, 400C) opposite the first side. [6] The device of claim 5, further comprising a thermal interface material (462) disposed between the thermal module (460) and the first package component (400B, 400C), wherein a mechanical clamp (450B, 450C) secures the thermal module (460) to the first package component (400B, 400C). [7] Method comprising: Forming a second package component (100A, 100B, 100C), wherein forming the second package component (100A, 100B, 100C) comprises: Attaching a first integrated passive device (50A) to a rear redistribution structure (106); Encapsulating the first integrated passive device (50A) with an encapsulating substance (120); and Forming a front-side redistribution structure (122) over the first integrated passive device (50A) and the encapsulating substance (120); Attaching a power module (160) to the rear redistribution structure (106); and Bonding the front-side redistribution structure (122) to a third redistribution structure (430) of a first package component (400A, 400B, 400C), the first package component (400A, 400B, 400C) comprising a first integrated circuit die (405) coupled to the third redistribution structure (430). [8] The method of claim 7, further comprising singulating the second package component (100A, 100B, 100C) after attaching the power module (160) to the second package component (100A, 100B, 100C) and before bonding the second package component (100A, 100B, 100C) to the first package component (400A, 400B, 400C). [9] The method of claim 7, wherein the power module (160) is attached to the second package component (100A, 100B, 100C) after the second package component (100A, 100B, 100C) has been bonded to the first package component (400A, 400B, 400C). [10] The method of claim 9, wherein attaching the power module (160, 160A-C) to the second package component (100A, 100B, 100C) comprises placing the power module (160, 160A-C) over the second package component (100A, 100B, 100C) using a pick and place machine and attaching the power module (160, 160A-C) to the second package component (100A, 100B, 100C) using a mechanical clamp (450A, 450C), the mechanical clamp (450A, 450C) having screws extending through the first package component (400A, 400B, 400C). [11] The method of claim 10, wherein the power module (160B) includes spring-type contacts (166), and wherein the mechanical clamp (450A) applies pressure to the spring-type contacts (166) to compress the spring-type contacts (166). [12] The method of any one of claims 7 to 11, further comprising applying a first underfill material (164) between the power module (160) and the first side of the second package component (100A, 100B, 100C) and applying a second underfill material (440) between the second side of the second package component (100A, 100B, 100C) and the first package component (400A, 400B, 400C).

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