INTEGRATED CHIPS AND METHOD FOR MANUFACTURING THESE, IN PARTICULAR WITH AN RRAM STRUCTURE

Abstract

Integrated chip with: a lower electrode (112) arranged above one or more interconnection layers (108); a diffusion barrier layer (114) arranged above the lower electrode (112); a data storage layer (116) which is separated from the lower electrode (112) by the diffusion barrier layer (114); and an upper electrode (118) arranged above the data storage layer (116); wherein the diffusion barrier layer (114) comprises a noble metal oxide or a noble metal nitride.

Description

Background of the invention

[0001] Many modern electronic devices contain electronic memory configured to store data. Electronic memory can be volatile or non-volatile. Volatile memory stores data as long as it is powered on, while non-volatile memory can store data even when power is removed. A resistive random access memory (RRAM) device is a promising candidate for a next-generation non-volatile memory technology. This is due to the numerous advantages that RRAM devices offer, such as fast write time, high endurance, low power consumption, and low susceptibility to radiation damage.

[0002] From the document US 2014 / 0 192 589 A1 a chip device is known which has a barrier layer with a thickness between 3 nm and 10 nm.

[0003] The publication US 2017 / 0 141 300 A1 describes the use of a bottom-electrode diffusion barrier for an integrated chip. The objective is to create correspondingly improved integrated chips. Summary of the invention

[0004] The object is achieved by an integrated chip according to claim 1, an integrated chip according to claim 10 and a method for producing an integrated chip according to claim 16. Preferred embodiments are specified in the dependent claims. Short description of the drawings

[0005] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 shows a cross-sectional view of some embodiments of an integrated chip with a disclosed RRAM (resistive random access memory) device having a diffusion barrier layer disposed between a bottom electrode and a data storage layer. Fig. 2 shows a cross-sectional view of some further embodiments of an integrated chip with a disclosed RRAM device having a diffusion barrier layer. The Fig. 3A and Fig. 3B show some further embodiments of an integrated chip with a disclosed RRAM device having a diffusion barrier layer. The Fig. 4A and Fig. 4B show some further embodiments of an integrated chip with an embedded RRAM device having a diffusion barrier layer disposed between a bottom electrode and a data storage layer. The Fig. 5 and Fig. 6 show some further embodiments of an integrated chip with a disclosed RRAM device having a diffusion barrier layer. The Fig. 7 to 17 show cross-sectional views of some embodiments of a method for manufacturing an integrated chip with a disclosed RRAM device having a diffusion barrier layer disposed between a bottom electrode and a data storage layer. Fig. 18 shows a flow diagram of some embodiments of a method for manufacturing an integrated chip with a disclosed RRAM device having a diffusion barrier layer disposed between a bottom electrode and a data storage layer. Detailed description

[0006] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.These repetitions are for simplicity and clarity and do not, in and of themselves, dictate any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] RRAM (Resistive Random Access Memory) devices generally comprise a data storage layer (e.g., a layer of high-k dielectric material) sandwiched between a conductive bottom electrode and a conductive top electrode disposed within a back end of line (BEOL) metallization stack. RRAM devices are configured to operate through a process of reversible switching between resistive states. This reversible switching is enabled by selectively creating a conductive filament through the data storage layer. For example, the data storage layer, which is normally insulating, can be made current-carrying by applying a voltage across the conductive electrodes to create a conductive filament through the data storage layer. An RRAM device comprising a first (e.g.,high) resistive state corresponds to a first data value (e.g., a logic 0), and an RRAM device that has a second (e.g., low) resistive state corresponds to a second data value (e.g., a logic 1).

[0009] To improve the reliability of an RRAM device, its bottom electrode can comprise a noble metal (e.g., an inert metal). Since a noble metal has lower reactivity, using a noble metal in the bottom electrode of the RRAM device can prevent performance degradation of the bottom electrode due to interactions with ions (e.g., oxygen ions) from an overlying data storage layer. However, it has been discovered that during high-temperature processes used in the fabrication of top layers of an RRAM device, metal atoms from a noble metal can diffuse into an overlying data storage layer. The diffusion of noble metal atoms from the bottom electrode creates etch bumps (i.e., protrusions) along a top surface of the bottom electrode. The etch bumps comprise a combination of the noble metal atoms and the data storage layer (e.g., hafnium titanium oxide).The etch bumps extend into the data storage layer, effectively thinning the data storage layer and reducing the reliability of the resulting RRAM device and / or causing leakage between the bottom and top electrodes of the resulting RRAM device.

[0010] The present invention, in some embodiments, relates to an RRAM device having a bottom electrode separated from a top electrode by a data storage layer. A diffusion barrier layer is disposed between the bottom electrode and the data storage layer. The diffusion barrier layer is configured to prevent the diffusion of metal atoms (e.g., noble metal atoms) from the bottom electrode into the data storage layer, thereby preventing the formation of etch bumps in the data storage layer. By preventing the diffusion of metal atoms from the bottom electrode into the data storage layer, the data storage layer may have a substantially uniform thickness, which increases the reliability of the RRAM device.

[0011] Fig. 1 shows a cross-sectional view of some embodiments of an integrated chip 100 with a resistive random access memory (RRAM) device having a diffusion barrier layer disposed between a bottom electrode and a data storage layer.

[0012] The integrated chip 100 includes an RRAM device 111 disposed in a dielectric structure 106 over a substrate 102. The RRAM device 111 is separated from the substrate 102 by one or more lower interconnect layers 108 disposed in the dielectric structure 106. In some embodiments, the one or more lower interconnect layers 108 may include conductive contacts 107 connected to overlying alternating layers of interconnect vias 109 and bond wires 110. The one or more lower interconnect layers 108 are configured to connect the RRAM device 111 to an access transistor 104 disposed in the substrate 102.

[0013] The RRAM device 111 includes a data storage dielectric layer 116 disposed between a bottom electrode 112 and a top electrode 118. The bottom electrode 112 is connected to one or more bottom interconnect layers 108, and the top electrode 118 is connected to an top interconnect structure 120 comprising a bond wire or via. The data storage dielectric layer 116 is configured to store data states by undergoing reversible changes between a high-resistance state associated with a first data state (e.g., a 0) and a low-resistance state associated with a second data state (e.g., a 1).For example, to achieve a low-resistance state in the data storage dielectric layer 116 during operation, a first set of bias conditions may be used for the bottom electrode 112 and the top electrode 118. The first set of bias conditions drives oxygen from the data storage dielectric layer 116 to the top electrode 118, creating a conductive filament 117 of oxygen vacancies across the data storage dielectric layer 116. Alternatively, to achieve a high-resistance state in the data storage dielectric layer 116, a second set of bias conditions may be used for the bottom electrode 112 and the top electrode 118. The second set of bias conditions disrupts the conductive filament 117 by driving oxygen from the top electrode 118 to the data storage dielectric layer 116.

[0014] A diffusion barrier layer 114 is disposed between the bottom electrode 112 and the data storage dielectric layer 116. The diffusion barrier layer 114 is configured to prevent the diffusion of metal atoms (e.g., noble metal atoms) from the bottom electrode 112 to the dielectric via 608. Preventing the diffusion of metal atoms from the bottom electrode 112 to the data storage dielectric layer 116 prevents etch bumps comprising the metal atoms from forming along a top surface of the bottom electrode 112. Preventing the formation of etch bumps along the top surface of the bottom electrode 112 improves the thickness uniformity of the data storage dielectric layer 116, thereby improving the performance and / or reliability of the RRAM device 111.The diffusion barrier layer 114 also improves the variation in the thicknesses of dielectric data storage layers between RRAM cells, thereby improving cell-to-cell variation and yield.

[0015] Fig. 2 shows another embodiment of a cross-sectional view of an integrated chip 200 with an RRAM device.

[0016] The integrated chip 200 includes an RRAM device 111 disposed in a dielectric structure 106 over a substrate 102. In some embodiments, the dielectric structure 106 includes a plurality of stacked ILD (interlevel dielectric) layers 202a-202d. The plurality of stacked ILD layers 202a-202d laterally enclose one or more lower interconnect layers 108 having interconnect vias 109 and interconnect wires 110. The one or more lower interconnect layers 108 are configured to connect the RRAM device 111 to an access transistor 104 disposed in the substrate 102.In some embodiments, the access transistor 104 may comprise a MOSFET device having a gate electrode 104d disposed between a source region 104a and a drain region 104b and separated from the substrate 102 by a gate dielectric 104c.

[0017] The RRAM device 111 includes a data storage dielectric layer 116 disposed between a bottom electrode 112 and a top electrode 118. The bottom electrode 112 is disposed above the one or more bottom interconnect layers 108 and is laterally enclosed by a bottom insulating layer 208. In various embodiments, the bottom insulating layer 208 may comprise silicon nitride, silicon dioxide, silicon carbide, or the like. In some embodiments, the data storage dielectric layer 116 may have a bottom surface with a first width and a top surface with a second width that is less than the first width. In these embodiments, the data storage dielectric layer 116 may have a bottom sidewall connected to an upper sidewall by a horizontally extending surface located above the data storage dielectric layer 116.In some embodiments, the data storage dielectric layer 116 may have a thickness of about 3 nm to about 10 nm. In other embodiments, the data storage dielectric layer 116 may have a thickness of about 2.5 nm to about 7.5 nm. In some embodiments, the top electrode 118 may have a thickness of about 5 nm to about 20 nm.

[0018] In some embodiments, the bottom electrode 112 may include a bottom electrode diffusion barrier 112a and a bottom electrode metal 112b disposed over the bottom electrode diffusion barrier 112a. The bottom electrode diffusion barrier 112a is laterally enclosed by the bottom insulating layer 208. The bottom electrode diffusion barrier 112a fills an opening defined by sidewalls of the bottom insulating layer 208. In some embodiments, the bottom electrode diffusion barrier 112a may extend from a position in the opening to a position above the bottom insulating layer 208. In these embodiments, the bottom electrode diffusion barrier 112a may have a first thickness between the sidewalls of the bottom insulating layer 208 and a smaller second thickness above the bottom insulating layer 208. In some embodiments, the first thickness may be about 20 nm to about 40 nm.In some embodiments, the bottom electrode metal 112b may have a thickness of about 5 nm to about 30 nm. In some embodiments, the bottom electrode diffusion barrier 112a has a curved bottom sidewall enclosed by the bottom insulating layer 208 and a substantially planar top sidewall above the bottom insulating layer 208. In some embodiments, the bottom electrode diffusion barrier 112a may have a substantially planar top surface.

[0019] In some embodiments, the bottom electrode metal 112b may comprise a first conductive material, and the bottom electrode diffusion barrier 112a and the top electrode 118 may comprise one or more conductive materials different from the first conductive material. In some embodiments, the bottom electrode metal 112b may be, for example, a noble metal such as platinum, ruthenium, iridium, gold, or the like. The noble metal provides the RRAM device 111 with good durability and data retention. This is because the noble metal has low reactivity with ions (e.g., oxygen ions) and thus may help prevent oxygen ions from entering the bottom electrode 112 during RRAM run-through. The bottom electrode diffusion barrier 112a and the top electrode 118 may comprise a metal such as titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, or the like.In some embodiments, the bottom electrode diffusion barrier 112a and the top electrode 118 may comprise the same material.

[0020] A diffusion barrier layer 114 is disposed between the bottom electrode 112 and a data storage dielectric layer 116. The diffusion barrier layer 114 is vertically separated from the bottom electrode diffusion barrier 112a by the bottom electrode metal 112b. In some embodiments, the diffusion barrier layer 114 contacts the bottom electrode metal 112b along a substantially planar interface. The diffusion barrier layer 114 may comprise a different material than the bottom electrode metal 112b. In some embodiments, the diffusion barrier layer 114 may comprise tantalum nitride, titanium nitride, titanium carbonitride, tungsten nitride, or the like. In other embodiments, the diffusion barrier layer 114 may comprise a noble metal oxide (e.g., ruthenium oxide, iridium oxide, rhodium oxide, or the like) or a noble metal nitride (e.g., ruthenium nitride, iridium nitride, or the like).

[0021] The diffusion barrier layer 114 has a thickness t1 sufficient to prevent etch bumps containing metal atoms (e.g., noble metal atoms) of the bottom electrode 112 from forming and extending into the data storage dielectric layer 116. In some embodiments, the thickness t1 is about 0.5 nm to about 3 nm. A thickness of the diffusion barrier layer 114 less than 0.5 nm may not effectively and reliably prevent the diffusion of metal atoms from the bottom electrode metal 112b, while a thickness of the diffusion barrier layer 114 greater than 3 nm may impair the performance of the RRAM device 111 because the benefits of using a noble metal in the bottom electrode 112 are mitigated. In other embodiments, the thickness t1 may have different values.

[0022] A capping layer 210 is disposed between the data storage dielectric layer 116 and the top electrode 118. The capping layer 210 is configured to store oxygen, which may facilitate resistive changes in the data storage dielectric layer 116. In various embodiments, the capping layer 210 may comprise hafnium, titanium, tantalum, aluminum, zirconium, or the like. In some embodiments, the capping layer 210 may have a thickness of about 7 nm to about 20 nm. In some embodiments, a dielectric spacer 212 may be disposed along sidewalls of the capping layer 210 and the top electrode 118. In some embodiments, the dielectric spacer 212 may also be disposed along a sidewall of the data storage dielectric layer 116.In some embodiments, the dielectric spacer 212 may be disposed on a horizontally extending surface of the top electrode 118 and / or the data storage dielectric layer 116. In some embodiments, the dielectric spacer 212 may comprise a nitride (e.g., silicon nitride), an oxide (e.g., silicon oxide), a carbide (e.g., silicon carbide), or the like.

[0023] In some embodiments, sidewalls of the diffusion barrier layer 114 may be inclined at a first angle α relative to a top surface of the lower insulating layer 208. The first angle α may be greater than 90°. In some embodiments, the sidewalls of the diffusion barrier layer 114 may be aligned along a line with sidewalls of the lower electrode 112 and the data storage dielectric layer 116. In some embodiments, the sidewalls of the capping layer 210 may be aligned at a second angle β relative to a top surface of the data storage dielectric layer 116. The second angle β may also be greater than 90°. In some embodiments, the first angle α is different from (e.g., greater than) the second angle β.

[0024] Fig. 3A shows a cross-sectional view of another embodiment of an integrated chip 300 with an RRAM device.

[0025] The integrated chip 300 includes an RRAM device 301 disposed over a substrate 102. The RRAM device 301 includes a data storage dielectric layer 116 disposed between a bottom electrode 112 and a top electrode 118. The bottom electrode 112 includes a bottom electrode diffusion barrier 112a and a bottom electrode metal 112b over the bottom electrode diffusion barrier 112a. A capping layer 210 may be disposed between the data storage dielectric layer 116 and the top electrode 118.

[0026] The bottom electrode diffusion barrier 112a, the bottom electrode metal 112b, the data storage dielectric layer 116, the capping layer 210, and the top electrode 118 each have an inner region 302 laterally enclosed by an outer region 304. The inner region 302 has a recessed top surface disposed laterally between and vertically below top surfaces of the outer region 304. As shown in a top view 306 of Fig. 3B, the outer region 304 of the bottom electrode diffusion barrier 112a extends along an outer perimeter of the bottom electrode diffusion barrier 112a. In some embodiments, the outer region 304 may extend continuously in a seamless ring around the inner region 302.

[0027] In some embodiments, the bottom electrode diffusion barrier 112a, the bottom electrode metal 112b, the diffusion barrier layer 114, the capping layer 210, and the top electrode 118 may each have a substantially equal thickness between outer sidewalls. For example, the bottom electrode diffusion barrier 112a may have a substantially equal thickness of about 3 nm to about 20 nm. In some embodiments, the inner region 302 of the data storage dielectric layer 116 may have a first thickness, and the outer region of the data storage dielectric layer 116 may have a second thickness that is less than the first thickness.

[0028] Fig. 4A shows a cross-sectional view of another embodiment of an integrated chip 400 with an RRAM device.

[0029] The integrated chip 400 includes a substrate 102 with a logic region 402 and an embedded memory region 404. As shown in a top view 416 of Fig. 4B, in some embodiments, the logic region 402 may enclose the embedded memory region 404.

[0030] In Fig. 4A, a dielectric structure 106 is disposed over the substrate 102. The dielectric structure 106 includes a plurality of stacked ILD layers 202a-202d separated by etch stop layers 406. In some embodiments, the plurality of stacked ILD layers 202a-202d may include an oxide layer, a low-k dielectric layer, and / or an ultra-low-k dielectric layer, or the like. In some embodiments, the etch stop layers 406 may include a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

[0031] The logic region 402 includes a transistor device 408 arranged in the substrate 102. The transistor device 408 includes a source region 408a, a drain region 408b separated from the source region 408a by a channel region, and a gate structure 408g over the channel region. In some embodiments, the transistor device 408 may comprise a high-k metal gate (HKMG) transistor. In these embodiments, the gate structure 408g may include a metal gate electrode (e.g., made of aluminum, ruthenium, palladium, or the like) and a gate dielectric that is a high-k dielectric (e.g., aluminum oxide, hafnium oxide, or the like). In other embodiments, the gate structure 408g may include a polysilicon gate electrode and a gate dielectric comprising an oxide (e.g., silicon dioxide).

[0032] The source region 408a is connected to a plurality of interconnect layers enclosed by the dielectric structure 106. The plurality of interconnect layers include conductive contacts 410, bond wires 412, and interconnect vias 414. In some embodiments, the plurality of interconnect layers may comprise copper, tungsten, aluminum, and / or the like.

[0033] The embedded source region 408a includes an access transistor 104 disposed in the substrate 102. The access transistor 104 is connected to an RRAM device 111. The RRAM device 111 is disposed along a horizontal plane that crosses one of the interconnect vias 414 in the logic region 402. In some embodiments, one or more isolation structures 405 may be disposed in the substrate 102 on opposite sides of the access transistor 104. The isolation structures 405 may include one or more dielectric materials disposed in trenches defined by inner surfaces of the substrate 102. In some embodiments, the isolation structures 405 may include shallow trench isolation (STI) structures.In these embodiments, the isolation structures 405 may comprise the same isolation structure that extends in a closed loop around a perimeter of the access transistor 104.

[0034] Fig. 5 shows some further embodiments of an integrated chip 500 with an RRAM device.

[0035] The integrated chip 500 has a 1T1R RRAM cell architecture (1T1R: 1 transistor, 1 resistor) with an access transistor 104 connected to an RRAM device 111. The access transistor 104 is arranged in a substrate 102. In some embodiments, the access transistor 104 may comprise a MOSFET device with a gate electrode 104d arranged between a source region 104a and a drain region 104b and separated from the substrate 102 by a gate dielectric 104c.

[0036] A dielectric structure 106 is arranged above the substrate 102. One or more lower interconnect layers 108 with conductive contacts 107, interconnect vias 109, and interconnect wires 110 are enclosed by the dielectric structure 106. The interconnect wires 110 comprise a source line SL with a first interconnect wire electrically connected to the source region 104a. In some embodiments, the source line SL can be arranged in a second interconnect wire layer connected to the source region 104a via a conductive contact, a first interconnect wire, and a first interconnect via. The interconnect wires 110 further comprise a word line WL with a second interconnect wire electrically connected to the gate electrode 104d.In some embodiments, the word line WL may be arranged in the first bond wire layer, which is connected to the gate electrode 104d via a conductive contact.

[0037] An RRAM device 111 is arranged above the dielectric structure 106. The RRAM device 111 has a lower electrode 112 separated from an upper electrode 118 by a diffusion barrier layer 114, a dielectric data storage layer 116, and a capping layer 210. The lower electrode 112 is directly connected to the drain region 104b by one or more lower interconnect layers 108. The upper electrode 118 is connected to a bit line BL by an upper interconnect structure 120.

[0038] In some embodiments, dielectric spacers 212 are disposed along opposite sides of the top electrode 118. In some embodiments, the dielectric spacers 212 may include a horizontally extending segment 212a extending from a sidewall of the dielectric spacers 212. In various embodiments, horizontally extending segments may extend from opposite sides of the dielectric spacers 212, or a horizontally extending segment may extend from only one side, but not an opposite side, of the dielectric spacers 212.

[0039] In integrated chip 500, while the word line WL, the source line SL, the bit line BL, and the RRAM device 111 are illustrated as being arranged at specific levels in a back end of line (BEOL) stack, it should be understood that the positions of these elements are not limited to the positions illustrated. Rather, the elements may be arranged at other positions in a BEOL stack. For example, in some alternative embodiments, the RRAM device 111 may be arranged between a second and a third bond wire.

[0040] Fig. 6 shows some further embodiments of an integrated chip 600 with an RRAM device.

[0041] The integrated chip 600 has a 2T1R RRAM cell architecture (2T1R: 2 transistors, 1 resistor) with a first access transistor 602 and a second access transistor 604 connected in parallel with an RRAM device 111. The first access transistor 602 and the second access transistor 604 are arranged in a substrate 102. In some embodiments, the first access transistor 602 has a first gate electrode 602a arranged between a first source region 602b and a common drain region 603. The first source region 602b is connected to a source line SL, and the first gate electrode 602a is connected to a word line WL. The second access transistor 604 has a second gate electrode 604a arranged between a second source region 604b and the common drain region 603.The second source region 604b is connected to the source line SL, and the second gate electrode 604a is connected to the word line WL.

[0042] One or more lower interconnect layers 108 connect the common drain region 603 to the RRAM device 111, which is arranged in a dielectric structure 106 above the substrate 102. By connecting the common drain region 603 to the RRAM device 111, a drive current provided to the RRAM device 111 can be increased over RRAM cells that use only one access transistor (such as in Fig. 5 is shown).

[0043] The Fig. 7 to 17 show sectional views 700 to 1700 of some embodiments of a method for manufacturing an integrated chip with an RRAM device having a diffusion barrier layer disposed between a bottom electrode and a data storage layer. Fig. Although paragraphs 7 to 17 are described for one procedure, it should be understood that the Fig. 7 to 17 are not limited to this method, but rather can be used as stand-alone structures independent of the method.

[0044] As shown in a sectional view 700 of Fig. 7, a substrate 102 is provided. In various embodiments, the substrate 102 may include any type of semiconductor body (e.g., silicon / CMOS bulk material, SiGe, SOI, etc.), such as a semiconductor wafer or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers formed thereon and / or otherwise associated therewith. In some embodiments, one or more isolation structures 405 (e.g., STI structures) may be formed in the substrate 102. The one or more isolation structures 405 may be formed by selectively etching the substrate 102 to form a trench 702 defined by sidewalls of the substrate 102. The trench 702 is then filled with one or more conductive materials.

[0045] An access transistor 104 is formed over the substrate 102. In some embodiments, the access transistor 104 may be formed by forming a gate dielectric over the substrate and depositing a gate material over the gate dielectric. The gate dielectric and gate material may be deposited using vapor deposition processes (e.g., CVD, PECVD, PVD, or ALD). In some embodiments, the gate material may comprise doped polysilicon. In some embodiments, the gate material may be a sacrificial gate material that is later replaced with a metallic gate material, such as aluminum, cobalt, ruthenium, or the like.

[0046] The gate dielectric and the gate material are patterned to define a gate structure including a gate dielectric 104c and a gate electrode 104d over the gate dielectric 104c. In some embodiments, the gate dielectric and the gate material may be selectively patterned according to a masking layer (not shown) formed over the gate material. In some embodiments, the masking layer may comprise a photosensitive material (e.g., photoresist) deposited by spin coating. In these embodiments, the photosensitive material is selectively exposed to electromagnetic radiation according to a photomask. The electromagnetic radiation modifies a solubility of exposed regions in the photosensitive material to define soluble regions.The photosensitive material is then developed to define openings in the photosensitive material by removing the soluble regions. In other embodiments, the masking layer may comprise a hard mask layer (e.g., a silicon nitride layer, a silicon carbide layer, or the like).

[0047] As shown in a sectional view 800 of Fig. 8, one or more lower interconnect layers 108 are formed in one or more stacked lower ILD layers 202a-202c (e.g., comprising an oxide, a low-k dielectric, or an ultra-low-k dielectric) over the substrate 102. In some embodiments, the one or more lower interconnect layers 108 may each be formed by selectively etching one of the one or more stacked lower ILD layers 202a-202c to define an opening in the ILD layer. Then, a conductive material (e.g., copper, aluminum, or the like) is deposited to fill the opening, and a planarization process (e.g., chemical mechanical planarization) is performed to remove excess conductive material over the ILD layer.

[0048] As shown in a sectional view 900 of Fig. 9, a lower insulating layer 208 is formed on the one or more lower interconnect layers 108 and the one or more lower ILD layers 202a-202c. In some embodiments, the lower insulating layer 208 may comprise silicon nitride (SiN) or silicon carbide (SiC), or a similar composite dielectric layer. In some embodiments, the lower insulating layer 208 may be deposited using a deposition technique such as physical vapor deposition (PVD), chemical vapor deposition (CVD), PECVD, atomic layer deposition (ALD), sputtering, or the like, to a thickness of about 5 nm to about 25 nm. After its deposition, the lower insulating layer 208 is selectively treated with a first etchant 902 (e.g., a dry etchant or a wet etchant) to form sidewalls that define an opening 904 in the lower insulating layer 208.The opening 904 extends through the lower insulating layer 208 to one of the one or more lower interconnect layers 108. In some embodiments, the lower insulating layer 208 may be selectively treated with the first etchant 902 corresponding to a masking layer (not shown) formed over the lower insulating layer 208.

[0049] As shown in a sectional view 1000 of Fig. 10, a bottom electrode structure 1002 is formed over the one or more bottom interconnect layers 108 and the bottom insulating layer 208. The bottom electrode structure 1002 extends from a position in the opening 904 to a position above the bottom insulating layer 208. In some embodiments, the bottom electrode structure 1002 is formed by performing separate depositions to form a bottom electrode barrier layer 1002a and then a bottom electrode metal layer 1002b over the bottom electrode barrier layer 1002a. In some embodiments, the separate depositions may be performed in situ (e.g., without breaking a vacuum in a processing chamber in which the depositions are performed). In some embodiments, the bottom electrode barrier layer 1002a may comprise tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), or the like.In some embodiments, the bottom electrode metal layer 1002b may comprise a noble metal such as platinum (Pt), ruthenium (Ru), iridium (Ir), gold (Au), or the like.

[0050] As shown in a sectional view 1100 of Fig. As shown in Figure 11, a diffusion barrier layer 1102 is formed on the bottom electrode structure 1002. The diffusion barrier layer 1102 is formed to a thickness of about 0.5 nm to about 3 nm. In some embodiments, the diffusion barrier layer 1102 may comprise tantalum nitride (TaN), titanium nitride (TiN), titanium carbonitride (TiCN), tungsten nitride (WN), or the like. In some further embodiments, the diffusion barrier layer 1102 may comprise a noble metal oxide (e.g., ruthenium oxide, iridium oxide, platinum oxide, palladium oxide, or the like) or a noble metal nitride (e.g., ruthenium nitride, iridium nitride, or the like).

[0051] In some embodiments, the diffusion barrier layer 1102 may be deposited using a deposition process (e.g., PVD, CVD, PECVD, ALD, sputtering, or the like). In other embodiments, the diffusion barrier layer 1102 may be formed by treating a noble metal on the bottom electrode 112 with an oxygen gas (e.g., O3) at an elevated temperature (e.g., a temperature greater than or equal to about 150°C) to form a noble metal oxide. In still other embodiments, the diffusion barrier layer 1102 may be formed by treating a noble metal on the bottom electrode 112 with a nitrogen-based plasma (e.g., an N2O plasma) to form a noble metal nitride.

[0052] In some embodiments, the diffusion barrier layer 1102 may be formed in situ with the bottom electrode metal layer 1002b (i.e., without breaking the vacuum). In these embodiments, the diffusion barrier layer 1102 is formed in direct contact with the bottom electrode metal layer 1002b. In other embodiments, the diffusion barrier layer 1102 may be formed ex situ with the bottom electrode metal layer 1002b. In these embodiments, an oxide layer (e.g., having a thickness of about 0.5 nm or less) may be formed on top of the bottom electrode metal layer 1002b. In these embodiments, the diffusion barrier layer 1102 may be separated from the bottom electrode metal layer 1002b by the oxide layer. In other embodiments, a hydrofluoric acid dip bath may be used to remove the oxide layer prior to deposition of the diffusion barrier layer 1102.

[0053] As shown in a sectional view 1200 of Fig. 12, a data storage dielectric layer 1202 is formed over the diffusion barrier layer 1102, a capping layer 1204 is formed over the data storage dielectric layer 1202, and a top electrode structure 1206 is formed over the capping layer 1204. In some embodiments, the data storage dielectric layer 1202 may comprise a high-k dielectric material with a variable resistance. For example, in some embodiments, the data storage dielectric layer 1202 may comprise hafnium oxide (HfO X ), zirconium oxide (ZrO X ), aluminum oxide (AlO X ), nickel oxide (NiO X ), tantalum oxide (TaO X ), titanium oxide (TiO X) or the like. In some embodiments, the capping layer 1204 may comprise a metal, e.g., titanium (Ti), hafnium (Hf), platinum (Pt), aluminum (Al), or the like, or a metal oxide, such as titanium oxide (TiO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), germanium oxide (GeO x ), cesium oxide (CeO x ) or the like. In some embodiments, the top electrode structure 1206 may comprise a metal such as titanium (Ti), tantalum (Ta), or the like.

[0054] As shown in a sectional view 1300 of Fig. 13, a first RRAM patterning process is performed. In the first RRAM patterning process, the top electrode structure 1206 of Fig. 12 is selectively patterned to define an upper electrode 118. In the first RRAM patterning process, the capping layer 1204 of Fig. 12 may be selectively patterned to define a capping layer 210. In some embodiments, the first patterning process includes forming a hard mask layer 1304 over the top electrode structure 1206 of Fig. 12. Then, the upper electrode structure is treated with a second etchant 1302 (e.g., a dry etchant) corresponding to the hard mask layer 1304 to remove unmasked portions of the capping layer 1204 from Fig. 12 and the upper electrode structure 1206 of Fig. 12. In various embodiments, the hard mask layer 1304 may comprise silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbide (SiC), or the like.

[0055] In some embodiments, the first RRAM patterning process may reduce a thickness of outer regions of the data storage dielectric layer 1202, such that the data storage dielectric layer 1202 has a central region with a first thickness and outer regions with a second thickness that is less than the first thickness. In some further embodiments (not shown), the first patterning process may etch the data storage dielectric layer 1202 into the diffusion barrier layer 1102. In these embodiments, the diffusion barrier layer 1102 may have a central region with a thickness that is greater than that of the outer regions.In some of these embodiments, due to different etch selectivities of the diffusion barrier layer 1102 and the data storage dielectric layer 1202, outer sidewalls of the data storage dielectric layer 1202 may be laterally offset by a non-zero distance from an outer sidewall defining the central region of the diffusion barrier layer 1102. In some embodiments, the hardmask layer 1304 may be removed after completion of the first RRAM patterning process.

[0056] As shown in a sectional view 1400 of Fig. 14, in some embodiments, dielectric spacers 212 may be formed on opposite sides of the top electrode 118 and the capping layer 210. The dielectric spacers 212 may also extend over a top surface of the top electrode 118. In various embodiments, the dielectric spacers 212 may comprise silicon nitride, silicon dioxide (SiO2), silicon oxynitride (SiON), or the like. In some embodiments, the dielectric spacers 212 may have outer sidewalls aligned at an angle Ω with respect to a sidewall of the diffusion barrier layer 114. In some embodiments, the angle Ω may be 90° to 180°.

[0057] The dielectric spacers 212 can be formed by depositing a spacer layer on the dielectric data storage layer 1202 of Fig. 13, the capping layer 210, the top electrode 118, and the hard mask layer 1304. In some embodiments, the spacer layer may be formed using a deposition process such as PVD, CVD, PECVD, ALD, sputtering, or the like, with a thickness of about 10 nm to about 50 nm. Subsequently, the spacer layer is patterned (e.g., using a lithographic process) to define the dielectric spacers 212 along opposite sides of the top electrode 118 and above the top electrode 118. In some embodiments, where the second etchant 1302 of Fig. 13 the dielectric data storage layer 116 is etched through, the dielectric spacers 212 can contact sidewalls of the diffusion barrier layer 114.

[0058] In some embodiments, the separate patterning process used to define the dielectric spacers 212 may result in the dielectric spacers 212 having a horizontally extending segment 212a protruding from a sidewall of the dielectric spacers 212. In some embodiments, horizontally extending segments may protrude from opposite sides of the dielectric spacers 212, while in other embodiments (not shown), a horizontally extending segment may protrude from only one side, but not an opposite side, of the dielectric spacers 212.

[0059] After the dielectric spacers 212 are formed, a second RRAM patterning process is performed. In the second RRAM patterning process, an RRAM device 111 is defined by the dielectric data storage layer 1202 being Fig. 13, the diffusion barrier layer 1102 of Fig. 13 and the lower electrode structure 1002 of Fig. 13 to define a data storage dielectric layer 116, a diffusion barrier layer 114, and a bottom electrode 112. In some embodiments, the second RRAM patterning process removes the data storage dielectric layer 1202 from Fig. 13, the diffusion barrier layer 1102 of Fig. 13 and the lower electrode structure 1002 of Fig. 13 is selectively treated with a third etchant 1402 corresponding to a mask having the dielectric spacers 212.

[0060] As shown in a sectional view 1500 from Fig. As shown in Figure 15, an upper insulating layer 1502 may be formed over the RRAM device 111. In various embodiments, the upper insulating layer 1502 may comprise silicon nitride, silicon dioxide (SiO2), silicon oxynitride (SiON), or the like. Subsequently, an upper ILD (interlevel dielectric) layer 202d is formed over the upper insulating layer 1502. The upper insulating layer 1502 has a first side facing the substrate 102 and a second side facing the upper ILD layer 202d.

[0061] As shown in a sectional view 1600 of Fig. As shown in Figure 16, the upper insulating layer 1502 is selectively patterned to form an opening 1602. The opening 1602 is defined by sidewalls of the upper ILD layer 202d, the upper insulating layer 1502, and the hard mask layer 1304. The opening 1602 extends vertically from a top surface of the upper ILD layer 202d to the top electrode 118 of the RRAM device 111.

[0062] As shown in a sectional view from 1700 by Fig. 17, a top interconnect structure 120 is formed in the opening 1602 in the top ILD layer 202d. In some embodiments, the top interconnect structure 120 may include a top interconnect wire or a top interconnect via. In some embodiments, the top interconnect structure 120 may be formed by filling the opening 1602 with a conductive material (e.g., copper and / or aluminum) and then performing a planarization process (e.g., chemical mechanical planarization) to remove excess conductive material from the top ILD layer 202d.

[0063] Fig. 18 shows a flow diagram of some embodiments of a method 1800 for manufacturing an integrated chip with an RRAM device.

[0064] While method 1800 is illustrated and described herein as a series of steps or events, it should be understood that the illustrated order of these steps or events should not be construed in a limiting sense. For example, some steps may occur in different orders and / or concurrently with other steps or events than those illustrated and / or described herein. Furthermore, not all illustrated steps need to implement one or more aspects or embodiments of the description, and one or more of the steps described herein may be performed in one or more separate steps and / or phases.

[0065] In a step 1802, an access transistor is fabricated in a substrate. Fig. 7 shows a sectional view 700 of some embodiments corresponding to step 1802.

[0066] In a step 1804, one or more lower interconnect layers are formed in one or more stacked ILD layers over the substrate. Fig. 8 shows a sectional view 800 of some embodiments corresponding to step 1804.

[0067] In a step 1806, a lower insulating layer is formed over the one or more lower interconnect layers and the one or more stacked ILD layers. The lower insulating layer has an opening extending through the lower insulating layer to the one or more lower interconnect layers. Fig. 9 shows a sectional view 900 of some embodiments corresponding to step 1806.

[0068] In a step 1808, a lower electrode structure is formed over the lower insulating layer and the one or more lower interconnect layers. Fig. 10 shows a cross-sectional view 1000 of some embodiments corresponding to step 1808. In some embodiments, the bottom electrode structure may be formed according to steps 1810 and 1812. In step 1810, a bottom electrode diffusion barrier layer is formed over the plurality of bottom interconnect layers and the bottom insulating layer. Subsequently, in step 1812, a bottom electrode metal layer is formed over the bottom electrode diffusion barrier layer.

[0069] In a step 1814, a diffusion barrier layer is formed over the lower electrode structure. Fig. 11 shows a sectional view 1100 of some embodiments corresponding to step 1814.

[0070] In a step 1816, a dielectric data storage layer is formed over the diffusion barrier layer. Fig. 12 shows a sectional view 1200 of some embodiments corresponding to step 1816.

[0071] In a step 1818, in some embodiments, a capping layer is formed over the dielectric data storage layer. Fig. 12 shows a sectional view 1200 of some embodiments corresponding to step 1818.

[0072] In a step 1820, an upper electrode structure is formed over the capping layer. Fig. 12 shows a sectional view 1200 of some embodiments corresponding to step 1820.

[0073] In a step 1822, the upper electrode structure is selectively patterned to define an upper electrode. Fig. 13 shows a sectional view 1300 of some embodiments corresponding to step 1822.

[0074] In a step 1824, dielectric spacers are formed on opposite sides of the top electrode. Fig. 14 shows a sectional view 1400 of some embodiments corresponding to step 1824.

[0075] In a step 1826, the data storage dielectric layer, the diffusion barrier layer, and the bottom electrode structure are selectively patterned to define a data storage dielectric layer, a diffusion barrier layer, and a bottom electrode. Fig. 14 shows a sectional view 1400 of some embodiments corresponding to step 1826.

[0076] In a step 1828, an upper ILD layer (ILD: interlevel dielectric) is deposited over the upper electrode. Fig. 15 shows a sectional view 1500 of some embodiments corresponding to step 1828.

[0077] In a step 1830, an upper connection structure is formed on the upper electrode. Fig. 16 and Fig.17 show sectional views 1600 and 1700 of some embodiments corresponding to step 1830.

[0078] While the disclosed figures and description refer to RRAM (resistive random access memory) devices, it should be understood that the disclosed diffusion barrier layer is not limited to these memory devices. Rather, in some alternative embodiments, the disclosed diffusion barrier layer may also be used for other types of memory devices (e.g., programmable metallization cell memory devices, phase-change memory devices, or the like).

[0079] Thus, in some embodiments, the present invention relates to an integrated chip with an RRAM cell having a diffusion barrier layer disposed between a bottom electrode and a data storage dielectric layer. The diffusion barrier layer is configured to prevent diffusion of metal atoms (e.g., noble metal atoms) from the bottom electrode into the data storage dielectric layer, allowing the data storage dielectric layer to have a substantially uniform thickness, which increases the reliability of the RRAM device.

[0080] In some embodiments, the present invention relates to an integrated chip. The integrated chip comprises: a bottom electrode disposed over one or more interconnect layers; a diffusion barrier layer disposed over the bottom electrode; a data storage layer separated from the bottom electrode by the diffusion barrier layer; and a top electrode disposed over the data storage layer. In some embodiments, the diffusion barrier layer has a bottom surface directly contacting the bottom electrode and a top surface directly contacting the data storage layer. In some embodiments, the diffusion barrier layer comprises tantalum nitride, titanium nitride, titanium carbonitride, or tungsten nitride. In some embodiments, the diffusion barrier layer comprises a noble metal oxide or a noble metal nitride.In some embodiments, the bottom electrode comprises a bottom electrode diffusion barrier and a bottom electrode metal, wherein the bottom electrode metal is disposed directly between the diffusion barrier layer and the bottom electrode diffusion barrier. In some embodiments, the bottom electrode metal comprises a noble metal. In some embodiments, the top electrode and the bottom electrode diffusion barrier comprise the same material. In some embodiments, the integrated chip further comprises an insulating layer disposed over one or more stacked interlevel dielectric (ILD) layers disposed over the substrate, wherein the bottom electrode diffusion barrier has a curved bottom sidewall enclosed by the insulating layer and a substantially planar top sidewall over the insulating layer.In some embodiments, the diffusion barrier layer has a thickness of about 0.5 Å to about 3 nm. In some embodiments, the diffusion barrier layer has a maximum width that is greater than a width of a top surface of the data storage layer.

[0081] In other embodiments, the present invention relates to an integrated chip. The integrated chip comprises: one or more interconnect layers disposed in one or more stacked interlevel dielectric (ILD) layers over a substrate; a bottom electrode diffusion barrier laterally enclosed by an insulating layer disposed over the one or more stacked ILD layers; a bottom electrode metal having a bottom surface contacting the bottom electrode diffusion barrier, the bottom electrode metal comprising a noble metal; a diffusion barrier layer contacting a top surface of the bottom electrode metal; a data storage dielectric layer contacting the diffusion barrier layer; and a top electrode separated from the bottom electrode metal by the data storage dielectric layer and the diffusion barrier layer.In some embodiments, the top electrode and the bottom electrode diffusion barrier comprise a first material that is different from a second material of the bottom electrode metal. In some embodiments, the top electrode and the bottom electrode diffusion barrier comprise titanium nitride, tantalum nitride, tungsten, or tungsten nitride. In some embodiments, the diffusion barrier layer has an inner region enclosed by an outer region, the inner region having a recessed top surface disposed laterally between and vertically below top surfaces of the outer region. In some embodiments, the diffusion barrier layer has a substantially equal thickness between outer sidewalls.In some embodiments, the integrated chip further comprises dielectric spacers disposed along sidewalls of the top electrode, the dielectric spacers having a horizontal segment extending from a sidewall of the dielectric spacers.

[0082] In still further embodiments, the present invention relates to a method of manufacturing an integrated chip. The method comprises the following steps: forming a bottom electrode structure over one or more interconnect layers, wherein the one or more interconnect layers are arranged in one or more stacked ILD (interlevel dielectric) layers over a substrate; forming a diffusion barrier layer over the bottom electrode structure; forming a data storage dielectric layer on the diffusion barrier layer; forming a top electrode structure over the data storage dielectric layer; and patterning the top electrode structure, the data storage dielectric layer, the diffusion barrier layer, and the bottom electrode structure to define a memory device.In some embodiments, the method further comprises forming the diffusion barrier layer with a thickness that prevents etch bumps comprising noble metal atoms from the bottom electrode structure from forming and extending into the data storage dielectric layer. In some embodiments, forming the bottom electrode structure comprises forming a bottom electrode diffusion barrier layer over the one or more interconnect layers; and forming a bottom electrode metal layer in contact with a top surface of the bottom electrode diffusion barrier layer. In some embodiments, the method further comprises forming the diffusion barrier layer in contact with a top surface of the bottom electrode metal layer; and forming the data storage dielectric layer in contact with a top surface of the diffusion barrier layer.

Claims

[1] Integrated chip with: a lower electrode (112) disposed over one or more interconnect layers (108); a diffusion barrier layer (114) disposed over the lower electrode (112); a data storage layer (116) separated from the lower electrode (112) by the diffusion barrier layer (114); and a top electrode (118) disposed over the data storage layer (116); wherein the diffusion barrier layer (114) comprises a noble metal oxide or a noble metal nitride. [2] The integrated chip of claim 1, wherein the diffusion barrier layer (114) has a bottom surface directly contacting the bottom electrode (112) and a top surface directly contacting the data storage layer (116). [3] The integrated chip of claim 1 or 2, wherein the diffusion barrier layer (114) comprises tantalum nitride, titanium nitride, titanium carbonitride, or tungsten nitride. [4] Integrated chip according to claim 1, wherein the lower electrode (112) comprises a lower electrode diffusion barrier (112a) and a lower electrode metal (112b), and the bottom electrode metal (112b) is arranged directly between the diffusion barrier layer (114) and the bottom electrode diffusion barrier (112a). [5] The integrated chip of claim 4, wherein the bottom electrode metal (112b) comprises a noble metal. [6] The integrated chip of claim 4, wherein the upper electrode (118) and the lower electrode diffusion barrier (112a) comprise the same material. [7] The integrated chip of any one of claims 4 to 6, further comprising an insulating layer (208) disposed over one or more stacked ILD layers (202a-202d) disposed over a substrate (102), wherein the bottom electrode diffusion barrier (112a) has a curved lower sidewall enclosed by the insulating layer (208) and a substantially planar upper sidewall over the insulating layer (208). [8] The integrated chip of any preceding claim, wherein the diffusion barrier layer (114) has a thickness (t1) of about 0.5 nm to about 3 nm. [9] The integrated chip of any preceding claim, wherein the diffusion barrier layer (114) has a maximum width that is greater than a width of a top surface of the data storage layer (116). [10] Integrated chip with: one or more interconnect layers (108) arranged in one or more stacked ILD layers (202a-202d) over a substrate (102); a bottom electrode diffusion barrier (112a) laterally enclosed by an insulating layer (208) disposed over the one or more stacked ILD layers (202a-202d); a bottom electrode metal (112b) having a bottom surface contacting the bottom electrode diffusion barrier (112a), the bottom electrode metal (112b) comprising a noble metal; a diffusion barrier layer (114) contacting a top surface of the bottom electrode metal (112b); a dielectric data storage layer (116) contacting the diffusion barrier layer (114); and a top electrode (118) separated from the bottom electrode metal (112b) by the dielectric data storage layer (116) and the diffusion barrier layer (114). [11] The integrated chip of claim 10, wherein the top electrode (118) and the bottom electrode diffusion barrier (112a) comprise a first material different from a second material of the bottom electrode metal (112b). [12] The integrated chip of claim 10 or 11, wherein the upper electrode (118) and the lower electrode diffusion barrier (112a) comprise titanium nitride, tantalum nitride, tungsten or tungsten nitride. [13] The integrated chip of any one of claims 10 to 12, wherein the diffusion barrier layer (114) comprises an inner region (302) enclosed by an outer region (304), the inner region (302) having a recessed top surface disposed laterally between and vertically below top surfaces of the outer region (304). [14] The integrated chip of any one of claims 10 to 13, wherein the diffusion barrier layer (114) has a substantially equal thickness between outer sidewalls. [15] The integrated chip of any one of claims 10 to 14, further comprising dielectric spacers (212) disposed along sidewalls of the top electrode (118), the dielectric spacers (212) having a horizontally extending segment extending from a sidewall of the dielectric spacers (212). [16] A method of manufacturing an integrated chip comprising the following steps: Forming a lower electrode structure (112) over one or more interconnect layers (108), wherein the one or more interconnect layers (108) are arranged in one or more stacked ILD layers (202a-202d) over a substrate (102); Forming a diffusion barrier layer (114) over the lower electrode structure (112), the diffusion barrier layer (114) comprising a noble metal oxide or a noble metal nitride; forming a dielectric data storage layer (116) on the diffusion barrier layer (114); forming an upper electrode structure (118) over the dielectric data storage layer (116); and Patterning the top electrode structure (118), the dielectric data storage layer (116), the diffusion barrier layer (114), and the bottom electrode structure (112) to define a memory device. [17] The method of claim 16, further comprising forming the diffusion barrier layer (114) with a thickness (t3) that is about 0.5 nm to about 3 nm. [18] The method of claim 16 or 17, wherein forming the lower electrode structure (112) comprises: forming a bottom electrode diffusion barrier layer (114) over the one or more interconnect layers (108); and Forming a bottom electrode metal layer (112b) in contact with a top surface of the bottom electrode diffusion barrier layer (114). [19] The method of claim 18, further comprising: Producing the diffusion barrier layer (114) in contact with an upper surface of the lower electrode metal layer (112b); and Producing the dielectric data storage layer (116) in contact with a top surface of the diffusion barrier layer (114).

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