SENSOR PACKAGE AND PROCEDURE

Abstract

Device with: a sensor die with a first surface and a second surface opposite the first surface, wherein the sensor die has an input / output area and a first sensor area on the first surface; an encapsulation material that encapsulates the sensor die at least laterally; a conductive via that runs through the encapsulation material; a front-side redistribution structure on the first face of the sensor die, wherein the front-side redistribution structure is connected to the conductive via and the sensor die, covers the input / output area of ​​the sensor die, and has a first opening that exposes the first sensor area of ​​the sensor die; and a rear-side redistribution structure on the second surface of the sensor die, wherein the rear-side redistribution structure is connected to the conductive via, wherein the sensor die has a second sensor area on the second surface and the rear redistribution structure has a second opening that exposes the second sensor area of ​​the sensor die.

Description

Background of the invention

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely due to repeated reductions in the minimum feature size, allowing more components to be integrated into a given area. As the demand for miniaturization of electronic components has increased, a need has arisen for faster and more creative packaging methods for semiconductor dies. One example of these packaging systems is InFO technology (InFo: integrated fan-out).

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2018 / 0150667 A1 and US 2017 / 0228529 A1.

[0003] The invention provides a device according to claim 1, a method according to claim 9, and a method according to claim 14. Embodiments are specified in the dependent claims. Short description of the drawings

[0004] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. The Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5A, Fig. 5B, Fig. 5C, Fig. 5D, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 and Fig. 11 show cross-sectional views of intermediate stages in a process for manufacturing a sensor package, according to some embodiments. The Fig. 12, Fig. 13A, Fig. 13B, Fig. 13C, Fig. 13D, Fig. 14A, Fig. 14B, Fig. 14C and Fig. 14D illustrate a sensor device implementing a sensor package, according to some embodiments. The Fig. 15 and Fig. 16 show cross-sectional views of intermediate stages in a process for manufacturing a sensor package, according to some further embodiments. Fig. 17 shows a sensor device implementing a sensor package, according to some further embodiments. The Fig. 18 and Fig. 19 show cross-sectional views of intermediate stages in a process for manufacturing a sensor package, according to some further embodiments. Fig. 20 shows a sensor device implementing a sensor package, according to some further embodiments. The Fig. 21, Fig. 22 and Fig. 23 illustrate a sensor device implementing a sensor package, according to some further embodiments. The Fig. 24A, Fig. 24B and Fig. 24C illustrate package components, according to some embodiments. Detailed description

[0005] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] In some embodiments, a sensor die is encapsulated in an InFO package. The sensor die may include sensing regions on active areas and / or backsides of the sensor die. The InFO package may include openings that expose the sensing regions of the sensor die, while other regions, e.g., input / output (I / O) regions, of the sensor die may remain protected. Compared to other (e.g., wire-bonded) packaging systems, encapsulating a sensor die in an InFO package may allow the form factor of the final sensor package to be smaller, the mechanical reliability of the encapsulated sensor may increase, and the production yield may be higher.

[0008] The Fig. 1 to 11 show cross-sectional views of intermediate stages in a process for manufacturing a package component 100, according to some embodiments. Shown is a single package region in which a sensor package 101 (see Fig. 12). The sensor package 101 may be an integrated fan-out package (InFO package). It should be understood that the package component 100 has numerous package areas. Fig. Figure 12 shows a sensor device 200 implementing the sensor package 101, according to some embodiments. The sensor device 200 may be a device implementing the sensor package 101, such as a smartphone, a tablet, or the like.

[0009] In Fig. 1, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer, allowing multiple packages to be fabricated simultaneously on the carrier substrate 102. The release layer 104 may be made of a polymer-based material that can be removed along with the carrier substrate 102 from overlying structures fabricated in later steps. In some embodiments, the release layer 104 is a heat-removable, epoxy-based material that loses its adhesiveness upon heating, such as a light-to-heat conversion (LTHC) release liner. In other embodiments, the release layer 104 may be an ultraviolet (UV) adhesive that loses its adhesive strength when exposed to UV light.The release layer 104 may be dispensed as a liquid and cured, or it may be a laminate layer coated onto the carrier substrate 102, or the like. The top surface of the release layer 104 may be leveled and may have a high degree of planarity.

[0010] In Fig. 2, a backside redistribution structure 106 is formed on the release layer 104. In the illustrated embodiment, the backside redistribution structure 106 includes a dielectric layer 108 and a metallization structure 110 (sometimes referred to as redistribution layers or redistribution lines). The backside redistribution structure 106 is optional. In some embodiments, the metallization structure 110 is omitted, and only the dielectric layer 108 is formed.

[0011] The dielectric layer 108 is formed on the release layer 104. The underside of the dielectric layer 108 may be in contact with the top side of the release layer 104. In some embodiments, the dielectric layer 108 is made of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 108 is made of a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like; or the like. The dielectric layer 108 may be formed using a suitable deposition method, such as spin coating, chemical vapor deposition (CVD), lamination, or the like, or a combination thereof. The dielectric layer 108 is then patterned to create an opening 112 that exposes portions of the release layer 104.Patterning may be performed using any suitable method, such as by exposing the dielectric layer 108 if the dielectric layer 108 is a photosensitive material, or by etching, for example, by anisotropic etching. The opening 112 has a first width W1. In some embodiments, the first width W1 is about 20,030 µm to about 32,030 µm, which is large enough to accommodate an integrated circuit die.

[0012] Metallization structure 110 is formed on dielectric layer 108. As an example of forming metallization structure 110, a seed layer is formed over dielectric layer 108 and in opening 112. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers made of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, by physical vapor deposition (PVD) or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to metallization structure 110.Patterning creates openings through the photoresist to expose the seed layer. A conductive material is deposited in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be deposited by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof. Then, the photoresist and the portions of the seed layer on which the conductive material has not been deposited are removed. The photoresist can be removed using a suitable stripping process, such as using an oxygen plasma or the like. After the photoresist has been removed, the exposed portions of the seed layer are also removed, for example, using a suitable etching process, such as wet or dry etching.The remaining parts of the seed layer and the conductive material form the metallization structure 110.

[0013] It should be understood that the backside redistribution structure 106 may include any number of dielectric layers and metallization structures. Additional dielectric layers and metallization structures may be formed by repeating the processes for forming the dielectric layer 108 and the metallization structure 110. The metallization structures may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization structure by depositing the seed layer and the conductive material of the metallization structure into the opening of the underlying dielectric layer. The conductive vias may therefore physically and electrically connect the various conductive lines to each other.In embodiments where the backside redistribution structure 106 has multiple layers, the opening 112 may extend through each individual dielectric layer.

[0014] In some embodiments, the backside redistribution structure 106 includes a top dielectric or passivation layer covering and protecting the metallization structure 110. In the illustrated embodiment, the top layer is omitted, and a later-formed encapsulation material is used to protect the metallization structure 110.

[0015] Additionally, conductive vias 116 are formed on the dielectric layer 108 extending away therefrom. As an example of forming the conductive vias 116, a seed layer is formed over the backside redistribution structure 106, e.g., over the dielectric layer 108 and the metallization structure 110. The seed layer for the conductive vias 116 may be different from the seed layer for the metallization structure 110 and may also be formed over the metallization structure 110. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer having a plurality of sublayers composed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer.The seed layer can be formed, for example, by PVD or the like. Then, a photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like and can be exposed for patterning. The pattern of the photoresist corresponds to the conductive vias. Patterning creates openings through the photoresist to expose the seed layer. A conductive material is deposited in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be deposited by plating, such as electroplating or electroless plating, or the like. The conductive material can be a metal such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof. The photoresist and the portions of the seed layer on which the conductive material has not been deposited are removed.The photoresist can be removed using a suitable stripping process, such as using an oxygen plasma or the like. After the photoresist has been removed, the exposed portions of the seed layer are also removed, for example, using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the conductive vias 116. In the illustrated embodiment, the conductive vias 116 are formed directly on the dielectric layer 108 and are connected to the metallization structure 110 by conductive lines. In other embodiments (described below), the conductive vias 116 are plated from features of the metallization structure 110.

[0016] In Fig. 3, an integrated circuit die 126 is adhered to the release layer 104 with an adhesive 128. The integrated circuit die 126 can be arranged in the opening 112 of the backside redistribution structure 106. The integrated circuit die 126 can be any type of die, such as a sensor die, a logic die (e.g., a central processing unit, a microcontroller, etc.), a memory die [e.g., a DRAM die (DRAM: dynamic random access memory), an SRAM die (SRAM: static random access memory), etc.], a power management die [e.g., a PMIC die (PMIC: power management integrated circuit)], a radio frequency (RF) die, a MEMS die (MEMS: microelectromechanical system), a signal processing die [e.g., e.g., a DSP die (DSP: digital signal processing)], a front-end die [e.g., an analog front-end die (AFE die)], or the like, or a combination thereof. The integrated circuit die 126 has a second width W2.When the integrated circuit die 126 is placed in the opening 112, the second width W2 is less than or equal to the first width W1 (see . Fig. 2). In some embodiments, the second width W2 is about 20,000 µm to about 32,000 µm. In other embodiments, the integrated circuit die 126 may be disposed over the opening 112, and in these embodiments, the second width W2 is greater than the first width W1.

[0017] Before the integrated circuit die 126 is adhered to the release layer 104, it may be processed using suitable manufacturing processes to fabricate integrated circuits within the integrated circuit die 126. The integrated circuit die 126 includes, for example, a semiconductor substrate 130, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.Components such as transistors, diodes, capacitors, resistors, etc., may be fabricated in and / or on the active area of ​​the semiconductor substrate 130, which may be interconnected by interconnect structures formed, for example, by metallization structures in one or more dielectric layers on the semiconductor substrate 130 to produce an integrated circuit.

[0018] The integrated circuit die 126 further includes pads 134, such as aluminum pads, copper pads, or the like, for forming external connections. The pads 134 are arranged on the active area of ​​the integrated circuit die 126. One or more passivation layers 136 are arranged on the integrated circuit die 126 and on portions of the pads 134. Openings extend through the passivation layers 136 to expose the pads 134.

[0019] In some embodiments, the integrated circuit die 126 is a sensor die. The sensor die may be an image sensor, an acoustic sensor, or the like. The sensor die may include one or more transducers, and it may also include one or more structural elements that emit signals for measurement during operation. For example, the sensor die may be a fingerprint sensor that operates to emit ultrasonic acoustic waves and measure reflected waves. The integrated circuit die 126 has an I / O region 126A and a sensor region 126B on the active area. The I / O region 126A may (or may not) enclose the sensor region 126B. The sensor region 126B has a third width W3 that is less than the second width W2. In some embodiments, the third width W3 is about 16,000 µm to about 30,000 µm.In some embodiments, the sensor die is packaged in an InFO package such that the sensor region 126B is exposed. In some embodiments, the integrated circuit die 126 further includes a sensor region 126C on the backside of the integrated circuit die 126. In these embodiments, the sensor die is packaged such that the sensor region 126C is also exposed.

[0020] The adhesive 128 is applied to the backside of the integrated circuit die 126 and adheres the integrated circuit die 126 to the release layer 104. The adhesive 128 may be any suitable adhesive, an epoxy, a die attach layer (DAF), or the like. The adhesive 128 may be applied to a backside of the integrated circuit die 126 or over the surface of the carrier substrate 102. For example, the adhesive 128 may be applied to the backside of the integrated circuit die 126 before it is singulated. Likewise, the adhesive 128 may be applied in the opening 112 of the backside redistribution structure 106 before the integrated circuit die 126 is attached.

[0021] While it is shown that only one integrated circuit die 126 is adhered in the illustrated package region, it should be understood that more integrated circuit dies 126 may be adhered in each package region. For example, multiple integrated circuit dies 126 may be adhered in each package region. Furthermore, the sizes and types of integrated circuit dies 126 may vary. In some embodiments, the integrated circuit die 126 may be a die with a large footprint, such as a system-on-chip (SoC) device. In embodiments where the integrated circuit die 126 has a large footprint, the space available for the conductive vias 116 in the package regions may be limited.The use of the rear redistribution structure 106 enables improved interconnect arrangement when the package areas have limited space available for the conductive vias 116. In embodiments using a sensor die, logic dies, memory dies, or a combination thereof may also be integrated into the sensor die.

[0022] In Fig. 4, an encapsulation material 142 is formed on the various components. Once formed, the encapsulation material 142 encapsulates the conductive vias 116 and the integrated circuit die 126, at least laterally. Thus, the metallization structure 110 is disposed between the encapsulation material 142 and the dielectric layer 108. The encapsulation material 142 may be a molding compound, an epoxy, or the like. The encapsulation material 142 may be applied by compression molding, transfer molding, or the like. Subsequently, the encapsulation material 142 is cured. In the illustrated embodiment, the encapsulation material 142 is formed by transfer molding, so that the conductive vias 116 and the integrated circuit die 126 are exposed after molding, and planarization steps (e.g., CMP) can be omitted.Because the encapsulation material 142 is formed by injection molding, recesses 142R may be formed in the encapsulation material 142 between respective conductive vias 116 and the integrated circuit die 126. Furthermore, a top surface of the passivation layers 136 may be located above a top surface of the encapsulation material 142.

[0023] When the integrated circuit die 126 is adhered to the release layer 104, it is pressed onto the release layer 104 to improve the adhesion of the adhesive 128. The adhesive 128 is a moldable material. Therefore, during adhesion, a portion of the adhesive 128 can be squeezed out around the edges of the integrated circuit die 126, and the encapsulation material 142 can be formed around the squeezed-out adhesive 128. Fig. 5A to 5D are detailed views of an area 100A of Fig. 4, showing aspects of the adhesive 128, according to various embodiments.

[0024] The Fig. 5A and Fig. 5B show embodiments in which the first width W1 of the opening 112 (see Fig. 2) greater than the second width W2 of the integrated circuit die 126 (see Fig. 3) is. In Fig. 5A, the adhesive 128 contacts the encapsulation material 142 and a sidewall of the dielectric layer 108. The adhesive 128 has a curved portion that extends from the sidewall of the integrated circuit die 126 to the dielectric layer 108. The curved portion of the adhesive 128 contacts the encapsulation material 142. The nearest edge of the dielectric layer 108 is physically separated from the sidewall of the integrated circuit die 126 only by the adhesive 128. In Fig. 5B, the adhesive 128 contacts the encapsulation material 142 and is physically separated from the dielectric layer 108. The adhesive 128 has a curved portion that extends from the sidewall of the integrated circuit die 126 to below the integrated circuit die 126. The curved portion of the adhesive 128 contacts the encapsulation material 142. The nearest edge of the dielectric layer 108 is physically separated from the sidewall of the integrated circuit die 126 by the adhesive 128 and the encapsulation material 142.

[0025] Fig. Figure 5C shows an embodiment in which the first width W1 of the opening 112 (see Fig. 2) equal to the second width W2 of the integrated circuit die 126 (see Fig. 3) is. In Fig. 5C, the adhesive 128 contacts the encapsulation material 142 as well as a sidewall and a top surface of the dielectric layer 108. The adhesive 128 has a curved portion that extends from the sidewall of the integrated circuit die 126 to the dielectric layer 108. The curved portion of the adhesive 128 contacts the encapsulation material 142. The nearest edge of the dielectric layer 108 is physically separated from the sidewall of the integrated circuit die 126 only by the adhesive 128.

[0026] Fig. Figure 5D shows an embodiment in which the first width W1 of the opening 112 (see Fig. 2) smaller than the second width W2 of the integrated circuit die 126 (see Fig. 3) is. In Fig. 5D, the adhesive 128 contacts the encapsulation material 142 as well as a sidewall and a top surface of the dielectric layer 108. The adhesive 128 has a curved portion extending from the sidewall of the integrated circuit die 126 to the dielectric layer 108. The curved portion of the adhesive 128 contacts the encapsulation material 142. The nearest edge of the dielectric layer 108 is physically separated from the sidewall of the integrated circuit die 126 only by the adhesive 128.

[0027] The Fig. 6 to 8 show the production of a front redistribution structure 144 (see Fig. 8) over the conductive vias 116, the encapsulation material 142, and the integrated circuit die 126. The front-side redistribution structure 144 includes a dielectric layer 146, a metallization structure 148, and a dielectric layer 150. The metallization structure may also be referred to as redistribution layers or redistribution lines. The front-side redistribution structure 144 is shown as an example, and an exemplary method for forming the front-side redistribution structure 144 is discussed herein. More or fewer dielectric layers and metallization structures may be formed in the front-side redistribution structure 144. If more dielectric layers and metallization structures are to be formed, steps and processes discussed below may be repeated.

[0028] The front-side redistribution structure 144 (see Fig. 8) has an opening 152 exposing the sensor region 126B of the integrated circuit die 126. The opening 152 extends through the dielectric layers 146 and 150 of the front-side redistribution structure 144. The metallization structure 148 is not formed in the opening 152, so no materials of the front-side redistribution structure 144 (e.g., materials of the metallization structure 156 and the dielectric layers 146 and 150) are present in the opening 152. In other words, an air gap is located above the sensor region 126B, which is laterally disposed between portions of the front-side redistribution structure 144 and is free of liquid and solid materials. The opening 152 exposes the sensor region 126B of the integrated circuit die 126 so that it can be used even if the integrated circuit die 126 is capped and encapsulated.After creating the opening 152, the I / O region 126A of the integrated circuit die 126 remains uncovered by the front-side redistribution structure 144. The opening 152 has a fourth width W4, which may be greater than or equal to the third width W3. In some embodiments, the fourth width W4 is about 16,006 μm to about 29,734 μm.

[0029] In Fig. 6, the dielectric layer 146 is deposited on the encapsulation material 142, the conductive vias 116, the passivation layers 136, and the pads 134. In some embodiments, the dielectric layer 146 is made of a photosensitive material, such as PBO, polyimide, BCB, or the like, which can be patterned using a lithographic mask. The dielectric layer 146 can be formed by spin coating, lamination, CVD, or the like, or a combination thereof. If the encapsulation material 142 has the recesses 142R, portions of the dielectric layer 146 fill the recesses 142R. The dielectric layer 146 is then patterned. Patterning creates openings 152, 154, and 156 that expose the sensor area 126B, the pads 134, and the conductive vias 116, respectively. The width of opening 152 is greater than the widths of openings 154 and 156.Patterning can be performed using a suitable method, such as by exposing the dielectric layer 146 if the dielectric layer 146 is a photosensitive material, or by etching, for example, anisotropic etching. If the dielectric layer 146 is a photosensitive material, it can be developed after exposure.

[0030] In Fig. 7, the metallization structure 148 is formed. The metallization structure 148 includes conductive lines on and along the main surface of the dielectric layer 146. The metallization structure 148 further includes conductive vias extending through the dielectric layer 146 to physically and electrically connect (e.g., via pads 134) to the conductive vias 116 and the integrated circuit die 126. When the encapsulation material 142 has the recesses 142R, the top surfaces of the encapsulation material 142, the conductive vias 116, and the integrated circuit die 126 may not be at the same height (e.g., in embodiments where the planarization step is omitted).In these embodiments, the vias of the metallization structure 148 that are connected to the integrated circuit die 126 have different lengths than the vias of the metallization structure 148 that are connected to the conductive vias 116.

[0031] To form the metallization structure 148, a seed layer is formed over the dielectric layer 146 and in the openings 152, 154, and 156 that extend through the dielectric layer 146. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers made of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, by PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by spin coating or the like and may be exposed for patterning. The pattern of the photoresist corresponds to the metallization structure 148.Patterning creates openings through the photoresist to expose the seed layer. A conductive material is then deposited in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be deposited by plating, such as electroplating or electroless plating, or the like. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof. The combination of the conductive material and the underlying portions of the seed layer forms the metallization structure 148. The photoresist and the portions of the seed layer on which the conductive material has not been deposited are then removed. The photoresist may be removed using a suitable stripping or stripping process, such as using an oxygen plasma or the like.After the photoresist has been removed, the exposed parts of the seed layer are also removed, for example using a suitable etching process, such as wet or dry etching.

[0032] In Fig. 8, the dielectric layer 150 is deposited on the metallization structure 148 and the dielectric layer 146. The dielectric layer 150 may be formed in a similar manner to the dielectric layer 146 and may be made of the same material as the dielectric layer 146. The opening 152 is then extended through the dielectric layer 150 by patterning the dielectric layer 150 in a similar manner to the dielectric layer 146. After the opening 152 has been extended, it has a first depth D1 measured from a major surface of the passivation layers 136 to a top surface of the dielectric layer 150. In some embodiments, the first depth D1 is about 17 μm to about 25 μm (e.g., less than about 25 μm).

[0033] In the illustrated embodiment, the opening 152 is created during the formation of the front-side redistribution structure 144. The opening 152 may also be created after the formation of the front-side redistribution structure 144. The opening 152 may be created, for example, with an anisotropic etch through the dielectric layers 146 and 150 after their formation.

[0034] In Fig. 9, a carrier substrate stripping is performed to strip the carrier substrate 102 from the adhesive 128 and the backside redistribution structure 106, e.g., the dielectric layer 108. In some embodiments, stripping includes projecting light, such as laser light or UV light, onto the release layer 104 so that the heat of the light decomposes the release layer 104 and the carrier substrate 102 can be removed. The structure is then flipped and placed on a belt 160.

[0035] In Fig. 10, openings 162 are created through the dielectric layer 108 to expose portions of the metallization structure 110 and / or the conductive vias 116. The openings 162 may be created, for example, by laser drilling, etching, or the like. Furthermore, during the opening process, the openings 112 in the backside redistribution structure 106 may be recreated by removing at least a portion of the adhesive 128. The adhesive 128 may be removed, for example, by laser drilling, etching, or the like. In some embodiments, the openings 162 are created and the opening 112 is recreated in the same process, such as the same laser drilling process. After the laser drilling process, a cleaning process may be performed to remove remaining residues of the adhesive 128 and the dielectric layer 108.In embodiments where the integrated circuit die 126 has a sensor region 126C on the backside, the opening 112 exposes the sensor region 126C. Additional elements, such as heat dissipation elements or acoustic insulation layers, can be attached to the integrated circuit die 126 through the opening 112. The InFO package allows these elements to be integrated into the sensor die more easily than with a wire-bonded package.

[0036] In Fig. 11, conductive interconnects 164 are formed in openings 162 and physically and electrically connected to metallization structure 110 and / or conductive vias 116. Conductive interconnects 164 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, conductive interconnects 164 are formed by first forming a layer of solder using such commonly used techniques as vapor deposition, electroplating, printing, solder transfer, ball placement, or the like. After the solder layer is formed on the structure, reflow may be performed to form the material into the desired bump shapes.In another embodiment, the conductive interconnect elements 164 include a flux and are formed in a flux dipping process. In some embodiments, the conductive interconnect elements 164 include a conductive paste, such as solder paste, silver paste, or the like, added in a printing process.

[0037] The Sensor Package 101 (see Fig. 12) is manufactured by performing a singulation process along scribe trench regions of the package component 100. The singulation can be performed by sawing, laser drilling, or the like along the scribe trenches between adjacent package regions. The singulation process separates the adjacent package regions of the package component 100. The resulting singulated sensor packages originate from one of the package regions of the package component 100.

[0038] In Fig. 12, the sensor package 101 is mounted to a package substrate 202 using the conductive interconnect elements 164. The package substrate 202 may be made of a semiconductor material, such as silicon, germanium, diamond, or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide, combinations thereof, and the like may be used. Furthermore, the package substrate 202 may be an SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In an alternative embodiment, the package substrate 202 is based on an insulating core, such as a glass fiber reinforced resin core.An exemplary core material is glass fiber resin, such as FR4. Alternatives for the core material include bismaleimide triazine (BT) resin or other printed circuit board materials or layers. Build-up layers, such as an Ajinomoto build-up layer (ABF), or other laminates can also be used for the package substrate 202.

[0039] The package substrate 202 may include active and passive components (not shown). As one of ordinary skill in the art will appreciate, many different components, such as transistors, capacitors, resistors, combinations thereof, and the like, may be used to meet the structural and functional design requirements for the sensor device 200. The components may be fabricated using any suitable techniques.

[0040] The package substrate 202 may also include metallization layers and vias (not shown) and bond pads 204 over the metallization layers and vias. The metallization layers may be formed over the active and passive components and are designed to connect the various components into functional circuits. The metallization layers may consist of alternating layers of a dielectric material (e.g., a low-k dielectric material) and a conductive material (e.g., copper), with vias connecting the conductive material layers, and may be formed using any suitable method (such as deposition, single-damascene process, dual-damascene process, or the like). In some embodiments, the package substrate 202 includes substantially no active and passive components.

[0041] In some embodiments, the conductive interconnects 164 are reflowed to attach the sensor package 101 to the bond pads 204. The conductive interconnects 164 electrically and / or physically connect the package substrate 202, which includes metallization layers, to the sensor package 101. In some embodiments, passive components, e.g., surface mount devices (SMDs) (not shown), may be attached to the sensor package 101 (e.g., bonded to the bond pads 204) before being mounted on the package substrate 202. In these embodiments, the passive components may be bonded to the same surface of the sensor package 101 as the conductive interconnects 164.

[0042] The conductive interconnects 164 may have an epoxy flux (not shown) applied to them before being reflowed, with at least a portion of the epoxy portion of the epoxy flux remaining after the sensor package 101 has been attached to the package substrate 202. This remaining epoxy portion may act as an underfill to reduce stress and protect the interconnects created by reflowing the conductive interconnects 164. In some embodiments, an underfill (not shown) may be formed between the sensor package 101 and the package substrate 202 to enclose the conductive interconnects 164.The underfill may be formed using a capillary flow process after the sensor package 101 has been attached, or it may be formed using a suitable deposition process before the sensor package 101 is attached.

[0043] In some embodiments, a residue of the adhesive 128 may remain after the opening 112 has been recreated. Fig. 13A to 13D are detailed views of an area 100A of Fig. 12, according to various embodiments. The embodiments of the Fig. 13A to 13D correspond to the embodiments of the Fig. 5A through 5D illustrate embodiments in which, after the removal process, portions of the extruded adhesive 128 remain around sidewalls of a portion of the integrated circuit die 126. As a result, the opening 112 exposes the adhesive 128 but not the sidewalls of the integrated circuit die 126.

[0044] In Fig. 13A, remaining portions of the adhesive 128 have a curved portion extending from the sidewall of the integrated circuit die 126 to the dielectric layer 108. The nearest edge of the dielectric layer 108 is physically separated from the sidewall of the integrated circuit die 126 only by the adhesive 128. In Fig. 13B, remaining portions of the adhesive 128 have a curved portion extending from the sidewall of the integrated circuit die 126 to below the integrated circuit die 126. The nearest edge of the dielectric layer 108 is physically separated from the sidewall of the integrated circuit die 126 by the adhesive 128 and the encapsulation material 142. In Fig. 13C, remaining portions of the adhesive 128 have a curved portion extending from the sidewall of the integrated circuit die 126 to the dielectric layer 108, with no remaining adhesive 128 contacting the sidewalls of the dielectric layer 108. In Fig. 13D, remaining portions of the adhesive 128 have a curved portion extending from the sidewall of the integrated circuit die 126 to the dielectric layer 108, and a portion between the integrated circuit die 126 and the dielectric layer 108 where no remaining adhesive 128 contacts the sidewalls of the dielectric layer 108.

[0045] In some embodiments, no residue of the adhesive 128 remains after the opening 112 has been recreated. Fig. 14A to 14D are detailed views of area 100A of Fig. 12, according to various embodiments. The embodiments of the Fig. 14A to 14D correspond to the embodiments of the Fig. 5A through 5D illustrate embodiments in which no portions of the extruded adhesive 128 remain around the integrated circuit die 126 after the removal process. As a result, the opening 112 extends partially into the encapsulation material 142 and exposes sidewalls of a portion of the integrated circuit die 126.

[0046] In Fig. 14A, the opening 112 has a curved portion that extends from the sidewall of the integrated circuit die 126 to the dielectric layer 108. In Fig. 14B, the opening 112 has a curved portion in the encapsulation material 142. In Fig. 14C, the opening 112 has a curved portion extending from the sidewall of the integrated circuit die 126 to the dielectric layer 108, wherein an edge of the dielectric layer 108 is coplanar with an edge of the integrated circuit die 126. In Fig. 14D, the opening 112 has a curved portion extending from the sidewall of the integrated circuit die 126 to the dielectric layer 108, with an edge of the dielectric layer 108 located below an edge of the integrated circuit die 126.

[0047] The Fig. 15 and Fig. 16 show cross-sectional views of intermediate stages in a process for manufacturing package component 100, according to some further embodiments. In these embodiments, integrated circuit die 126 further includes a sacrificial layer 166 over passivation layers 136 and pads 134. Sacrificial layer 166 is made of a photosensitive polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like.

[0048] In Fig. 15, the encapsulation material 142 is manufactured. The encapsulation material 142 is formed by compression molding such that the conductive vias 116 and the integrated circuit die 126 are buried after molding.

[0049] In Fig. 16, a planarization process is performed on the encapsulation material 142 to expose the conductive vias 116 and the sacrificial layer 166. During the planarization process, the sacrificial layer 166 may also be ground. After the planarization process, the top surfaces of the conductive vias 116, the encapsulation material 142, and the sacrificial layer 166 are coplanar. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, or the like. Subsequently, the sacrificial layer 166 is removed, exposing the sensor area 126B of the integrated circuit die 126. If the sacrificial layer 166 is a photosensitive polymer, it may be removed by exposure and development.

[0050] Fig. 17 shows the sensor device 200. By removing the sacrificial layer 166, a top surface of the passivation layers 136 is located below a top surface of the encapsulation material 142. The opening 152 has a second depth D2 measured from a major surface of the passivation layers 136 to a top surface of the dielectric layer 150. The second depth D2 is greater than the first depth D1. In some embodiments, the second depth D2 is about 22.5 µm to about 32.5 µm.

[0051] The Fig. 18 and Fig. 19 show cross-sectional views of intermediate stages in a process for manufacturing the package component 100, according to some further embodiments. In these embodiments, the integrated circuit die 126 further includes die interconnects 138, such as conductive pillars (e.g., made of a metal such as copper), that extend through the openings in the passivation layers 136 to physically and electrically connect to a respective one of the pads 134. The die interconnects 138 may be formed, for example, by plating or the like. This electrically connects the die interconnects 138 to the integrated circuits of the integrated circuit die 126. A dielectric material 140 is disposed on the active area of ​​the integrated circuit die 126, such as on the passivation layers 136 and the die interconnects 138.The dielectric material 140 laterally encapsulates the die interconnects 138 and is laterally adjacent to the integrated circuit die 126. The dielectric material 140 may be a nitride, such as silicon nitride or the like, and may be deposited, for example, by CVD or the like. The dielectric material 140 has an opening 168 that exposes the sensor region 126B of the integrated circuit die 126 and may be formed using suitable photolithographic and etching techniques. The sacrificial layer 166 is first formed over the dielectric material 140 and in the opening 168.

[0052] In Fig. 18, the encapsulation material 142 is manufactured. The encapsulation material 142 is formed by compression molding such that the conductive vias 116 and the integrated circuit die 126 are buried after molding.

[0053] In Fig. 19, a planarization process is performed on the encapsulation material 142 to expose the conductive vias 116 and the die interconnects 138. The planarization process may also include grinding the sacrificial layer 166. After the planarization process, the top surfaces of the conductive vias 116, the die interconnects 138, the encapsulation material 142, and the dielectric material 140 are coplanar. The planarization process may be, for example, a CMP, a grinding process, or the like. Subsequently, the sacrificial layer 166 is removed, exposing the sensor area 126B of the integrated circuit die 126. If the sacrificial layer 166 is a photosensitive polymer, it may be removed by exposure and development.

[0054] Fig. 20 shows the sensor device 200. The opening 168 has a fifth width W5, which may be smaller than the fourth width W4 of the opening 152. In some embodiments, the fifth width W5 is about 15,806 µm to about 29,534 µm. The openings 152 and 168 have a common third depth D3, which is measured from the main surface of the passivation layers 136 to the top of the dielectric layer 150. The third depth D3 is greater than the second depth D2. In some embodiments, the third depth D3 is about 22.5 µm to about 32.5 µm.

[0055] The Fig. 21, Fig. 22 and Fig. 23 show the sensor device 200 according to some further embodiments. Fig. 21, Fig. 22 and Fig. 23 are each modifications of the embodiments shown in the Fig. 12, Fig. 17 and Fig. 20. In these embodiments, the opening 112 is not created by the backside redistribution structure 106. The opening 112 need not be created in embodiments where the integrated circuit die 126 does not have a sensor region 126C on its backside. In these embodiments, the manufacturing costs are lower.

[0056] The Fig. 24A to 24C show the package component 100 according to further embodiments. Fig. 24A to 24C show modifications of the embodiment of Fig. 21 (where, for example, the encapsulation material 142 is formed by transfer molding and the opening 112 is not formed by the rear redistribution structure 106), but it should be clear that the variations described in the Fig. 24A to 24C can be combined with one of the other embodiments described herein. Fig. 24A shows a modification of the package component 100 in which the metallization structure 110 is omitted and only the dielectric layer 108 is formed. Fig. 24B and Fig. 24C show variations in which the conductive vias 116 are plated from structural elements of the metallization structure 110. The metallization structure 110 may, for example, include pads 114 from which the conductive vias 116 are plated (e.g., using the same seed layer as the pads 114). Fig. 24B, the width of the pads 114 is greater than the width of the conductive vias 116. In these embodiments, for example, the pads 114 may have a width of about 160 µm to about 320 µm, and the conductive vias 116 may have a width of about 150 µm to about 280 µm. In Fig.24C, the width of the pads 114 is smaller than the width of the conductive vias 116. In these embodiments, for example, the pads 114 may have a width of about 140 µm to about 270 µm, and the conductive vias 116 may have a width of about 150 µm to about 280 µm.

[0057] Embodiments may achieve advantages. By encapsulating a sensor die (e.g., integrated circuit die 126) in an InFO package (e.g., sensor package 101), the form factor of the final sensor package can be reduced. For example, some InFO sensor packages can be up to 500 µm smaller than wire-bonded sensor packages. Furthermore, wire loops over the I / O region 126A can be eliminated, reducing the distance between the sensor region 126B and a target, thus increasing the sensitivity of the sensor die. The mechanical reliability of the sensor package can also be improved compared to other (e.g., wire-bonded) packaging systems. The production yield of InFO packages can also be higher than that of wire-bonded packages.Because an InFO package exposes a smaller area of ​​a sensor die than other packaging systems, sensor areas of the sensor die are easier to keep clean, thus increasing accuracy. Finally, support layers or heat dissipation elements can be more easily integrated on an InFO package than on a wire-bonded package.

[0058] In one embodiment, a device comprises: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input / output region and a first sensor region on the first surface; an encapsulation material at least laterally encapsulating the sensor die; a conductive via extending through the encapsulation material; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure connected to the conductive via and the sensor die, covering the input / output region of the sensor die, and having a first opening exposing the first sensor region of the sensor die.

[0059] In some embodiments, the device further comprises a backside redistribution structure on the second surface of the sensor die, wherein the backside redistribution structure is connected to the conductive via. In some embodiments of the device, the backside redistribution structure comprises: a dielectric layer; and a metallization structure disposed between the dielectric layer and the encapsulation material, wherein the metallization structure is electrically connected to the conductive via. In some embodiments of the device, the sensor die comprises a second sensing region on the second surface, wherein the backside redistribution structure has a second opening exposing the second sensing region of the sensor die.In some embodiments of the device, the second opening extends partially into the encapsulation material and exposes sidewalls of a portion of the sensor die. In some embodiments, the device further comprises an adhesive enclosing a portion of the sensor die, wherein the second opening exposes the adhesive. In some embodiments of the device, the sensor die comprises: a semiconductor substrate; pads on the semiconductor substrate, wherein the pads are connected to the front-side redistribution structure; and a passivation layer on the pads and the semiconductor substrate, wherein a top surface of the passivation layer is located above a top surface of the encapsulation material.In some embodiments of the device, the sensor die comprises: a semiconductor substrate; pads on the semiconductor substrate, the pads connected to the front-side redistribution structure; and a passivation layer on the pads and the semiconductor substrate, wherein a top surface of the passivation layer is below a top surface of the encapsulation material. In some embodiments of the device, the sensor die comprises: a semiconductor substrate; pads on the semiconductor substrate, the pads connected to the front-side redistribution structure; a passivation layer on the pads and the semiconductor substrate; and a dielectric layer over the passivation layer, the dielectric layer having a second opening exposing the first sensor region of the sensor die, wherein a width of the second opening is smaller than a width of the first opening.In some embodiments of the device, the first sensor region of the sensor die and the first opening of the front-side redistribution structure have the same width.

[0060] In one embodiment, a method comprises the steps of: placing a sensor die adjacent to a conductive via, the sensor die having an input / output region and a first sensor region; encapsulating the sensor die and the conductive via with an encapsulation material; forming a first dielectric layer on the encapsulation material, the sensor die, and the conductive via; patterning the first dielectric layer with a first opening exposing the conductive via, a second opening exposing the input / output region of the sensor die, and a third opening exposing the first sensor region of the sensor die;Forming a first metallization structure extending through the first opening and the second opening of the first dielectric layer, wherein the first metallization structure is not located in the third opening of the first dielectric layer; Forming a second dielectric layer on the first metallization structure and the first dielectric layer; and Extending the third opening through the second dielectric layer to expose the first sensor region of the sensor die.

[0061] In some embodiments of the method, the sensor die comprises a semiconductor substrate and pads on the semiconductor substrate, wherein encapsulating the sensor die comprises: forming the encapsulation material by transfer molding such that a recess in the encapsulation material is located between the semiconductor substrate and the conductive via. In some embodiments of the method, the sensor die comprises a semiconductor substrate and pads on the semiconductor substrate, wherein encapsulating the sensor die comprises: forming the encapsulation material by compression molding; and planarizing the encapsulation material such that top surfaces of the encapsulation material and the conductive via extend over a top surface of the semiconductor substrate.In some embodiments of the method, the sensor die has a sacrificial layer over the semiconductor substrate, and the method further comprises: removing the sacrificial layer to create a fourth opening exposing the first sensor region of the sensor die. In some embodiments, the method further comprises: plating the conductive via on a third dielectric layer; and forming a second metallization structure on the third dielectric layer. In some embodiments of the method, placing the sensor die comprises adhering the sensor die to the third dielectric layer with an adhesive. In some embodiments, the method further comprises creating a fourth opening in the third dielectric layer.In some embodiments of the method, placing the sensor die comprises adhering the sensor die in the fourth opening with an adhesive, the method further comprising: after encapsulating the sensor die, removing at least a portion of the adhesive to expose a second sensor region on the backside of the sensor die.

[0062] In one embodiment, a method comprises the steps of: forming a backside redistribution structure, the backside redistribution structure having a first opening; adhering a sensor die in the first opening of the backside redistribution structure with an adhesive, the sensor die having a first surface and a second surface opposite the first surface; encapsulating the sensor die with an encapsulation material; forming a frontside redistribution structure over the encapsulation material and the sensor die, the frontside redistribution structure having a second opening exposing the second surface of the sensor die; and after forming the frontside redistribution structure, removing the adhesive to expose the first surface of the sensor die.

[0063] In some embodiments, the method further comprises: attaching the backside redistribution structure to a package substrate with conductive interconnects, wherein the conductive interconnects extend through a dielectric layer of the backside redistribution structure to contact a metallization structure of the backside redistribution structure.

Claims

[1] Device with: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input / output region and a first sensor region on the first surface; an encapsulation material that encapsulates the sensor die at least laterally; a conductive via passing through the encapsulation material; a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, covering the input / output region of the sensor die, and having a first opening exposing the first sensor region of the sensor die; and a backside redistribution structure on the second surface of the sensor die, wherein the backside redistribution structure is connected to the conductive via, wherein the sensor die has a second sensor region on the second surface and the backside redistribution structure has a second opening exposing the second sensor region of the sensor die. [2] The device of claim 1, wherein the rear redistribution structure comprises: a dielectric layer; and a metallization structure disposed between the dielectric layer and the encapsulation material, wherein the metallization structure is electrically connected to the conductive via. [3] The device of claim 1 or 2, wherein the second opening extends partially into the encapsulation material and exposes sidewalls of a portion of the sensor die. [4] The device of any preceding claim, further comprising an adhesive enclosing a portion of the sensor die, the second opening exposing the adhesive. [5] Device according to one of the preceding claims, wherein the sensor die comprises: a semiconductor substrate; Pads on the semiconductor substrate, the pads being connected to the front-side redistribution structure; and a passivation layer on the pads and the semiconductor substrate, wherein a top surface of the passivation layer is located above a top surface of the encapsulation material. [6] Device according to one of the preceding claims, wherein the sensor die comprises: a semiconductor substrate; Pads on the semiconductor substrate, the pads being connected to the front-side redistribution structure; and a passivation layer on the pads and the semiconductor substrate, wherein a top surface of the passivation layer is located below a top surface of the encapsulation material. [7] Device according to one of the preceding claims, wherein the sensor die comprises: a semiconductor substrate; Pads on the semiconductor substrate, the pads being connected to the front-side redistribution structure; a passivation layer on the pads and the semiconductor substrate; and a dielectric layer over the passivation layer, the dielectric layer having a second opening exposing the first sensor region of the sensor die, a width of the second opening being smaller than a width of the first opening. [8] The device of any preceding claim, wherein the first sensor region of the sensor die and the first opening of the front-side redistribution structure have the same width. [9] Procedure with the following steps: Placing a sensor die adjacent to a conductive via, the sensor die having an input / output region and a first sensor region; Encapsulating the sensor die and the conductive via with an encapsulation material; Forming a first dielectric layer on the encapsulation material, the sensor die and the conductive via; Patterning the first dielectric layer with a first opening exposing the conductive via, with a second opening exposing the input / output region of the sensor die, and with a third opening exposing the first sensor region of the sensor die; Forming a first metallization structure extending through the first opening and the second opening of the first dielectric layer, wherein the first metallization structure is not located in the third opening of the first dielectric layer; Forming a second dielectric layer on the first metallization structure and the first dielectric layer; Extending the third opening through the second dielectric layer to expose the first sensor region of the sensor die; Plating the conductive via on a third dielectric layer; forming a second metallization structure on the third dielectric layer; and Creating a fourth opening in the third dielectric layer, wherein placing the sensor die comprises adhering the sensor die in the fourth opening with an adhesive, and the method further comprises: after encapsulating the sensor die, removing at least a portion of the adhesive to expose a second sensor area on the backside of the sensor die. [10] The method of claim 9, wherein the sensor die comprises a semiconductor substrate and pads on the semiconductor substrate, wherein encapsulating the sensor die comprises: Producing the encapsulation material by transfer molding such that a recess in the encapsulation material is located between the semiconductor substrate and the conductive via. [11] The method of claim 9, wherein the sensor die comprises a semiconductor substrate and pads on the semiconductor substrate, wherein encapsulating the sensor die comprises: Producing the encapsulation material by compression molding; and Planarizing the encapsulation material such that top surfaces of the encapsulation material and the conductive via extend over a top surface of the semiconductor substrate. [12] The method of claim 11, wherein the sensor die further comprises a sacrificial layer over the semiconductor substrate, and the method further comprises: Removing the sacrificial layer to create a fourth opening that exposes the first sensor area of ​​the sensor die. [13] The method of any one of claims 9 to 12, wherein placing the sensor die comprises adhering the sensor die to the third dielectric layer with an adhesive. [14] Procedure with the following steps: Producing a rear redistribution structure, the rear redistribution structure having a first opening; Adhering a sensor die in the first opening of the backside redistribution structure with an adhesive, the sensor die having a first surface and a second surface opposite the first surface; Encapsulating the sensor die with an encapsulation material; forming a front-side redistribution structure over the encapsulation material and the sensor die, the front-side redistribution structure having a second opening exposing the second surface of the sensor die; and After fabricating the front-side redistribution structure, remove the adhesive to expose the first surface of the sensor die. [15] The method of claim 14, further comprising: Attaching the rear redistribution structure to a package substrate with conductive interconnects, wherein the conductive interconnects extend through a dielectric layer of the rear redistribution structure to contact a metallization structure of the rear redistribution structure.

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