Method for processing a silicon carbide wafer

Abstract

A method (100) for processing a silicon carbide wafer (300), the method (100) comprising: Implanting (110) ions into the silicon carbide wafer (300) to form an absorption layer (310) in the silicon carbide wafer (300), wherein for light of a target wavelength, an absorption coefficient of the absorption layer (310) is at least 100 times an absorption coefficient of a silicon carbide material of the silicon carbide wafer (300) outside the absorption layer, wherein the implanting (110) of the ions comprises: implanting ions at a first implantation dose through a first surface of the silicon carbide wafer; Obtaining a wafer surface with reduced near-surface crystal defects compared to the first surface after implanting the ions with the first implantation dose, wherein obtaining the wafer surface with reduced near-surface crystal defects comprises: Annealing the silicon carbide wafer to reduce the near-surface crystal defects on the first surface, wherein the first surface after annealing forms the wafer surface with reduced near-surface crystal defects and / or Forming a silicon carbide layer on the first surface of the silicon carbide wafer, wherein a surface of the silicon carbide layer after its formation forms the wafer surface with reduced near-surface crystal defects; and Implanting ions with a second implantation dose through the wafer surface, after obtaining the wafer surface with reduced near-surface crystal defects; and Cleaving (120) the silicon carbide wafer (300) along the absorption layer (310), at least by irradiating the silicon carbide wafer (300) with light of the target wavelength, to obtain a silicon carbide device wafer (360) and a remaining silicon carbide wafer (362).

Description

AREA

[0001] Examples relate to methods for processing a silicon carbide wafer and to a silicon carbide semiconductor device. BACKGROUND

[0002] Methods for forming silicon carbide semiconductor devices may include grinding a silicon carbide wafer, e.g., to reduce the electrical resistance of the silicon carbide semiconductor device. Grinding can be time-consuming and may involve high consumption of silicon carbide material, leading to high costs for silicon carbide devices. For example, in this case, reuse concepts for forming further silicon carbide semiconductor devices using the silicon carbide wafer are not possible.

[0003] Silicon carbide wafers can be cleaved, enabling reuse concepts. However, cleaving the silicon carbide wafer can limit some semiconductor processes required to form a silicon carbide semiconductor device or can result in an inaccurate thickness of the split wafer portion. For example, a required thickness of a cleaved wafer portion may not be achievable using some cleaving concepts.

[0004] Publication US 2017 / 0 372 965 A1 discloses a method for processing a semiconductor substrate, in which the semiconductor substrate is cleaved at an absorption layer produced by ion implantation using laser radiation. Publication US 2014 / 0 252 373 A1 relates to a manufacturing method for a semiconductor component, in which a semiconductor substrate is bonded to a temporary carrier.

[0005] There is a need for improved concepts for processing silicon carbide wafers. SUMMARY

[0006] Claim 1 relates to a method for processing a silicon carbide wafer. According to the method, ions are implanted into the silicon carbide wafer to form an absorption layer in the silicon carbide wafer. For light of a target wavelength, an absorption coefficient of the absorption layer is at least 100 times an absorption coefficient of a silicon carbide material of the silicon carbide wafer outside the absorption layer. Implanting the ions comprises implanting ions with a first implantation dose through a first surface of the silicon carbide wafer, obtaining a wafer surface with reduced near-surface crystal defects compared to the first surface after implanting the ions with the first implantation dose, and implanting ions with a second implantation dose through the wafer surface after obtaining the wafer surface with reduced near-surface crystal defects.Obtaining the wafer surface with reduced near-surface crystal defects comprises annealing the silicon carbide wafer to reduce the near-surface crystal defects on the first surface, wherein the first surface after annealing forms the wafer surface with reduced near-surface crystal defects, and / or forming a silicon carbide layer on the first surface of the silicon carbide wafer, wherein a surface of the silicon carbide layer after its formation forms the wafer surface with reduced near-surface crystal defects. Furthermore, the method according to claim 1 comprises cleaving the silicon carbide wafer along the absorption layer, at least by irradiating the silicon carbide wafer with light of the target wavelength, to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.

[0007] Another method for processing a silicon carbide wafer according to claim 13 comprises implanting ions into the silicon carbide wafer through a porous silicon carbide layer of the silicon carbide wafer at a front side of the silicon carbide wafer to form an absorption layer in the silicon carbide wafer and cleaving the silicon carbide wafer along the absorption layer at least by irradiating the silicon carbide wafer with light of the target wavelength to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.

[0008] An unclaimed example relates to a silicon carbide semiconductor device. The silicon carbide semiconductor device comprises a silicon carbide semiconductor substrate having a 4H crystal structure and a metallization structure on a front side of the silicon carbide semiconductor substrate. Furthermore, the silicon carbide semiconductor device comprises a backside layer positioned on a backside surface of the silicon carbide semiconductor substrate. The backside layer has a thickness of at least 50 nm and at least partially has a 3C crystal structure. SHORT DESCRIPTION OF THE CHARACTERS

[0009] Some examples of devices and / or methods are described below solely by way of example and with reference to the accompanying figures, in which: Fig. 1 shows a flowchart of a method for processing a silicon carbide wafer, comprising cleaving the silicon carbide wafer; Fig. 2 shows a flowchart of a method for processing a silicon carbide wafer, comprising implanting ions through a porous layer of the silicon carbide wafer; Fig. 3 shows a schematic cross-section of a silicon carbide semiconductor device comprising a porous silicon carbide layer; Fig. 4 shows a schematic cross-section of a silicon carbide semiconductor device comprising a substrate having a 4H crystal structure and a backside layer having a 3C crystal structure; Fig. Figure 5 is a diagram schematically showing vacancy concentrations as a function of the depth of the silicon carbide wafer; Fig. 6 is a diagram schematically showing a reflectance and a transmittance of the silicon carbide wafer as a function of a wavelength; and Fig. 7a-7h show an example of a method for cleaving a semiconductor wafer along an implanted layer by laser illumination. DETAILED DESCRIPTION

[0010] Various examples will now be described in more detail with reference to the accompanying drawings, which illustrate some examples. In the figures, the thicknesses of lines, layers, and / or regions may be exaggerated for clarity.

[0011] Accordingly, while further examples are susceptible to various modifications and alternative forms, certain specific examples thereof are shown in the figures and are described in detail below. However, this detailed description does not limit further examples to the specific forms described. Further examples may cover all modifications, equivalents, and alternatives that fall within the scope of the disclosure. Like or similar reference numerals refer to like or similar elements throughout the description of the figures, which, when compared to one another, may be implemented identically or in modified form while providing the same or a similar function.

[0012] It is understood that when an element is referred to as being "connected" or "coupled" to another element, the elements may be connected or coupled directly, or through one or more intermediate elements. When two elements A and B are combined using "or," it is understood that all possible combinations are disclosed, i.e., only A, only B, and both A and B, unless explicitly or implicitly stated otherwise. Alternative wording for the same combinations is "at least one of A and B" or "A and / or B." The same applies, mutatis mutandis, to combinations of more than two elements.

[0013] The terminology used herein for the purpose of describing specific examples is not intended to be limiting of further examples. Where a singular form, such as "a," "an," and "the," is used, and the use of only a single element is neither explicitly nor implicitly defined as mandatory, further examples may also use plural elements to implement the same function. Where a function is subsequently described as being implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity.It is further understood that the terms "comprises", "comprising", "comprises" and / or "having" when used specify the presence of the specified features, integers, steps, operations, processes, acts, elements and / or components thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components and / or group thereof.

[0014] Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning in the field to which examples belong.

[0015] Fig. 1 shows a flowchart of a method 100 for processing a silicon carbide wafer according to an embodiment. The silicon carbide wafer may be a doped silicon carbide crystal (e.g., with a doping concentration of at least 2 1017 cm -3 and a maximum of 1·10 19 cm -3 , for example of at least 5·10 17 cm -3 and a maximum of 1·10 19 cm -3 ), or can be nominally undoped (e.g. with a doping concentration of at most 1·10 17 cm -3 or of not more than 1·10 ı5 cm -3; so-called "non-intentionally doped silicon carbide"). The method 100 may include implanting 110 ions into the silicon carbide wafer to form an absorption layer within the silicon carbide wafer. The ions may be implanted 110 into the silicon carbide material of the silicon carbide wafer within a region extending laterally across the silicon carbide wafer. Additionally, the silicon carbide wafer with the implanted ions may be annealed to form the absorption layer, for example. The absorption layer may be a lateral absorption layer and / or a buried absorption layer. The absorption layer may extend over the entire silicon carbide wafer or over at least 95% of the wafer area. For example, the ions may be implanted through a front surface of the silicon carbide wafer.For example, an implantation depth or distance of the absorption layer to the surface of the silicon carbide wafer depends on the selected implantation energy.

[0016] A lateral absorption layer may have a lateral dimension that is significantly larger than a vertical dimension. For example, a maximum lateral dimension of the lateral absorption layer may be at least five times (or at least 10 times, or at least 20 times, or at least 100 times, or at least 1000 times, or at least 10,000 times, or at least 50,000 times) a maximum vertical dimension of the lateral absorption layer. The lateral absorption layer may be positioned at a surface of the silicon carbide wafer or may be buried within the silicon carbide wafer. The vertical dimension may be measured orthogonal to a front surface of the silicon carbide wafer, and the lateral dimension may be measured parallel to the front surface of the silicon carbide wafer.

[0017] For example, the buried absorption layer may be formed within the silicon carbide wafer such that the buried absorption layer is positioned at a distance from a surface of the silicon carbide wafer. In other words, the buried absorption layer may be buried within the silicon carbide wafer. For example, a first portion of the silicon carbide wafer is positioned between a front surface of the silicon carbide wafer and the buried absorption layer, and a second portion of the silicon carbide wafer is positioned between a back surface of the silicon carbide wafer and the buried absorption layer.

[0018] For example, an absorption coefficient of the absorption layer may be higher than an absorption coefficient of a silicon carbide material of the silicon carbide wafer outside the absorption layer, at least for light of a target wavelength. This means that the absorption layer may have a higher refractive index (e.g., a higher imaginary part) than the silicon carbide material, at least for the target wavelength. Hereinafter, an absorption coefficient of a layer and / or material may be the average absorption coefficient of the layer and / or material, wherein regions of the layer and / or material that have an absorption coefficient that deviates by more than two standard deviations from the average absorption coefficient may not be included in the average.

[0019] The silicon carbide material of the silicon carbide wafer outside the absorption layer can surround the absorption layer at least vertically. The absorption coefficient of the absorption layer can be at least 5 times (or at least 10 times, at least 20 times, at least 30 times, or at least 50 times) the absorption coefficient of the silicon carbide material of the silicon carbide wafer outside the absorption layer, or the absorption coefficient of the absorption layer can, as claimed, be at least 100 times (or at least 200 times, at least 500 times, at least 850 times, or at least 1,000 times) the absorption coefficient of the silicon carbide material of the silicon carbide wafer outside the absorption layer, for light of the target wavelength. Achieving an absorption coefficient of the absorption layer, e.g.higher than 100 times the absorption coefficient, as claimed, of the silicon carbide material of the silicon carbide wafer outside the absorption layer, e.g. in a silicon carbide wafer used to form a semiconductor device, may be possible using a concept proposed below.

[0020] The target wavelength may be a characteristic wavelength (e.g., wavelength of a laser or a maximum in a spectrum) of the light used to cleave 120 the silicon carbide (SiC) wafer. For example, the term "light of a target wavelength" may refer to light with a wavelength distribution that has a local, in particular a global, maximum at the target wavelength. Additionally or as an alternative, the term "light of a target wavelength" may refer to light with a frequency distribution that has a local, in particular a global, maximum that differs by at most 1 GHz (or at most 0.5 GHz, or at most 100 MHz) from the frequency corresponding to the target wavelength.However, higher frequency deviations from the local or global maximum of the frequency distribution may be possible, for example, if the energy of the light at the target wavelength exceeds the energy required for the chemical decomposition of the absorption layer. In the following, the term "light" is not to be understood as encompassing only a visible wavelength, but refers to electromagnetic radiation, such as visible light, UV light, and infrared light.

[0021] The ions implanted 110 into the silicon carbide material can increase the absorption coefficient within the absorption layer compared to the silicon carbide material without the implanted ions. For example, an implantation dose can be adjusted and / or a species of the implanted ions can be selected depending on the wafer material to achieve the higher absorption coefficient and / or to control the value of the absorption coefficient of the absorption layer.

[0022] The method 100 may further comprise cleaving 120 the silicon carbide wafer along the absorption layer, as claimed. For example, the absorption layer may be formed to provide a defined cleavage region of the silicon carbide wafer. Cleaving 120 may be achieved by irradiating at least the silicon carbide wafer with light of the target wavelength. For example, the silicon carbide wafer may be cleaved solely by irradiating the silicon carbide wafer, or additional processes (e.g., heating, applying mechanical stress, and / or force and / or ultrasonic treatment) may be performed to cleave the SiC (silicon carbide) wafer.

[0023] For cleaving 120 the silicon carbide wafer, for example, an energy of the light of the target wavelength can be selected based on an energy required to cleave the SiC wafer, based on the absorption coefficient of the absorption layer, based on a thickness of the silicon carbide wafer, based on a thickness of the absorption layer, and / or based on a position of the absorption layer within the silicon carbide wafer (e.g., to account for additional absorption by the silicon carbide wafer). The light of the target wavelength can be radiated onto the front side and / or onto a back side of the silicon carbide wafer. Due to the higher absorption coefficient of the absorption layer, a larger proportion of the light of the target wavelength can be absorbed within the absorption layer than in the SiC material of the SiC wafer outside the absorption layer.For example, light of the target wavelength absorbed within the absorption layer may cause decomposition or destruction of at least a portion, e.g., a laterally connected region, of the absorption layer, so that the silicon carbide wafer may be cleaved along the absorption layer 120. Released energy from the light of the target wavelength absorbed within the absorption layer may cause cleavage 120 of the silicon carbide wafer.

[0024] For example, a silicon carbide device wafer and a remaining silicon carbide wafer may be obtained by cleaving 120 the silicon carbide wafer. Both the remaining silicon carbide wafer and the silicon carbide device wafer may comprise the silicon carbide material of the silicon carbide wafer outside the absorption layer as a main material or may be made of the silicon carbide material. Cleaving 120 the silicon carbide wafer along the absorption layer by irradiating the absorption layer may make it possible to define a thickness of the silicon carbide device wafer more precisely and / or with reduced variation along a lateral extent of the silicon carbide device wafer and / or more homogeneously along a lateral extent of the silicon carbide device wafer, e.g., compared to other cleaving methods. For example, the method 100 may improve control over the thickness of the silicon carbide device wafer.A thickness of the absorption layer may be smaller compared to a thickness of other cleavage regions, so that a variation in the thickness of the silicon carbide device wafer can be reduced. Material consumption of the silicon carbide wafer for cleavage 120 can also be reduced by providing a reduced thickness to the absorption layer, e.g., compared to using thicker cleavage regions, which may be required, in particular, by other concepts without using an absorption layer.

[0025] Examples relate to aspects that may enable the formation of absorption layers with an absorption coefficient that is higher than 5 times, or even higher than 100 times, as claimed, compared to the absorption coefficient of the silicon carbide material of the silicon carbide wafer outside the absorption layer. To increase the absorption coefficient of the absorption layer, it may be necessary to implant ions with an increased implantation dose 110. However, when ions are implanted 110 through a first surface of the silicon carbide wafer, defects such as vacancies may occur at the first surface and / or in a region near the first surface. With a higher implantation dose, the defect density may increase. Such defects, e.g., above a critical defect density, may, for example, limit the quality of an epitaxial layer grown on the first surface.

[0026] For example, above a critical implantation dose (e.g. used to implant the ions 110 to form the absorption layer), surface irregularities (e.g. defects such as vacancies and / or vacancy clusters) may arise after implantation, which may prevent proper epitaxial growth on the surface (e.g.

[0027] Growth of an epitaxial silicon carbide layer having a 4H crystal structure, i.e., a 4H-SiC layer). For example, a high-quality epitaxial layer may be required, and the maximum absorption capacity (e.g., upper limit of the absorption coefficient) of the introduced layer (e.g., the absorption layer) may be limited according to some examples, since a maximum implantation dose for implanting 110 ions may be limited by the occurrence of surface defects. For example, a vacancy concentration of, e.g., 3 10 22 cm-3 in a region near or in direct contact with the first surface after implantation may be an upper limit for proper epitaxial growth (e.g., regardless of the type of implanted 110 species or ions). Hereinafter, the vacancy concentration in a region near or in direct contact with a specific surface is also referred to as the vacancy concentration "of" the specific surface.

[0028] It may be necessary to provide methods that enable an increased implantation dose for forming the absorption layer with an increased absorption coefficient while simultaneously keeping a defect concentration, e.g., a maximum vacancy concentration, of a silicon carbide wafer surface below a certain limit. Examples are suggested below that may enable the formation of an absorption layer with a high absorption coefficient while simultaneously providing a good surface quality of a surface of the silicon carbide wafer through which the ions are implanted 110.

[0029] For example, a temperature of the silicon carbide wafer during the ion implantation 110 may be at least 250°C (or at least 300°C, at least 350°C, at least 400°C, at least 450°C, at least 500°C, at least 600°C, at least 700°C, or at least 800°C) and / or at most 1000°C (or at most 800°C, at most 700°C, or at most 600°C). For example, the silicon carbide wafer may be heated to a temperature of at least 300°C prior to implanting 110 of the ions into the silicon carbide wafer to form the absorption layer, and the temperature of the silicon carbide wafer may be maintained at a temperature above 300°C during the ion implantation 110.

[0030] When ions are implanted through a surface of the silicon carbide wafer at an elevated temperature during implantation, defects at or near the surface (e.g., near-surface crystal damage such as V, V2, Z1, Z2, and / or other defects) may be limited. For example, when implanting 110 ions at a silicon carbide wafer temperature of 300°C or higher, good crystal quality (e.g., of an epitaxial layer) may be achieved after a high-dose implantation. For example, stable end-of-domain defects (e.g., within the absorption layer) may not be significantly affected by the elevated temperatures. A temperature range to be used may be between 300°C and a maximum implantation temperature, e.g., 700°C. For example, a 4H-SiC configuration may be maintained at the surface of the silicon carbide wafer at implantation temperatures of 300°C and higher. In other processes, e.g.,With a high-dose implantation at a wafer temperature of only 200°C (and, for example, with an 1800°C anneal for, say, 3 minutes after implantation), a 3C-SiC epitaxial layer can grow on the surface. Since high implantation doses may be required to form the absorption layer, the additional time required to raise the wafer temperature from room temperature to the elevated temperature (e.g., above 300°C) may only slightly increase the process cost or time.

[0031] For example, the implantation 110 of the ions may be performed through two or more implantation processes and an intermediate process such as annealing or layer growth in between. Accordingly, ions may be implanted with a first implantation dose. After implanting the ions with the first implantation dose, a separate process may be performed to obtain a wafer surface with reduced near-surface crystal defects or fewer near-surface crystal defects (e.g., lower defect density), for example. Subsequently, the implantation 110 of the ions may comprise implanting ions with a second implantation dose after obtaining the wafer surface with reduced near-surface crystal defects. The ions may be implanted with the second implantation dose through the surface with reduced or lower defect density.

[0032] The first implantation dose may be above a critical dose if, for example, the defect density at the surface is reduced after implanting the first implantation dose. For example, if ions are implanted with an implantation dose above the critical dose before reducing the near-surface crystal defects in order to obtain the wafer surface with reduced near-surface crystal defects, only a low-quality epitaxial layer may be grown on the surface, whereas after reducing the near-surface crystal defects, a high-quality epitaxial layer may be grown on the surface. For example, the first and / or second implantation dose may be at most 3.0 10 16 cm -2 (or at most 2.00·10 16 cm -2 , maximum 1.35·10 16 cm -2 , maximum 1.2·10 16 cm -2 , maximum 1.0·10 16 cm -2, maximum 1.8·10 ı5 cm -2 , maximum 4.0·10 14 cm -2 , or at most 2.0·10 14 cm -2 ). For example, the first and / or second implantation dose may not exceed 1.35·10 16 cm -2 for an implantation of nitrogen atoms or at most 1.8·10 15 cm -2 for an implantation of phosphorus ions. For example, the first and / or second implantation dose may be a critical dose.

[0033] For example, after implanting the ions with the second implantation dose, a wafer surface with reduced near-surface crystal defects can be obtained again, e.g., through a further process. Subsequently, a third implantation step can be performed by implanting ions with a third implantation dose. Similarly, further implantation doses can be subsequently implanted. It may be possible to form the absorption layer in two, three, four, or five subsequent implantation steps. For example, the surface defects of the surface of the silicon carbide wafer can be reduced after one or more (e.g., after each) of the implantation steps.

[0034] For example, the ions can be implanted with the first implantation dose through a first surface of the silicon carbide wafer, and after implanting the ions with the first implantation dose, a process step can be performed to reduce the crystal defects of the first surface. Various methods or processes can be used to obtain the wafer surface with reduced near-surface crystal defects or increased crystal quality.

[0035] For example, as claimed, after implanting the ions with the first implantation dose, the silicon carbide wafer (e.g., at least the first surface of the silicon carbide wafer) may be annealed to obtain the wafer surface with reduced near-surface crystal defects. An annealing temperature for annealing the silicon carbide wafer may be at least 1600°C (or at least 1650°C, at least 1700°C, at least 1750°C, or at least 1800°C) and / or at most 1850°C (or at most 1800°C, at most 1750°C, or at most 1700°C). The first surface may, for example, be annealed between implanting ions with the first implantation dose and ions with the second implantation dose. An annealing time, e.g.,The time the wafer surface is exposed to the annealing temperature can be, for example, more than 1 minute (or more than 2 minutes, more than 3 minutes, or more than 5 minutes) and / or less than 7 minutes (or less than 5 minutes, or less than 4 minutes). For example, the annealing time can be 3 minutes. After annealing, the defect density may be lower than before annealing, e.g., below a critical defect density that allows the growth of a high-quality epitaxial layer.

[0036] For example, annealing the silicon carbide wafer to obtain a wafer surface with reduced near-surface crystal defects can be performed in an annealing chamber. For example, the silicon carbide wafer can be annealed by laser annealing. Laser annealing can, for example, enable shorter annealing times. For example, annealing the surface near the implantation damage layer can be performed by non-melting mode laser annealing.

[0037] According to one example, the ions with the first implantation dose can be implanted with a first implantation energy, and the ions with the second implantation dose can be implanted with a second implantation energy. The second implantation energy can differ from the first implantation energy by at least 5% (or at least 7%, at least 9%, at least 15%, or at least 20%) and / or by at most 40% (or at most 30%, at most 20%, or at most 10%) of the first implantation energy. Implanting the ions with different implantation energies can make it possible to form an absorption layer with a greater thickness. By varying the implantation energies in the different implantation steps, the damage generated (e.g., surface defects due to implantation) can be reduced more efficiently (e.g.,In the process step for obtaining the wafer surface with reduced near-surface crystal defects), for example.

[0038] Forming the absorption layer by implanting 110 ions with two or more implantation steps and with at least one intermediate step may allow ions to be implanted and the silicon carbide wafer to be annealed sequentially. For example, in each step, only a portion of the required dose (e.g., to obtain a predefined absorption coefficient of the absorption layer) may be implanted, followed by annealing (e.g., a furnace annealing procedure) to harden near-surface damage or defects, while, for example, the stable crystal defect centers may remain in the absorption layer (e.g., required to obtain the high absorption coefficient).

[0039] Alternatively or additionally, obtaining the wafer surface with reduced near-surface crystal defects or lower defect density as claimed may comprise forming a silicon carbide layer on a first side of the silicon carbide wafer (e.g., a first surface on a front side of the silicon carbide wafer) after implanting the ions with the first implantation dose from the first side (e.g., through the first surface). For example, prior to forming the silicon carbide layer, a defect density of the first surface of the silicon carbide wafer may be at a critical limit for forming a high-quality silicon carbide layer. After forming the silicon carbide layer, the surface of the silicon carbide layer provides the surface of the silicon carbide wafer. Since the silicon carbide layer may have a lower defect density than a layer (e.g.,With a second ion implantation dose (i.e., with a thickness of the silicon carbide layer) on the surface of the silicon carbide wafer without the silicon carbide layer, the surface or a layer on the surface of the silicon carbide wafer may have a lower or reduced defect density after forming the silicon carbide layer. Upon implantation of ions with the second implantation dose, new defects may appear on the surface with the reduced defect density due to the implantation; however, it may still be possible to form another silicon carbide layer (e.g., an epitaxial layer) on the surface, for example. In a process sequence that performs subsequent ion implantation and epitaxial growth, for example, a reduction in the surface damage caused by the silicon carbide layer formed on the surface may be achieved, e.g., still suitable for high-quality epitaxial growth.

[0040] When forming a silicon carbide layer on the first side (e.g., the first surface) prior to implanting the ions with the second implantation energy, it may be necessary to implant the ions of the second implantation dose with a higher implantation energy than the ions of the first implantation dose, e.g., in order to implant the ions in a same region of the silicon carbide wafer, e.g., the absorption layer. The implantation energies may be adjusted accordingly, e.g., to achieve the new target implantation depth, taking into account the formed silicon carbide layer. For example, the increase in the second implantation energy relative to the first implantation energy may depend on the thickness of the formed silicon carbide layer. Alternatively, the first and second implantation energies may be at least substantially equal to form an absorption layer with an increased thickness, for example.For example, the surface may remain intact and the absorption layer may extend over a larger vertical distance in the silicon carbide wafer.

[0041] For example, forming the silicon carbide layer may include epitaxially growing a silicon carbide layer on the surface of the first side or depositing the silicon carbide layer by chemical vapor deposition on the surface of the first side. Using chemical vapor deposition to form the silicon carbide layer may enable rapid formation of the silicon carbide layer at a low cost.

[0042] For example, the silicon carbide layer formed may have a thickness of at least 20 nm (or at least 50 nm, at least 100 nm, at least 200 nm, at least 300 nm, or at least 500 nm) and / or of at most 700 nm (or at most 500 nm, at most 300 nm, at most 200 nm, or at most 150 nm).

[0043] For example, if two or more (e.g., three) implantation processes with two or more intermediate processes for obtaining the wafer surface with reduced near-surface crystal defects are used for implanting 110 the ions to form the absorption layer, a first of the at least two intermediate processes may be annealing, and a second of the at least two intermediate processes may be layer growth. For example, both annealing and layer growth may be performed between a first and a subsequent second implantation process.

[0044] For example, processing the silicon carbide wafer may include forming a porous silicon carbide layer on a first side (e.g., the front side) of the silicon carbide wafer. The porous silicon carbide layer may be formed within the silicon carbide wafer or on a surface of the silicon carbide wafer, for example. Forming the porous silicon carbide layer may make it possible to increase the absorption coefficient of the absorption layer and / or provide the surface of the silicon carbide wafer with a defect density at or below a critical limit, potentially allowing growth of a high-quality epitaxial layer on the surface of the first side, e.g., after forming the porous silicon carbide layer.

[0045] The porous silicon carbide layer can be formed in the silicon carbide wafer, for example, by anodization, e.g., in an electrolyte containing fluorine. The electrolyte can comprise hydrofluoric acid (HF) and / or ethanol. The anodization electrochemically decomposes the silicon carbide crystal in the region of the porous silicon carbide layer to some extent. Instead of uniformly decomposing the silicon crystal, the electrochemical decomposition can locally remove silicon atoms from the silicon carbide crystal lattice, forming small holes or pores within the silicon carbide crystal. For example, the crystal structure of the silicon carbide wafer outside the porous silicon carbide layer may remain unaffected by the anodization.

[0046] The porous silicon carbide layer can be formed by anodization between the surface of the first side (e.g., the front surface) and a base region of the silicon carbide wafer (e.g., on the back side), which may not be affected by the anodization. The porous silicon carbide layer can be formed by anodic etching of at least a portion of the surface of the silicon carbide wafer, for example, by anodic etching in hydrofluoric acid (HF). The porous silicon carbide layer can be formed by electrochemical or photoelectrochemical etching of the semiconductor substrate.

[0047] The porosity of the porous silicon carbide layer can be measured as a ratio of the effective pore volume (e.g., volume of pores) in the porous silicon carbide layer to the total volume of the porous silicon carbide layer (comprising the silicon carbide wafer volume and the pore volume within the porous silicon carbide layer). For example, a higher porosity value may indicate a higher pore density or pore volume in the porous silicon carbide layer, while a lower porosity value may indicate a lower pore density or pore volume in the porous silicon carbide layer. For example, the porous silicon carbide layer may have a porosity between 5% and 95% (or between 10% and 80%, or between 25% and 60%), for example.For example, the silicon carbide layer may have a density (weight per volume) of about 90%, 80%, or 70% of the silicon carbide material of the silicon carbide wafer surrounding the porous silicon carbide layer.

[0048] For example, the ions may be implanted 110 through at least a portion (e.g., a vertical portion) of the porous silicon carbide layer. For example, the porous silicon carbide layer may be formed prior to implanting 110 ions to form the absorption layer. The absorption layer may be formed within the porous silicon carbide layer (e.g., the absorption layer may be formed entirely within the porous silicon carbide layer), and ions may be implanted through a first vertical portion of the porous silicon carbide layer. For example, at least a first vertical portion of the absorption layer may be formed below the porous silicon carbide layer. For example, the porous silicon carbide layer may be positioned vertically between the surface of the silicon carbide wafer through which the ions are implanted and the first vertical portion of the absorption layer.

[0049] Implanting 110 ions to form the absorption layer through the porous silicon carbide layer can increase the depth of implantation (e.g., increased distance between the surface of the silicon carbide wafer and the absorption layer), while potentially keeping the surface damage close to its intrinsic value, for example, for the applied implantation dose. Consequently, the distance between the absorption layer and, for example, an electrically active device layer of the silicon carbide wafer (e.g., formed after forming the absorption layer and before cleaving the silicon carbide wafer) can be increased, and, for example, fewer interactions may occur during cleaving (e.g., by irradiation with light, e.g., laser) with the active part of the device.

[0050] As mentioned, the absorption layer, or at least a vertical section of the absorption layer, can be formed within the porous silicon carbide layer. Implanting the absorption layer into a porous silicon carbide layer can increase the absorption capacity of this layer (e.g., can lead to a higher absorption coefficient), e.g., enabling a combination of mechanical and electrical / optical active light absorption centers. For example, cleavage (e.g., by light irradiation, e.g., laser) can be enabled with a lower implantation dose (e.g., a combined implantation dose to form the absorption layer), resulting in less surface damage and consequently a surface quality suitable for epitaxial growth.

[0051] For example, the porous silicon carbide layer may be formed after forming the absorption layer. The porous silicon carbide layer may extend vertically into at least a region of the silicon carbide wafer that includes the absorption layer. An implantation dose for forming the absorption layer may be a critical dose, e.g., at most 1.35 10 16 cm -2This can be the case if the porous silicon carbide layer is formed after the absorption layer, for example. The implantation dose used to form the absorption layer can lead to surface defects that still allow high-quality epitaxial growth on the surface, for example. By forming the porous silicon carbide layer after forming the absorption layer, the absorption coefficient of the absorption layer can be further increased, for example, without creating further implantation defects on the surface. For example, after forming the porous silicon carbide layer, the absorption coefficient of the absorption layer can be higher than before forming the porous silicon carbide layer.

[0052] Ion implantation into the silicon carbide wafer prior to a porosity process (e.g., forming the porous silicon carbide layer) can make it possible to adjust the porosity intensity (e.g., porosity) and / or the depth profile of the porous silicon carbide layer. This can increase the absorption coefficient (e.g., higher absorption of irradiated light) in the absorption layer and / or can lead to a better surface quality for epitaxial growth with a sufficiently high absorption coefficient in the absorption layer and / or can have a positive impact on the development of the porous layer (e.g., the porous silicon carbide layer) due to the thermal budget of further processing of the silicon carbide wafer (e.g., epitaxial growth, activation annealing, etc.).

[0053] For example, before growing an epitaxial layer on the porous silicon carbide layer, a surface layer (e.g., a thin surface layer) of the porous silicon carbide layer can be transformed or converted into a non-porous silicon carbide layer (e.g., a so-called skin layer or seed layer). Additionally, or as an alternative, the porosification can be performed such that a non-porous silicon carbide layer remains on the surface. The quality of an epitaxial layer grown on a non-porous silicon carbide layer can be higher than the quality of an epitaxial layer grown on a porous silicon carbide layer, for example.

[0054] For example, the porous silicon carbide layer can be formed with at least two layers, e.g., vertically adjacent to each other, with different porosities. The porosity of the upper layer (e.g., providing the surface of the silicon carbide wafer) can be selected in a way that allows a suitable skin layer to be formed on the surface, e.g., before growing an epitaxial layer on the surface of the silicon carbide wafer. For example, after forming the absorption layer, a surface layer of the porous silicon carbide layer can be transformed into a non-porous silicon carbide layer. For example, the surface layer that has been transformed into the non-porous silicon carbide layer can be the skin layer and can be used as a starting layer for growing an epitaxial layer, for example.

[0055] To transform the surface layer of the porous silicon carbide layer into a non-porous crystalline starter layer, the surface layer of the porous silicon carbide layer can be heated, e.g., in a reducing atmosphere comprising hydrogen. The heat treatment can lead to a rearrangement of the silicon carbide atoms in a thin layer along the exposed surface of the porous silicon carbide layer, wherein the atoms in the thin surface layer of the porous silicon carbide layer can be rearranged in a reflow process to form a continuous, non-porous crystalline starter layer, for example, having a high crystal quality. Alternatively or additionally, the non-porous crystalline starter layer can be formed by epitaxial growth on the porous silicon carbide layer or by laser annealing, which causes a rearrangement of the atoms on the surface of the porous silicon carbide layer.

[0056] The nonporous crystalline seed layer can be used as a base for growing an epitaxial layer. Since the nonporous crystalline seed layer can exhibit high crystal quality, the epitaxial layer with high crystal quality can grow on the nonporous crystalline seed layer. For example, the epitaxial layer grown on the nonporous crystalline seed layer can have a crystal defect density comparable to epitaxial layers grown directly on conventional nonporous single-crystal silicon carbide wafers. For example, the nonporous crystalline seed layer with the grown epitaxial layer can be used as a substrate to form semiconductor device structures, as described later.

[0057] For example, the porous silicon carbide layer may have a thickness of at least 0.3 µm (or of at least 0.5 µm, of at least 0.8 µm, or of at least 1.2 µm) and / or of at most 3 µm (or of at most 2 µm, or of at most 1.5 µm).

[0058] For example, the porous silicon carbide layer may limit penetration of critical defects from a substrate of the silicon carbide wafer (e.g., between a backside surface of the silicon carbide wafer and the porous silicon carbide layer) into a drift zone of a device of the silicon carbide wafer (e.g., formed after forming the absorption layer and before cleaving the silicon carbide wafer), so that the defect density and / or harmful bipolar degradation effects in the drift zone may at least be reduced.

[0059] By using at least one of the concepts proposed above or below, it may be possible to provide a method for increasing an implantation-induced absorption layer efficiency, e.g. for wafer cleaving applications, in particular with so-called cold splitting. For example, the proposed methods may make it possible to reduce surface layer damage, e.g. of a surface of a semiconductor wafer (e.g. of a SiC wafer), in order to enable good (e.g. proper) epitaxial growth, e.g. SiC epitaxial growth, e.g. before cleaving. Concepts are proposed to increase the absorption efficiency in several ways, e.g. simultaneously enabling epitaxial growth at the surface with a good quality of the epitaxial layer with an uncritical defect density. Concepts are proposed to limit crystal damage generation during the implantation 110 of ions, e.g.B. to form the absorption layer.

[0060] The proposed aspects relate to methods for improving implantation-induced absorption layer efficiency with reduced SiC surface layer damage. For example, it may be possible to reduce SiC surface damage to enable proper SiC epitaxial growth, e.g., prior to front-side processes and / or the cleavage process.

[0061] In addition, by increasing the implantation dose for forming the absorption layer, it may be possible to limit wafer bow and / or wafer wrap. For example, by implanting ions with a higher implantation dose, it may be possible to reduce wafer bow and / or wafer warpage. For example, when implanting ions into a semiconductor wafer with an initial center bow before ion implantation of between 3 µm and -14 µm, a final center bow after ion implantation may be between -180 µm and -450 µm, depending on the implantation dose used. In general, a higher implantation dose can lead to a more convex center bow. In particular, at an implantation dose of 0.9 10 16 cm -2 a central deflection after implantation of -427 µm; with an implantation dose of 2.25·10 16 cm -2the central deflection after implantation can be -268 µm; and / or at an implantation dose of 2.7·10 16 cm -2 The central warpage after implantation can be -205 µm (e.g., negative numbers indicate a convex warpage). For example, when implanting ions into a semiconductor wafer with an initial total warpage of between 20 µm and 35 µm before ion implantation, the final total warpage after ion implantation can be between 200 µm and 480 µm, depending on the implantation dose used. In particular, with an implantation dose of 0.9 10 16 cm -2 A total warpage after implantation will be 457 µm; with an implantation dose of 2.25·10 16 cm -2 the total warpage after implantation can be 293 µm; and / or at an implantation dose of 2.7·10 16 cm -2the central deflection after implantation can be 231 µm.

[0062] Since central warpage and / or overall warpage may be increased after implantation, wafer handling problems may arise during non-manual processing, and it may be difficult to achieve volume production with such a process. Therefore, it may be necessary to provide methods to reduce central warpage and / or overall warpage after implantation. By providing concepts to increase the implantation dose (e.g., while still enabling good surface quality for epitaxial growth), wafer warpage and / or overall warpage may decrease due to the higher implantation dose, and, for example, automated wafer handling may be enabled. For example, intermediate annealing steps (e.g., between two implantation steps with a first and a second implantation dose) can also reduce wafer warpage, e.g., of SiC wafers.

[0063] According to examples, processing the silicon carbide wafer may further comprise removing a surface layer of the silicon carbide wafer from a first side (e.g., the front side) of the silicon carbide wafer. A thickness of the surface layer may extend from a first surface (e.g., front side surface) of the silicon carbide wafer into the silicon carbide wafer. The surface layer may be in direct contact with and / or may comprise the first surface. The surface layer may have a thickness of less than 100 nm (or less than 95 nm, less than 90 nm, or less than 80 nm) and / or greater than 50 nm (or greater than 70 nm, or greater than 85 nm). The ions may be implanted 110 from the first side, and the surface layer may be removed after implanting the ions 110 and before cleaving 120 the silicon carbide wafer.

[0064] For example, the surface layer may be removed from the first side by etching the first side of the silicon carbide wafer. For example, after removing the surface layer, an epitaxial layer may be grown on the surface of the first side of the silicon carbide wafer, as described above or below.

[0065] For example, after removing the surface layer from the first side of the silicon carbide wafer, a maximum vacancy concentration (e.g., surface vacancy concentration) within a layer on the first side of the silicon carbide wafer may be at most 3·10 22 cm -3 (or at most 2·10 22 cm -3 , or at most 1·10 22 cm -3). The layer may have a thickness between 5 nm and 20 nm, e.g., 10 nm, and a thickness of the layer extends from the surface of the silicon carbide wafer into the silicon carbide wafer. The vacancy concentration of the layer may be an averaged vacancy concentration of the layer, for example. The layer may be a layer with a higher defect density compared to the removed surface layer. For example, the near-surface region of the silicon carbide wafer after removal of the surface layer has a relatively low near-surface defect density, e.g., vacancy concentration, of at most 3 10 22 cm -3The low near-surface defect density can enable the growth of a high-quality epitaxial layer on the surface of the silicon carbide wafer, for example. The defect concentration of the removed surface layer can be lower than the defect concentration of the layer (e.g., the 10 nm thick layer). However, in epitaxial growth processes, for example, a pre-etch may be required before epitaxial growth, and the surface layer may be removed (e.g., the surface layer may have a thickness of 90 nm). Therefore, the critical defect density can be considered to be that at approximately 100 nm depth of the silicon carbide wafer, including the surface layer, for example.

[0066] For example, the ions may be implanted 110 with an implantation dose that is higher than an amorphous dose required for amorphization of silicon carbide material of the absorption layer. For example, if the ions are implanted in subsequent implantation processes, e.g., with a first and a second implantation dose, the implantation dose may be higher than the amorphous dose in each of the subsequent implantation processes. For example, the implanted ions may disrupt a crystal structure within the silicon carbide material of the silicon carbide wafer and / or may lead to an amorphous region within the silicon carbide wafer. Here, the crystal structure of the silicon carbide wafer may correspond to one of the polymorphs of silicon carbide.

[0067] Furthermore, the silicon carbide wafer may be annealed after ion implantation 110, as claimed. This may result in partial or complete recrystallization of the amorphous region, which may result in a crystal structure that differs from the crystal structure of the silicon carbide material of the silicon carbide wafer outside the absorption layer. For example, the different crystal structures may result in different band gaps of the absorption layer and the silicon carbide material of the silicon carbide wafer outside the absorption layer, such that the wavelength-dependent absorption coefficients of the absorption layer and the silicon carbide material outside the absorption layer exhibit maxima at different wavelengths depending on the band gaps.In other words, the different crystal structures can lead to different absorption bands of the absorption layer and the silicon carbide material outside the absorption layer. For other semiconductor materials, e.g., silicon, it may not be possible to increase an absorption coefficient by providing a different crystal structure. Furthermore, annealing the silicon carbide wafer, e.g., after implanting 110 ions to form the absorption layer, can reduce surface defects on the surface of the silicon carbide wafer through which the ions are implanted.

[0068] For example, the absorption layer may have a 3C crystal structure. For example, the silicon carbide material of the absorption layer may have the 3C crystal structure. The silicon carbide material of the silicon carbide wafer surrounding the absorption layer may have a 4H, 6H, or 15R crystal structure.

[0069] Additionally or alternatively, the ions may be implanted 110 into the silicon carbide wafer with an implantation dose that is higher than a solubility of the silicon carbide material of the silicon carbide wafer. For example, the implantation dose used may cause precipitation (or segregation) within the absorption layer. To create segregation or precipitation, the silicon carbide wafer may be annealed after implanting 110 the ions. For example, due to annealing of the silicon carbide wafer, the implanted ions may react with each other and with ions of the silicon carbide material of the silicon carbide wafer to form segregations. The segregation of the implanted ions may cause the absorption layer to have a higher absorption coefficient compared to the silicon carbide material outside the absorption layer, for example.

[0070] For example, the implanted ions may be at least one of nitrogen (N) ions, vanadium (V) ions, boron (B) ions, argon (Ar) ions, carbon (C) ions, nickel (Ni) ions, silicon (Si) ions, titanium (Ti) ions, tantalum (Ta) ions, molybdenum ions, tungsten ions, and aluminum (Al) ions. The implanted ions may integrate into the crystal lattice of the silicon carbide material of the silicon carbide wafer within the absorption layer to form an absorption barrier for light of the target wavelength. For example, nitrogen (N) ions, vanadium (V) ions, boron (B) ions, argon (Ar) ions, carbon (C) ions, nickel (Ni) ions, silicon (Si) ions and / or titanium (Ti) ions can form a strong absorption band after their integration into the SiC crystal lattice.For example, aluminum ions, tantalum ions, boron ions, titanium ions, and / or nickel ions may be implanted 110 into the silicon carbide wafer, and the silicon carbide wafer may be annealed after implantation 110 of the ions. For example, ions (e.g., phosphorus ions) may be implanted with an implantation dose of at least 2 10 . 15 cm -2 (or at least 1·10 16 cm -2 or at least 5·10 16 cm -2 ) can be implanted. For example, nitrogen ions can be used, which can cause minimal damage to the implantation surface compared to other ions. If the implanted ions are donors or acceptors, the resulting locally increased charge carrier density can support the absorption process, especially when using high implantation doses.

[0071] For example, a thickness of the absorption layer may be at least 30 nm (or at least 50 nm, at least 100 nm, at least 200 nm, or at least 300 nm) and / or at most 1500 nm (or at most 750 nm, at most 500 nm, or at most 400 nm). In a typical embodiment, the thickness of the absorption layer is at least 100 nm and at most 500 nm. For example, a thinner absorption layer may result in less variation in the thickness of the silicon carbide device wafer. For example, a surface roughness of a surface of the silicon carbide device wafer after cleaving 120 the silicon carbide wafer may be less than 1 µm (or less than 500 nm, or less than 200 nm). In another example, the surface roughness of the surface of the silicon carbide device wafer may be less than 20 µm. In general, the surface roughness can be smaller than the thickness of the absorption layer.The surface with the surface roughness may be opposite a front side of the silicon carbide device wafer and may, for example, comprise a remaining portion of the absorption layer. The surface roughness may exist directly after cleaving 120 of the silicon carbide wafer (e.g., without subsequent polishing). The surface roughness may be reduced by further processing, for example, by surface polishing.

[0072] For example, the absorption layer may be formed within the silicon carbide wafer at a distance, e.g., a vertical distance, from a surface of the silicon carbide wafer of at least 300 nm (or at least 500 nm, at least 1000 nm, or at least 2000 nm) and / or at most 5 µm (or at most 4 µm, or at most 3 µm). The distance may be achieved by controlling the implantation energy of the ion implantation 110. The thickness of the silicon carbide device wafer may be controlled based on the selected distance between the surface of the silicon carbide wafer and the absorption layer.

[0073] For example, the target wavelength may be at least 100 nm (or at least 200 nm, at least 400 nm, at least 500 nm, at least 600 nm, at least 700 nm, at least 750 nm, at least 1.0 µm, or at least 1.25 µm, or at least 1.5 µm) and / or at most 3.5 µm (or at most 2 µm, at most 1.6 µm, at most 1.1 µm, at most 750 nm, at most 650 nm, or at most 550 nm). In a typical embodiment, the target wavelength may be at least 300 nm and at most 600 nm. For example, the target wavelength can be between 370 nm and 430 nm (or between 390 nm and 410 nm, e.g., 395 nm, 400 nm, or 405 nm) or between 620 nm and 720 nm). For example, the target wavelength is higher than 500 nm, e.g., between 500 nm and 800 nm. It is possible that the target wavelength corresponds to the band gap of the absorption layer material, for example, within ± 1 GHz.In a typical example, the target wavelength should be low enough to ensure energy deposition into the absorption layer, but high enough to allow high transmission in the material outside the absorption layer. For example, if the absorption layer has a 3C crystal structure, the band gap can be 3.2 eV, which corresponds to a target wavelength of approximately at least 350 nm to at most 400 nm, especially 388 nm.

[0074] The light of the target wavelength used for cleaving 120 may be laser light. An energy density of the light of the target wavelength may be at least 0.5 J / cm 2 , e.g. 1 J / cm 2 , and a maximum of 100 J / cm 2 , e.g. maximum 10 J / cm 2Such an energy density can be high enough to allow chemical decomposition of the absorption layer. For example, the light of the target wavelength can be pulsed laser light and / or unfocused laser light. Using unfocused laser light can make it possible to reduce the complexity of a light source or an optical system for irradiating and cleaving 120 the silicon carbide wafer, e.g., compared to other cleaving concepts using focused laser light. The pulsed laser light can have a pulse length of at most 100 ns, for example, at most 10 ns.

[0075] For example, at least 5% (or at least 7%, at least 10%, or at least 15%) of the light of the target wavelength that penetrates the silicon carbide material of the silicon carbide wafer outside the absorption layer and / or impinges on the absorption layer may be absorbed by the absorption layer. A further percentage of the light of the target wavelength may be absorbed by the material outside the absorption layer. In a typical example, at least 20% of the light of the target wavelength that impinges on the absorption layer is absorbed. The high absorption within the absorption layer (possibly caused by the high absorption coefficient in combination with the thickness of the absorption layer) may make it possible to reduce the influence of the light of the target wavelength on regions of the silicon carbide wafer outside the absorption layer, e.g., behind the absorption layer.

[0076] For example, the light of the target wavelength may be radiated from a first side (e.g., back side) of the silicon carbide wafer and may be almost completely absorbed within the absorption layer and the material of the silicon carbide wafer between the absorption layer and the first side, such that the light of the target wavelength may not alter regions of the silicon carbide wafer positioned between the absorption layer and a surface of a second side (e.g., front side) of the silicon carbide wafer and / or structures (e.g., metallization structures) positioned on the second side of the silicon carbide wafer.

[0077] According to at least one example, the method 100 may further comprise at least one of the following additional method steps (i)-(iii): (i) heating the silicon carbide wafer, (ii) applying mechanical stress and / or force to the silicon carbide wafer, and (iii) ultrasonicating the silicon carbide wafer. The at least one additional method step (i)-(iii) may be applied during and / or after irradiating the silicon carbide wafer with the light of the target wavelength. The at least one additional method step (i)-(iii) may be applied in particular for cleaving 120 the silicon carbide wafer. For example, heating or annealing the silicon carbide wafer (optional step (i)) may facilitate cleaving 120 of the silicon carbide wafer, e.g., by introducing thermomechanical stress to the absorption layer to assist cleaving 120 of the silicon carbide wafer.Mechanical force and / or stress (optional step (ii)) can be applied, for example, by forming an additional layer on the silicon carbide wafer, the additional layer of which can be mechanically pre-stressed (e.g., twisted and / or tensioned) with respect to the silicon carbide wafer. Additionally or as an alternative, the application of mechanical force and / or stress in optional step (ii) can comprise applying compressed gas or compressed air to a side surface of the wafer. The ultrasonic treatment (optional step (iii)) can comprise applying ultrasonic radiation to the silicon carbide wafer. The ultrasonic treatment can also result in heating of the silicon carbide wafer, analogously to optional step (i).

[0078] For example, the absorption layer can be irradiated through a backside of the silicon carbide wafer. For example, the light of the target wavelength can be irradiated onto the backside of the silicon carbide wafer and can be transmitted to the absorption layer through a region of the silicon carbide wafer between the backside and the absorption layer. Radiating the light of the target wavelength from the backside can prevent the irradiated light from impinging on structures on the frontside of the silicon carbide wafer. Thus, it may be possible to form structures, e.g., metallization structures of a silicon carbide semiconductor device, on the frontside of the silicon carbide wafer before the silicon carbide wafer is cleaved 120.Cleaving 120 the silicon carbide wafer after forming a silicon carbide semiconductor device may facilitate forming a thin silicon carbide semiconductor device because structures of the silicon carbide semiconductor device may already be formed on a silicon carbide wafer before the wafer is cleaved to obtain the thinner device wafer.

[0079] For example, a support structure (e.g., carrier wafer) may be provided on the front side of the silicon carbide wafer prior to dividing the silicon carbide wafer. Placing or attaching the support structure on the front side may facilitate handling of the silicon carbide device wafer and / or provide mechanical support to the silicon carbide device wafer, for example.

[0080] According to one example, the method 100 may further comprise forming a further absorption layer within the remaining silicon carbide wafer. The further absorption layer may be formed by implanting ions into the remaining silicon carbide wafer, e.g., according to forming the absorption layer within the silicon carbide wafer as described herein. The method 100 may further comprise cleaving the remaining silicon carbide wafer along the further absorption layer, e.g., analogous to cleaving 120 of the silicon carbide wafer as described herein. By further cleaving, further silicon carbide device wafers may be obtained. In other words, reuse of the remaining silicon carbide wafer may be enabled.For example, it may be possible to form a plurality of silicon carbide device wafers while simultaneously preventing a high consumption of silicon carbide material for cleaving the respective silicon carbide device wafers.

[0081] For example, a net doping concentration of the silicon carbide wafer can be at most 2·10 19 cm -3 (or at most 5·10 18 cm -3 , or at most 1·10 18 cm -3 ) and / or at least 1·10 17 cm -3 (or at least 5·10 17 cm -3 ). Here, the doping atoms used can be nitrogen atoms and / or phosphorus atoms. The net doping concentration can be an average net doping concentration of silicon carbide material of the silicon carbide wafer outside the absorption layer, for example. Alternatively, a net doping concentration of the silicon carbide wafer can be at most 1 10 15 cm-3 (so-called nominally undoped silicon carbide).

[0082] For example, the method 100 may be used to form silicon carbide semiconductor devices. The method 100 may further include growing an epitaxial layer on a front side of the silicon carbide wafer. The epitaxial layer may be grown or deposited prior to cleaving the silicon carbide wafer. For example, if a porous silicon carbide layer is formed on the front surface of the silicon carbide wafer, a non-porous skin layer, e.g., a non-porous crystalline seed layer, may be formed on the surface of the porous silicon carbide layer prior to growing the epitaxial layer on the front side, and the epitaxial layer may be grown on the non-porous crystalline seed layer. For example, the epitaxial layer may be homoepitaxial with respect to a semiconductor material of the silicon carbide wafer on the front side of the silicon carbide wafer.The epitaxial layer may be a silicon carbide layer. For example, the epitaxial layer may have a thickness of at least 3 µm (or at least 5 µm, at least 10 µm, or at least 20 µm) and at most 300 µm (or at most 200 µm, or at most 100 µm, or at most 50 µm, or at most 30 µm). The epitaxial layer may define at least one of a drain region, a buffer region, a backside emitter, and a drift region of a silicon carbide semiconductor device.

[0083] For example, prior to cleaving the silicon carbide wafer, method 100 may further comprise forming a metallization structure on a front side of the silicon carbide wafer. The metallization structure may be formed on the epitaxial layer, for example. The metallization structure (e.g., source metallization or gate wiring structure) may be a metallization structure of a silicon carbide semiconductor device to be formed, for example.

[0084] For example, one or more silicon carbide semiconductor devices may be formed on the silicon carbide wafer. For example, each silicon carbide semiconductor device may include or be a transistor. At least one of a gate trench and a gate electrode of the transistor may be formed before cleaving 120, for example. It may be possible to cleave 120 the silicon carbide wafer after all structures of the silicon carbide semiconductor device have been formed on the front side of the silicon carbide wafer. For example, the silicon carbide device wafer may be singulated (e.g., by sawing) to obtain a plurality of silicon carbide devices.

[0085] The transistor may be a field-effect transistor (e.g., a metal oxide semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT)) or a thyristor. The gate of the transistor may be positioned in a gate trench extending into a silicon carbide semiconductor substrate of the silicon carbide semiconductor device or may be positioned on a lateral surface of the silicon carbide semiconductor substrate. The transistor may include one or more transistor cells. For example, the silicon carbide semiconductor substrate may include one or more source regions, one or more body regions, and a drift region of the transistor. The one or more source regions and the drift region may each be of a first conductivity type (e.g., n-doped).The one or more body regions may be of a second conductivity type (e.g. p-doped).

[0086] The transistor may be a vertical transistor structure that conducts current between a front surface of the silicon carbide semiconductor substrate and a back surface of the silicon carbide semiconductor substrate. For example, the transistor of the silicon carbide semiconductor device may include a plurality of source doping regions connected to a source wiring structure, a plurality of gate electrodes or a gate electrode grid connected to a gate wiring structure, and a backside drain metallization or a backside collector metallization.

[0087] For example, the silicon carbide wafer may be one of a silicon carbide base substrate, a silicon carbide base substrate with a silicon carbide epitaxial layer grown on the silicon carbide base substrate, or a silicon carbide epitaxial layer. The silicon carbide wafer may be a monocrystalline silicon carbide wafer or may have at least one monocrystalline silicon carbide layer.

[0088] The front side of the silicon carbide wafer may be the side used to implement more sophisticated and complex structures (e.g., transistor gates) than those on the back side of the silicon carbide wafer. Process parameters (e.g., temperature) and handling may be restricted for forming structures on the back side to avoid altering the structures formed on the front side.

[0089] For example, the vertical dimension or vertical distance and thickness of layers may be measured orthogonal to the front surface of the semiconductor substrate, and a lateral direction and lateral dimensions may be measured parallel to the front surface of the semiconductor substrate.

[0090] A silicon carbide semiconductor device to be formed on the silicon carbide wafer may be a power semiconductor device. The power semiconductor device or an electrical structure (e.g., a transistor of the silicon carbide device or a diode) of the power semiconductor device may, for example, have a breakdown voltage or reverse voltage of more than 100 V (e.g., a breakdown voltage of 200 V, 300 V, 400 V, or 500 V), or more than 500 V (e.g., a breakdown voltage of 600 V, 700 V, 800 V, or 1000 V), or more than 1000 V (e.g., a breakdown voltage of 1200 V, 1500 V, 1700 V, 2000 V, 3300 V, or 6500 V).

[0091] Examples are described above and below in connection with a silicon carbide wafer. Alternatively, in a manner not claimed, a wide-bandgap semiconductor wafer may be processed, e.g., comprising a wide-bandgap semiconductor material other than silicon carbide. The wide-bandgap semiconductor wafer may have a bandgap that is larger than the bandgap of silicon (1.1 eV). For example, the wide-bandgap semiconductor wafer may be a silicon carbide (SiC) wafer, a gallium arsenide (GaAs) wafer, or a gallium nitride (GaN) wafer.

[0092] More details and aspects are mentioned in connection with the embodiments described above or below. Processing the wide-bandgap semiconductor wafer may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0093] Fig. 2 shows a flowchart of a method 100a for processing a silicon carbide wafer, e.g., comprising implanting ions through at least a portion of a porous layer of the silicon carbide wafer. The method 100a may comprise implanting 110a ions into the silicon carbide wafer through at least a portion of a porous silicon carbide layer of the silicon carbide wafer at a front side of the silicon carbide wafer to form an absorption layer in the silicon carbide wafer. The method 100a may further comprise cleaving 120a the silicon carbide wafer along the absorption layer, at least by irradiating the silicon carbide wafer with light of the target wavelength, to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.

[0094] For example, the porous silicon carbide layer of the silicon carbide wafer may be formed according to a method described above or below, prior to implanting 11a of the ions. Implanting ions through the porous silicon carbide layer may enable formation of the absorption layer at an increased distance from the surface (e.g., a front surface) of the silicon carbide wafer. For example, fewer defects may occur on the surface of the silicon carbide wafer when the ions are implanted through the porous silicon carbide layer. For example, forming at least a portion of the absorption layer within the porous silicon carbide layer may increase the absorption coefficient of the absorption layer.

[0095] More details and aspects are mentioned in connection with the embodiments described above or below. Fig. 2 may comprise one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more of the above or below (e.g. Fig. 1 and 3-7h) described embodiments.

[0096] Fig. 3 shows a schematic cross-section of a silicon carbide semiconductor device 200a, which may include a porous silicon carbide layer 230a. The silicon carbide semiconductor device 200a may further include a silicon carbide semiconductor substrate 210a, e.g., having a 4H crystal structure, and a metallization structure 220a positioned on a front side of the silicon carbide semiconductor substrate 210a. The porous silicon carbide layer 230a may be positioned between the front side and a backside surface 245a of the silicon carbide semiconductor substrate 210a.

[0097] The silicon carbide semiconductor device 200a may be formed according to a method described above or below. For example, providing the porous silicon carbide layer 230a may enable improved manufacturing of the silicon carbide semiconductor device 200a.

[0098] For example, the silicon carbide semiconductor device 200a may include a backside layer 240a positioned at a backside of the silicon carbide semiconductor device 200a and providing the backside surface 245a. The backside layer may, for example, be a non-porous layer. Alternatively, the porous silicon carbide layer may extend to the backside surface 245a of the silicon carbide semiconductor substrate. In other words, it is possible for the backside layer 240a to be a porous layer.

[0099] For example, the backside silicon carbide layer 240a of the silicon carbide semiconductor substrate 200a may have a thickness of at least 50 nm and / or at least partially have a 3C crystal structure. For example, the 3C crystal structure of the backside silicon carbide layer 240a may be caused by cleaving the silicon carbide semiconductor device 200a from a silicon carbide wafer.

[0100] More details and aspects are mentioned in connection with the embodiments described above or below. Fig. 3 may have one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more of the above or below (e.g. Fig. 1-2 and 4-7h) described embodiments.

[0101] Fig. 4 shows a schematic cross-section of a silicon carbide semiconductor device 200. The silicon carbide semiconductor device 200 may include a silicon carbide semiconductor substrate 210, e.g., having a 4H crystal structure. The silicon carbide semiconductor device 200 may further include a metallization structure 220 arranged on a front side of the silicon carbide semiconductor substrate 210.

[0102] For example, the silicon carbide semiconductor device 200 may include a backside silicon carbide layer 230 positioned on a backside surface of the silicon carbide semiconductor substrate 210. For example, the backside layer may have a thickness of at least 30 nm (or at least 50 nm, at least 100 nm, or at least 150 nm) and / or of at most 300 nm (or of at most 200 nm, or of at most 150 nm). The backside silicon carbide layer 230 may have a 3K crystal structure. For example, a thickness of the silicon carbide semiconductor substrate 220 may be greater than the thickness of the backside silicon carbide layer 230.

[0103] For example, the silicon carbide semiconductor device 200 may have been formed using the method 100. A thickness of the silicon carbide semiconductor device 200 may be at most 300 µm (or at most 200 µm, or at most 100 µm, or at most 50 µm, or at most 20 µm), for example. The backside silicon carbide layer 230 may be a remaining part of the absorption layer, e.g., remaining on the backside of the remaining silicon carbide wafer after cleaving the silicon carbide wafer. The thin backside silicon carbide layer 230, which has the 3C crystal structure, may not have a significant influence on a parameter of the silicon carbide semiconductor device 200, e.g., compared to an influence of the silicon carbide semiconductor substrate 220, which has the 4H crystal structure. The contact resistance to a backside metallization can be reduced by this layer, e.g.,due to the smaller band gap and the higher defect / doping level.

[0104] More details and aspects are mentioned in connection with the embodiments described above or below. Fig. 4 may have one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more of the embodiments described above or below (e.g. Fig. 1-3 and 5-7h) described embodiments.

[0105] Fig. Figure 5 shows a schematic diagram 500 illustrating a first and a second vacancy concentration 510, 520 as a function of the depth of a silicon carbide wafer (e.g., the vertical distance from the surface of the silicon carbide wafer). The vacancies or defects may be caused by an implantation of ions to form an absorption layer (e.g., in a region of the silicon carbide wafer having a maximum vacancy concentration).

[0106] A critical vacancy concentration 505 indicates a boundary of defects or vacancies in a layer that allows high-quality epitaxial growth on the layer. For example, nitrogen ions can be implanted with a first implantation dose (e.g., critical dose) that results in the first vacancy concentration 510, and with a higher second implantation dose that results in the second vacancy concentration 520. For example, at the surface of the silicon carbide wafer (depth 0 nm), both vacancy concentrations 510 and 520 are lower than the critical vacancy concentration 505.

[0107] However, prior to epitaxial growth, a surface layer of a thickness x, e.g., 90 nm, may be removed, resulting in an increased vacancy concentration at the surface (e.g., new surface) of the silicon carbide wafer, i.e., the vacancy concentration indicated at depth x in diagram 500. As can be seen, the second vacancy concentration 520 is above the critical limit, potentially leading to poor-quality epitaxial growth. However, the first vacancy concentration 510, corresponding to the first implantation dose, is at the critical limit and thus enables growth of a high-quality epitaxial layer, for example. The first vacancy concentration 510 can be increased by implanting nitrogen ions with a combined implantation dose (e.g., in three subsequent implantation steps) of 1.35 10 16 cm -2 can be achieved, for example.

[0108] By using concepts proposed above and below, it may be possible to reduce the vacancy concentration 520 at the surface region, e.g., from a depth of 0 nm to at least the depth x (e.g., 90 nm), upon implanting the ions with the second implantation dose. For example, during implanting the ions with the second implantation dose, the silicon carbide wafer may be heated and / or the ions may be used in subsequent steps (in a combination resulting in the second implantation dose), whereby the surface defect density may be reduced between subsequent steps. Consequently, even upon implanting the ions with the second implantation dose (e.g., higher than the critical dose), a high-quality epitaxial layer may be grown on the surface of the silicon carbide wafer after removing the surface layer.

[0109] For example, to obtain the first and second vacancy concentrations 510, 520, a silicon carbide wafer is implanted with three implantation steps with energies of, for example, 1200 keV (1.9226·10 -13 J), 1000 keV (1.6022 10 -13 J) and 800keV (1.2817·10 -13 J) with nitrogen ions, for example, to allow for a broader damage peak. Proper epitaxial quality can be achieved up to an implantation dose of 1.35 10 16 cm -2 can be achieved, while surface irregularities (e.g. leading to poor epitaxial growth) above an implantation dose of 1.35·10 16 cm -2 can start, e.g. they can start at a dose of 1.80·10 16 cm -2 From experiments and simulations of phosphorus (not shown) and nitrogen-implanted wafers, it can be deduced that a surface vacancy concentration of, for example, 3·10 22 cm -2may be a limit for proper epitaxial growth (e.g. independent of implanted species).

[0110] For example, when phosphorus atoms are implanted to form the absorption layer, a maximum implantation dose without serious effects on the epitaxial quality (e.g., a quality of an epitaxial layer grown on the surface) can be 1.8 10 15 cm -2 and when nitrogen atoms are implanted, the maximum implantation dose can be 13.5 10 15 cm -2For example, a stronger influence on absorption (e.g., a higher absorption coefficient) may be observed after nitrogen implantation (e.g., due to a higher implantation dose), while maintaining good surface morphology. For example, absorption may only be further increased in spectral regions of already pronounced absorption; for example, new absorption fringes (e.g., wavelength ranges with high absorption coefficients) may not be created.

[0111] More details and aspects are mentioned in connection with the embodiments described above or below. Fig. 5 may include one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more of the above or below (e.g. Fig. 1-4 and 6-7h) described embodiments.

[0112] Fig. Figure 6 shows a schematic diagram 600 illustrating the reflectance and transmittance of the silicon carbide wafer as a function of a target wavelength. Light absorption in the silicon carbide wafer is high at low values ​​of reflectance and transmittance.

[0113] The diagram 600 shows two exemplary sketches of a transmission of light through a silicon carbide wafer, wherein a first transmission line 610 shows the transmission of light through an undoped silicon carbide wafer and a second transmission line 620 shows the transmission of light through a doped silicon carbide wafer, e.g., having an absorption layer doped with phosphorus P. Alternatively, the silicon carbide wafer may be doped with nitrogen N, for example, to form the absorption layer. As shown in Fig. As can be seen in Figure 6, at a wavelength of, for example, about 400 nm, a first difference 630a between the values ​​of the transmission lines 610 and 620 is high, so that at this wavelength, light radiated to the silicon carbide wafer with an absorption layer transmits through the (e.g., undoped) silicon carbide material of the silicon carbide wafer outside the absorption layer and is absorbed to a large extent within the absorption layer. Therefore, a wavelength of about 400 nm is a suitable target wavelength for cleaving the silicon carbide wafer, for example. Furthermore, a second difference 630b between the first and second transmission lines 610, 620 begins to increase at wavelengths of about 500 nm. Therefore, alternatively or additionally, a target wavelength of at least 500 nm may be used for cleaving the silicon carbide wafer.

[0114] For example, at wavelengths of 300 nm and higher, the absorption of undoped silicon carbide may be lower than the absorption of doped silicon carbide (not in Fig. 6). Consequently, at these wavelengths, a higher amount of light can be absorbed within the absorption layer, so that splitting of the absorption layer may be possible.

[0115] For example, for both P- and N-type implantations, absorption measurements of a silicon carbide wafer with an absorption layer show an increase in absorption around 400 nm (and above 500 nm). The absorption effect is greater, for example, for N-type implantation, with an increase of approximately twofold due to a 300 nm layer (e.g., thickness of the absorption layer) in a 350 µm-thick wafer (e.g., silicon carbide wafer). The local absorption in the implantation layer (e.g., absorption layer) can be about 1000 times greater than in the substrate, e.g., silicon carbide material outside the absorption layer.

[0116] More details and aspects are mentioned in connection with the embodiments described above or below. Fig. 6 may include one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more aspects described above or below (e.g. Fig. 1-5 and 7a-7h) described embodiments.

[0117] Fig. 7A-7h show an example of a method for cleaving a semiconductor wafer along an implanted layer by laser illumination. A silicon carbide (SiC) wafer 300 may be provided. The silicon carbide wafer 300 may be a 4H-SiC wafer with a surface prepared for epitaxy. Ions may be implanted into the silicon carbide wafer 300 with a very high dose to create subsurface amorphization / supersaturation, e.g., in a subsurface region 312. The implantation may be performed with a high dose to a depth of, e.g., 0.5-5 µm with one of several of the following characteristics. The dose in the region of the depth peak (e.g., end of region) may be greater than an amorphous dose. For example, during subsequent tempering / annealing processes, poly-recrystallization of the amorphous SiC may occur, which may, for example, partially form 3C SiC (e.g., 3C SiC may have a smaller band gap (e.g., 2.4eV), e.g.compared to 4H SiC (e.g., 3.2 eV). Alternatively or additionally, ions can be implanted with an implantation dose that is greater than their solubility in the SiC. e.g., during subsequent annealing processes, segregations of the implanted ions can form in the SiC (e.g., Al→aluminum carbide (AlC), Ta→TaC, B→BC, Ti→TiC, Ni→Ni2Si). Alternatively or additionally, the implanted ions can form a strong absorption band after their integration into the SiC crystal lattice (e.g., N, V, B, Ar, C, Ni, Si, Ti).

[0118] For example, after implantation, an epi (epi: epitaxial) process can be performed, as in Fig. 7b. An epitaxial layer 320 may be grown. The epitaxial layer 320 may include at least one of a drain layer, a buffer layer, a backside emitter, and a drift layer of a silicon carbide semiconductor device, which may be, for example, a transistor or a diode. In particular, the epitaxial layer 320 may be grown before the silicon carbide wafer is cleaved. A thickness of the epitaxial layer may be at least as large as the larger of the two thickness values ​​for a) a desired electrical blocking capability; b) the required mechanical stability for a cleavage layer. During epitaxy, the buried implanted region may at least partially anneal and may form an absorption layer 310 (e.g., the absorption layer 310 may be at a wavelength at which the SiC wafer 300 is substantially transparent or substantially opaque). E.g.Epi-growth can be performed together with recrystallization of the amorphous region / precipitation / high-dose doping.

[0119] Alternatively or additionally, the preceding or following (e.g. in the description referring to Fig. 1 or Fig. 2) may be used to form the absorption layer 310. For example, the absorption layer may be formed by implanting ions while the SiC wafer 300 has a temperature of at least 300°C. For example, the ions may be implanted in at least two implantation processes with at least a first and a second implantation dose. For example, the SiC wafer 300 may be annealed and / or a thin epitaxial layer may be grown on a surface of the SiC wafer 300 through which the ions are implanted, between implanting the first and second implantation doses. For example, a porous layer may be formed and / or to form the absorption layer 310, the ions may pass through at least a portion of a porous layer of the SiC wafer 300 (the porous layer is in Fig. 7a to 7h not shown).

[0120] Afterwards, as in Fig. As shown in Figure 7c, a process sequence required for a respective SiC device may be performed on the front side of the SiC wafer (e.g., implantation of doping regions 330, 332, formation of trench structures, metallizations 334, etc.). For example, implant wells, metal layers, and / or trenches may be formed.

[0121] Optionally, a front-side carrier 340 can be attached to the front side of the silicon carbide wafer 300. Laser illumination from the back side can be performed (shown in Fig. 7d, wherein the laser light is schematically illustrated by light beams 350, 352), e.g., for SiC cleaving within the absorption layer, e.g., after completion of the device front side. The wafer may be incident on the back side / irradiated from the back side, e.g., using a laser, wherein the wafer may be largely transparent to the wavelength of the laser light used, while the absorption layer may, however, not be transparent to the wavelength of the laser light used. Approximately 10% and / or at least 10% or at least 30% or at least 50% or at least 70% or at least 90% of the laser energy may be absorbed in the absorption layer, and consequently, no damage to the metal structures on the wafer front side may occur.

[0122] Due to the laser power released in the absorption layer, decomposition of the SiC in this area may result, which may lead to lift-off, as in Fig. 7e. Consequently, two sub-wafers may be obtained: a) a system wafer or silicon carbide device wafer 360, which may comprise the drift zone, an optional buffer zone, a drain zone (in the case of a diode or an IGBT also emitter zone) and / or the front-side device structures, for example; b) a residual wafer or a remaining silicon carbide wafer 362 suitable for a regeneration process (e.g., growth of an epi layer with a thickness approximately corresponding to the cleavage thickness, for example) may be obtained to be provided again as a substrate for another process cycle, as described above, for example. The system wafer 360 may be lifted off from the regeneration wafer 362. Optionally, the separation process of the system wafer from the residual wafer may also be assisted by thermomechanical stress during and / or after the laser irradiation, for example.

[0123] The system wafer 360 may be subjected to backside contact metallization and subsequent chip singulation (shown in Fig. 7f-h). For example, an ohmic backside contact 370 may be formed. Bonding to a glass frame and / or screen printing may be performed, for example. For example, a backside power metal 372 may be sintered. It is possible to perform backside planarization, removal of the frontside glass carrier 340, testing, mounting the silicon carbide device wafer 360 on a saw band 374, and / or chip separation, for example.

[0124] More details and aspects are mentioned in connection with the embodiments described above or below. Fig. The embodiments shown in Figures 7A to 7h may comprise one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more aspects described above or below (e.g. Fig. 1-6) described embodiments are mentioned.

[0125] Examples relate to cleaving silicon carbide (SiC) wafers with an epitaxial layer by laser removal and to forming an absorption layer for cleaving the SiC wafer. For example, it is proposed, e.g., by means of ion implantation prior to epitaxial growth of a drift zone / buffer zone / drain zone, to create a layer just below the surface of the SiC wafer, which layer consists essentially of SiC and has an absorption coefficient that is at least an order of magnitude higher in a certain wavelength range than the SiC wafer itself. Thus, focusing the laser may no longer be necessary for the cleaving process, and the thickness of the layer that is cleaved off can be the sum of the implantation depth and epitaxial thickness.Components suitable for applying the process can be SiC-based power MOSFETs, diodes, J-FETs (J-FET: junction-field effect transistor), IGBTs, etc.

[0126] For example, for thin wafers, the use of a carrier wafer (attached to the front side, e.g., system side) can be advantageous. The thickness of the system wafer can be kept minimal (e.g., < 100 µm, < 50 µm, or even < 30 µm) because the mechanical force required for cleaving and backside metallization can be ensured by the carrier wafer (e.g., a glass carrier).

[0127] Furthermore, prior to cleaving, deep trenches can be etched at the component boundaries / edges (e.g., in saw frames) that can reach the absorption layer (if necessary, the absorption layer can be used as an etch stop and / or marking layer). After cleaving, the components can already be available as individual chips on the carrier. The gaps between the chips can be temporarily filled with an easily separable medium, such as epoxy or spin-on silicon. Before removing the carrier wafer, the system wafer can be bonded to a permanently conductive carrier: e.g., to a metal carrier (e.g., molybdenum (Mo), copper (Cu), etc.), soldered, diffusion soldered, or friction welded. The system wafer can thus exhibit mechanical stability even with a very low semiconductor thickness. The conductive carrier can also be bonded along the component boundaries (e.g.,by laser ablation) and can remain part of the component in its complete state.

[0128] Bonding / adhesion of the system wafer to a sufficiently stable glass frame is also possible. It can be advantageous if glass bridges stabilize the frame along the saw frame areas (e.g., the saw frame areas for dicing). In this case, backside contact reinforcement may be possible, for example, by screen printing and / or gravure printing, for example, comprising a doctor blade in which the areas between the glass bridges are filled (Cu, Ag, paste, subsequent drying and sintering steps, for example). A planarization step may be included after sintering of the metallization areas and before dicing.

[0129] By using at least one of the proposed concepts, good control of the thickness of the cleaving system wafer and the protection of the front-side metallization by the opaque characteristics of the absorption layer can be achieved at the used laser wavelength. Compared to other cleaving concepts, it may be possible to perform the cleaving process after the front-side is completed. Thus, relatively costly and time-consuming high-temperature carriers can be omitted. Furthermore, the defects that typically exist in the starting substrate may not have a negative impact on the long-term electrical stability of the devices, since the migration of such effects can occur during the so-called bipolar degradation during device operation, e.g., at a time when the substrate has already been removed. Reuse of the SiC wafers can be enabled. Today's wafer costs can be approximately50% of the total chip cost. Proposed concepts can enable ultra-thin wafer processes with SiC devices similar to silicon power field-effect transistors (e.g., better thermomechanical characteristics, reduced contribution from SiC substrate resistance).

[0130] After cleaving, the devices may, for example, have residues of the absorption layer on the chip backsides. In case the resulting backside roughness is used for improved backside contact, the surface roughness may be characteristic of devices formed according to at least one of the proposed concepts. Furthermore, the higher defect density within this layer may be a clear indication of the use of the proposed concept. The chip thickness may provide information that a proposed cleaving process / support concept of some kind is being used, since the production of very thin SiC chips, e.g., only by grinding, can be relatively costly and time-consuming.

[0131] SiC wafers can be expensive and may only serve as a mechanical support and a seed base for the epitaxial growth of an active drift zone capable of blocking, for example. Regarding electrical characteristics, the wafer may add undesirable resistance, which is why, for example, a portion of the wafer as large as possible is removed from the front side by grinding after processing according to some concepts (e.g., with a target thickness of ~ 110 µm, assuming a wafer thickness of 350 µm). This grinding process can be costly and time-consuming, as SiC is a hard material, and the abraded, expensive monocrystalline SiC is lost for further processing. One aspect may be to find ways to separate the unused portion of the SiC wafer in a non-destructive manner (e.g., instead of grinding) and provide it as a starting wafer for further (re)use.Thus, the relative base material costs of the SiC starting wafer can be significantly reduced, since in the case of repeated reuse in the overall process, the proportional wafer consumption can be reduced to approximately 20%, for example, in the case of 5-fold reuse. It may be necessary to be able to cleave a specific wafer thickness with high accuracy.

[0132] Some reference cleaving concepts may utilize hydrogen implantation and annealing. For example, depending on the implantation depth (implantation energy), only thin layers may be cleaved. To cleave 20–40 µm (e.g., thickness for a future SiC chip), high implantation energies, which simultaneously require high ion current, would be required. Due to thermal induction of the cleaving process in some processes in a range of 800°C–1200°C, this may not be compatible with high-temperature processes such as SiC epitaxy (e.g., approximately 1600°C), dopant activation annealing (e.g., approximately 1800°C), and possibly trench rounding (e.g., approximately 1500°C). This may either lead to premature partial cleaving from the system wafer or omission of the cleaving process due to hydrogen diffusion, for example, according to some concepts.Consequently, some cleavage processes can only be used prior to epitaxy in combination with a high-temperature compatible support system, for example.

[0133] Some methods may be based on irradiation using a focused laser, for example, having a wavelength within the absorption range of SiC. A high photon density at the focal point may generate a charge carrier plasma, which in turn may increase absorption, for example. Consequently, a positive feedback mechanism may result, allowing, for example, the SiC to be locally decomposed and thus create a gap level that can subsequently be used for the cleavage process with assisted thermomechanical stress. The gap level may be influenced by the quality of the optical system and may not be automatically adjusted with respect to the active region of the device. For example, the cleavage process may be performed when device processing is more or less complete (short thin-wafer process).For example, the wafer may already be metallized on the front side. If the back side of the wafer is irradiated by the laser and the laser light is not immediately completely absorbed in the focal plane, the laser power passing through to the front side can, for example, damage the metal / semiconductor interface there.

[0134] The creation of a mechanically separating layer can be achieved, for example, by bonding a thin monocrystalline SiC layer to a patterned nitride layer and / or by producing porous SiC with subsequent epitaxial growth. Presented concepts suggest, for example, an optimization of the implantation dose and various measures for wafer regeneration.

[0135] The aspects and features mentioned and described together with one or more of the previously detailed examples and figures may also be combined with one or more of the other examples to replace a like feature of the other example or to additionally introduce the feature into the other example.

[0136] The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples provided herein are expressly intended to serve only illustrative purposes to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to advance the art. All statements herein regarding principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to include their equivalents.

[0137] It should be understood that the disclosure of multiple acts, processes, operations, steps, or functions disclosed in the description or claims should not be construed as occurring within the specific order unless otherwise explicitly or implicitly stated, for example, for technical reasons. Therefore, the disclosure of multiple steps or functions is not limited to a particular order unless those steps or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single step, function, process, or operation may include and / or be broken down into multiple sub-acts, functions, processes, operations, or steps. Such sub-steps may be included and be part of the disclosure of that single step unless explicitly excluded.

[0138] Furthermore, the following claims are hereby incorporated into the Detailed Description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it should be noted that although a dependent claim may refer to a particular combination with one or more other claims in the claims, other examples may include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are explicitly suggested herein unless it is stated that a particular combination is not intended. Furthermore, features of a claim for any other independent claim are also intended to be included, even if that claim is not made directly dependent on the independent claim.

Claims

[1] A method (100) for processing a silicon carbide wafer (300), the method (100) comprising: Implanting (110) ions into the silicon carbide wafer (300) to form an absorption layer (310) in the silicon carbide wafer (300), wherein for light of a target wavelength, an absorption coefficient of the absorption layer (310) is at least 100 times an absorption coefficient of a silicon carbide material of the silicon carbide wafer (300) outside the absorption layer, wherein the implanting (110) of the ions comprises: implanting ions at a first implantation dose through a first surface of the silicon carbide wafer; Obtaining a wafer surface with reduced near-surface crystal defects compared to the first surface after implanting the ions with the first implantation dose, wherein obtaining the wafer surface with reduced near-surface crystal defects comprises: Annealing the silicon carbide wafer to reduce the near-surface crystal defects on the first surface, wherein the first surface after annealing forms the wafer surface with reduced near-surface crystal defects and / or Forming a silicon carbide layer on the first surface of the silicon carbide wafer, wherein a surface of the silicon carbide layer after its formation forms the wafer surface with reduced near-surface crystal defects; and Implanting ions with a second implantation dose through the wafer surface, after obtaining the wafer surface with reduced near-surface crystal defects; and Cleaving (120) the silicon carbide wafer (300) along the absorption layer (310), at least by irradiating the silicon carbide wafer (300) with light of the target wavelength, to obtain a silicon carbide device wafer (360) and a remaining silicon carbide wafer (362). [2] The method (100) of claim 1, wherein a temperature of the silicon carbide wafer during implanting the ions is at least 300°C. [3] The method (100) according to claim 1 or 2, wherein the first implantation dose is at most 1.35·10 16 cm -2 and the second implantation dose is not more than 1.35·10 16 cm -2 is. [4] The method (100) according to any one of the preceding claims, wherein the ions with the first implantation dose are implanted with a first implantation energy and the ions with the second implantation dose are implanted with a second implantation energy, wherein the second implantation energy differs by at least 5% from the first implantation energy. [5] The method (100) according to any one of the preceding claims, wherein the ions with the first implantation dose are implanted with a first implantation energy and the ions with the second implantation dose are implanted with a second implantation energy, wherein the second implantation energy is higher than the first implantation energy. [6] The method (100) according to any one of the preceding claims, wherein forming the silicon carbide layer comprises epitaxially growing a silicon carbide layer or depositing the silicon carbide layer by chemical vapor deposition. [7] The method (100) according to any one of the preceding claims, wherein the silicon carbide layer has a thickness of at least 50 nm and at most 200 nm. [8] The method (100) of any preceding claim, further comprising forming a porous silicon carbide layer on a first side of the silicon carbide wafer. [9] The method (100) of claim 8, wherein the ions are implanted through at least a portion of the porous silicon carbide layer. [10] The method (100) according to claim 8 or 9, wherein the absorption layer is formed within the porous silicon carbide layer. [11] The method (100) according to claim 8 or 10, wherein the porous silicon carbide layer is formed after forming the absorption layer, wherein the porous silicon carbide layer extends vertically at least into a region of the silicon carbide wafer comprising the absorption layer, wherein an implantation dose for forming the absorption layer is at most 1.35 10 16 cm -2 is. [12] The method (100) according to any one of claims 8 to 11, wherein the porous silicon carbide layer has a thickness of at least 0.5 µm and at most 2.0 µm. [13] A method (100a) for processing a silicon carbide wafer, the method comprising: Implanting (110a) ions into the silicon carbide wafer (300) through a porous silicon carbide layer of the silicon carbide wafer (300) on a front side of the silicon carbide wafer (300) to form an absorption layer (310) in the silicon carbide wafer (300); and Cleaving (120a) the silicon carbide wafer (300) along the absorption layer (310), at least by irradiating the silicon carbide wafer (300) with light of the target wavelength, to obtain a silicon carbide device wafer (360) and a remaining silicon carbide wafer (362). [14] The method (100) according to any one of the preceding claims, wherein the target wavelength is between 370 nm and 430 nm or between 620 nm and 720 nm. [15] The method (100) of any preceding claim, further comprising removing a surface layer of the silicon carbide wafer from a first side of the silicon carbide wafer, wherein a thickness of the surface layer extends from a first surface of the silicon carbide wafer into the silicon carbide wafer, the surface layer having a thickness of less than 100 nm, wherein the ions are implanted from the first side, wherein the surface layer is removed after implanting the ions and before cleaving the silicon carbide wafer. [16] The method (100) of claim 15, wherein removing the surface layer from the first side comprises etching the first side of the silicon carbide wafer. [17] The method (100) according to claim 15 or 16, wherein after removing the surface layer from the first side of the silicon carbide wafer, a maximum vacancy concentration within a layer on the first side of the silicon carbide wafer is at most 3 10 22 cm -3 wherein the layer has a thickness of 10 nm and a thickness of the layer extends from the surface of the silicon carbide wafer into the silicon carbide wafer. [18] The method (100) according to any one of the preceding claims, wherein the ions are implanted (110) with an implantation dose higher than an amorphous dose required for amorphization of silicon carbide material of the absorption layer (310). [19] The method (100) according to any one of the preceding claims, wherein the ions are implanted (110) into the silicon carbide wafer (300) with an implantation dose that is higher than a solubility of the ions in the silicon carbide material of the silicon carbide wafer (300), such that precipitation occurs within the absorption layer (310) during annealing of the silicon carbide wafer (300). [20] The method (100) according to any one of the preceding claims, wherein the implanted ions are at least one of nitrogen ions, phosphorus ions, vanadium ions, boron ions, argon ions, carbon ions, nickel ions, silicon ions, titanium ions, tantalum, molybdenum, tungsten ions, gallium ions and aluminum ions. [21] The method (100) according to any one of the preceding claims, wherein a thickness of the absorption layer (310) is at least 300 nm and at most 600 nm. [22] The method (100) according to any one of the preceding claims, wherein the absorption layer (310) is formed within the silicon carbide wafer (300) at a distance from a surface of the silicon carbide wafer (300) of at least 500 nm and at most 5 µm. [23] The method (100) according to any one of the preceding claims, wherein the absorption layer (310) has a 3C crystal structure and the silicon carbide material of the silicon carbide wafer (300) surrounding the absorption layer (310) has a 4H crystal structure. [24] The method (100) according to any one of the preceding claims, wherein at least 10% of the light of the target wavelength penetrating through the silicon carbide material of the silicon carbide wafer (300) outside the absorption layer is absorbed by the absorption layer (310). [25] The method (100) according to any one of the preceding claims, further comprising at least one of the following method steps during and / or after irradiating the silicon carbide wafer (300) with the light of the target wavelength: (i) heating the silicon carbide wafer (300), (ii) applying mechanical force and / or stress to the silicon carbide wafer (300) and (iii) Ultrasonic treatment of the silicon carbide wafer (300). [26] The method (100) of any preceding claim, further comprising growing an epitaxial layer (320) on a front side of the silicon carbide wafer (300) prior to cleaving (120) the silicon carbide wafer (300). [27] The method (100) according to the preceding claim, wherein the epitaxial layer (320) has a thickness of at least 5 µm and of at most 300 µm. [28] The method (100) according to any one of the preceding claims, further comprising: forming a further absorption layer within the remaining silicon carbide wafer (362); and Cleaving the remaining silicon carbide wafer (362) along the further absorption layer.

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