METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

Method for manufacturing a semiconductor device, comprising: Forming a fin structure (30, 30A, 30B) comprising a lower fin structure (11, 11A 11B) and an upper fin structure arranged above the lower fin structure (11, 11A 11B), wherein the upper fin structure comprises first semiconductor layers (20) and second semiconductor layers (25) stacked alternately; Partial etching of the first semiconductor layers (20) to reduce the widths of the first semiconductor layers (20); Forming an oxide layer (45) over the upper fin structure, wherein the oxide layer (45) is formed by thermal oxidation, wherein an annealing operation is carried out after the thermal oxidation; Forming a sacrificial gate structure (50) over the upper fin structure with the oxide layer (45); Formation of a source / drain epitaxy layer (60A, 60B, 62A, 62B) over a source / drain region of the fin structure (30, 30A, 30B); Removing the sacrificial gate structure (50) to form a gate space; Removing the oxide layer (45) to expose the second semiconductor layers (25) in the gate space; and Forming a gate structure around the second semiconductor layers (25) in the gate space.

Description

GENERAL STATE OF THE ART

[0001] As the semiconductor industry has evolved toward nanometer-scale process nodes to achieve higher device density, greater performance, and lower cost, both manufacturing and design challenges have arisen in the development of three-dimensional designs such as multiple-gate field-effect transistors (FETs), including fin FETs and gate-all-around (GAA) FETs. In a fin FET, a gate electrode is adjacent to three side surfaces of a channel region with a gate dielectric layer in between. Because the gate structure wraps around (wraps) the fin on three surfaces, the transistor essentially has three gates that control the current through the fin or channel region. Unfortunately, the fourth side, the bottom of the channel, is far from the gate electrode and thus is not subject to tight gate control.In contrast, in a GAA FET, all side surfaces of the channel region are surrounded by the gate electrode, enabling more complete utilization of the channel region and resulting in reduced short-channel effects due to a steeper sub-threshold current swing (SS) and a smaller drain-induced barrier lowering (DIBL). As transistor dimensions are continuously scaled down to technology nodes below 10-15 nm, further improvements to the GAA FET are necessary. A manufacturing process is known, for example, from US 2016 / 0 240 652 A1 and US 2018 / 0 277 448 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 shows a view of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 2 shows a view of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 3A and Fig. 3B show various views of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 4A and Fig. 4B show various views of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 5 shows a view of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 6A, Fig. 6B, Fig. 6C and Fig. 6D show various views of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 7A, Fig. 7B, Fig. 7C and Fig. 7D show various views of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 8A, Fig. 8B, Fig. 8C and Fig. 8D show various views of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 9A, Fig. 9B, Fig. 9C, Fig. 9D and Fig. 9E show various views of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 10E and Fig. 10F show various views of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 11A, Fig. 11B, Fig. 11C, Fig. 11D, Fig. 11E, Fig. 11F and Fig. 11G show various views of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 12A, Fig. 12B, Fig. 12C, Fig. 12D and Fig. 12E show various views of one of the various stages of a sequential manufacturing process for a GAA FET device according to an embodiment of the present disclosure. Fig. 13A shows a view of one of the various stages of a sequential fabrication process for a GAA FET device according to another embodiment of the present disclosure. Fig. 13B shows a view of one of the various stages of a sequential fabrication process for a GAA FET device according to another embodiment of the present disclosure. Fig. 13C shows a view of one of the various stages of a sequential fabrication process for a GAA FET device according to another embodiment of the present disclosure. Fig. 14A, Fig. 14B, Fig. 14C, Fig. 14D, Fig. 14E and Fig. 14F show various views of one of the various stages of a sequential fabrication process for a GAA FET device according to another embodiment of the present disclosure. Fig. 15A, Fig. 15B, Fig. 15C, Fig. 15D, Fig. 15E and Fig. 15F show various views of one of the various stages of a sequential fabrication process for a GAA FET device according to another embodiment of the present disclosure. Fig. 16A, Fig. 16B, Fig. 16C, Fig. 16D and Fig. 16E show various views of one of the various stages of a sequential fabrication process for a GAA FET device according to another embodiment of the present disclosure. Fig. 17A, Fig. 17B, Fig. 17C and Fig. 17D show various views of one of the various stages of a sequential fabrication process for a GAA FET device according to another embodiment of the present disclosure. Fig. 18A, Fig. 18B, Fig. 18C and Fig. 18D show various views of one of the various stages of a sequential fabrication process for a GAA FET device according to another embodiment of the present disclosure. Fig. 19A, Fig. 19B, Fig. 19C, Fig. 19D and Fig. 19E show various views of one of the various stages of a sequential fabrication process for a GAA FET device according to another embodiment of the present disclosure. Fig. 20A, Fig. 20B, Fig. 20C and Fig. 20D show various views of GAA FET devices according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0003] It should be understood that the following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the device. Further, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features such that the first and second features may not be in direct contact.For the sake of simplicity and clarity, various features may be arbitrarily drawn at different scales.

[0004] Furthermore, spatially related terms such as "beneath," "beneath," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially related terms are intended to encompass various orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or with other orientations), and the spatially related descriptors used herein may also be interpreted accordingly. Additionally, the phrase "made of" can mean either "comprising" or "consisting of."In the present disclosure, a term "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element of A, one element of B, and one element of C unless described to the contrary.

[0005] In the following embodiments, the material, configurations, dimensions, operations, and / or processes of one embodiment may be employed in another embodiment unless described to the contrary, and detailed explanation thereof may be omitted.

[0006] Gate-all-around (GAA) FETs with a nano-sized channel, such as a nanowire or nanosheet, are promising devices for the next technology nodes in semiconductor integrated circuits, achieving lower operating current, higher device performance, higher device density, and lower process costs. The question of how to optimize the process flow is a key challenge with respect to the previous criteria. In a GAA FET manufacturing flow, the processes for channel epitaxy, an internal spacer, nanowire formation, and a metal gate with high-k dielectric formation are common process bottlenecks.

[0007] In the present disclosure, a device structure and a method of manufacturing the same are presented to solve the problems as set forth above.

[0008] Fig. 1-12E illustrate a sequential process for fabricating a GAA FET device according to an embodiment of the present disclosure. It should be understood that additional operations may be performed before, during, and after the operations described by Fig. 1-12E, and some of the operations described below may be replaced or removed by additional embodiments of the method. The order of the operations / processes may be interchangeable.

[0009] As in Fig. As shown in Figure 1, impurity ions (dopants) 12 are implanted into a silicon substrate 10 to form a well region. The ion implantation is performed to prevent a breakdown effect. In some embodiments, the substrate 10 has a single-crystal semiconductor layer on at least its surface portion. The substrate 10 may comprise a single-crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In one embodiment, the substrate 10 is made of crystalline Si.

[0010] The substrate 10 may have one or more buffer layers (not shown) in its surface region. The buffer layers may serve to gradually change the lattice constant from that of the substrate to that of the source / drain regions. The buffer layers may be formed from epitaxially grown single-crystal semiconductor materials, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate 10 includes silicon germanium (SiGe) buffer layers epitaxially grown on the silicon substrate 10. The Ge concentration of the SiGe buffer layers may increase from 30 atomic percent germanium for the bottommost buffer layer to 70 atomic percent germanium for the topmost buffer layer. The substrate 10 may have various regions suitably doped with impurities (e.g., p-type or n-type conductivity).The dopants 12 are, for example, boron (BF2) for an n-type fin FET and phosphorus for a p-type fin FET.

[0011] As in Fig. As shown in Figure 2, stacked semiconductor layers are formed over the substrate 10. The stacked semiconductor layers include first semiconductor layers 20 and second semiconductor layers 25. Furthermore, a mask layer 15 is formed over the stacked layers. The first semiconductor layers 20 and the second semiconductor layers 25 are made of materials having different lattice constants and may include one or more layers of Si, Ge, SiGe, GeSn, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP.

[0012] In some embodiments, the first semiconductor layers 20 and the second semiconductor layers 25 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. In certain embodiments, the first semiconductor layers 20 are Si1-x Ge x , where 0.15 ≤ x ≤ 0.5, and the second semiconductor layers 25 are Si. In some embodiments, 0.15 ≤ x ≤ 0.25. In other embodiments, the second semiconductor layers 25 are made of Si 1-y Ge y where y is approximately 0.2 or less and x > y.

[0013] In Fig. 2, five layers of the first semiconductor layer 20 and five layers of the second semiconductor layer 25 are arranged. However, the number of layers is not limited to five and can be as small as one (each layer), and in some embodiments, 2-20 layers of each of the first and second semiconductor layers are formed. By adjusting the number of stacked layers, a drive current of the GAA FET device can be adjusted.

[0014] The first semiconductor layers 20 and the second semiconductor layers 25 are formed epitaxially over the substrate 10. The thickness of the first semiconductor layers 20 may be equal to or less than that of the second semiconductor layers 25 and is in a range from about 2 nm to about 10 nm in some embodiments and is in a range from about 3 nm to about 5 nm in other embodiments. The thickness of the second semiconductor layers 25 is in a range from about 5 nm to about 20 nm in some embodiments and is in a range from about 7.5 nm to about 12.5 nm in other embodiments. The thickness of each of the first and second semiconductor layers may be the same or may vary.

[0015] In some embodiments, the lower first semiconductor layer (the next layer to the substrate 10) is thicker than the remaining first semiconductor layers. The thickness of the lower first semiconductor layer is in a range of approximately 10 nm to approximately 50 nm in some embodiments, or in a range of approximately 20 nm to 40 nm in other embodiments.

[0016] In some embodiments, the mask layer 15 includes a first mask layer 15A and a second mask layer 15B. The first mask layer 15A is a pad oxide layer made of a silicon oxide, which can be formed by thermal oxidation. The second mask layer 15B is made of a silicon nitride (SiN), which can be formed by chemical vapor deposition (CVD), including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable process. The mask layer 15 is patterned into a mask structure using patterning operations, including photolithography and etching.

[0017] As in Fig. 3A and Fig. Next, as shown in Figure 3B, the stacked layers of the first and second semiconductor layers 20, 25 are patterned by using the patterned mask layer, wherein the stacked layers are formed into fin structures 30 extending in the Y direction and arranged along the X direction.

[0018] The fin structures 30 may be patterned using any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that, for example, have slopes that are smaller than what can otherwise be obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed, and the remaining spacers, or mandrels, can then be used to pattern the fin structures.

[0019] In Fig. 3A and Fig. 3B, two fin structures 30A and 30B are arranged in the X-direction. However, the number of fin structures is not limited to two and can be as small as one, three, or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures 30 to improve the pattern fidelity during patterning operations. As shown in Fig. 3A and Fig. 3B, the fin structures 30 have upper portions formed by the stacked semiconductor layers 20, 25 and well portions 11 corresponding to the lower fin structure. In some embodiments, the fin structure 30A is for a p-channel GAA FET and the fin structure 30B is for an n-channel GAA FET. As shown in Fig. As shown in Figure 4A, fin structures 30A and 30B are disposed above lower fin structures 11A and 11B, respectively. In other embodiments, the fin structures are of the same type for an FET.

[0020] The width W1 of the upper portion of the fin structure 30 along the X-direction is in a range from approximately 5 nm to approximately 30 nm in some embodiments and is in a range from approximately 7.5 nm to approximately 15 nm in other embodiments. The height H1 along the Z-direction of the fin structure 30 is in a range from approximately 50 nm to approximately 200 nm.

[0021] After the fin structure is formed, the first semiconductor layers 20 are partially etched laterally, as in Fig. 4A and Fig. 4B. In some embodiments, plasma dry etching is used to selectively etch the first semiconductor layers 20 opposite the second semiconductor layers 25, followed by a wet cleaning process using buffered HF. In some embodiments, a plasma source gas comprises O2. In other embodiments, a wet etching process is used to selectively etch the first semiconductor layers 20. The etching solution (etchant) comprises an aqueous solution of NH4OH, H2O2, and H2O and / or an aqueous solution of H2SO4, H2O2, and H2O. In other embodiments, the wet etchant comprises a tetramethylammonium hydroxide (TMAH) solution. In some embodiments, an additional wet cleaning process is performed using buffered HF. In certain embodiments, both plasma dry etching and wet etching are used.In some embodiments, the etching amount D1 is in a range from about 1 nm to about 10 nm and is in a range from about 2 nm to about 5 nm. As shown in . Fig. 4B, the cross-sectional shape of the etched first semiconductor layers 20 has a dogbone shape or a spool (or reel) shape.

[0022] After the first semiconductor layers 20 are partially etched, an insulating material layer including one or more layers of insulating material is formed over the substrate so that the fin structures 30A and 30B are completely embedded in the insulating material layer. The insulating material for the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric material formed by LPCVD (Low Pressure Chemical Vapor Deposition), plasma CVD, or flowable CVD. An annealing operation may be performed after the formation of the insulating layer. Then, a planarization operation, such as a chemical mechanical polishing (CMP) process and / or an etch-back process, is performed so that the upper surface of the uppermost second semiconductor layer 25 is exposed from the insulating material layer.

[0023] In some embodiments, one or more fin liner layers 35 are formed before the insulating material layer is formed, as shown in Fig. 5. The liner layer 35 is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). In some embodiments, the fin liner layers 35 include a first fin liner layer 35A formed over the substrate 10 and the side surfaces of the lower fin structures 11, and a second fin liner layer 35B formed on the first fin liner layer 35A. Each of the liner layers has a thickness between about 1 nm and about 20 nm in some embodiments. In some embodiments, the first fin liner layer 35A comprises silicon oxide and has a thickness between about 0.5 nm and about 5 nm, and the second fin liner layer 35B comprises silicon nitride and has a thickness between about 0.5 nm and about 5 nm.The fin liner layers 35 may be deposited by one or more processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), although any acceptable process may be used.

[0024] As in Fig. 5, the insulating material layer is then recessed to form an insulating layer 40, so that the upper portions of the fin structures 30 are exposed. With this operation, the fin structures 30 are electrically separated from each other by the insulating layer 40, which is also called shallow trench isolation (STI). In the Fig. In the embodiment shown in Figure 5, the insulating material layer is left out until the top of the lower fin structure 11 is exposed. The first semiconductor layers 20 are sacrificial layers, which are subsequently partially removed, and the second semiconductor layers 25 are subsequently formed into the channel layers of a GAA FET. In other embodiments, the first semiconductor layers 20 are partially etched after the insulating layer 40 is formed.

[0025] After the insulating layer 40 is formed, an oxide layer 45 is formed over the upper portion of the fin structures 30A and 30B, as shown in Fig. 6A-6D shown. Fig. 6A shows a perspective view, Fig. 6B shows a cross-sectional view along the X direction, Fig. 6C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, and Fig. 6D shows a cross-sectional view along the Y direction intersecting the fin structure 30B.

[0026] In some embodiments, the oxide layer 45 is formed by a thermal oxidation process to oxidize the first semiconductor layers 20 and the second semiconductor layer 25. In some embodiments, the thermal oxidation process is performed in an oxidizing environment including O2 and / or O3. In certain embodiments, the thermal process is performed at a temperature in a range of approximately 800°C to approximately 1000°C. In other embodiments, a wet oxidation process is used. In certain embodiments, a chemical oxidation process is performed.

[0027] In some embodiments, the thermal oxidation completely oxidizes the first semiconductor layers 20 in the oxide layer 45. In other embodiments, a portion of the first semiconductor layers 20 remains in the fin structures. In some embodiments, the width of the remaining first semiconductor layer 20 is in a range from approximately 0.5 nm to approximately 2 nm. In some embodiments, the thickness of the oxide layer 45 is in a range from approximately 1 nm to approximately 5 nm.

[0028] When the first semiconductor layers 20 are made of SiGe and the second semiconductor layers 25 are made of Si, the oxide layer 45 includes a silicon germanium oxide portion and a silicon oxide portion at corresponding portions. In some embodiments, the silicon germanium oxide portion is primarily disposed between adjacent second semiconductor layers 25. In some embodiments, the silicon oxide portion is primarily disposed on side surfaces of the second semiconductor layers 25.

[0029] In some embodiments, an annealing operation is performed after the oxide layer 45 is formed. The annealing process is performed at a temperature in a range of approximately 800°C to approximately 1000°C in some embodiments.

[0030] After the oxide layer 45 is formed, a sacrificial gate structure 50 is formed over the fin structures 30A and 30B with the oxide layer 45, as shown in Fig. 7A-7D shown. Fig. 7A shows a perspective view, Fig. 7B shows a cross-sectional view along the X direction intersecting a sacrificial gate structure, Fig. 7C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, and Fig. 7D shows a cross-sectional view along the Y direction intersecting the fin structure 30B.

[0031] The sacrificial gate structure 50 includes a sacrificial gate electrode 54. In some embodiments, no sacrificial gate dielectric layer is formed. The sacrificial gate structure 50 is formed over a portion of the fin structures intended to be a channel region. The sacrificial gate structure 50 defines the channel region of the GAA FET.

[0032] The sacrificial gate structure 50 is formed by first depositing the sacrificial gate electrode layer over the fin structures 30A and 30B so that the fin structures are fully embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range from approximately 100 nm to approximately 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate electrode layer is deposited using CVD, including LPCVD and PECVD, PVD, ALD, or another suitable process. Subsequently, a mask layer 56 is formed over the sacrificial gate electrode layer. The mask layer 56 comprises one or more of a silicon nitride (SiN) layer and a silicon oxide layer.

[0033] Next, a patterning operation is performed on the mask layer and the sacrificial gate electrode layer in the sacrificial gate structure 50 is patterned as shown in Fig. 7A-7D. The sacrificial gate structure 50 includes the sacrificial gate electrode layer 54 (e.g., polysilicon) and the mask layer 56.

[0034] By patterning the sacrificial gate structure, the upper portion of the fin structure with the second semiconductor layers 25 and the oxide layer 45 is partially exposed on opposite sides of the sacrificial gate structure 50, defining source / drain (S / D) regions, as shown in Fig. 7A-7D. In this disclosure, a source and a drain are used interchangeably, and their structures are essentially the same. Fig. 7A-7D, a sacrificial gate structure 50 is formed, however, the number of sacrificial gate structures is not limited to one. Two or more sacrificial gate structures are arranged in the Y direction in some embodiments. In certain embodiments, one or more dummy sacrificial gate structures are formed on either side of the sacrificial gate structures to improve pattern fidelity.

[0035] After the sacrificial gate structure 50 is formed, the gate sidewall spacers 55 are formed as shown in Fig. 8A-8D shown. Fig. 8A shows a perspective view, Fig. 8B shows a cross-sectional view along the X direction intersecting the sacrificial gate structure 50, Fig. 8C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, and Fig. 8D shows a cross-sectional view along the Y direction intersecting the fin structure 30B.

[0036] To form the gate sidewall spacer 55, a cap layer of an insulating material is conformally formed using CVD or other suitable methods. The cap layer is deposited in a conformal manner such that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top surface of the sacrificial gate structure. In some embodiments, the cap layer is deposited to a thickness in a range of about 2 nm to about 20 nm. In some embodiments, the insulating material of the cap layer is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. In certain embodiments, the insulating material is one of SiOC, SiCON, and SiCN.

[0037] As in Fig. 8A-8D, the gate sidewall spacers 55 are further formed on opposite sidewalls of the sacrificial gate structures by anisotropic etching. After the cap layer is formed, anisotropic etching is performed on the cap layer using, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the insulating material is removed from horizontal surfaces, leaving the dielectric spacer layer on the vertical surfaces, such as the sidewalls of the sacrificial gate structures and the sidewalls of the exposed fin structures. The mask layer 56 may be exposed from the sidewall spacers. In some embodiments, an isotropic etching process may subsequently be performed to remove the insulating material from the upper portions of the S / D region of the exposed fin structures 30.

[0038] Subsequently, the oxide layer 45 formed around the second semiconductor layer 25 in the source-drain region is removed by suitable dry and / or wet etching operations.

[0039] As in Fig. 9A-9E, source / drain epitaxial layers 60A and 60B are formed next. Fig. 9A shows a perspective view, Fig. 9B shows a cross-sectional view along the X direction intersecting the sacrificial gate structure 50, Fig. 9C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, Fig. 9D shows a cross-sectional view along the Y direction intersecting the fin structure 30B, and Fig. Figure 9E shows a cross-sectional view along the X direction intersecting the source / drain region.

[0040] The first S / D epitaxial layer 60A is formed by wrapping the second semiconductor layers 25 in the S / D region of the fin structure 30A. The first S / D epitaxial layer 60A includes one or more layers of Si, SiGe, and SiGeP for a p-channel FET. The first S / D epitaxial layer 60A is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). In some embodiments, boron (B) is included in the first S / D epitaxial layer 60A. The second S / D epitaxial layer 60B is formed by wrapping the second semiconductor layers 25 in the S / D region of the fin structure 35B. The second S / D epitaxial layer 60B comprises one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET. The second S / D epitaxial layer 60B is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE).In some embodiments, the first source / drain (S / D) epitaxial layer 60A for a p-channel FET and the second S / D epitaxial layer 60B for an n-channel FET are formed separately.

[0041] Subsequently, a first insulating liner layer 63 is formed and then an interlayer dielectric (ILD) 65 is formed, and then the sacrificial gate structure 50 is removed, as shown in Fig. 10A-10F shown. Fig. 10A shows a perspective view, Fig. 10B shows a cross-sectional view along the X direction intersecting the channel region, Fig. 10C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, Fig. 10D shows a cross-sectional view along the Y direction intersecting the fin structure 30B, Fig. 10E shows a cross-sectional view along the X direction intersecting the source / drain region, and Fig. 10F shows a cross-sectional view along the X direction intersecting the gate sidewall spacer 55.

[0042] The first insulating liner layer 63 is made of a silicon nitride-based material, such as silicon nitride, and functions as a first contact etch stop layer (CESL) in subsequent etching operations. Materials for the first ILD layer 65 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, can be used for the first ILD layer 65. After the first ILD layer 65 is formed, a planarization operation, such as CMP, is performed to expose the sacrificial gate electrode layer 54.

[0043] As in Fig. 10A-10F, the sacrificial gate electrode layer 54 is removed next, and the oxide layer 45 is further removed, exposing channel regions of the second semiconductor layers 25 (semiconductor nanowires). The first ILD layer 65 protects the first and second S / D epitaxial layers 60A and 60B during the removal of the sacrificial gate structure. The sacrificial gate structure may be formed using plasma dry etching and / or wet etching. If the sacrificial gate electrode layer 54 is polysilicon and the first ILD layer 65 is silicon oxide, a wet etchant, such as a TMAH solution, may be used to selectively remove the sacrificial gate electrode layer 54. The oxide layer 45 is then removed using plasma dry etching and / or wet etching.

[0044] In some embodiments, a portion of the oxide layer 45 remains under the gate sidewall spacers 55 as internal spacers, as shown in Fig. 10C, Fig. 10D and Fig. 10F. The thickness of the remaining oxide layer 45 is in a range from about 0.2 nm to about 2 nm in some embodiments.

[0045] After the wires of the second semiconductor layers 25 are exposed, a gate dielectric layer 104 is formed around the wires of the second semiconductor layer 25 in the structures 30A and the fin structure 30B, as shown in Fig. 11A-11G shown. Fig. 11A shows a perspective view, Fig. 11B shows a cross-sectional view along the X direction intersecting the channel region, Fig. 11C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, Fig. 11D shows a cross-sectional view along the Y direction intersecting the fin structure 30B, Fig. 11E shows a cross-sectional view along the X direction intersecting the source / drain region, Fig. 11F shows a cross-sectional view along the X direction intersecting the gate sidewall spacer 55, and Fig. Figure 11G shows an enlarged view of the canal region.

[0046] In some embodiments, the gate dielectric layer 104 comprises one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, a hafnium dioxide-aluminum (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, an interface layer 102 is formed between the channel layers and the gate dielectric layer 104. The gate dielectric layer 104 may be formed by CVD, ALD, or any suitable method.In one embodiment, the gate dielectric layer 104 is formed using a highly conformal deposition process, such as ALD, to ensure the formation of a gate dielectric layer having a uniform thickness around each channel layer. The thickness of the gate dielectric layer 104 ranges from approximately 1 nm to approximately 6 nm in one embodiment.

[0047] Furthermore, a gate electrode layer 108 is formed over the gate dielectric layer 104, as shown in Fig. 11A-11G. The gate electrode layer 108 is formed over the gate dielectric layer 104 to surround each channel layer in some embodiments. The gate electrode 108 includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 108 may be formed by CVD, ALD, electroplating, or another suitable method. The gate electrode layer is also deposited over the top surface of the first ILD layer 65. The gate dielectric layer and the gate electrode layer formed over the first ILD layer 65 are then planarized using, for example, CMP until the first ILD layer 65 is exposed.

[0048] In certain embodiments, one or more work-function matching layers 106 are interposed between the gate dielectric layer 104 and the gate electrode layer 108. The work-function matching layers 106 are made of a conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work-function matching layer. The work-function matching layer 106 can be formed by ALD, PVD, CVD, electron beam evaporation, or another suitable process. Furthermore, the work function matching layer 106 may be formed separately for the n-channel FET and the p-channel FET, which may use different metal layers.

[0049] Subsequently, a second insulating liner layer 110 is formed over the first ILD layer 65 and the second ILD layer 115 is formed over the second insulating layer 110, as shown in Fig. 12A-12E shown. Fig. 12A shows a perspective view, Fig. Figure 12B shows a cross-sectional view along the X direction intersecting the channel region, Fig. 12C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, Fig. 12D shows a cross-sectional view along the Y direction intersecting the fin structure 30B, and Fig. Figure 12E shows a cross-sectional view along the X direction intersecting the source / drain region.

[0050] The second insulating liner layer 110 is made of a silicon nitride-based material, such as silicon nitride, and acts as a second CESL during subsequent etching operations. Materials for the second ILD layer 115 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, can be used for the second ILD layer 110. After the second ILD layer 110 is formed, a planarization operation, such as CMP, is performed.

[0051] Then, contact openings are formed to expose the source / drain epitaxial layers 60A and 60B, respectively. The contact openings are filled with one or more layers of conductive materials, forming S / D contacts, as shown in Fig. 12A-12E. One or more layers of conductive materials are formed in and over the contact openings, and then a planarization operation, such as a CMP operation, is performed to form the S / D contacts. In some embodiments, the S / D contact includes a liner layer 122 and a body layer 120. The liner layer 122 is a barrier layer and / or an adhesive (adhesion) layer. In some embodiments, a Ti layer is formed on the source / drain epitaxial layers 60A and 60B, and a TiN or TaN layer is formed on the Ti layer as the liner layer 122. The body layer 120 includes one or more layers of Co, Ni, W, Ti, Ta, Cu, and Al, or any other suitable material. As shown in Fig. 12A and Fig. As shown in Figure 12E, the conductive S / D contact wraps around the source / drain epitaxial layers 60A and 60B, respectively.

[0052] In some embodiments, when the first semiconductor layer is made of SiGe and the second semiconductor layer is made of Si, the oxide layer 45 includes a silicon germanium oxide portion and a silicon oxide portion below the gate sidewall spacers 55. In some embodiments, the silicon germanium oxide portion below the gate sidewall spacers 55 is primarily disposed between adjacent second semiconductor layers 25, and the silicon oxide portion is primarily disposed on side surfaces of the second semiconductor layers 25.

[0053] In some embodiments, the second semiconductor layer 25 below the gate sidewall spacers has a cross-section that includes two vertical sides, a V-shaped bottom side and an inverted V-shaped top side. In other embodiments, the second semiconductor layers 25 below the gate sidewall spacers have a cross-section that includes two vertical sides, an upwardly projecting top side and a downwardly projecting bottom side. In some embodiments, the topmost one of the second semiconductor layers 25 below the gate sidewall spacers has a cross-section that includes two vertical sides, a flat top side and a downwardly projecting bottom side.

[0054] It is understood that the GAA FETs undergo further CMOS processes to form various features such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0055] Fig. 13A-16E illustrate a sequential process for fabricating a GAA FET device according to another embodiment of the present disclosure. It should be understood that additional operations may be performed before, during, and after the processes described by Fig. 13A-16E, and some of the operations described below may be replaced or removed by additional embodiments of the method. The order of operations / processes may be interchangeable.

[0056] After the Fig. 9A-9E is formed, the n-channel region including the fin structure 30A is covered by a mask layer, such as a silicon nitride layer, to protect the n-channel region. Then, similar to the operations described with reference to Fig. 10A-10E, the second semiconductor layers 25 are exposed in the channel region. Fig. Figure 13A shows an enlarged view of one of the second semiconductor layers 25 in the channel region for a p-channel FET. Then, a third semiconductor layer 26 is formed over the second semiconductor layer 25, as shown in Fig. 13B. In some embodiments, the third semiconductor layer is made of Si 1-z Ge z where 0.2 ≤ z ≤ 1.0. In other embodiments, 0.3 ≤ z ≤ 0.5. The thickness of the third semiconductor layer 26 is in a range from about 0.2 nm to about 2 nm in some embodiments.

[0057] After the third semiconductor layer 26 is formed, a thermal process is performed to form an alloy 27 of the second semiconductor layer 25 (e.g., Si) and the third semiconductor layer 26 (e.g., SiGe). The alloy 27 is Si 1-w Ge w , where 0.3 ≤ w ≤ 0.7 in some embodiments and 0.4 ≤ z ≤ 0.6 in other embodiments. The heat treatment is performed at 900°C to 1100°C in some embodiments. In some embodiments, rapid thermal annealing (RTA) is used. In certain embodiments, laser annealing is used.

[0058] In some embodiments, an oxide cap layer is formed over the third semiconductor layer 26 prior to the thermal process, and the oxide cap layer is removed after the thermal process.

[0059] Subsequently, the p-channel region with the alloy semiconductor wires 27 is protected by a cap layer, and then the n-channel region is processed to expose the second semiconductor layers 25 in the channel region. Then, the cap layer of the p-channel region is removed, obtaining the structure as shown in Fig. 14A-14F shown. Fig. 14A shows a perspective view, Fig. 14B shows a cross-sectional view along the X direction intersecting the channel region, Fig. 14C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, Fig. 14D shows a cross-sectional view along the Y direction intersecting the fin structure 30B, Fig. 14E shows a cross-sectional view along the X direction intersecting the source / drain region, and Fig. 14F shows a cross-sectional view along the X direction intersecting the gate sidewall spacer 55. As in Fig. 14B-14F, the second semiconductor layer 25 remains in the source / drain region and under the gate sidewall spacers.

[0060] After the wires of the second semiconductor layers 25 are exposed in the p-channel region and the n-channel region, a gate dielectric layer 104 is formed around the wires of the second semiconductor layer 25, as shown in Fig. 15A-15F, similar to Fig. 11A-11G. Fig. 15A shows a perspective view, Fig. Figure 15B shows a cross-sectional view along the X direction intersecting the channel region, Fig. 15C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, Fig. 15D shows a cross-sectional view along the Y direction intersecting the fin structure 30B, Fig. 15E shows a cross-sectional view along the X direction intersecting the source / drain region, and Fig. 15F shows a cross-sectional view along the X direction intersecting the gate sidewall spacer 55.

[0061] Similar to Fig. 12A-12E, source / drain contacts 120 are subsequently formed, as in Fig. 16A-16E shown. Fig. 16A shows a perspective view, Fig. 16B shows a cross-sectional view along the X direction intersecting the channel region, Fig. 16C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, Fig. 16D shows a cross-sectional view along the Y direction intersecting the fin structure 30B, and Fig. Figure 16E shows a cross-sectional view along the X direction intersecting the source / drain region.

[0062] In some embodiments, the oxide layer 45 wraps around the Si portion of the semiconductor wires 25 beneath the gate sidewall spacers 55.

[0063] It is understood that the GAA FETs undergo further CMOS processes to form various features such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0064] Fig. 17A-19E illustrate a sequential process for fabricating a GAA FET device according to another embodiment of the present disclosure. It should be understood that additional operations may be performed before, during, and after processes performed by Fig. 17A-19E, and some of the operations described below may be replaced or removed by additional embodiments of the method. The order of the operations / processes may be interchangeable.

[0065] After the Fig. 8A-8D is formed, the source / drain regions of the fin structures including the second semiconductor layer 25 and the oxide layer 45 are removed as shown in Fig. 17A-17D shown. Fig. 17A shows a perspective view, Fig. Figure 17B shows a cross-sectional view along the X direction intersecting the channel region, Fig. 17C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, and Fig. 17D shows a cross-sectional view along the Y direction intersecting the fin structure 30B.

[0066] As in Fig. 18A-18D, source / drain epitaxial layers 62A and 62B are formed next. Fig. 18A shows a perspective view, Fig. 18B shows a cross-sectional view along the X direction intersecting the sacrificial gate structure 50, Fig. 18C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, and Fig. 18D shows a cross-sectional view along the Y direction intersecting the fin structure 30B.

[0067] The first S / D epitaxial layer 62A is formed on end sides of the second semiconductor layers 25 in the S / D region of the fin structure 30A. The first S / D epitaxial layer 62A includes one or more layers of Si, SiGe, and SiGeP for a p-channel FET. The first S / D epitaxial layer 62A is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). In some embodiments, boron (B) is included in the first S / D epitaxial layer 62A. The second S / D epitaxial layer 62B is formed on end sides of the second semiconductor layers 25 in the S / D region of the fin structure 35B. The second S / D epitaxial layer 62B includes one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET. The second S / D epitaxial layer 62B is formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE).In some embodiments, the first source / drain (S / D) epitaxial layer 62A for a p-channel FET and the second S / D epitaxial layer 62B for an n-channel FET are formed separately.

[0068] Subsequently, the same or similar operations are carried out with reference to Fig. 10A-12E source / drain contacts 120 formed as in Fig. 19A-19E shown. Fig. 19A shows a perspective view, Fig. Figure 19B shows a cross-sectional view along the X direction intersecting the channel region, Fig. 19C shows a cross-sectional view along the Y direction intersecting the fin structure 30A, Fig. 19D shows a cross-sectional view along the Y direction intersecting the fin structure 30B, and Fig. Figure 19E shows a cross-sectional view along the X direction intersecting the source / drain region.

[0069] It is understood that the GAA FETs undergo further CMOS processes to form various features such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0070] Fig. 20A-20D show various structures of the fin structure under the gate sidewall spacers 55. In some embodiments, during the oxidation process of the first semiconductor layer 20, the first semiconductor layers 20 are not completely oxidized, and a portion of the first semiconductor layers 20 remains. Thus, after the gate structure is formed, the remaining portion of the first semiconductor layers 20 is present under the gate sidewall spacers 55, as shown in Fig. 20A. The oxide layer 45 is arranged continuously on side surfaces of the second semiconductor layer 25 and the remaining first semiconductor layers 20.

[0071] In other embodiments, when the oxide layer 45 in the gate space is removed, the oxide layer between the second semiconductor layers 25 is substantially completely removed. Thus, after the gate structure is formed, air gaps 29 are formed between the second semiconductor layers under the gate sidewall spacers 55, as shown in Fig. 20B. The oxide layer 45 is arranged discontinuously on side surfaces of the second semiconductor layer 25.

[0072] Furthermore, in some embodiments, the air gaps are filled with one or more dielectric materials, as in Fig. 20C. In certain embodiments, the barrier layer 102 is formed on upper and lower sides of the second semiconductor layers 25, or the alloy semiconductor layers 27 and the gate dielectric layer 104 fill the spaces between the barrier layer 102, as shown in Fig. 20C. As shown in Fig.20D, in other embodiments, the barrier layer 102 connects the adjacent second semiconductor layers 25, and the gate dielectric layer 104 is formed on the barrier layer 102. The oxide layer 45 is disposed discontinuously on side surfaces of the second semiconductor layer 25.

[0073] The various embodiments or examples described herein offer several advantages over the existing state of the art. For example, the internal spacers can be formed in a self-aligned manner. Additionally, Si nanowire channels and SiGe nanowire channels are formed through a single-channel epitaxy process. Thus, it is possible to improve the performance of GAA FETs and reduce manufacturing costs.

[0074] It should be understood that not all advantages have necessarily been discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0075] The invention is defined by the main claim and the subordinate claims.

Claims

[1] A method of manufacturing a semiconductor device, comprising: Forming a fin structure (30, 30A, 30B) having a lower fin structure (11, 11A 11B) and an upper fin structure disposed above the lower fin structure (11, 11A 11B), the upper fin structure having first semiconductor layers (20) and second semiconductor layers (25) stacked alternately; partially etching the first semiconductor layers (20) to reduce widths of the first semiconductor layers (20); Forming an oxide layer (45) over the upper fin structure, wherein the oxide layer (45) is formed by thermal oxidation, wherein an annealing operation is performed after the thermal oxidation; Forming a sacrificial gate structure (50) over the upper fin structure with the oxide layer (45); Forming a source / drain epitaxial layer (60A, 60B, 62A, 62B) over a source / drain region of the fin structure (30, 30A, 30B); removing the sacrificial gate structure (50) to form a gate space; Removing the oxide layer (45) to expose the second semiconductor layers (25) in the gate space; and Forming a gate structure around the second semiconductor layers (25) in the gate space. [2] The method according to claim 1, wherein the annealing operation is carried out at 800 °C to 1000 °C. [3] Method according to one of the preceding claims 1 to 2, wherein the etched first semiconductor layers (20) are completely oxidized by the thermal oxidation. [4] Method according to one of the preceding claims 1 to 2, wherein the etched first semiconductor layers (20) are partially oxidized by the thermal oxidation. [5] The method of claim 4, wherein after the oxide layer (45) in the gate space is removed, the first semiconductor layers (20) in the gate space are removed. [6] A method according to any one of the preceding claims, wherein, before the source / drain epitaxial layer (60A, 60B, 62A, 62B) is formed, the oxide layer (45) in the source / drain region is removed. [7] The method of claim 6, wherein the source / drain epitaxial layer (60A, 60B, 62A, 62B) wraps the second semiconductor layers (25) in the source / drain region. [8] A method according to any one of the preceding claims, wherein a portion of the oxide layer (45) remains between the source / drain epitaxial layer (60A, 60B, 62A, 62B) and the gate structure (50). [9] The method of any preceding claim, further comprising forming an insulating insulating layer (40) around the lower fin structure (11, 11A 11B) after the first semiconductor layers (20) are partially etched. [10] Method according to one of the preceding claims, wherein: the sacrificial gate structure (50) has a sacrificial gate electrode (54), and the sacrificial gate electrode (54) is in contact with the oxide layer (45). [11] Method according to one of the preceding claims, wherein the first semiconductor layers (20) are made of SiGe and the second semiconductor layers (25) are made of Si. [12] The method of any preceding claim, wherein after forming the sacrificial gate structure (50), gate sidewall spacers (55) are formed on opposite sidewalls of the sacrificial gate structure (50). [13] A method of manufacturing a semiconductor device, comprising: Forming a fin structure (30, 30A, 30B) having a lower fin structure (11, 11A 11B) and an upper fin structure disposed above the lower fin structure (11, 11A 11B), the upper fin structure having first semiconductor layers (20) and second semiconductor layers (25) stacked alternately; partially etching the first semiconductor layers (20) to reduce widths of the first semiconductor layers (20); Forming an oxide layer (45) over the upper fin structure, wherein the oxide layer (45) is formed by thermal oxidation, wherein an annealing operation is performed after the thermal oxidation; Forming a sacrificial gate structure (50) over the upper fin structure with the oxide layer (45); Forming a source / drain epitaxial layer (60A, 60B, 62A, 62B) over a source / drain region of the fin structure (30, 30A, 30B); removing the sacrificial gate structure (50) to form a gate space; Removing the oxide layer (45) in the gate space to expose the second semiconductor layers (25) in the gate space; Forming a third semiconductor layer (26) on each of the exposed second semiconductor layers (25); Forming channel wires (27) by mixing the third semiconductor layer (26) and the second semiconductor layer (25); and Forming a gate structure around the channel wires (27) in the gate space. [14] The method of claim 13, wherein: the first semiconductor layers (20) are made of SiGe, the second semiconductor layers (25) are made of Si, and the third semiconductor layer (26) is made of SiGe or Ge. [15] Method according to one of the preceding claims 13 to 14, wherein the etched first semiconductors are completely oxidized by the thermal oxidation. [16] The method of any one of the preceding claims 13 to 15, wherein a portion of the oxide layer (45) remains between the source / drain epitaxial layer (60A, 60B, 62A, 62B) and the gate structure. [17] The method of any one of the preceding claims 13 to 16, wherein after forming the sacrificial gate structure (50), gate sidewall spacers (55) are formed on opposite sidewalls of the sacrificial gate structure (50).

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