Bulk semiconductor substrate configured to demonstrate semiconductor-on-insulator behavior

Abstract

Device (100) for integrated circuit comprising a bulk substrate (102) exhibiting semiconductor-on-insulator behavior, wherein the device for integrated circuit comprises: a channel area (114) defined in the bulk substrate, wherein the channel area has a first section (114A) arranged above a second section (114B), and wherein further: the first section (114A) is arranged between epitaxial source-drain features (140) that are arranged in the bulk substrate (102), the second section (114B) is defined by a first isolation feature (130) arranged in the bulk substrate (102), wherein the epitaxial source-drain features (140) are arranged on the first isolation feature (130), and a strength of the channel area (114) is approximately equal to a sum (tsi) of a strength (t2) of the first isolation feature and a strength (t3) of the epitaxial source-drain features; a second isolation feature (182) arranged in the bulk substrate, wherein the second isolation feature defines an active area comprising the first section of the channel area (114A) located between the epitaxial source-drain features (140); wherein a resistance of a section of the bulk substrate (120) located on the bulk substrate and below the first insulation feature (130) and the channel region (114) is greater than a resistance of the bulk substrate (102); wherein the channel region (114) has a tapered width (W7) that decreases, while the thickness of the channel region (t si ) increases; and where a width (L G ) of the first section (114A) is essentially the same, while the strength (t si) of the channel area (114) increases, and a width (W7) of the second section (114B) decreases, while the strength of the channel area increases.

Description

GENERAL STATE OF THE ART

[0001] The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of integrated circuits with smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (the number of interconnected devices per unit area) has generally increased, while geometric size (the smallest component or trace that can be created using a manufacturing process) has decreased. This miniaturization process generally provides benefits by increasing production efficiency and reducing associated costs.

[0002] Such miniaturization has also increased the complexity of processing and manufacturing integrated semiconductor circuits. Crosstalk, for example, has become a significant challenge as more IC devices, circuits, and / or systems incorporate multiple functionalities densely packed onto a single substrate to meet the demands of advanced IC technology nodes. Crosstalk often arises from capacitive, inductive, and / or conductive coupling between IC devices and / or components on the same substrate. Semiconductor-on-insulator (SOI) technology has been implemented to improve isolation and eliminate crosstalk between IC devices and / or components. In SOI technology, IC devices are fabricated on a semiconductor-insulator-semiconductor substrate, such as a silicon-oxide-silicon substrate, instead of a bulk semiconductor substrate.However, SOI substrates are very expensive, making the large-volume production of ICs on SOI substrates prohibitively expensive. Therefore, alternative, cost-effective approaches are needed for isolating ICs and / or suppressing crosstalk between them.

[0003] US 2011 / 0024840 A1 relates to a silicon-on-insulator (SOI) transistor device comprising a buried insulator layer formed over a bulk substrate and an SOI layer formed on the buried insulator layer, as well as a pair of silicon-containing epitaxial regions located adjacent to opposite sides of a gate conductor.

[0004] US 2013 / 0240991 A1 relates to a device comprising a single-crystal semiconductor substrate and an SOI substrate separated from the single-crystal semiconductor substrate by a thin buried insulating film and comprising a thin single-crystal semiconductor thin film.

[0005] US 2013 / 0320459 A1 relates to a device comprising a semiconductor substrate, a contact plug over the semiconductor substrate and an inter-layer dielectric (ILD) layer over the semiconductor substrate, wherein the contact plug is located in the ILD. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The invention is defined according to the independent claims. The dependent claims relate to corresponding embodiments. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale and are used solely for illustrative purposes. The dimensions of the various features may be arbitrarily enlarged or reduced for clarity of discussion. Fig. Figure 1 is a flowchart of a process for manufacturing a component of an integrated circuit (IC) according to various aspects of the present disclosure. The Fig. Figures 2A to 15A are schematic top views of an IC component, either as a section or in its entirety, at various manufacturing stages of a process, such as the process of Fig. 1, according to various aspects of the present revelation. The Fig. 2B to 15B are schematic cross-sectional views of the IC component, either as a section or in its entirety, each along line BB. Fig. 2A to 15A according to various aspects of the present revelation. Fig. Figure 16 is a schematic cross-sectional view of another IC component as a section or in its entirety according to various aspects of the present disclosure. Fig. Figure 17 is a schematic cross-sectional view of yet another IC component as a section or in its entirety according to various aspects of the present disclosure. Fig. Figure 18A is a schematic top view of an IC component as a section or in its entirety according to various aspects of the present disclosure. Fig. 18B is a schematic cross-sectional view of the IC component as a section or in its entirety, each along line BB of the Fig. 18A according to various aspects of the present revelation. Fig. Figure 19A is a schematic top view of an IC component as a section or in its entirety according to various aspects of the present disclosure. Fig. 19B is a schematic cross-sectional view of the IC component as a section or in its entirety, each along line BB of the Fig. 19A according to various aspects of the present revelation. DETAILED DESCRIPTION

[0007] The present disclosure relates generally to components of an integrated circuit (IC) and in particular to semiconductor-on-insulator (SOI)-like structures that can be manufactured in bulk substrates of IC components, such that the bulk substrates exhibit SOI-like behavior.

[0008] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact.

[0009] Furthermore, the present disclosure may repeat reference numerals and / or reference letters in the various examples. This repetition is intended for simplicity and clarity and does not itself prescribe any relationship between the various embodiments and / or configurations discussed. Moreover, the formation of a feature on, connected with, and / or coupled with another feature in the present disclosure, which follows below, may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features can be formed by inserting the features so that the features are not in direct contact. Furthermore, spatial reference terms, for example, "below," "above," "horizontal," "vertical," "above," "over," "below," "below," "on," "off," "top," "bottom," etc., are used.as well as derivatives thereof (for example, "in a horizontal direction," "downward," "upward," etc.) are used to facilitate the present disclosure of the relationship of one feature to another. The spatial reference terms are intended to cover different orientations of the component exhibiting the features.

[0010] Crosstalk has become a significant challenge as more IC devices, circuits, and / or systems incorporate multiple functionalities densely packed onto a single substrate to meet the demands of advanced IC technology nodes. Crosstalk generally refers to any phenomenon where signals from a first IC device and / or component pass through the substrate and couple to a second IC device and / or component, thereby unintentionally interrupting or impairing the operation of the second IC device and / or component. Crosstalk often arises from capacitive, inductive, and / or conductive coupling between IC devices and / or components on the same substrate.When digital, analog and radio frequency (RF) systems (also called microwave systems) are implemented on the same substrate, it has been observed that RF systems are extremely susceptible to crosstalk as operating frequencies increase (for example, to GHz ranges) and IC technology nodes shrink.

[0011] Semiconductor-on-insulator (SOI) technology was implemented to improve isolation and reduce crosstalk (noise) between IC devices and / or IC components compared to conventional isolation structures, such as shallow trench isolation (STI) and / or deep trench isolation (DTI) features implemented on bulk semiconductor substrates. In SOI technology, IC devices are fabricated on a semiconductor-insulator-semiconductor substrate, such as a silicon oxide-silicon substrate, instead of a bulk semiconductor substrate. SOI substrates can completely isolate IC devices and / or IC components from each other, significantly reducing any parasitic signals between IC devices and / or IC components on the same substrate. However, SOI substrates are very expensive, often costing up to ten times more than bulk semiconductor substrates.Manufacturing large volumes of IC devices on SOI substrates is therefore often prohibitively expensive. Bulk semiconductor substrates with high resistivity were introduced as an alternative to SOI substrates, but it has been observed that the high resistivity characteristics of the bulk semiconductor substrate create barriers to desired IC performance (for example, by reducing charge carrier mobility).

[0012] This disclosure proposes alternative approaches for cost-effective isolation of IC devices while significantly suppressing crosstalk and / or improving performance. For example, it discloses methods for fabricating SOI-like structures in bulk semiconductor substrates such that the bulk semiconductor substrates exhibit SOI (or SOI-like) behavior. Each of the SOI-like structures described herein features a dual-insulation structure that defines a substantially (or completely) isolated active region and a substantially (or completely) isolated channel region of an IC device, such as a transistor. The dual-insulation structure, for example, includes a first isolation trench that defines a channel region of a bulk substrate and a second isolation trench that defines an active region containing the channel region.The first isolation trench can define a desired gate length of the IC device. In some implementations, the channel region has a tapered width that decreases along its thickness, which can minimize (or eliminate) any connection between a bottom portion of the channel region and adjacent IC devices and / or features. The first isolation trench is filled with a first insulating material and a semiconductor material, with the semiconductor material positioned above the first insulating material. In some implementations, the semiconductor material forms epitaxial source / drain features between which the channel region is positioned. A second insulating material fills the second isolation trench. A portion of the bulk substrate located below the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.In some implementations, the portion of the bulk substrate located beneath the first isolation trench and the channel region is an amorphous layer. The first isolation trench, the second isolation trench, and the higher-resistance bulk substrate section can effectively isolate the channel region and source / drain regions of the IC device from neighboring IC devices and / or adjacent IC features, thus preventing crosstalk and / or improving the performance of the IC device.

[0013] Relatively inexpensive bulk semiconductor substrates implementing the SOI-like structures described herein exhibit SOI-like properties and characteristics, such that IC devices fabricated on these bulk semiconductor substrates exhibit improved performance similar to that observed when fabricated on SOI substrates. The disclosed SOI structures can therefore significantly suppress crosstalk and / or improve IC performance at a fraction of the cost of SOI technology and / or high-resistance bulk substrate technology. The SOI-like structures are particularly well-suited for RF applications by providing strong isolation for RF devices, which can significantly improve their performance. Different embodiments may offer different advantages, and no particular advantage is necessarily required for any one embodiment.

[0014] With reference to Fig. 1 is Fig. 1 A flowchart of a process 10 for fabricating an IC device such that a bulk substrate of the IC device exhibits SOI behavior, according to various aspects of the present disclosure. In block 15, the process 10 features the formation of a first isolation trench in the bulk substrate. The first isolation trench defines a channel region of the bulk substrate and, in particular, defines a gate length of the IC device. In some implementations, an etching process is performed in two steps to form the first isolation trench, such that the first isolation trench has a first section arranged above a second section. In some implementations, the first section has substantially vertical sidewalls, and the second section has negatively sloping sidewalls, with the first section defining the gate length.In Block 20, the process involves increasing the resistance of a section of the bulk substrate located below the first isolation trench and the channel region of the bulk substrate. In some reactions, an implantation process is performed, introducing ions and / or dopants to this section of the bulk substrate, thereby forming a layer of high resistance. In some reactions, the layer of high resistance is an amorphous layer of the bulk substrate. In Block 25, the process involves filling the first section of the first isolation trench with a first insulator material, such as any material suitable for insulation purposes. In Block 30, the process involves filling the second section of the first isolation trench with a semiconductor material.In some transformations, the semiconductor material is an epitaxial semiconductor material that can form epitaxial source / drain features of the IC device. In Block 35, Method 10 involves forming a second insulating trench in the bulk substrate. The second insulating trench defines an active region that exhibits the channel region of the bulk substrate. In some transformations, the active region further exhibits the epitaxial source / drain features. In Block 40, Method 10 fills the second insulating trench with a second insulator material, such as any material suitable for insulating purposes. In some transformations, the second insulator material is the same as the first insulator material. In some transformations, the second insulator material is different from the first insulator material. In Block 45, Method 10 can proceed to complete the fabrication of the IC device.Additional steps may be provided before, during and after method 10, and some of the steps described may be relocated, replaced or eliminated for additional embodiments of method 10.

[0015] The Fig. Figures 2A to 15A are schematic top views of an IC component 100 as a section or in its entirety at various manufacturing stages of a process, such as process 10 of the Fig. 1, according to various aspects of the present revelation. The Fig. 2B to 15B are schematic cross-sectional views of the IC component 100 as a section or in its entirety, each along line BB. Fig. 2A to 15A according to various aspects of the present disclosure. The IC component 100 can be contained in a microprocessor, a memory, and / or another component of an integrated circuit. In some implementations, the IC component 100 is a section of an IC chip, a system-on-chip (SoC), or a section thereof, which incorporates various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.The various transistors can be planar transistors or multi-gate transistors, such as FETs (FinFETs), depending on the design requirements of the IC component 100. The . Fig. 2A to 15A and Fig. Sections 2B to 15B have been simplified for clarity and to better illustrate the inventive concepts of the present disclosure. Additional features may be added to the IC device 100, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the IC device 100.

[0016] With reference to Fig. 2A and Fig. In Figure 2B, the IC device 100 comprises a bulk substrate (wafer) 102. In the illustrated embodiment, the bulk substrate 102 comprises silicon, which can generally be called a bulk silicon substrate. Alternatively or additionally, the bulk substrate 102 comprises another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon-germanium (SiGe), SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. In some implementations, the bulk substrate 102 comprises one or more materials from Group III-V and / or one or more materials from Group II-IV, or combinations thereof. The bulk substrate 102 can have various doped areas (not shown) configured according to the design requirements of the IC device 100.In some reactions, the bulk substrate exhibits p-type doped regions, n-type doped regions, or combinations thereof. P-type doped regions (for example, p-type wells) contain p-type dopants such as boron, indium, another p-type dopant, or combinations thereof. N-type doped regions (for example, n-type wells) contain n-type dopants such as phosphorus, arsenic, another n-type dopant, or combinations thereof. In some reactions, the bulk substrate 102 exhibits doped regions formed with a combination of p-type and n-type dopants. The various doped regions can be formed directly on and / or within the bulk substrate 102 by providing, for example, a p-well structure, an n-well structure, a dual-well structure, a raised structure, or combinations thereof.An ion implantation process, a diffusion process and / or another suitable doping process can be carried out to form the various doped regions.

[0017] A structuring layer 104 is formed over the bulk substrate 102, in particular over an upper surface 105 of the bulk substrate 102. The structuring layer 104 has a material that differs from a material of the bulk substrate 102 in order to achieve etch selectivity during subsequent etching processes. In the illustrated embodiment, the structuring layer 104 has a multilayer structure. The structuring layer 104 has, for example, a mask barrier layer 106 arranged over an upper surface 105 of the bulk substrate 102, and a mask layer 108 arranged over the mask barrier layer 106.The mask barrier layer 106 comprises a material with high etch resistance that achieves the desired etch selectivity (for example, between the mask barrier layer 106 and the mask layer 108), such as a material containing titanium and nitrogen (for example, titanium nitride), and the mask layer 108 comprises a material that achieves the desired etch selectivity (for example, between the mask layer 108 and the bulk substrate 102), such as a dielectric material containing silicon and nitrogen (for example, silicon nitride). In some reactions, the structuring layer 104 comprises silicon, amorphous silicon, oxygen, nitrogen, carbon, another suitable structuring layer component, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbide).In some implementations, the structuring layer 104 includes a resist layer (also called a photoresist layer) containing a suitable resist material. The structuring layer 104 is formed by any suitable deposition process. For example, the mask barrier layer 106 and / or the mask layer 108 are formed over bulk substrate 102 by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma-compressed ionic vapour (HDPCVD), metal-organic CVD (MOCVD), remote plasma-compressed ionic vapour (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), electroplating, other suitable processes, or combinations thereof.

[0018] The structuring layer 104 has an opening 110 that defines an isolation region and a channel region of the IC device 100 (generally called an isolation region structure), wherein the isolation region structure further defines a desired gate length (L G ) of a transistor of the IC device 100 is defined. In the illustrated embodiment, the opening 110 divides the structuring layer 104 into a section 104A and a section 104B. The section 104A defines an inner perimeter of the isolation area and the channel area of ​​the IC device 100. A width W1 of the section 104A extends along the gate longitudinal direction of the IC device 100, where the width W1 is essentially equal to the desired gate length of the transistor (in other words, W1 ≈ L GSection 104B defines an outer perimeter of the isolation area, with sections of the aperture 110, defined along the gate longitudinal direction between section 104A and section 104B, having a width W2. The aperture 110 is then formed by performing a lithography process to create a structured resist layer over the mask layer 108 and an etching process to transfer a structure defined in the structured resist layer to the mask layer 108. The lithography process may include creating a resist layer on the mask layer 108 (for example, by spin coating), performing a pre-exposure bake-off process, performing an exposure process using a mask, performing a post-exposure bake-off process, and performing a development process.During the exposure process, the resist layer is exposed to radiant energy (such as ultraviolet (UV), deep UV (DUV), or extreme UV (EUV) light). The mask blocks, transmits, and / or reflects radiation to the resist layer depending on the mask's structure and / or type (e.g., binary, phase-change, or EUV mask), projecting an image onto the resist layer that corresponds to the mask's structure. Because the resist layer is sensitive to radiant energy, exposed portions of the resist layer undergo chemical changes. These exposed (or unexposed) portions are then resolved during the development process, depending on the characteristics of the resist layer and the developer solution used. After development, the structured resist layer exhibits a resist structure that corresponds to the mask.The etching process uses the structured resist layer as an etching mask to remove sections of mask layer 108 and / or mask barrier layer 106. The etching processes can be dry etching, wet etching, other suitable etching processes, or combinations thereof. The structured resist layer is then removed from mask layer 108, for example, by a resist stripping process. In some reactions, the structured resist layer is used as an etching mask to remove sections of mask layer 108 and mask barrier layer 106. In other reactions, the structured resist layer is used as an etching mask to remove sections of mask layer 108, and then mask layer 108 is used as an etching mask to remove sections of mask barrier layer 106 (in some reactions, after the removal of the structured resist layer).Alternatively, the exposure process can be implemented or replaced by other methods that employ maskless lithography, electron beam lithography, ion beam lithography and / or nanoimprint technology.

[0019] A two-step etching process is then performed using the structuring layer 104 as a mask to form an isolation trench that defines a channel area of ​​the bulk substrate 102. With reference to Fig. 3A and Fig. In step 3B, a first etching process removes sections of bulk substrate 102 exposed through openings 110, defining an isolation trench 112 with a depth D1 in the bulk substrate 102. The isolation trench 112 defines a channel region 114 of the bulk substrate 102. In some implementations, the depth D1 is approximately 50 nm to approximately 200 nm. The first etching process is configured to etch essentially in one direction (for example, the vertical direction) to achieve essentially vertical sidewalls for the isolation trench 112. A width W3 of the channel region 114 is therefore essentially equal to the width W1 of section 104A of the patterning layer 104 and thus essentially equal to the desired gate length of the transistor of the IC device 100 (in other words, W3 ≈ W1 ≈ L). GIn some implementations, the first etching process is an anisotropic etching process. In the illustrated embodiment, the channel area 114 is defined between sections of the isolation area 112 corresponding to sections of the opening 110 arranged between section 104A and section 104B along the gate longitudinal direction. For ease of discussion, these sections of the isolation channel 112 may herein be referred to as a first isolation channel and a second isolation channel. A width W4 of the sections of the isolation channel 112 along the gate longitudinal direction (here the first isolation channel and the second isolation channel) is essentially equal to the width W2 of the sections of the opening 110 that are equal along the gate longitudinal direction between section 104A and section 104B (in other words, W4 ≈ W2).In some implementations, the first etching process is a dry etching process, a wet etching process, another suitable etching process, or combinations thereof.

[0020] With reference to Fig. 4A and Fig. 4B A second etching process removes sections of the bulk substrate 102 exposed through the openings 110 to widen the isolation trench 112, thereby extending the channel area 114 of the bulk substrate 102. The second etching process is configured to etch in more than one direction (for example, the vertical and horizontal directions) to achieve a width of the isolation trench 112 that increases with the depth of the isolation trench 112. The width of the isolation trench 112 therefore increases in one direction towards the bottom surface of the isolation trench 112. The second etching process may involve dry etching, wet etching, or a combination thereof. In some implementations, the first etching process is an isotropic etching process.After the second etching process, the isolation trench 112 has an isolation trench section 112A having a depth D2, which defines the channel section 114A, and an isolation trench section 112B having a depth D3, which defines the channel section 114B. In the illustrated embodiment, the depth D3 is greater than the depth D2, although the present disclosure considers various configurations of depth D2 and depth D3. In some implementations, the depth D2 is essentially equal to the depth D1 (in other words, D2 ≈ D1). In some implementations, the depth D2 is about 50 nm to about 200 nm, and the depth D3 is about 50 nm to about 200 nm. In some implementations, the total depth of the isolation trench 112 is essentially equal to a desired thickness (t. si ) of canal area 114 (in other words t si = D2 + D3 = Total depth of the isolation trench 112).

[0021] Isolation trench section 112A has essentially vertical side walls, and isolation trench section 112B has essentially negatively sloping side walls. In other words, the side walls of the isolation trench section 112A form an angle that is substantially equal to about 90° (a right angle) with respect to the upper surface 105 of the bulk substrate 102, and the side walls of the isolation trench section 112B form an angle that is greater than about 90° (an obtuse angle) with respect to the upper surface 105 of the bulk substrate 102. This results in the isolation trench section 112A having a width W5 that is substantially the same as the depth D2 increases (which, in the illustrated embodiment, is substantially equal to the width W4 (in other words, W5 ≈ W4 ≈ W2)), and the isolation trench section 112B having a width W6 that increases with the depth D3.The isolation trench section 112B therefore has a tapered width, wherein the width of an upper section of the isolation trench section 112B (near the isolation trench section 112A) is smaller than the width of a bottom section of the isolation trench section 112B. A shape of the channel area 114 is consequently defined by a shape of the isolation trench 112 such that the width of an upper surface of the channel area 114 (here, an upper surface of the channel area 114A) is greater than the width of a bottom surface of the channel area 114 (here, a bottom surface of the channel area 114B). In the illustrated embodiment, a width of the channel area 114A (here, L.) remains G ) essentially along the strength t si of channel section 114, while channel section 114B has a tapered width along the thickness t siof channel section 114. A width W7 of channel section 114B decreases, while a thickness t si increases.

[0022] With reference to Fig. 5A and Fig. In step 5B, a process is carried out to increase the resistance of a section of the bulk substrate 102 located beneath the isolation trench 112 and the channel area 114. For example, an implantation process is performed to form a high-resistance layer 120 of the bulk substrate 102 located beneath the isolation trench 112 and the channel area 114, such that the bottom surface of the isolation trench 112 and the bottom surface of the channel area 114 are defined by the high-resistance layer 120, which has a thickness t1. In some transformations, the thickness t1 is approximately 20 nm to approximately 100 nm. The ohmic resistance of the high-resistance layer 120 is greater than the ohmic resistance of the bulk substrate 102.In some reactions, the bulk substrate 102 is a low-resistance substrate, exhibiting, for example, an ohmic resistance of approximately several ohm-cm (Ω-cm) to approximately several hundred ohm-cm, while the high-resistance layer 120 exhibits an ohmic resistance of approximately several hundred ohm-cm to approximately several thousand ohm-cm. In some reactions, the ohmic resistance of the bulk substrate 102 is less than or equal to approximately 750 Ω-cm, and the ohmic resistance of the high-resistance layer 120 is greater than approximately 750 Ω-cm. In some implementations, the implantation process is performed at a tilt angle to ensure that the portion of the bulk substrate 102 lying below the channel area 114 (which is covered by the section 104A of the structuring layer 104) is modified in a way that increases the ohmic resistance of the high-resistance layer 120 with respect to the bulk substrate 102.In some implementations, the tilt angle is configured to ensure that the high-resistance layer 120 extends continuously between exposed sections (in the opening 110) and unexposed sections of the bulk substrate 102 (which are covered by section 104A and section 104B of the structuring layer 104).

[0023] In some transformations, the implantation process bombards the bulk substrate 102 with ions that can modify its structure, such as argon (Ar) ions, xenon (Xe) ions, other suitable ions, or combinations thereof. For example, if the bulk substrate 102 is a material with an ordered atomic structure (often called a crystalline structure), the implantation process can use xenon ions to modify the atomic structure of the bulk substrate 102 such that the high-resistance layer 120 is a section of the bulk substrate 120 that has a non-crystalline structure (in other words, a material with a disordered atomic structure). In the illustrated embodiment, where the bulk substrate 102 has silicon in a crystalline structure, the high-resistance layer 120 has silicon in a non-crystalline structure, such as amorphous silicon.In such reactions, the high-resistance layer 120 can be called an amorphous silicon layer. In some reactions, the implantation process introduces dopants into the bulk substrate 102 to increase the resistance of the high-resistance layer 120 with respect to the bulk substrate 102. In such reactions, the high-resistance layer 120 contains n-type dopants (for example, arsenic, phosphorus, another n-type dopant, or combinations thereof), p-type dopants (for example, boron, germanium, indium, another p-type dopant, or combinations thereof), or combinations thereof. In reactions where the bulk substrate 102 contains silicon, the high-resistance layer 120 contains doped silicon.It should be noted that in reactions where the bulk substrate 102 contains a dopant, the dopant concentration of the high-resistance layer 120 is greater than the dopant concentration of the bulk substrate 102. In some reactions, the implantation process involves bombarding the bulk substrate 102 with ions to modify its atomic structure and introduce dopants into the bulk substrate 102. In some reactions, any other suitable process can be carried out to increase the resistance of the section of the bulk substrate 102 located below the isolation trench 112 and the channel area 114, thereby forming the high-resistance layer 120.

[0024] With reference to Fig. 6A and Fig. In step 6B, an insulation feature 130, having a thickness t2, is formed on the high-resistance layer 120 by filling the insulation trench section 112B with an insulating material. The insulation trench 112 is therefore partially filled by forming the insulation feature 130. The thickness t2 is essentially equal to the depth D3 of the insulation trench section 112B (in other words, t2 ≈ D3). In some transformations, the thickness t2 is approximately 50 nm to approximately 200 nm. The insulation feature 130 has a tapered width, with the width of an upper section of the insulation feature 130 being smaller than the width of a bottom section of the insulation feature 130. For example, the insulation feature 130 has a width W8 that increases as its thickness t2 increases. In the illustrated embodiment, the width W8 is essentially equal to the width W6 of the isolation trench section 112B (in other words, W8 ≈ W6).The insulating material comprises silicon, oxygen, nitrogen, carbon, other suitable insulating components, or combinations thereof (for example, silicon oxide, silicon nitride, and / or silicon oxynitride). The insulating feature 130 can be formed by depositing an insulating material that completely or partially fills the insulating trench 112 (in some reactions, the insulating material is also deposited above the structuring layer 104), and etching back the insulating material such that the insulating material remains only in the insulating trench section 112B.For example, a high-density plasma chemical vapor deposition (HDP-CVD) process completely or partially fills isolation trench 112 with an oxide material, and an HDP oxide re-etching process (for example, a wet etching process) removes a portion of the oxide material (for example, from isolation trench section 112A) such that the oxide material fills isolation trench section 112B. In such reactions, the isolation feature can be called an HDP-CVD oxide layer. In some reactions, a minimum amount of isolation material remains in isolation trench section 112A, so that isolation feature 130 partially fills isolation trench section 112A. In some reactions, the isolation material is deposited by CVD, PVD, ALD, a spin-on-glass process, another suitable process, or combinations thereof.In some implementations, the insulating material is deposited by a flowable CVD (FCVD) process, which includes, for example, the deposition of a flowable material (such as a liquid compound) over the insulation trench 112 and the conversion of the flowable material into a solid material by a suitable technique, such as thermal annealing and / or ultraviolet radiation treatment. In some implementations, the insulating feature 130 has a multilayer structure, such as a dielectric bulk layer arranged over a dielectric liner layer, wherein the dielectric bulk layer and the dielectric liner layer comprise materials that depend on design requirements (for example, a dielectric bulk layer comprising silicon nitride arranged over a dielectric liner layer comprising thermal oxide).In some implementations, the insulation feature 130 has a dielectric layer arranged over a doped liner layer (including, for example, boron silicon glass (Boron Silicon Glass - BSG) or phosphorus glass (Phosphosilicate Glass - PSG)).

[0025] Epitaxial source features and epitaxial drain features (generally referred to as an epitaxial source / drain feature 140) are then formed on the isolation feature 130 by filling any remaining section of the isolation trench 112. With reference to Fig. 7A and Fig. 7B Semiconductor material is epitaxially grown on the isolation feature 130, forming the epitaxial source / drain feature 140. In the illustrated embodiment, the epitaxial source / drain feature 140 has an epitaxial seed layer 142 and an epitaxial layer 144, which combine to completely fill the isolation trench section 112A and the opening 110 in the structuring layer 104. The epitaxial seed layer 142 comprises any material that can facilitate the growth of the epitaxial layer 144. In some implementations, the epitaxial layer 144 partially fills the opening 110. An epitaxial process for forming the epitaxial seed layer 142 and / or the epitaxial layer 144 can employ CVD deposition techniques (for example, gas-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD and / or PECVD), molecular beam epitaxy, other suitable SEG processes or combinations thereof.The epitaxial process can use gaseous and / or liquid precursors. For example, in the illustrated embodiment, where the epitaxial seed layer 142 and the epitaxial bulk layer 144 are silicon-containing epitaxial layers, the epitaxial process can use a silicon-containing precursor gas, such as silane (SiH4), disilane (Si2H6), trisilane (Si3H8), dichlorosilane (DCS) (Si2H2Cl2), other suitable silicon-containing precursor gases, or combinations thereof. The epitaxial process can further utilize a carrier gas, including helium, nitrogen, hydrogen, argon, other suitable carrier gases, or combinations thereof.In some embodiments where the epitaxial seed layer 142 and / or the epitaxial bulk layer 144 further comprise germanium, the epitaxial process can utilize a germanium-containing precursor gas, such as germanium (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), germanium dichloride (GeCl2), another suitable germanium-containing precursor gas, or combinations thereof. In some reactions, the epitaxial source-drain feature 140 is doped with n-type and / or p-type dopants. The epitaxial seed layer 142 and / or the epitaxial layer 144 are, for example, silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers doped with phosphorus, arsenic, another n-type dopant or combinations thereof (forming, for example, an epitaxial Si:P source / drain feature or an epitaxial Si:C:P source / drain feature).In another example, the epitaxial seed layer 142 and / or the epitaxial layer 144 are silicon- and germanium-containing epitaxial layers doped with boron, carbon, another p-type dopant, or combinations thereof (forming, for example, an epitaxial Si:Ge:B source / drain feature). In some reactions, the epitaxial source / drain feature 140 incorporates materials and / or dopants that achieve desired tensile and / or compressive strength in the channel region 114 of the bulk substrate 102. In some reactions, the epitaxial source / drain feature 140 is doped during deposition by adding impurities to a source material of the epitaxial process. In some reactions, the epitaxial source / drain feature 140 is doped by an ion implantation process performed after a deposition process.

[0026] With reference to Fig. 8A and Fig. In step 8B, a process is performed to reduce the thickness of the epitaxial source / drain feature 140 such that the epitaxial source / drain feature 140 has a thickness t3. The thickness t3 is essentially equal to the depth D2 of the isolation trench section 112A (in other words, t3 ≈ D2). The epitaxial source / drain feature 140 therefore fills the isolation trench section 112A. In some reactions, the thickness t3 is approximately 50 nm to approximately 200 nm. In some reactions, a back-etching process, such as a wet etching process, is performed until the upper surface 105 of the bulk substrate 102 is reached. In some reactions, a CMP process is performed until the upper surface 105 of the bulk substrate 102 is reached. In some reactions, both a back-etching process and a CMP process are performed. In some implementations, the re-etching process uses a dry etching process.In the illustrated embodiment, the IC device 100 has a substantially planar surface after the thickness of the epitaxial source / drain feature 140 has been reduced such that the upper surface 105 of the bulk substrate 102 is substantially planar with the upper surface of the epitaxial source / drain feature 140. The present disclosure considers alternative implementations in which a portion of the epitaxial source / drain feature 140 remains extending over the upper surface 105 of the bulk substrate 102, so that the epitaxial source / drain feature 140 is a raised epitaxial source / drain feature.

[0027] With reference to Fig. 9A and Fig. In 9B, a structuring layer 160 is formed over the IC device 100, specifically over the bulk substrate 102 and the epitaxial source-drain feature 140. The structuring layer 160 has a material different from that of the epitaxial source-drain feature 140 to achieve etch selectivity during subsequent etching processes. In the illustrated embodiment, the structuring layer 160 has a multilayer structure. For example, the structuring layer 160 has a mask barrier layer 162 arranged over an upper surface 105 of the bulk substrate 102 and an upper surface of the epitaxial source-drain feature 140, and a mask layer 164 arranged over the mask barrier layer 162.The mask barrier layer 162 comprises a material with high etch resistance that achieves the desired etch selectivity (for example, between the mask barrier layer 162 and the mask layer 164), such as a material containing titanium and nitrogen (for example, titanium nitride), and the mask layer 164 comprises a material that achieves the desired etch selectivity (for example, between the mask layer 164 and the epitaxial source-drain feature 140), such as a dielectric material containing silicon and nitrogen (for example, silicon nitride). In some reactions, the structuring layer 160 comprises silicon, amorphous silicon, oxygen, nitrogen, carbon, another suitable structuring layer component, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbide).In some implementations, the structuring layer 160 includes a resist layer (also called a photoresist layer) containing a suitable resist material. The structuring layer 160 is formed by any suitable deposition process. The mask barrier layer 162 and the mask layer 164, for example, are formed by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, another suitable process, or combinations thereof.

[0028] The structuring layer 160 has an opening 170 that defines another isolation region of the IC device 100 (generally called an isolation region structure), wherein the isolation region structure further defines a device region, such as an active region of the transistor of the IC device 100. In the illustrated embodiment, the opening 170 divides the structuring layer 104 into a section 160A and a section 160B. Section 160A defines an inner perimeter of the isolation region and the channel region of the transistor. A width W9 of section 160A extends along the gate longitudinal direction of the IC device 100, wherein the width W9 is essentially equal to a desired length of an active region of the transistor.Section 160B defines an outer perimeter of the isolation area, with sections of the opening 170, defined along the gate longitudinal direction between section 160A and section 160B, having a width W10. In the illustrated embodiment, the width W10 is smaller than the width W2, which corresponds to a width of the opening 110 defined along the gate longitudinal direction between section 104A and section 104B of the structuring layer 104. The opening 170 is formed by performing a lithography process to create a structured resist layer (not shown) over the mask layer 164 and by performing an etching process to transfer a structure defined in the structured resist layer to the mask layer 164.The lithography process can involve forming a resist layer on the mask layer 164 (for example, by spin coating), performing a bake-out process after exposure, performing an exposure process using a mask, performing a bake-out process after exposure, and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (such as UV light, DUV light, or EUV light), with the mask blocking, transmitting, and / or reflecting radiation to the photoresist layer depending on the mask structure and / or the mask type (for example, binary mask, phase-change mask, or EUV mask), so that an image corresponding to the mask structure is projected onto the resist layer.Because the resist layer is sensitive to radiation energy, exposed portions of the resist layer undergo chemical changes, and exposed (or unexposed) portions of the resist layer are dissolved during the development process depending on characteristics of the resist layer and characteristics of a developing solution used in the development process. After development, the structured resist layer exhibits a resist structure corresponding to the mask. The etching process uses the structured resist layer as an etching mask to remove portions of the mask layer 164 and / or mask barrier layer 162. The etching processes may include dry etching, wet etching, other suitable etching processes, or combinations thereof. The structured resist layer is then removed from the mask layer 164, for example, by a resist stripping process.In some implementations, the structured resist layer is used as an etching mask to remove sections of mask layer 164 and mask barrier layer 162. In other implementations, the structured resist layer is used as an etching mask to remove sections of mask layer 164, and then mask layer 164 is used as an etching mask to remove sections of mask barrier layer 162 (in some implementations, after removal of the structured resist layer). Alternatively, the exposure process can be implemented or replaced by other methods employing maskless lithography, electron beam lithography, ion beam lithography, and / or nanoimprint technology.

[0029] With reference to Fig. 10A and Fig. In step 10B, an etching process removes sections of the epitaxial source-drain feature 140 and the isolation feature 130 exposed through the opening 170, forming an isolation trench 172 that defines an active region of the IC device 100, such as the active region of the transistor of the IC device 100. The isolation trench 172 has a depth D4 that is greater than or equal to the thickness t3 (in other words, D4 ≥ t3). In some implementations, the depth D4 is approximately 50 nm to approximately 400 nm. The etching process is configured to etch in more than one direction (for example, in the vertical and horizontal directions) to achieve an isolation trench 172 width that decreases with increasing depth of the isolation trench 172. The width of the isolation trench 172 therefore decreases in one direction towards the ground surface of the isolation trench 172.For example, isolation trench 122 has positively sloping sidewalls (here, sidewalls sloping in the opposite direction to isolation trench 112). In other words, the sidewalls of isolation trench 172 form an angle less than approximately 90° (an acute angle) with respect to the upper surface 105 of the bulk substrate 102. This results in isolation trench 172 having a tapered width, such as a width W11 that decreases as the depth D4 increases (instead of a width that increases with depth, as in isolation trench 112). Therefore, the width of an upper section of isolation trench 172 is greater than the width of a bottom section of isolation trench 172. The etching process includes dry etching, wet etching, or combinations thereof. In some reactions, the initial etching process is an isotropic etching process.

[0030] The isolation trench 172 extends through the entire epitaxial source-drain feature 140, thereby forming a separate epitaxial source-drain feature of the IC device 100, such as epitaxial source-drain feature 1404, epitaxial source-drain feature 140B, epitaxial source-drain feature 140C, and epitaxial source-drain feature 140D. The isolation trench 172 further extends through at least one section of the isolation element 130 such that the epitaxial source-drain features 140A to 140D are sufficiently isolated from one another. In the illustrated embodiment, for example, the isolation trench 172 extends through the entire isolation feature 130.In such implementations, the isolation trench 172 can divide the isolation feature into separate isolation features that isolate respective components of the IC component 100, such as an isolation feature 130A that surrounds and isolates the channel region 114 of the transistor of the IC component 100, an isolation feature 130B that surrounds and isolates another channel region of another component of the IC component 100, and an isolation feature 130C that surrounds and isolates yet another component of the IC component 100. In some implementations, the isolation trench 172 further extends through at least one section of the high-resistance layer 120, where the etching process removes sections of the high-resistance layer 120 exposed through the opening 170.In the illustrated embodiment, for example, the isolation trench 172 extends through the entire high-resistance layer 120, although the present disclosure considers embodiments in which the isolation trench extends only through a section of the high-resistance layer 120 or to an upper surface of the high-resistance layer 120. In some implementations, various selective etching processes are carried out to separately etch the epitaxial source-drain feature 140, the isolation feature 130, and / or the high-resistance layer 120.

[0031] With reference to Fig. 11A and Fig. In 11B, a deposition process is carried out to fill the insulation trench 172 with an insulating material 180. In the illustrated embodiment, the insulating material 180 also fills the opening 170 of the structuring layer 160, and the insulating material 180 is positioned above the structuring layer 160. The insulating material 180 comprises silicon, oxygen, nitrogen, carbon, other suitable insulating components, or combinations thereof (for example, silicon oxide, silicon nitride, and / or silicon oxynitride). A high-density plasma chemical vapor deposition (HDP-CVD) process fills the insulation trench 172 (and, in some reactions, the opening 170) with an oxide material. In some implementations, the insulating material 180 is deposited by CVD, PVD, ALD, a spin-on-glass process, another suitable process, or combinations thereof.In some implementations, the insulating material 180 is deposited by an FCVD process. In some implementations, the insulating material 180 has a multilayer structure, such as a dielectric bulk layer arranged over a dielectric liner layer, where the dielectric bulk layer and the dielectric liner layer comprise materials that depend on design requirements (for example, a dielectric bulk layer comprising silicon nitride arranged over a dielectric liner layer comprising thermal oxide). In some implementations, the insulating material 180 has a dielectric layer arranged over a doped liner layer (including, for example, BSG or PSG). In some implementations, the insulating material 180 and the insulating material of the insulating feature 130 have the same materials, layers, thicknesses, and / or structures.In some implementations, the insulation material 180 and the insulation material of insulation feature 130 have different materials, layers, thicknesses, and / or structures. See below for further details. Fig. 12A and Fig. 12B A CMP process or other suitable planarization process is performed to remove sections of insulation material 180 that are arranged above the structuring layer 160, thereby planarizing a surface of the insulation material 180. For example, an upper surface of the insulation material 180 is essentially planar to an upper surface of the structuring layer 160 after the planarization process.

[0032] With reference to Fig. 13A and Fig. In step 13B, a process is carried out to remove the structuring layer 160 and excess insulating material 180 (for example, insulating material 180 that fills the openings 170 and / or is located above the top surface 105 of the bulk substrate 102) such that an insulating feature 182 defines an active region 184 (also called an OD region) of the IC device 100. The insulating feature 182 surrounds the active region 184, which in the illustrated embodiment comprises the channel region 114 of the bulk substrate 102 located between the epitaxial source-drain feature 140B and the epitaxial source-drain feature 140C. In some implementations, the active region 184 is configured for the transistor of the IC device 100. The insulating feature 182 has a thickness t4, which is essentially equal to the depth D4 of isolation trench 172 (in other words, t4 ≈ D4). For some transformations, the thickness t4 ranges from approximately 50 nm to approximately 400 nm.The insulation feature 182 has a tapered width, wherein the width of an upper section of the insulation feature 182 is greater than the width of a lower section of the insulation feature 182. For example, the insulation feature 182 has positively sloping side walls such that a width W12 of the insulation feature 182 decreases while a thickness t4 increases, wherein, in the illustrated embodiment, the width W12 is essentially equal to the width W11 of the insulation trench 172 (in other words, W12 ≈ W11). The active area 184 of the transistor of the IC device 100 consequently has a tapered width, wherein the active area 184 has negatively sloping side walls such that the width of the active area 184 increases while its depth increases.To support the illustrated embodiment, the width W12 of the isolation feature 182 is smaller than the width W8 of the isolation feature 130 (in other words, W12 < W8). In some implementations, the width W12 is approximately 40 nm to approximately 300 nm. In some implementations, the width W12 is greater than approximately 300 nm, depending on the spacing between adjacent components, such as a component spacing. In some implementations, dry etching processes, wet etching processes, or combinations thereof are used to remove the structuring layer 160 and / or isolation material 180. In some implementations, various selective etching processes are performed to separately etch the isolation material 180, the mask layer 164, and / or the mask barrier layer 162.In some implementations, a planarization process, such as a CMP process, is performed to planarize a surface of the IC device 100, so that an upper surface of the insulating feature 182 is essentially planar with the upper surface 105 of the bulk substrate 102. The insulating material 180, the mask layer 164, and / or the mask barrier layer 162 can be removed during the planarization process.

[0033] The isolation feature 182, the isolation feature 130A, and the high-resistance layer 120 completely isolate the active area 184 and / or the channel area 114 such that the active area 184 and / or channel area 114 are not connected to other active areas and / or other channel areas of the IC device 100. Such a configuration establishes isolation and crosstalk rejection characteristics equivalent to those achieved by SOI substrates, so that a transistor manufactured in the active area 184 exhibits improved performance.

[0034] With reference to Fig. 14A and Fig. In 14B, a gate structure 190 is formed over the channel region 114 of the bulk substrate 102 (defined by the insulation feature 130A) such that the gate structure 190 is inserted between epitaxial source-drain features 140. During operation of the IC device 100, current can flow in a channel region 114 between epitaxial source-drain features 140B and 140C. The gate structure 190 has a gate stack configured to provide desired functionality according to the design requirements of the IC device 100. In the illustrated embodiment, a gate stack of the gate structure 190 includes a gate dielectric 192 and a gate electrode 194. The gate dielectric 192 is arranged on the channel area 114 of the bulk substrate 102, and the gate electrode 194 is arranged on the gate dielectric 192.In some implementations, the gate dielectric 192 is shaped to conform to the sidewall and bottom surfaces of the IC device 100, which forms the gate stack of the gate structure 190, such that the gate dielectric 192 is generally U-shaped and has a substantially uniform thickness. The gate dielectric 192 comprises a dielectric material such as silicon dioxide, a high-κ dielectric material, other suitable dielectric material, or combinations thereof. The high-κ dielectric material generally refers to dielectric materials that have a high dielectric constant, such as greater than the dielectric constant of silicon dioxide (κ ≈ 3.9). Exemplary high-κ dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable components, or combinations thereof.In some reactions, the gate dielectric 132 can have a multilayer structure, such as an interface layer comprising, for example, silicon oxide, and a high-κ dielectric layer comprising, for example, HfO₂, HfSiO₂, HfSiON₂, HfTaO, HfTiO₂, HfZrO₂, ZrO₂, Al₂O₃, HfO₂-Al₂O₃, TiO₂, Ta₂O₅, La₂O₃, Y₂O₃, other high-κ dielectric materials, or combinations thereof. The gate electrode 194 comprises an electrically conductive material. In some reactions, the gate electrode 194 has multiple layers, such as one or more cover layers, working exit layers, adhesive / barrier layers, and / or metal filler (or bulk) layers. A cover layer can have a material that prevents or eliminates the fusion and / or reaction of components between the gate dielectric 192 and other layers of the gate structure 190.In some reactions, the coating layer contains a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or combinations thereof.

[0035] An exit work layer incorporates a conductive material tuned to exhibit a desired exit work (such as n-type or p-type exit work), such as n-type exit work materials and / or p-type exit work materials. p-type exit work materials contain TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type exit work materials, or combinations thereof. n-type exit work materials contain Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type exit work materials, or combinations thereof. An adhesive / barrier layer may comprise a material that promotes adhesion between adjacent layers, such as between the exit working layer and the metal filler layer 46, and / or a material that blocks and / or reduces diffusion between gate layers, such as between the exit working layer and the metal filler layer.The adhesive / barrier layer may contain, for example, metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metal, or combinations thereof), metal oxides, metal nitrides (e.g., TiN), or combinations thereof. A metal filler layer may contain a suitable conductive material, such as Al, W, and / or Cu.

[0036] The gate structure 190 further comprises gate spacers 196, which are arranged adjacent to (for example, along side walls of) the gate stack. The gate spacers 196 are formed by any suitable process and comprise a dielectric material. The dielectric material can comprise silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof. For example, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, can be deposited over the bulk substrate 102 and the gate stack (here, the gate dielectric 192 and the gate electrode 194) and subsequently anisotropically etched to form the gate spacers 196. In some transformations, the gate spacers 196 have a multilayer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide.In some implementations, the gate spacers 196 feature more than one set of gate spacers, such as gasket spacers, offset spacers, sacrificial spacers, dummy spacers, and / or principal spacers formed adjacent to the gate stack. In such implementations, the various sets of spacers may consist of materials with different etch rates. For example, a first dielectric layer containing silicon and oxygen may be deposited and then anisotropically etched to form a first set of spacers adjacent to the gate stack, and a second dielectric layer containing silicon and nitrogen may be deposited and then anisotropically etched to form a second set of gate spacers adjacent to the first set.

[0037] The implantation, diffusion, and / or annealing processes are performed to form a source feature and drain features (generally called source-drain features 198) in epitaxial source-drain features 140A to 140D before and / or after the formation of the gate spacers 196. The source-drain features 198 exhibit lightly doped source-drain (LDD) features and / or heavily doped source-drain (HDD) features. In some implementations, the source-drain features 198 are formed by implanting and / or diffusing n-type dopants, p-type dopants, or combinations thereof into the epitaxial source-drain features 140A to 140D, depending on a desired transistor configuration (for example, PMOS or NMOS).An annealing process, such as rapid thermal annealing (RTA) and / or laser annealing, can be performed to activate dopants of the source-drain features 198 and / or epitaxial source-drain features 140A to 140D.

[0038] A dielectric layer (ILD) 200 is also formed over the bulk substrate 102. The ILD 200 comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, a low-θ dielectric material, another suitable dielectric material, or combinations thereof. Examples of low-θ dielectric materials include FSG, carbon-doped silicon oxide, Black Diamond® (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-θ dielectric materials, or combinations thereof. In some reactions, the ILD 200 exhibits a multilayer structure with several dielectric materials. In some implementations, a contact etch stop layer (CESL) is arranged between the ILD layer 200 and the bulk substrate 102 and / or the gate structure 190.The CESL comprises a different material than the ILD layer 200, such as a dielectric material that differs from the dielectric material of the ILD layer 200. In the illustrated embodiment, where the ILD layer 200 comprises a low-κ dielectric material, the CESL comprises silicon and nitrogen (for example, silicon nitride or silicon oxynitride). The ILD layer 200 and / or the CESL is formed, for example, by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, other suitable processes, or combinations thereof). In some implementations, the ILD layer 200 and / or the CESL are formed by an FCVD process. Following the deposition of the ILD layer 200 and / or the CESL, a CMP process and / or another planarization process is carried out such that an upper section of the gate structure 190 is reached (exposed).In some implementations, an upper surface of the gate structure 190 is essentially planar with an upper surface of the ILD layer 200.

[0039] The gate stack of the gate structure 190 is fabricated according to a gate-last process, a gate-first process, or a hybrid gate-last / gate-first process. In gate-last process implementations, the gate structure 190 has a dummy gate stack, which is subsequently replaced with metal gate stacks. The dummy gate stack has, for example, an interface layer (which may contain silicon oxide) and a dummy gate electrode layer (which may contain polysilicon). In such implementations, the dummy gate electrode layer is removed to form an opening (trench) in which the gate dielectric 192 and / or the gate electrode 194 are subsequently formed. In some implementations, the dummy gate stack is formed before the formation of the ILD layer 200, and the dummy gate stack is replaced with a metal gate stack after the formation of the ILD 200.Gate-last and / or gate-first processes can implement deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. The deposition processes include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, coating, or other suitable methods or combinations thereof. The lithography structuring processes include resist coating (e.g., spin-on coating), soft bakeout, mask alignment, exposure, post-exposure bakeout, resist development, rinsing, drying (e.g., hard bakeout), other suitable processes, or combinations thereof. Alternatively, the lithography exposure process is supported, implemented, or replaced by other methods, such as maskless lithography, e-beam writing, or ion beam writing. The etching processes include dry etching, wet etching, other etching processes, or combinations thereof.

[0040] With reference to Fig. 15A and Fig. In 15B, the ILD layer 200 is a section of a multilayer interconnect (MLI) feature 210, which is arranged above the bulk substrate 102, with processing continuing to form various features of the MLI feature 210. The MLI feature 210 electrically couples various devices and / or components of the IC device 100, enabling various devices and / or components to function as specified by the design requirements of the IC device 100. The MLI feature 210 has a combination of dielectric layers and electrically conductive layers (for example, metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features, such as contacts and / or vias, and / or horizontal interconnect features, such as conductive traces.Vertical interconnection features typically connect horizontal interconnection features in different layers (or different levels) of the MLI feature 210. During operation of the IC device 100, the interconnection features are configured to route signals between the components and / or sub-components of the IC device 100 and / or to distribute signals (for example, clock signals, voltage signals, and / or ground signals) to the components and / or sub-components of the IC device 100. It should be noted that, although the MLI feature 210 is depicted with a given number of dielectric and conductive layers, this disclosure considers an MLI feature 210 that has more or fewer dielectric and / or conductive layers.

[0041] An intermetallic dielectric (IMD) layer 212 of MLI feature 210 is formed over the ILD layer 200. The ILD layer 210 is similar to the IMD layer 200. The IMD layer 210, for example, comprises a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, a low-κ dielectric material, another suitable dielectric material, or combinations thereof. Examples of low-κ dielectric materials include FSG, carbon-doped silicon oxide, Black Diamond® (Applied Materials in Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK® (Dow Chemical, Midland, Michigan), polyimide, other low-κ dielectric materials, or combinations thereof. In the illustrated embodiment, the IMD layer 212 comprises a dielectric low-κ material. The IMD layer 212 can have a multilayer structure.The IMD layer 212 can be formed by a deposition process such as CVD, PVD, ALD, FCVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, another suitable deposition process, or a combination thereof. In some implementations, a CESL is placed between the IMD feature 210 and the ILD layer 200.

[0042] Contacts 220 are arranged in one or more dielectric layers of the MLI feature 210 such that the ILD layer 200 and / or the IMD layer 212 form sections of interconnection structures. The contacts 220 couple IC device features electrically and / or physically, such as source-drain regions (for example, epitaxial source-drain features 140A to 140D and / or source-drain feature 198) and / or gate structures (for example, the gate structure 190) to vias and / or conductive traces of the MLI feature 210. The contacts 220 comprise any electrically conductive material, such as Ta, Ti, Al, Cu, Co, W, TiN, TaN, other suitable conductive materials, or combinations thereof. Various conductive materials can be combined to provide the contacts 220 with multiple layers, such as a barrier layer, an adhesive layer, a liner layer, a bulk layer, another suitable layer or combinations thereof.The contacts 220 are formed by structuring the ILD layer 200 and / or the IMD layer 212. Structuring the ILD layer 200 and / or the IMD layer 212 can involve lithography and / or etching processes to create openings (trenches), such as contact openings, in the ILD layer 200 and / or the IMD layer 212. In some implementations, the lithography processes include forming a photoresist layer over the ILD layer 200 and / or the IMD layer 212, exposing the photoresist layer with structured radiation, and developing the exposed photoresist layer, thereby forming a structured photoresist layer that can be used as a masking element for etching one or more openings in the ILD layer 200 and / or the IMD layer 212. The etching processes include dry etching processes, wet etching processes, other etching processes, or combinations thereof.The opening(s) are then filled with one or more conductive materials. The conductive material(s) can be deposited by PVD, CVD, ALD, electroplating, electroless plating, another suitable deposition process, or a combination thereof. Excess conductive material can then be removed by a planarization process, such as a CMP process, thereby planarizing the top surface of the ILD layer 200, the IMD layer 212, and / or the contacts 220. Manufacturing can then proceed with the formation of various vias and / or conductive traces of the MLI feature 210.

[0043] Fig. Figure 16 is a schematic cross-sectional view of an IC device 300, either as a section or in its entirety, according to various aspects of the present disclosure. For clarity and simplification, similar features of the IC device 100 are shown in the Fig. 2A to 15A and the Fig. 2B to 15B and the IC component 300 in Fig. 17 with the same reference numerals. For example, the IC component 300 has the bulk substrate 102, which includes a channel area 114, a high-resistance layer 120 located below the channel area 114 and the insulation feature 130, epitaxial source-drain features 140A to 140D arranged on the insulation feature 130, the insulation feature 182, the active area 184, the gate structure 190 (including, for example, the gate dielectric 192, the gate electrode 194, and the gate spacer 196), and the MLI feature 210 (including, for example, the ILD layer 200, the IMD layer 212, and the contacts 220). The IC 300 component can be contained in a microprocessor, a memory and / or another IC component.In some implementations, the IC 300 component is a section of an IC chip, a SoC, or a section thereof, which incorporates various passive and active microelectronic components such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The various transistors can be planar transistors or multi-gate transistors, such as FinFETs, depending on the design requirements of the IC 300 component. Fig. Reference 16 has been simplified for clarity and to better illustrate the inventive concepts of the present disclosure. Additional features may be added to the IC device 300, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the IC device 300.

[0044] The IC 300 features a bulk substrate configured to exhibit SOI behavior. The IC 300 is similar to the IC 100 in many respects, except that the insulation feature 182 has negatively sloping sidewalls, and the active area 184 has positively sloping sidewalls, such that the width of the insulation feature 182 increases as its thickness t4 increases, and the width of the active area 184 decreases as its thickness t4 decreases. siof the channel area 114 increases. The insulation feature 182 also has an air gap 302. In some implementations, the insulation feature 182 has a high aspect ratio, so that an air gap 302 can be formed during the deposition of the insulating material 180. In the illustrated embodiment, the air gap 302 has a width that increases as the thickness t4 increases. The air gap 302 can also enhance the insulation between adjacent active areas of the IC device 100, thereby increasing crosstalk suppression between the adjacent active areas.

[0045] Fig. Figure 17 is a schematic cross-sectional view of an IC device 400, either as a section or in its entirety, according to various aspects of the present disclosure. For clarity and simplification, similar features of the IC device 100 are shown in the Fig. 2A to 15A and the Fig. 2B to 15B and the IC component 400 in Fig. 17 with the same reference numerals. For example, the IC component 400 has the bulk substrate 102, which includes a channel area 114, a high-resistance layer 120 located below the channel area 114 and the insulation feature 130, epitaxial source-drain features 140A to 140D arranged on the insulation feature 130, the insulation feature 182, the active area 184, the gate structure 190 (including, for example, the gate dielectric 192, the gate electrode 194, and the gate spacer 196), and the MLI feature 210 (including, for example, the ILD layer 200, the IMD layer 212, and the contacts 220). The 400 component can be contained in a microprocessor, a memory and / or another IC component.In some implementations, the IC 400 component is a section of an IC chip, a SoC, or a section thereof, which incorporates various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The various transistors can be planar transistors or multi-gate transistors, such as FinFETs, depending on the design requirements of the integrated circuit 400 component. Fig. Reference 17 has been simplified for clarity and to better illustrate the inventive concepts of the present disclosure. Additional features may be added to the IC device 400, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the IC device 400.

[0046] The IC device 400 has a bulk substrate configured to exhibit SOI behavior. The IC device 400 is similar to the IC device 100 in many respects, except that the isolation feature 182 extends only a portion of the isolation feature 130 instead of the entirety of the isolation feature 130. For example, the isolation feature 182 extends the entirety of the epitaxial source-drain feature 140, which defines the epitaxial source-drain features 140A through 140D, and of an upper surface (or upper portion) of the isolation feature 130. The thickness t4 is therefore greater than or equal to the thickness t3 and less than the sum of the thickness t3 and the thickness t2 (in other words, t2 + t3 > t4 ≥ t3).In such implementations, the isolation feature 182 does not divide the isolation feature 130 into separate isolation features (such as the isolation features 130A to 130C) for adjacent active areas of the IC device 100, so that the isolation feature 130 extends continuously between adjacent active areas. In the illustrated embodiment, the insulation feature 130 lies beneath epitaxial source-drain features of adjacent components of the IC component 100, such as epitaxial source-drain features 140A to 140D, each belonging to three different components of the IC component 100 (for example, a transistor having epitaxial source-drain feature 140A, a transistor having epitaxial source-drain features 140B, 140C, and a transistor having epitaxial source-drain feature 140D).The present disclosure further considers embodiments in which the insulation feature 182 stops at an upper surface of the insulation feature 182 (in other words t4 ≈ t3).

[0047] Fig. Figure 18A is a schematic top view of an IC component 500 as a section or in its entirety, which has an SOI-like structure, according to various aspects of the present disclosure. Fig. Figure 18B shows a schematic cross-sectional view of the IC component 600 as a section or in its entirety, each along line BB. Fig. 18A, according to various aspects of the present disclosure. For clarity and simplification, similar features of the IC device 100 are described in the Fig. 2A to 15A and the Fig. 2B to 15B and the IC component 500 in Fig. 18A and Fig. 18B is identified with the same reference numerals. The IC component 600 is similar to the IC component 100 except that the isolation feature 182 is depicted as separating adjacent component areas of bulk substrate 102, such as the active area 584A and the active area 584B, each configured for a single-finger IC component, such as a transistor 500A and a transistor 500B. For example, the active area 184A and the active area 584B are each defined (surrounded) by the isolation feature 182, such that the active area 584A has a channel area 114A located between epitaxial source-drain features 140A and 140B, and the active area 584B has a channel area 114B located between epitaxial source-drain features 140C and 140D. The isolation feature 182 therefore separates and isolates source-drain areas of adjacent components.To illustrate the example, isolation feature 130A lies beneath the epitaxial source-drain features 140A and 140B of active region 584A, and isolation feature 130B lies beneath the epitaxial source-drain features 140C and 140D of active region 584B. Isolation features 130A and 130B also lie beneath a portion of the upper part of channel region 114A and channel region 114B, respectively. The high-resistance layer 120 is located beneath channel regions 114A and 114B and isolation features 130A and 130B. Such a configuration of the IC component 500 completely isolates the channel areas 114A, 114B and source-drain areas from the IC component 600 (which here has the epitaxial source-drain features 140A to 140D) and further isolates the active area 584A completely from the active area 584B, so that the adjacent active areas 584A, 584B of the IC component 600 are not connected.The present disclosure considers implementations in which the isolation feature 182 does not extend through the high-resistance layer 120 and / or the isolation features 130. The component 500 may be contained within a microprocessor, a memory, and / or another IC component. In some implementations, the IC component 500 is a section of an IC chip, a SoC, or a section thereof, comprising various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The various transistors may be planar transistors or multi-gate transistors, such as FinFETs, depending on the design requirements of the integrated circuit component 500. Fig. References 18A to 18B have been simplified for clarity and to better illustrate the inventive concepts of the present disclosure. Additional features may be added to the IC device 500, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the IC device 500.

[0048] Fig. Figure 19A is a schematic top view of an IC component 600 as a section or in its entirety, which has an SOI-like structure, according to various aspects of the present disclosure. Fig. Figure 19B shows schematic cross-sectional views of the IC component 600, either as a section or in its entirety, along line BB. Fig. 19A, according to various aspects of the present disclosure. For clarity and simplification, similar features of the IC device 100 are described in the Fig. 2A to 15A and the Fig. 2B to 15B and the IC component 600 cm in Fig. 19A and Fig. 19B is identified with the same reference numerals. The IC device 600 is similar to the IC device 100, except that the isolation feature 182 is shown surrounding and defining an active region 684 of the bulk substrate 102, which is configured for a multi-finger IC device, such as a transistor. The active region 684, for example, has several channel regions 114, with each channel region 114 positioned between respective epitaxial source-drain features 140. The isolation feature 182 therefore separates and isolates the multi-finger IC device from other components of the IC device 600. For the sake of illustration, each epitaxial source-drain feature 140 is positioned on top of a respective isolation feature 130. Each isolation feature 130 is further located beneath a portion of the upper section of its respective channel region 114.The high-resistance layer 120 is located beneath the channel regions 114 and the isolation features 130. Such a configuration of the IC device 600 completely isolates the channel regions 114 and source-drain regions of the IC device 600 (here including the epitaxial source-drain features 140) and the active region 684. The present disclosure considers implementations in which the isolation feature 182 does not extend over a depth of the epitaxial source-drain features 140, isolation features 130, and / or the high-resistance layer 120. The IC device 600 can be contained in a microprocessor, a memory, and / or another IC device.In some implementations, the IC 600 component is a section of an IC chip, a SoC, or a section thereof, which incorporates various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The various transistors can be planar transistors or multi-gate transistors, such as FinFETs, depending on the design requirements of the integrated circuit 600 component. Fig. References 19A to 19B have been simplified for clarity and to better illustrate the inventive concepts of the present disclosure. Additional features may be added to the IC device 600, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the IC device 600.

[0049] The present disclosure provides numerous different embodiments. Bulk substrates configured to exhibit semiconductor-on-insulator (SOI) behavior and corresponding fabrication methods are disclosed herein. Various SOI-like structures that can be implemented in bulk substrates to exhibit SOI behavior are disclosed herein. The present disclosure considers the SOI-like structures disclosed herein being implemented in a variety of device types. For example, aspects of the present disclosure can be implemented to form SOI-like structures for isolating planar field-effect transistors (FETs), multi-gate transistors (planar or vertical), such as FinFET devices, gate-all-around (GAA) devices, omega-gate (Ω-gate) devices, or pi-gate (Π-gate) devices, as well as strained semiconductor devices or other devices.The present disclosure takes into account that an average person skilled in the art will recognize other IC devices that can benefit from the SOI-like structures described herein.

[0050] An exemplary integrated circuit component features a bulk substrate exhibiting semiconductor-on-insulator behavior. The integrated circuit component has a channel region defined within the bulk substrate. The channel region comprises a first section positioned above a second section. The first section is located between epitaxial source-drain features embedded in the bulk substrate. The second section is defined by a first isolation feature embedded in the bulk substrate. The epitaxial source-drain features are located on top of the first isolation feature. The thickness of the channel region is approximately equal to the sum of the thickness of the first isolation feature and the thickness of the epitaxial source-drain features. The integrated circuit component further features a second isolation feature embedded in the bulk substrate.The second isolation feature defines an active region comprising the first portion of the channel region, which is located between the epitaxial source-drain features. The resistance of a portion of the bulk substrate located beneath the first isolation feature and the channel region is greater than the resistance of the bulk substrate itself. In some implementations, the integrated circuit further incorporates an air gap located within the second isolation feature, which has a tapered width that increases with depth. In some implementations, the integrated circuit also features a gate structure located above the channel region.

[0051] In some transformations, the channel area has a tapered width that decreases as the thickness of the channel area increases. In some transformations, the width of the first section is essentially the same as the thickness of the channel area increases, and the width of the second section decreases as the thickness of the channel area increases. In some transformations, the thickness of the second isolation feature is greater than or equal to the strength of the epitaxial source-drain features. In some transformations, the thickness of the second isolation feature is less than the thickness of the channel area. In some transformations, the thickness of the second isolation feature is greater than the thickness of the channel area. In some transformations, the thickness of the second isolation feature is greater than the sum of the thickness of the channel area and the thickness of the bulk substrate section below the first isolation feature and the channel area.In some transformations, the bulk substrate consists of a material that has a crystalline structure, and the section of the bulk substrate that lies below the first insulating element and the channel area consists of the material that has a non-crystalline structure.

[0052] An exemplary semiconductor-on-insulator-like structure features a bulk substrate and a dual-insulation structure. The dual-insulation structure has a first insulation trench and a second insulation trench defined within the bulk substrate. The first insulation trench is configured to define a channel region of the bulk substrate. The first insulation trench has a first insulation trench section and a second insulation trench section positioned above the first insulation trench section. A first insulation material fills the first insulation trench section. An epitaxial material fills the second insulation trench section of the first insulation trench, with the epitaxial material positioned on top of the first insulation material. The second insulation trench defines an active region that includes the channel region. A second insulation material fills the second insulation trench.The semiconductor-on-insulator-like structure further features an amorphous layer embedded in the bulk substrate located beneath the first insulating trench and the channel region. The resistance of the amorphous layer is greater than that of the bulk substrate. In some reactions, an air gap is incorporated into the second insulating material.

[0053] In some transformations, the first isolation trench has negatively sloping sidewalls, and the second isolation trench has positively sloping sidewalls. In some transformations, the first isolation trench has negatively sloping sidewalls, and the second isolation trench has negatively sloping sidewalls. In some transformations, the first isolation trench section has essentially vertical sidewalls, and the second isolation trench section has negatively sloping sidewalls. In some transformations, the second isolation trench extends through at least one section of the first isolation trench. In some transformations, the second isolation trench further extends through at least one section of the amorphous layer.

[0054] An exemplary method for fabricating an integrated circuit component such that a bulk substrate of the integrated circuit component exhibits semiconductor-on-insulator behavior, comprises forming a first insulating trench in a bulk substrate, wherein the first insulating trench defines a channel region of the bulk substrate; increasing the resistance of a section of the bulk substrate located beneath the first insulating region and the channel region of the bulk substrate; filling a first section of the first insulating trench with a first insulating material; filling a second section of the first insulating trench with a semiconductor material; forming a second insulating trench in the bulk substrate, wherein the second insulating trench defines an active region comprising the channel region; and filling the second insulating trench with a second insulating material.In some implementations, forming the first isolation trench involves performing a two-step etching process to create the first and second sections. In other implementations, increasing the resistance of the bulk substrate section located beneath the first isolation trench and the bulk substrate channel area involves performing an implantation process.

Claims

[1] An integrated circuit device (100) comprising a bulk substrate (102) exhibiting semiconductor-on-insulator behavior, the integrated circuit device comprising: a channel region (114) defined in the bulk substrate, the channel region having a first portion (114A) disposed over a second portion (114B), and further comprising: the first portion (114A) is disposed between epitaxial source-drain features (140) disposed in the bulk substrate (102), the second portion (114B) is defined by a first isolation feature (130) disposed in the bulk substrate (102), wherein the epitaxial source-drain features (140) are disposed on the first isolation feature (130), and a thickness of the channel region (114) is approximately equal to a sum (tsi) of a thickness (t2) of the first isolation feature and a thickness (t3) of the epitaxial source-drain features; a second isolation feature (182) disposed in the bulk substrate, the second isolation feature defining an active region comprising the first portion of the channel region (114A) disposed between the epitaxial source-drain features (140); wherein a resistance of a portion of the bulk substrate (120) lying on the bulk substrate and under the first insulation feature (130) and the channel region (114) is greater than a resistance of the bulk substrate (102); wherein the channel region (114) has a tapered width (W7) that decreases as the thickness of the channel region (t si ) increases; and wherein a width (L G ) of the first section (114A) is substantially the same, while the thickness (t si) of the channel region (114) increases, and a width (W7) of the second portion (114B) decreases while the thickness of the channel region increases. [2] The integrated circuit device of any preceding claim, wherein a thickness (t4) of the second isolation feature (182) is greater than or equal to the thickness (t3) of the epitaxial source-drain features (140). [3] The integrated circuit device of claim 2, wherein the thickness (t4) of the second isolation feature (182) is less than the thickness (t si ) of the canal area. [4] The integrated circuit device of claim 2, wherein the thickness (t4) of the second isolation feature (182) is greater than the thickness (t si ) of the canal area. [5] The integrated circuit device of claim 2, wherein the thickness (t4) of the second isolation feature (182) is greater than a sum of the thickness of the channel region (t si) and a thickness (t1) of the portion (120) of the bulk substrate (102) underlying the first insulation feature (130) and the channel region (114). [6] The integrated circuit device of any preceding claim, wherein the bulk substrate (102) comprises a material having a crystalline structure, and the portion of the bulk substrate (120) underlying the first isolation element and the channel region comprises the material having a non-crystalline structure. [7] The integrated circuit device of any preceding claim, further comprising an air gap (302) disposed in the second isolation feature (182), the second isolation feature (182) having a tapered width (W12) that increases with depth (t4). [8] The integrated circuit device of any preceding claim, further comprising a gate structure (190) disposed over the channel region. [9] Semiconductor-on-insulator-like structure comprising: a bulk substrate (102); a double insulation structure comprising: a first isolation trench (112) defined in the bulk substrate, the first isolation trench (112) being configured to define a channel region (114) of the bulk substrate (102), the first isolation trench (112) comprising a first isolation trench portion (112A) and a second isolation trench portion (112B) disposed above the first isolation trench portion, and: a first insulation material (130) fills the first insulation trench portion (112A) of the first insulation trench (112); and an epitaxial material (144) fills the second isolation trench portion (112B) of the first isolation trench (112), wherein the epitaxial material (144) is disposed on the first isolation material (130); and a second isolation trench (172) defined in the bulk substrate (102), the second isolation trench defining an active region including the channel region (114), and further wherein a second isolation material (180) fills the second isolation trench (172); and an amorphous layer (120) arranged in the bulk substrate (102) underlying the first isolation trench (112) and the channel region (114), wherein a resistance of the amorphous layer is greater than a resistance of the bulk substrate (102), wherein the channel region (114) has a tapered width (W7) which decreases as the thickness of the channel region (t si ) increases; and where a width (L G) of the first section (114A) is substantially the same, while the thickness (t si ) of the channel region (114) increases, and a width (W7) of the second portion (114B) decreases while the thickness of the channel region increases. [10] The semiconductor-on-insulator-like structure of claim 9, wherein the first isolation trench (112) has negatively sloped sidewalls, and the second isolation trench (172) has positively sloped sidewalls. [11] The semiconductor-on-insulator-like structure of claim 9, wherein the first isolation trench (112) has negatively sloped sidewalls, and the second isolation trench (172) has negatively sloped sidewalls. [12] A semiconductor-on-insulator-like structure according to any one of the preceding claims 9 to 11, wherein an air gap (302) is arranged in the second insulating material (180). [13] A semiconductor-on-insulator-like structure according to any one of the preceding claims 9 to 12, wherein the first isolation trench portion (112A) has substantially vertical sidewalls, and the second isolation trench portion (112B) has negatively sloping sidewalls. [14] A semiconductor-on-insulator-like structure according to any one of the preceding claims 9 to 13, wherein the second isolation trench (172) extends through at least a portion of the first isolation trench (112). [15] The semiconductor-on-insulator-like structure of claim 14, wherein the second isolation trench (172) further extends through at least a portion of the amorphous layer (120). [16] A method of manufacturing an integrated circuit device (100) such that a bulk substrate (102) of the integrated circuit device exhibits semiconductor-on-insulator behavior, the method comprising: Forming a first isolation trench (112) in a bulk substrate, the first isolation trench defining a channel region (114) of the bulk substrate (102); Increasing a resistance of a portion (120) of the bulk substrate (102) underlying the first isolation trench (112) and the channel region (114) of the bulk substrate (102); Filling a first portion (112B) of the first isolation trench with a first isolation material (130); Filling a second portion (112A) of the first isolation trench with a semiconductor material (144); Forming a second isolation trench (172) in the bulk substrate (102), the second isolation trench defining an active region including the channel region (114); and Filling the second isolation trench (172) with a second insulation material (180); wherein forming the first isolation trench (112) comprises performing a two-step etching process to form the first portion (112B) and the second portion (112A). [17] The method of claim 16, wherein increasing the resistance of the portion (120) of the bulk substrate (102) underlying the first isolation trench (112) and the channel region (114) of the bulk substrate (102) comprises performing an implantation process.

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