METHOD AND DEVICE OF AN INTEGRATED CIRCUIT LAYOUT

Abstract

Method for generating a layout diagram of an integrated circuit cell (IC cell), wherein the IC layout diagram is stored in a non-volatile, computer-readable medium, the method comprising: Defining a boundary recess (200R3; 300R4) in a boundary (200B; 300B) of the cell (200C; 300C) by the following: Creating a first section (B10; B34) of the boundary (200B; 300B) along a first direction (Y); Creating a second section (B9; B33) of the boundary (200B; 300B) away from the first section (B10; B34) in a second direction (-X) perpendicular to the first direction (Y), with the second section (B9; B33) adjoining the first section; and Creating a third section (B11; B35) of the boundary (200B; 300B) away from the first section (B10; B34) in the second direction (-X), with the third section (B11; B35) adjoining the first section (B10; B34); and Arranging an active area (220) in the cell by creating the active area (220) away from the first section (B10; B34) in a third direction (X) opposite to the second direction (-X).

Description

STATE OF THE ART

[0001] An integrated circuit (IC) typically comprises multiple semiconductor devices, also known as integrated circuits (ICs). One way to represent an IC device is with a top-view diagram, called a layout diagram or IC layout diagram. An IC layout diagram is hierarchical, featuring modules that perform high-level functions according to the IC device's design specifications. The modules are often constructed from a combination of cells, which can include both standard and custom cells, each of which represents one or more semiconductor structures.

[0002] Cells are designed to provide common low-level functions, often performed by transistors based on gate regions that cross active regions, sometimes known as oxide definition (OD) regions. The elements of a cell are arranged within a cell boundary and electrically connected to other cells via interconnect structures.

[0003] From US 2011 / 0 084 312 A1, the use of a distance control for rectangular cells is known, which ensures minimum distances between conductive elements that are required for production. SUMMARY OF THE INVENTION

[0004] The invention relates to a method for generating a layout diagram of an integrated circuit cell according to claim 1, a manufacturing method according to claim 9, a method for generating a layout diagram of an integrated circuit according to claim 10, a manufacturing method according to claim 15, and an IC device according to claim 16. Preferred developments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is a flowchart of a method for generating a layout diagram of an IC according to some embodiments. Fig. 2 is an illustration of an IC layout diagram according to some embodiments. Fig. 3 is an illustration of an IC layout diagram according to some embodiments. Fig. 4 is an illustration of an active region according to some embodiments. Fig. 5A is a schematic diagram of an IC corresponding to IC layout diagrams, according to some embodiments. Fig. 5B1 to 5H2 are illustrations of IC layout diagrams according to some embodiments. Fig. 6 is a flowchart of a method for generating a layout diagram of an IC according to some embodiments. Fig. 7 is an illustration of an IC layout diagram according to some embodiments. Fig. 8 is an illustration of an IC layout diagram according to some embodiments. Fig. 9 is an illustration of an IC layout diagram according to some embodiments. Fig. 10 is an illustration of an IC layout diagram according to some embodiments. Fig. 11 is an illustration of an IC device according to some embodiments. Fig. 12 is an illustration of an IC device according to some embodiments. Fig. 13 is a schematic view of an electronic design automation (EDA) system according to some embodiments. Fig. 14 is an illustration of an IC manufacturing system and an associated IC manufacturing flow according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components, values, acts, materials, arrangements, or the like are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, acts, materials, arrangements, or the like are contemplated.For example, in the description below, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not, in and of itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] In addition, terms relating to spatial relativity, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0008] In various embodiments, an IC layout includes a first cell having a boundary protrusion on one side and a second cell having a compatible boundary recess on a side near the first cell, such that when the cells are abutted in a layout process, the protrusion is fitted into the recess. The resulting layout may thereby include a gate region used to define a transistor by crossing an active region in the protrusion of the first cell and extending into the second cell. The IC layouts of the various embodiments and IC devices based on the IC layouts avoid using dummy gate regions at cell boundaries, thereby reducing area requirements compared to approaches that do not include a gate region capable of defining a transistor in a first cell and extending into a second cell.

[0009] Fig. 1 is a flow diagram of a method 100 for generating a layout diagram of an IC according to some embodiments. The acts of method 100 may be performed as part of a method for forming one or more IC devices, e.g., one of the methods described below, each with reference to Fig. 11 and 12, respectively, which are manufactured based on the generated IC layout diagram. Non-limiting examples of IC devices include memory circuits, logic devices, processing devices, signal processing circuits, and the like.

[0010] In some embodiments, some or all of the acts of method 100 may be performed as part of an APR (placement and routing) process. In some embodiments, some or all of the acts of method 100 may be performed by an APR system, e.g., a system described in a Fig. 13 discussed EDA system 1300 and is designed to perform the APR procedure.

[0011] In some embodiments, some or all of the acts of method 100 may be performed as part of a system described below with reference to Fig. 6 for generating a layout diagram of an IC. Some or all of the operations of method 100 may be performed as part of a design process performed in a design house, e.g., a design house 1420, described below with reference to Fig. 14 is discussed.

[0012] In some embodiments, part or all of the method 100 is performed by a processor of a computer. In some embodiments, part or all of the method 100 is performed by a processor 1302 of a computer described below with reference to Fig. 13 discussed EDA system 1300.

[0013] In some embodiments, the operations of method 100 are performed in the manner described in Fig. 1. In some embodiments, the operations of method 100 are performed in a different order than those shown in Fig. 1. In some embodiments, one or more operations are performed before, between, during, and / or after performing one or more operations of method 100.

[0014] Fig. 2 to 4 and 5B1 to 5H2 are illustrations of non-limiting examples of respective IC layout diagrams 200 to 400 and 500B1 to 500H2 that are generated in some embodiments by performing one or more acts of method 100. The IC layout diagrams 200 to 400 and 500B1 to 500H2 are simplified for clarity. In various embodiments, one or more IC layout diagrams 200 to 400 and 500B1 to 500H2, in addition to those shown in Fig. 2 to 4 and 5B1 to 5H2, features such as one or more transistor elements, supply rails, isolation structures, wells, conductive elements or the like.

[0015] Each of the Fig. 2 to 4 and 5B1 to 5H2 also illustrate an X-direction and a Y-direction perpendicular to the X-direction. The X-direction being shown as horizontal and the Y-direction being shown as vertical is a non-limiting example for illustrative purposes. In various embodiments, the X- and Y-directions are perpendicular to each other and have orientations that differ from those in Fig. 2 to 4 and 5B1 to 5H2 are different.

[0016] The X-direction has a positive X-direction, which in Fig. 2 to 4 and 5B1 to 5H2, and a negative X-direction (not labeled) opposite to the positive X-direction. The Y-direction has a positive Y-direction shown in Fig. 2 to 4 and 5B1 to 5H2, and a negative Y direction (not marked) opposite to the positive Y direction.

[0017] Fig. Figure 2 is an illustration of an IC layout diagram 200 including a cell 200C, according to some embodiments. Cell 200C includes a boundary 200B and active regions 210, 220, 230, and 240.

[0018] Fig. 3 is an illustration of an IC layout diagram 300 including a cell 300C, according to some embodiments. Cell 300C includes a boundary 300B and active regions 210, 220, 230, and 240.

[0019] In addition to cells 200C and 300C, each of the Fig. 2 and Fig. 3 Gate traces T1 to T6. Gate traces T1 to T6 extend in the Y direction, have a gate pitch GP in the X direction, and correspond to positions where gate regions (not shown) are aligned in IC layout diagrams, e.g., IC layout diagrams 200 and 300.

[0020] In various embodiments, one or both of the IC layout diagrams 200 or 300 include one or more cells (not shown) in addition to the respective cell 200C or cell 300C.

[0021] In various embodiments, one or both of cell 200C or cell 300C is a layout diagram of a standard cell, a custom cell, an ECO (engineering change order) cell, a logic gate cell, a memory cell, or another type of cell or combination of cells that can be defined in an IC layout diagram. In various embodiments, a logic gate cell includes a layout diagram of one or more of an AND, OR, NAND, NOR, XOR, INV, AND-OR invert (AOI), OR-AND invert (OAI), MUX, flip-flop, BUFF, latch, delay, or clock device.In various embodiments, a memory cell comprises a layout diagram of one or more of an SRAM (Static Random Access Memory), a DRAM (Dynamic RAM), an RRAM (Resistive RAM), an MRAM (Magnetoresistive RAM), or a ROM (Read Only Memory) cell, or other device capable of having multiple states representing logical values.

[0022] As in Fig. 2, the boundary 200B of cell 200C includes sections B1 through B12. Section B12 extends along the Y direction and is adjacent to section B1, which extends along the X direction. For each of the other sections B2 through B11, a given section B[n] is adjacent to a section B[n-1], adjacent to a section B[n+1], and extends along one of the X or Y directions that is perpendicular to the other of the X or Y directions along which each of the sections B[n-1] and B[n+1] extends.

[0023] Section B1 extends in the positive X direction from a point corresponding to gate track T1 to a point corresponding to gate track T5. Section B2 extends along gate track T5 in the negative Y direction from section B1 to section B3. In various embodiments, section B1 extends from a position different from the point corresponding to gate track T1, and / or section B1 extends to a position different from the point corresponding to gate track T5, and section B2 extends along a position different from that of gate track T5.

[0024] Section B3 extends in the positive X direction from section B2 to a point corresponding to gate track T6. Section B4 extends along gate track T6 in the negative Y direction from section B3 to section B5. In various embodiments, section B3 extends from a position different from the point corresponding to gate track T5, and / or section B3 extends to a position different from the point corresponding to gate track T6, and section B4 extends along a position different from that of gate track T6.

[0025] Section B5 extends in the negative X direction from section B4 to a point corresponding to gate track T5. Section B6 extends along gate track T5 in the negative Y direction from section B5 to section B7. In various embodiments, section B5 extends from a position different from the point corresponding to gate track T6, and / or section B5 extends to a position different from the point corresponding to gate track T5, and section B6 extends along a position different from that of gate track T5.

[0026] Section B7 extends in the negative X direction from section B6 to a point corresponding to gate track T1. Section B8 extends along gate track T1 in the positive Y direction from section B7 to section B9. In various embodiments, section B7 extends from a position different from the point corresponding to gate track T6, and / or section B7 extends to a position different from the point corresponding to gate track T1, and section B8 extends along a position different from that of gate track T1.

[0027] Section B9 extends in the positive X direction from section B8 to a point corresponding to gate track T2. Section B10 extends along gate track T2 in the positive Y direction from section B9 to section B11. In various embodiments, section B9 extends from a position different from the point corresponding to gate track T1, and / or section B9 extends to a position different from the point corresponding to gate track T2, and section B10 extends along a position different from that of gate track T2.

[0028] Section B11 extends in the negative X direction from section B10 to a point corresponding to gate track T1. Section B12 extends along gate track T1 in the positive Y direction from section B11 to section B1. In various embodiments, section B11 extends from a position different from the point corresponding to gate track T2, and / or section B11 extends to a position different from the point corresponding to gate track T1, and section B12 extends along a position different from that of gate track T1.

[0029] In the Fig. In the embodiment illustrated in Figure 2, each of the sections B1, B3, B5, B7, B9, and B11 extends in the X direction. In various embodiments, one or more of the sections B1, B3, B5, B7, B9, or B11 extends in a direction different from the X direction and has a component in the X direction.

[0030] In the Fig. In the embodiment illustrated in Figure 2, each of the sections B2, B4, B6, B8, B10, and B12 extends in the Y direction. In various embodiments, one or more of the sections B2, B4, B6, B8, B10, or B12 extends in a direction different from the Y direction and has a component in the Y direction.

[0031] In the Fig. In the embodiment illustrated in Figure 2, section B2 is aligned with section B6 along the Y direction, section B3 is aligned with section B11 along the X direction, section B5 is aligned with section B9 along the X direction, and section B8 is aligned with section B12 along the Y direction. In various embodiments, one or more of section B2 is not aligned with section B6 along the Y direction, section B3 is not aligned with section B11 along the X direction, section B5 is not aligned with section B9 along the X direction, or section B8 is not aligned with section B12 along the Y direction.

[0032] A boundary having a shape other than a rectangular shape is considered to have one or more projections and / or one or more recesses based on one or more deviations from a rectangular shape. Due to the configuration of the boundary 200B discussed above, the sections B3, B4 and B5 have a shape of a boundary protrusion 200P1 of the cell 200C, the sections B7, B8 and B9 have a shape of a boundary protrusion 200P2 of the cell 200C, the sections B11, B12 and B1 have a shape of a boundary protrusion 200P3 of the cell 200C, the sections B2 and B3 have a shape of a boundary recess 200R1 of the cell 200C, the sections B5 and B6 have a shape of a boundary recess 200R2 of the cell 200C, and the sections B9, B10 and B11 have a shape of a boundary recess 200R3 of the cell 200C.

[0033] In the Fig. 2, cell 200C thereby includes two boundary protrusions 200P2 and 200P3 along a left side of cell 200C, one boundary protrusion 200P1 along a right side of cell 200C, zero boundary protrusions along a top side of cell 200C, and zero boundary protrusions along a bottom side of cell 200C. In various embodiments, cell 200C includes fewer or more than two boundary protrusions along the left side, more than one boundary protrusion along the right side, one or more boundary protrusions along the top side, and / or one or more boundary protrusions along the bottom side.

[0034] In the Fig. 2, cell 200C thereby has one boundary notch 200R3 along the left side, two boundary notches 200R1 and 200R2 along the right side, zero boundary notches along the top side, and zero boundary protrusions along the bottom side. In various embodiments, cell 200C has more than one boundary notch along the left side, fewer or more than two boundary notches along the right side, one or more boundary notches along the top side, and / or one or more boundary notches along the bottom side.

[0035] In the Fig. In the embodiment illustrated in Figure 2, each of the boundary protrusions 200P1, 200P2, and 200P3 and each of the boundary recesses 200R1, 200R2, and 200R3 extends in the X direction by a distance corresponding to the gate pitch GP. In various embodiments, one or more of the boundary protrusions 200P1, 200P2, or 200P3 or the boundary recesses 200R1, 200R2, or 200R3 extend in the X direction by a distance different from the gate pitch GP, e.g., by a multiple of the gate pitch GP or a fraction of the gate pitch GP.

[0036] In the Fig. In the embodiment illustrated in Figure 2, each of the boundary protrusions 200P1, 200P2, and 200P3 and each of the boundary recesses 200R1, 200R2, and 200R3 has a shape based on right angles formed by adjacent boundary portions. In various embodiments, one or more of the boundary protrusions 200P1, 200P2, or 200P3 or the boundary recesses 200R1, 200R2, or 200R3 has a shape based on one or more configurations other than a right angle formed by adjacent boundary portions, e.g., an acute or obtuse angle formed by adjacent boundary portions, a semicircular boundary portion, or a boundary portion having one or more arcs.

[0037] As in Fig. 3, the boundary 300B of cell 300C includes sections B21 through B36. Section B36 extends along the Y direction and is adjacent to section B21, which extends along the X direction. For each of the other sections B22 through B35, a given section B[n] is adjacent to a section B[n-1], adjacent to a section B[n+1], and extends along one of the X or Y directions that is perpendicular to the other of the X or Y directions along which each of the sections B[n-1] and B[n+1] extends.

[0038] Section B21 extends in the positive X direction from a point corresponding to gate track T1 to a point corresponding to gate track T5. Section B22 extends along gate track T5 in the negative Y direction from section B21 to section B23. In various embodiments, section B21 extends from a position different from the point corresponding to gate track T1, and / or section B21 extends to a position different from the point corresponding to gate track T5, and section B22 extends along a position different from that of gate track T5.

[0039] Section B23 extends in the positive X direction from section B22 to a point corresponding to gate track T6. Section B24 extends along gate track T6 in the negative Y direction from section B23 to section B25. In various embodiments, section B23 extends from a position different from the point corresponding to gate track T5, and / or section B23 extends to a position different from the point corresponding to gate track T6, and section B24 extends along a position different from that of gate track T6.

[0040] Section B25 extends in the negative X direction from section B24 to a point corresponding to gate track T5. Section B26 extends along gate track T5 in the negative Y direction from section B25 to section B27. In various embodiments, section B25 extends from a position different from the point corresponding to gate track T6, and / or section B25 extends to a position different from the point corresponding to gate track T5, and section B26 extends along a position different from that of gate track T5.

[0041] Section B27 extends in the positive X direction from section B26 to a point corresponding to gate track T6. Section B28 extends along gate track T6 in the negative Y direction from section B27 to section B29. In various embodiments, section B27 extends from a position different from the point corresponding to gate track T5, and / or section B27 extends to a position different from the point corresponding to gate track T6, and section B28 extends along a position different from that of gate track T6.

[0042] Section B29 extends in the negative X direction from section B28 to a point corresponding to gate track T2. Section B30 extends along gate track T2 in the positive Y direction from section B29 to section B31. In various embodiments, section B29 extends from a position different from the point corresponding to gate track T6, and / or section B29 extends to a position different from the point corresponding to gate track T2, and section B30 extends along a position different from that of gate track T2.

[0043] Section B31 extends in the negative X direction from section B30 to a point corresponding to gate track T1. Section B32 extends along gate track T1 in the positive Y direction from section B31 to section B33. In various embodiments, section B31 extends from a position different from the point corresponding to gate track T2, and / or section B31 extends to a position different from the point corresponding to gate track T1, and section B32 extends along a position different from that of gate track T1.

[0044] Section B33 extends in the positive X direction from section B32 to a point corresponding to gate track T2. Section B34 extends along gate track T2 in the positive Y direction from section B33 to section B35. In various embodiments, section B33 extends from a position different from the point corresponding to gate track T1, and / or section B33 extends to a position different from the point corresponding to gate track T2, and section B34 extends along a position different from that of gate track T2.

[0045] Section B35 extends in the negative X direction from section B34 to a point corresponding to gate track T1. Section B36 extends along gate track T1 in the positive Y direction from section B35 to section B21. In various embodiments, section B35 extends from a position different from the point corresponding to gate track T2, and / or section B35 extends to a position different from the point corresponding to gate track T1, and section B36 extends along a position different from that of gate track T1.

[0046] In the Fig. In the embodiment illustrated in Figure 3, each of the sections B21, B23, B25, B27, B29, B31, B33, and B35 extends in the X direction. In various embodiments, one or more of the sections B21, B23, B25, B27, B29, B31, B33, or B35 extends in a direction different from the X direction and has a component in the X direction.

[0047] In the Fig. In the embodiment illustrated in Figure 3, each of the sections B22, B24, B26, B28, B30, B32, B34, and B36 extends in the Y direction. In various embodiments, one or more of the sections B22, B24, B26, B28, B30, B32, B34, or B36 extends in a direction different from the Y direction and has a component in the Y direction.

[0048] In the Fig. 3, section B22 is aligned with section B26 along the Y direction, section B23 is aligned with section B35 along the X direction, section B24 is aligned with section B28 along the Y direction, section B25 is aligned with section B33 along the X direction, section B27 is aligned with section B31 along the X direction, section B30 is aligned with section B34 along the Y direction, and section B32 is aligned with section B36 along the Y direction.In various embodiments, one or more of section B22 is not aligned with section B26 along the Y direction, section B23 is not aligned with section B35 along the X direction, section B24 is not aligned with section B28 along the Y direction, section B25 is not aligned with section B33 along the X direction, section B27 is not aligned with section B31 along the X direction, section B30 is not aligned with section B34 along the Y direction, or section B32 is not aligned with section B36 along the Y direction.

[0049] Due to the above-discussed configuration of the boundary 300B, the sections B23, B24 and B25 have a shape of a boundary protrusion 300P1 of the cell 300C, the sections B27, B28 and B29 have a shape of a boundary protrusion 300P2 of the cell 300C, the sections B31, B32 and B33 have a shape of a boundary protrusion 300P3 of the cell 300C, the sections B35, B36 and B21 have a shape of a boundary protrusion 300P4 of the cell 300C, the sections B22 and B23 have a shape of a boundary recess 300R1 of the cell 300C, the sections B25, B26 and B27 have a shape of a boundary recess 300R2 of the cell 300C, the sections B30 and B31 have a Form of a boundary recess 300R3 of the cell 300C, and the sections B33, B34 and B35 have a shape of a boundary recess 300R4 of the cell 300C.

[0050] In the Fig. 3, cell 300C thereby includes two boundary protrusions 300P3 and 300P4 along a left side of cell 300C, two boundary protrusions 300P1 and 300P2 along a right side of cell 300C, zero boundary protrusions along a top side of cell 300C, and zero boundary protrusions along a bottom side of cell 300C. In various embodiments, cell 300C includes fewer or more than two boundary protrusions along the left side, fewer or more than two boundary protrusions along the right side, one or more boundary protrusions along the top side, and / or one or more boundary protrusions along the bottom side.

[0051] In the Fig. 3, cell 300C thereby has two boundary notches 300R3 and 300R4 along the left side, two boundary notches 300R1 and 300R2 along the right side, zero boundary notches along the top side, and zero boundary notches along the bottom side. In various embodiments, cell 300C has fewer or more than two boundary notches along the left side, fewer or more than two boundary notches along the right side, one or more boundary notches along the top side, and / or one or more boundary notches along the bottom side.

[0052] In the Fig. In the embodiment illustrated in Figure 3, each of the boundary protrusions 300P1, 300P2, 300P3, and 300P4 and each of the boundary recesses 300R1, 300R2, 300R3, and 300R4 extends in the X direction by a distance corresponding to the gate pitch GP. In various embodiments, one or more of the boundary protrusions 300P1, 300P2, 300P3, or 300P4 or the boundary recesses 300R1, 300R2, 300R3, or 300R4 extend in the X direction by a distance different from the gate pitch GP, e.g., by a multiple of the gate pitch GP or a fraction of the gate pitch GP.

[0053] In the Fig. In the embodiment illustrated in Figure 3, each of the boundary protrusions 300P1, 300P2, 300P3, and 300P4 and each of the boundary recesses 300R1, 300R2, 300R3, and 300R4 has a shape based on right angles formed by adjacent boundary portions. In various embodiments, one or more of the boundary protrusions 300P1, 300P2, 300P3, or 300P4 or the boundary recesses 300R1, 300R2, 300R3, or 300R4 has a shape based on one or more configurations other than a right angle formed by adjacent boundary portions, e.g., an acute or obtuse angle formed by adjacent boundary portions, a semicircular boundary portion, or a boundary portion having one or more arcs.

[0054] At operation 110, a boundary notch is defined in a boundary of an IC cell. Defining the boundary notch includes creating a first portion of the boundary along a first direction, creating a second portion of the boundary away from the first portion in a second direction perpendicular to the first direction, the second portion adjacent to the first portion, and creating a third portion away from the first portion in the second direction, the third portion adjacent to the first portion.

[0055] Creating the first portion in the first direction and the second and third portions in the second direction forms a first recess in the boundary. In some embodiments, defining the boundary recess includes forming one or more boundary recesses in addition to the first boundary recess. In various embodiments, defining the boundary recess includes forming one or more protrusions in the boundary.

[0056] In some embodiments, defining the boundary recess comprises forming an entirety of the boundary having a closed loop. In various embodiments, defining the boundary recess comprises forming an entirety of one of the boundaries 200B or 300B, each of which is described above with reference to Fig. 2 and 3 respectively.

[0057] In some embodiments, defining the boundary recess comprises defining at least a portion of the boundary 200B of the cell 200C, creating the first portion in the first direction comprises creating the portion B10 in the positive or negative Y direction, creating the second and third portions in the second direction comprises creating the portions B9 and B11 in the negative X direction, thereby forming the boundary recess 200R3 described above with reference to Fig. 2 was discussed.

[0058] In some embodiments, defining the boundary recess comprises defining at least a portion of the boundary 300B of the cell 300C, creating the first portion in the first direction comprises creating the portion B34 in the positive or negative Y direction, creating the second and third portions in the second direction comprises creating the portions B33 and B35 in the negative X direction, thereby forming the boundary recess 300R4 described above with reference to Fig. 3 was discussed.

[0059] In some embodiments, defining the boundary recess comprises defining at least a portion of the boundary 300B of the cell 300C, creating the first portion in the first direction comprises creating the portion B26 in the positive or negative Y direction, creating the second and third portions in the second direction comprises creating the portions B25 and B27 in the positive X direction, thereby forming the boundary recess 300R2, which was described above with reference to Fig. 3 was discussed.

[0060] In various embodiments, defining the boundary recess comprises further defining the boundary by creating one or more additional sections along the first or second direction or along one or more directions opposite to the first or second direction.

[0061] In some embodiments, further defining the boundary comprises forming an entirety of the boundary that has a closed loop. In various embodiments, further defining the boundary comprises forming an entirety of one of the boundaries 200B or 300B, each of which is described above with reference to Fig. 2 and 3 respectively.

[0062] In some embodiments, further defining the boundary comprises forming one or more boundary recesses in addition to the first boundary recess. In some embodiments, further defining the boundary comprises forming one or both of the boundary recesses 200R1 or 20R2 described above with reference to Fig. 2. In some embodiments, further defining the boundary includes forming one or more of the boundary recesses 300R1, 300R2, 300R3, or 300R4 discussed above with reference to Fig. 3 were discussed.

[0063] In some embodiments, further defining the boundary comprises forming one or more protrusions in the boundary. In some embodiments, further defining the boundary comprises forming one or more of the boundary protrusions 200P1, 200P2, or 200P3 described above with reference to Fig. 2. In some embodiments, further defining the boundary includes forming one or more of the boundary protrusions 300P1, 300P2, 300P3, or 300P4 discussed above with reference to Fig. 3 were discussed. 3.

[0064] Each of the active regions 210, 220, 230, and 240 is a layout component extending along the X-direction and defining an active area of ​​one or more transistor structures formed at one or more positions where the active regions 210, 220, 230, and 240 intersect the gate traces T1 to T6. In various embodiments, a transistor structure comprises one or more of a switching, logic, amplification, rectification, memory, or other integrated circuit device.

[0065] Each of the active regions 210, 220, 230, and 240 defines an active area in which source, drain, and channel features of one or more transistor structures are formed in and / or on a semiconductor substrate. A given active region 210, 220, 230, or 240 is either an N-type active region defining an N-type active region of one or more PMOS transistor structures or a P-type active region defining an N-type active region of one or more NMOS transistor structures. In some embodiments, each of the active regions 210 and 220 defines an N-type active region of one or more PMOS transistor structures, and each of the active regions 230 and 240 defines a P-type active region of one or more NMOS transistor structures.

[0066] In various embodiments, one or more of the active regions 210, 220, 230, or 240 include a single continuous active region or multiple active regions. In some embodiments, each of the active regions 210, 220, 230, and 240 includes an equal number of active regions. In various embodiments, one or more of the active regions 210, 220, 230, or 240 include a different number of active regions than a different number of active regions included in another or more of the active regions 210, 220, 230, or 240.

[0067] In various embodiments, one or more of the active regions 210, 220, 230, or 240 is incorporated in one or more planar transistors and / or one or more fin field effect transistors (FinFETS) in one or both of the cell 200C or the cell 300C. In some embodiments, one or more of the active regions 210, 220, 230, or 240 is an active region 400, which is described below with reference to Fig. 4 is discussed.

[0068] In the Fig. 2 and Fig. In the embodiment illustrated in Figure 3, each of the active regions 210, 220, 230, and 240 extends through three of the gate traces T2 to T5. In various embodiments, one or more of the active regions 210, 220, 230, or 240 extends through fewer than three of the gate traces T2 to T5, more than three of the gate traces T2 to T5, or one or more gate traces other than the gate traces T2 to T5.

[0069] In the Fig. In the embodiment illustrated in Figure 2, the active region 210 is disposed between the sections B12 and B2, is aligned with the sections B12 and B2 along the X-direction, and extends into the protrusion 200P3, and spaces (not labeled) separate the active region 210 from each of the sections B12 and B2. In various embodiments, the active region 210 borders one or both of the sections B12 or B2 and / or is aligned with one or both of the gate traces T1 or T5.

[0070] In some embodiments, cell 200C includes one or more active regions (not shown) in addition to active region 210 disposed between sections B12 and B2, aligned with sections B12 and B2 along the X direction, and extending into protrusion 200P3.

[0071] In the Fig. 2, each of the active regions 220 and 230 is disposed between the sections B10 and B4, is aligned with the sections B10 and B4 along the X-direction, and extends into the protrusion 200P1, and gaps (not labeled) separate each of the active regions 210 and 230 from each of the sections B10 and B4. In various embodiments, one or both of the active regions 220 or 230 borders one or both of the sections B10 or B4 and / or is aligned with one or both of the gate traces T2 or T6.

[0072] In some embodiments, cell 200C includes one or more other active regions (not shown) in addition to active regions 220 and 230 located between sections B10 and B4, aligned with sections B10 and B4 along the X direction, and extending into protrusion 200P1. In some embodiments, cell 200C does not include one of active regions 220 or 230, and one of active regions 220 or 230 is a single active region located between sections B10 and B4, aligned with sections B10 and B4 along the X direction, and extending into protrusion 200P1.

[0073] In the Fig. In the embodiment illustrated in Figure 2, the active region 240 is disposed between sections B8 and B6, is aligned with sections B8 and B6 along the X-direction, and extends into the protrusion 200P2, and spaces (not labeled) separate the active region 240 from each of the sections B8 and B6. In various embodiments, the active region 240 borders one or both of the sections B8 or B6 and / or is aligned with one or both of the gate traces T1 or T5.

[0074] In some embodiments, cell 200C includes one or more active regions (not shown) in addition to active region 240 disposed between sections B8 and B6, aligned with sections B8 and B6 along the X direction, and extending into protrusion 200P2.

[0075] In the Fig. In the embodiment illustrated in Figure 3, the active region 210 is disposed between the sections B36 and B22, is aligned with the sections B36 and B22 along the X-direction, and extends into the protrusion 300P4, and spaces (not labeled) separate the active region 210 from each of the sections B36 and B22. In various embodiments, the active region 210 borders one or both of the sections B36 or B22 and / or is aligned with one or both of the gate traces T1 or T5.

[0076] In some embodiments, cell 300C includes one or more active regions (not shown) in addition to active region 210 disposed between portions B36 and B22, aligned with portions B36 and B22 along the X direction, and extending into protrusion 300P4.

[0077] In the Fig. In the embodiment illustrated in Figure 3, the active region 220 is disposed between sections B34 and B24, is aligned with sections B34 and B24 along the X-direction, and extends into the protrusion 300P1, and spaces (not labeled) separate the active region 220 from each of the sections B34 and B24. In various embodiments, the active region 220 borders one or both of the sections B34 or B24 and / or is aligned with one or both of the gate traces T2 or T6.

[0078] In some embodiments, cell 300C includes one or more active regions (not shown) in addition to active region 220 disposed between portions B34 and B24, aligned with portions B34 and B24 along the X direction, and extending into protrusion 300P1.

[0079] In the Fig. In the embodiment illustrated in Figure 3, the active region 230 is disposed between the sections B32 and B26, is aligned with the sections B32 and B26 along the X-direction, and extends into the protrusion 300P3, and spaces (not labeled) separate the active region 230 from each of the sections B32 and B26. In various embodiments, the active region 230 borders one or both of the sections B32 or B26 and / or is aligned with one or both of the gate traces T1 or T5.

[0080] In some embodiments, cell 300C includes one or more active regions (not shown) in addition to active region 230 disposed between portions B32 and B26, aligned with portions B32 and B26 along the X-direction, and extending into protrusion 300P3.

[0081] In the Fig. In the embodiment illustrated in Figure 3, the active region 240 is disposed between sections B30 and B28, is aligned with sections B30 and B28 along the X-direction, and extends into the protrusion 300P2, and spaces (not labeled) separate the active region 240 from each of the sections B30 and B28. In various embodiments, the active region 240 is adjacent to one or both of the sections B30 or B28 and / or is aligned with one or both of the gate traces T2 or T6.

[0082] In some embodiments, cell 300C includes one or more active regions (not shown) in addition to active region 240 disposed between portions B30 and B28, aligned with portions B30 and B28 along the X direction, and extending into protrusion 300P2.

[0083] Fig. 4 is an illustration of an active region 400 according to some embodiments. The active region 400 is usable as one or more of the active regions 210, 220, 230, or 240 described above with reference to Fig. 2 and Fig. 3. In addition to the active area 400 shows Fig. 4 the X and Y directions described above with reference to Fig. 2 to 4, a gate track TR and a gate region P. In some embodiments, the gate track TR corresponds to one of the gate tracks T1 to T6 discussed above with reference to Fig. 2 and Fig. 3 were discussed.

[0084] The active region 400 includes a number M of active lines 410[1]..410[M]. Each active line 410[1]..410[M] extends along the X-direction and at least partially defines a fin structure of a FinFET. In some embodiments, each active line 410[1]..410[M] is an active region separate from every other active line 410[1]..410[M]. In some embodiments, two or more of the active lines 410[1]..410[M] are portions of a same active region.

[0085] In various embodiments, the active region 400 includes the number M of active lines 410[1]..410[M], which is in the range of one to four. In some embodiments, the active region 400 includes a number M of active lines 410[1]..410[M] that is greater than 4. Since both a current capability of the FinFET and an area occupied by the FinFET increase with the increasing number M of active lines 410[1]..410[M], in some cases the number M is based on current and area design criteria for an IC including the active region 400.

[0086] The gate region P extends along the Y-direction, is arranged on the gate trace TR, and crosses each active line 410[1]..410[M]. The gate region P at least partially defines a gate electrode of a gate structure included in the FinFET. In various embodiments, the gate region P at least partially defines a gate electrode comprising one or more of a polysilicon layer, a metal layer, a work function layer, or another material suitable for controlling a channel of a FinFET.

[0087] At operation 120, a first active region is arranged in the cell by creating the first active region away from the first portion in a third direction opposite the second direction. In some embodiments, arranging the first active region in the cell includes revising the layout diagram. Creating the first active region away from the first portion in the third direction is based on arranging the first active region by aligning the first active region and the first portion in the second and third directions.

[0088] Since the second and third portions of the boundary are created away from the first portion in the second direction, creating the first active region in the third direction opposite to the second direction causes the first active region to be located within the cell boundary and aligned with the first boundary notch in the second and third directions.

[0089] In some embodiments, the second direction corresponds to the negative X direction and the third direction corresponds to the positive X direction, each of which was described above with reference to Fig. 2 to 4 and 5B1 to 5H2 were discussed.

[0090] In some embodiments, arranging the first active region comprises arranging the first active region within a protrusion of the cell boundary. In various embodiments, arranging the first active region comprises arranging the first active region within one of the boundary protrusions 200P1, 200P2, or 200P3 described above with reference to Fig. 2, or within one or more of the boundary projections 300P1, 300P2, 300P3 or 300P4 discussed above with reference to Fig. 3 were discussed.

[0091] In some embodiments, arranging the first active region in the cell comprises arranging the first active region such that it does not overlap a boundary recess of the cell. In various embodiments, arranging the first active region in the cell comprises arranging the first active region such that it overlaps one or more of the boundary recesses 200R1, 200R2, or 200R3 described above with reference to Fig. 2, or with one or more of the boundary recesses 300R1, 300R2, 300R3 or 300R4 discussed above with reference to Fig. 3 were discussed, do not overlap.

[0092] In various embodiments, arranging the first active region comprises arranging one or more of the active regions 210 to 240 in one of the cells 200C or 300C described above with reference to Fig. 2 and Fig. 3. In some embodiments, arranging the first active region comprises arranging the active region 400 discussed above with reference to Fig. 4 was discussed.

[0093] At operation 130, in some embodiments, a second active region is disposed in the cell. Disposing the second active region comprises disposing the second active region along the second and third directions, and therefore parallel to the first active region. In various embodiments, disposing the second active region comprises aligning one, both, or neither of a first or second endpoint of the second active region with a first or second endpoint of the first active region along the first direction.

[0094] In various embodiments, arranging the second active region comprises arranging the second active region defining one of an N-type or P-type active region, which is the same as or different from an active region defined by the first active region.

[0095] In various embodiments, arranging the second active region in the cell comprises arranging one or more of the active regions 210 to 240 in one of the cells 200C or 300C described above with reference to Fig. 2 and Fig. 3. In some embodiments, arranging the second active region comprises arranging the active region 400 discussed above with reference to Fig. 4 was discussed.

[0096] In some embodiments, arranging the second active region in the cell comprises arranging the first active region within a protrusion of the cell boundary. In various embodiments, arranging the second active region in the cell comprises arranging the second active region within one of the protrusions 200P1, 200P2, or 200P3 described above with reference to Fig. 2, or within one or more of the projections 300P1, 300P2, 300P3 or 300P4 discussed above with reference to Fig. 3 were discussed.

[0097] In some embodiments, arranging the second active region in the cell comprises arranging the second active region such that it does not overlap a boundary recess of the cell. In various embodiments, arranging the second active region in the cell comprises arranging the second active region such that it overlaps one or more of the boundary protrusions 200R1, 200R2, or 200R3 described above with reference to Fig. 2, or one or more of the boundary recesses 300R1, 300R2, 300R3 or 300R4 discussed above with reference to Fig. 3 were discussed, do not overlap.

[0098] In some embodiments, arranging the second active region comprises revising the IC layout diagram.

[0099] Fig. 5A is a schematic diagram of an IC 500 corresponding to IC layout diagrams 500B1 to 500H2, respectively shown in Fig. 5B1 to 5H2, according to some embodiments. The IC 500 is a transmission gate circuit, and each of the IC layout diagrams 500B1 to 500H2 is, in some embodiments, a non-limiting example of a corresponding IC layout diagram generated by performing one or more acts of the method 100.

[0100] The IC 500 includes a PMOS transistor P1 having a gate terminal A1, a PMOS transistor P2 having a gate terminal B1, an NMOS transistor N1 having a gate terminal B2, and an NMOS transistor N2 having a gate terminal A2. The gate terminal A1 is electrically connected to the gate terminal A2, and the gate terminal B1 is electrically connected to the gate terminal B2.

[0101] First source / drain terminals of transistors P1, P2, N1, and N2 are electrically connected to each other. A second source / drain terminal of transistor P1 is electrically connected to a second source / drain terminal of transistor N1, and a second source / drain terminal of transistor P2 is electrically connected to a second source / drain terminal of transistor N2.

[0102] Fig. 5B1, Fig. 5C1, Fig. 5D1, Fig. 5E1, Fig. 5F1, Fig. 5G1 and Fig. 5H1 show IC layout diagrams 500B1, 500C1, 500D1, 500E1, 500F1, 500G1 and 500H1, respectively, each of which is based on the cell 200C described above with reference to Fig. 2 was discussed. Fig. 5B2, Fig. 5C2, Fig. 5D2, Fig. 5E2, Fig. 5F2, Fig. 5G2 and Fig. 5H2 show IC layout diagrams 500B2, 500C2, 500D2, 500E2, 500F2, 500G2 and 500H2, respectively, each of which is based on the cell 300C described above with reference to Fig. 3 was discussed.

[0103] Each of the Fig. 5B1 to 5H2 shows one of the respective IC layout diagrams 500B1 to 500H2 having active regions 210 to 240 arranged according to one of the cells 200C or 300C, but for clarity does not show any of the boundaries 200B or 300B. In addition to the active regions 210 to 240, each IC layout diagram 500B1 to 500H2 has gate terminals A1, A2, B2, and B2 and additional IC layout elements that define electrical connections to and within an IC device, e.g., one of the devices described below with reference to Fig. 11 and Fig. 12 discussed IC devices 1100 or 1200, which are manufactured on the basis of the respective IC layout diagram 500B1 to 500H2 and correspond to the IC 500.

[0104] In the Fig. 5B1 to 5H2, the additional IC layout elements include gate regions P1 to P5, conductive regions MD1 to MD5, and conductive regions M1 and M2 extending along the Y direction, conductive regions M01 to M07B, and a cut poly region CP extending along the X direction, vias Vo and V1.

[0105] Each gate region P1 to P5 at least partially defines a gate electrode of a gate structure included in a transistor structure. In various embodiments, one or more of the gate regions P1 to P5 at least partially define a gate electrode of a FET, a FinFET, or a dummy device. In various embodiments, one or more of the gate regions P1 to P5 at least partially define a gate electrode comprising one or more of a polysilicon layer, a metal layer, a work function layer, or another material suitable for controlling a channel.

[0106] The gate regions P1 to P2 are arranged at positions corresponding to subgroups of the tracks T1 to T6 described above with reference to Fig. 2 and Fig. 3 were discussed.

[0107] Each conductive region MD1 to MD5 at least partially defines a portion of a conductive layer that is electrically connected to an underlying active region. In some embodiments, one or more of the conductive regions MD1 to MD5 are referred to as a metal diffusion region. In various embodiments, one or more of the conductive regions MD1 to MD5 at least partially define a portion of a conductive layer that includes copper or another metal suitable for forming an electrical connection with an underlying active region.

[0108] The conductive regions MD1 to MD5 are arranged at positions parallel to and separated from the positions where the gate regions P1 to P5 are arranged.

[0109] Each conductive region M1 and M2 at least partially defines a portion of a conductive layer overlying the other additional elements of the IC device. In some embodiments, the conductive regions M1 and M2 define portions in a metal-one layer of the IC device. In various embodiments, one or more of the conductive regions M1 and M2 at least partially define a portion of a conductive layer comprising copper or another metal suitable for forming electrical connections in and with the IC device.

[0110] Each conductive region M01 to M07B at least partially defines a portion of a conductive layer that lies above portions defined by conductive regions MD1 to MD5 and gate electrodes defined by gate regions P1 to P5, and below portions defined by conductive regions M1 and M2. In some embodiments, conductive regions M01 to M07B define portions in a metal zero layer of the IC device. In various embodiments, one or more of conductive regions M01-M07B at least partially define a portion of a conductive layer that includes copper or another metal suitable for forming electrical connections in the IC device.

[0111] The cut poly region CP at least partially defines a region in which one or more gate electrodes defining the gate regions P1 to P5 are prevented from being formed, so that a gate region P1 to P5 crossed by the cut poly region CP is divided into separately controllable gate electrodes.

[0112] Each via Vo (only one of which is identified for clarity) is a conductive region that at least partially defines a portion of a conductive layer between a portion defined by a conductive region M01 to M07B and either an underlying portion defined by a conductive region MD1 to MD5 or an underlying gate electrode defined by a gate region P1 to P5. In various embodiments, one or more of the vias Vo at least partially define a portion of a conductive layer comprising copper or another metal suitable for forming electrical connections in the IC device.

[0113] Each via V1 (only one is identified for clarity) is a conductive region that at least partially defines a portion of a conductive layer between a portion defined by a conductive region M1 or M2 and an underlying portion defined by a conductive region M01 to M07B. In various embodiments, one or more of the vias V1 at least partially define a portion of a conductive layer comprising copper or another metal suitable for forming electrical connections in the IC device.

[0114] Fig. 5B1 shows an IC layout diagram 500B1 having a cut poly region CP that separates gate region P2 into gate terminals A1 and B2, and gate region P3 into gate terminals B1 and A2. Gate terminal A1 is electrically connected to gate terminal A2 via conductive regions M01, M04, and M05B and four vias Vo. Gate terminal B1 is electrically connected to gate terminal B2 via conductive region M03, conductive region P5, conductive region M07, and four vias Vo.

[0115] Fig. 5B2 shows an IC layout diagram 500B2 including a cut poly region CP that separates gate region P2 into gate terminals A1 and B2, and gate region P3 into gate terminals B1 and A2. Gate terminal A1 is electrically connected to gate terminal A2 via conductive regions M01, M04, and M07 and four vias Vo. Gate terminal B1 is electrically connected to gate terminal B2 via conductive region M03B, conductive region P5, conductive region M05, and four vias Vo.

[0116] Fig. 5C1 shows an IC layout diagram 500C1 including a cut poly region CP that separates gate region P2 into gate terminals A1 and B2, and gate region P3 into gate terminals B1 and A2. Gate terminal A1 is electrically connected to gate terminal A2 via conductive region Mo1, conductive region P5, conductive region Mo5, and four vias Vo. Gate terminal B1 is electrically connected to gate terminal B2 via conductive regions Mo3, Mo4, and Mo7 and four vias Vo.

[0117] Fig. 5C2 shows an IC layout diagram 500C2, which includes a cut poly region CP that separates gate region P2 into gate terminals A1 and B2, and gate region P3 into gate terminals B1 and A2. Gate terminal A1 is electrically connected to gate terminal A2 via conductive region Mo1, conductive region P5, conductive region Mo7, and four vias Vo. Gate terminal B1 is electrically connected to gate terminal B2 via conductive regions Mo3B, Mo4, and Mo5 and four vias Vo.

[0118] Fig. 5D1 shows an IC layout diagram 500D1, which includes a cut poly region CP that separates gate region P2 into gate terminals A1 and B2, and gate region P3 into gate terminals B1 and A2. Gate terminal A1 is electrically connected to gate terminal A2 via conductive regions Mo1, M1, Mo5, two vias V0, and two vias V1. Gate terminal B1 is electrically connected to gate terminal B2 via conductive regions Mo3, M2, and Mo7, two vias Vo, and two vias V1.

[0119] Fig. 5D2 shows an IC layout diagram 500D2, which includes a cut poly region CP that separates gate region P2 into gate terminals A1 and B2, and gate region P3 into gate terminals B1 and A2. Gate terminal A1 is electrically connected to gate terminal A2 via conductive regions M01, M1, M07, two vias Vo, and two vias V1. Gate terminal B1 is electrically connected to gate terminal B2 via conductive regions M03, M2, and Mo5, two vias Vo, and two vias V1.

[0120] Fig. 5E1 shows an IC layout diagram 500E1, which includes a cut poly region CP that separates gate region P2 into gate terminals A1 and B2. Gate terminal P3 corresponds to gate terminal A2, and gate terminal P4 corresponds to gate terminal B1. Gate terminal A1 is electrically connected to gate terminal A2 via conductive region MO1 and two vias V0. Gate terminal B1 is electrically connected to gate terminal B2 via conductive region MO7 and two vias V0.

[0121] Fig. 5E2 shows an IC layout diagram 500E2, which includes a cut poly region CP that separates gate region P2 into gate terminals A1 and B2. Gate terminal P3 corresponds to gate terminal B1, and gate terminal P4 corresponds to gate terminal A2. Gate terminal A1 is electrically connected to gate terminal A2 via conductive region MO1 and two vias V0. Gate terminal B1 is electrically connected to gate terminal B2 via conductive region MO5 and two vias V0.

[0122] Fig. 5F1 and Fig. 5F2 show IC layout diagrams 500F1 and 500F2, respectively, neither of which has the cut poly region CP. In each of the IC layout diagrams 500F1 and 500F2, the gate region P3 corresponds to the gate terminals A1 and A2, and the gate region P4 corresponds to the gate terminals B1 and B2.

[0123] Fig. 5G1 and Fig. 5G2 show IC layout diagrams 500G1 and 500G2, respectively, neither of which has the cut poly region CP. In each of the IC layout diagrams 500G1 and 500G2, the gate region P2 corresponds to the gate terminals A1 and A2, and the gate region P3 corresponds to the gate terminals B1 and B2.

[0124] Fig. 5H1 and Fig. 5H2 show IC layout diagrams 500H1 and 500H2, respectively, neither of which has the cut poly region CP. In each of the IC layout diagrams 500H1 and 500H2, the gate region P2 corresponds to the gate terminals A1 and A2, and the gate region P3 corresponds to the gate terminals B1 and B2.

[0125] At operation 140, in some embodiments, one or more gate regions are arranged in the cell. Arranging the one or more gate regions includes arranging the one or more gate regions along the first direction.

[0126] Arranging the one or more gate regions comprises arranging at least one gate region to cross at least two active regions of the cell, wherein a third active region of the cell is arranged between the at least two active regions. An active region is considered to cross a gate region if it extends through the gate region and away from the gate region in both the second and third directions.

[0127] Arranging the at least one gate region to cross the at least two active regions provides that the third active region extends away from the at least one gate region in only one of the second and third directions. In some embodiments, a gate region of the at least one gate region overlaps an edge of the third active region. In various embodiments, a gate region of the at least one gate region has a PODE (edge ​​of a poly on OD (active region)) or a continuous PODE (CPODE) region that overlaps an edge of the third active region. In some embodiments, no gate region of the at least one gate region overlaps an edge of the third active region.

[0128] In various embodiments, arranging the one or more gate regions comprises arranging one or more of the gate regions P2 to P4 as shown in Fig. 5B1 to 5H2. In various embodiments, arranging the at least one gate region to cross the at least two active regions comprises arranging the gate region P2 or P3 to cross the active regions 210 and 240, as shown in the non-limiting examples shown in Fig. 5B1, Fig. 5C1, Fig. 5D1, Fig. 5E1, Fig. 5F1, Fig. 5G1 and Fig. 5H1. In various embodiments, arranging the at least one gate region to cross the at least two active regions comprises arranging the gate region P2 or P3 to cross the active regions 210 and 230, or arranging the gate region 3 or 4 to cross the active regions 210 and 240, as in the non-limiting examples shown in Fig. 5B2, Fig. 5C2, Fig. 5D2, Fig. 5E2, Fig. 5F2, Fig. 5G2 and Fig. 5H2, which are non-limiting examples.

[0129] In various embodiments, arranging the one or more gate regions in the cell comprises arranging one or more gate regions in addition to the at least one gate region corresponding to the third active region, extending away from the at least one gate region in only one of the second and third directions. In various embodiments, arranging the one or more additional gate regions comprises arranging the one or more additional gate regions such that they intersect the third active region or such that they have a combination of the configurations discussed above.

[0130] In some embodiments, arranging the one or more gate regions comprises arranging one or more cut poly regions. Arranging the one or more cut poly regions comprises dividing one or more gate regions into two or more sections. In various embodiments, arranging the one or more cut poly regions comprises arranging the cut poly region CP as shown in the Fig. 5B1 to 5E2.

[0131] In some embodiments, arranging the one or more gate regions comprises arranging at least one gate region at a position corresponding to a gate track. In various embodiments, arranging at least one gate region at a position corresponding to a track comprises arranging at least one gate region at a position corresponding to at least one of the tracks T1 to T6 described above with reference to Fig. 2 and Fig. 3 were discussed.

[0132] In some embodiments, arranging the one or more gate regions in the cell comprises arranging at least one gate region extending into a boundary recess of the cell. In various embodiments, arranging at least one gate region extending into a boundary recess comprises arranging at least one gate region extending into one or both of the boundary recesses 200R1 or 200R2 or into the boundary recess 200R3 described above with reference to Fig. 2. In various embodiments, arranging at least one gate region extending into a boundary recess comprises arranging at least one gate region extending into one or both of the boundary recesses 300R1 or 300R2 or into one or both of the boundary recesses 300R3 or 300R4 discussed above with reference to Fig. 3 were discussed.

[0133] In some embodiments, arranging the one or more gate regions in the cell comprises arranging at least one gate region within a boundary protrusion of the cell. In various embodiments, arranging at least one gate region within a boundary protrusion comprises arranging at least one gate region within the boundary protrusion 200P1 or within one or both of the boundary protrusions 200P2 or 200P3 described above with reference to Fig. 2. In various embodiments, arranging at least one gate region within a boundary protrusion comprises arranging at least one gate region extending within one or both of the boundary protrusions 300P1 or 300P2 or within one or both of the boundary protrusions 300P3 or 300P4 discussed above with reference to Fig. 3 were discussed.

[0134] In some embodiments, arranging the one or more gate regions in the cell comprises revising the layout diagram.

[0135] At operation 150, in some embodiments, one or more conductive regions are disposed in the cell. Disposing the one or more conductive regions includes disposing one or more regions in an IC layout diagram that at least partially define one or more IC device features capable of forming an electrical connection with active areas and / or gate electrodes defined by the active and gate regions.

[0136] In various embodiments, arranging the one or more conductive regions comprises arranging the one or more conductive regions along the first direction and / or along the second and third directions. In various embodiments, arranging the one or more conductive regions comprises arranging one or more regions that at least partially define one or more of a metal diffusion portion, a source / drain contact, a metal zero portion, a metal one portion, a higher-level metal portion, or a via extending from a metal diffusion portion or a gate electrode to an overlying metal portion.

[0137] In various embodiments, arranging the one or more conductive regions comprises arranging one or more of the conductive regions MD1 to MD5, M1, M2 or M01 to M07B, or vias Vo or V1, as shown in the figures shown in Fig. 5B1 to 5H2, which are non-limiting examples.

[0138] In some embodiments, arranging the one or more conductive regions comprises arranging at least one of the one or more conductive regions within a protrusion of the cell boundary. In various embodiments, arranging the one or more conductive regions in the cell comprises arranging at least one of the one or more conductive regions within one of the protrusions 200P1, 200P2, or 200P3 described above with reference to Fig. 2, or within one or more of the projections 300P1, 300P2, 300P3 or 300P4 discussed above with reference to Fig. 3 were discussed.

[0139] In some embodiments, arranging the one or more conductive regions in the cell comprises arranging at least one of the one or more conductive regions such that they do not overlap a boundary recess of the cell. In various embodiments, arranging the one or more conductive regions in the cell comprises arranging at least one of the one or more conductive regions such that they overlap one or more of the boundary protrusions 200R1, 200R2, or 200R3 described above with reference to Fig. 2, or one or more of the boundary recesses 300R1, 300R2, 300R3 or 300R4 discussed above with reference to Fig. 3 were discussed, do not overlap.

[0140] In some embodiments, arranging the one or more conductive regions in the cell comprises revising the layout diagram.

[0141] At operation 160, in some embodiments, the revised layout diagram is stored in a storage device. In various embodiments, storing the layout diagram in the storage device comprises storing the layout diagram in a non-transitory, computer-readable memory or cell library, e.g., a database, and / or comprises storing the layout diagram over a network. In some embodiments, storing the layout diagram in the storage device comprises storing the layout diagram over a network 1314 of the EDA system 1300, described below with reference to Fig. 13 is discussed.

[0142] At operation 170, in some embodiments, at least one of one or more semiconductor masks, or at least one component in a layer of a semiconductor IC, is fabricated based on the revised layout diagram. Fabricating one or more semiconductor masks or at least one component in a layer of a semiconductor IC is described below with reference to Fig. 14 discussed.

[0143] At operation 180, in some embodiments, one or more manufacturing operations are performed based on the revised layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the layout diagram. Performing one or more manufacturing operations, e.g., one or more lithographic exposures, based on the layout diagram is described below with reference to Fig. 14 discussed.

[0144] By performing some or all of the acts of method 100, an IC layout diagram is generated in which a cell has a gate region that crosses one or more active regions in cell 100C and is capable of crossing one or more active regions of a neighboring cell. IC layout diagrams and IC devices fabricated based on the IC layout diagrams can thereby avoid dummy gate regions at cell boundaries, thereby reducing area requirements compared to approaches that do not have a gate region that crosses one or more active regions in a cell and is capable of crossing one or more active regions of a neighboring cell.

[0145] Fig. 6 is a flow diagram of a method 600 for generating a layout diagram of an IC according to some embodiments. The acts of method 600 may be performed as part of a method for forming one or more IC devices, e.g., one of the methods described below, each with reference to Fig. 11 and 12, respectively, which are manufactured based on the generated IC layout diagram. Non-limiting examples of IC devices include memory circuits, logic devices, processing devices, signal processing circuits, and the like.

[0146] In some embodiments, some or all of the acts of method 600 may be performed as part of an APR process. In some embodiments, some or all of the acts of method 600 may be performed by an APR system, e.g., a system described in the following with reference to Fig. 13 discussed EDA system 1300 and is designed to perform the APR procedure.

[0147] Some or all of the operations of method 600 may be performed as part of a design process performed in a design house, e.g., a design house 1420, described below with reference to Fig. 14 is discussed.

[0148] In some embodiments, part or all of the method 600 is performed by a processor of a computer. In some embodiments, part or all of the method 600 is performed by a processor 1302 of a computer described below with reference to Fig. 13 discussed EDA system 1300.

[0149] In some embodiments, the operations of method 600 are performed in the manner described in Fig. 6. In some embodiments, the operations of method 600 are performed in a different order than those shown in Fig. 6. In some embodiments, one or more operations are performed before, between, during, and / or after performing one or more operations of method 600.

[0150] Fig. 7 to 10 are illustrations of non-limiting examples of respective IC layout diagrams 700 to 1000 that are generated in some embodiments by performing one or more acts of method 600. The IC layout diagrams 700 to 1000 are simplified for clarity. In various embodiments, one or more IC layout diagrams 700 to 1000, in addition to those shown in Fig. 7 to 10, features such as one or more transistor elements, supply rails, insulation structures, wells, conductive elements or the like.

[0151] Fig. 7 is an illustration of an IC layout diagram 700 according to some embodiments. The layout diagram 700 includes cells 200C1-1 and 200C-2, active regions 210-1, 220-1, 230-1, and 240-2, gate traces T1 through T7, a gate pitch GP, gate regions P1 through P7, a place-and-route (PR1) boundary PR1, and the X and Y directions. In various embodiments, the IC layout diagram 700 includes one or more active regions (not shown) in addition to the active regions 210-2, 220-1, 230-1, and 240-2.

[0152] Fig. 8 is an illustration of an IC layout diagram 800 according to some embodiments. The layout diagram 800 includes cells 300C1-1 and 300C-2, active regions 210-2, 220-1, 230-2, and 240-1, gate traces T1 through T7, a gate pitch GP, gate regions P1 through P7, a place-and-route (PR1) boundary PR1, and the X and Y directions. In various embodiments, the IC layout diagram 800 includes one or more active regions (not shown) in addition to the active regions 210-2, 220-1, 230-2, and 240-1.

[0153] Fig. 9 is an illustration of an IC layout diagram 900 according to some embodiments. The layout diagram 900 includes cells 200C-1 through 200C-5 and the X and Y directions.

[0154] Fig. 10 is an illustration of an IC layout diagram 1000 according to some embodiments. The layout diagram 1000 includes cells 300C-1 through 300C-5 and the X and Y directions.

[0155] Each of the cells 200C-1 to 200C-5 is an embodiment of the cell 200C described above with reference to Fig. 2, and each of the cells 300C1 to 300C-5 is an embodiment of the cell 300C discussed above with reference to Fig. 3. Each of the active regions 210-2, 220-1, 230-1, 230-2, 240-1 and 240-2 is an embodiment of a respective active region 210 to 240 discussed above with reference to Fig. 2 and Fig. 3 were discussed.

[0156] The gate tracks T1 to T7 and the gate pitch GP correspond to the gate tracks T1 to T6, which have the pitch GP, which was described above with reference to Fig. 2 and Fig. 3. The gate regions P1 and P7 correspond to the gate regions P1 to P6 discussed above with reference to Fig. 5B1 to 5H2. The X and Y directions were discussed above with reference to Fig. 2 to 4 and 5B1 to 5H2 are discussed.

[0157] Each of the pr boundaries PR1 and PR2 is a closed boundary defining an area within which a set of electrical connections are routed to and / or from various features within the closed boundary from and / or to various features outside the area defined by the closed boundary. In some embodiments, the one or more routing operations are part of an APR method.

[0158] In various embodiments, one or more of the IC layout diagrams 700 to 1000 include, in addition to the two or more cells 200C-1 to 200C-5 or cells 300C-1 to 300C-5 shown in Fig. 7 to 10, one or more cells (not shown) on

[0159] In the IC layout diagram 700, as shown in Fig. 7, cell 200C-1 has boundary recesses 200R1-1 to 200R3-1 and boundary protrusions 200P1-1 to 200P3-1, and cell 200C-1 has boundary recesses 200R1-2 to 200R3-2 and boundary protrusions 200P1-2 to 200P3-2. The respective boundary recesses correspond to the boundary recesses 200R1 to 200R3, and the respective boundary protrusions correspond to the boundary protrusions 200P1 to 200P3, each of which was described above with reference to Fig. 2 was discussed.

[0160] Cell 200C-1 is adjacent to cell 200C-2, whereby boundary projection 200P1-1 is fitted in boundary recess 200R3-2, boundary projection 200P2-2 is therefore fitted in boundary recess 200R2-1, and boundary projection 200P3-2 is therefore fitted in boundary recess 200R1-1.

[0161] Each of the gate regions P4 and P5 is aligned along the Y direction at a position corresponding to the respective gate traces TR4 and TR5 and is included in both cells 200C-1 and 200C-2. The gate region P4 crosses the boundary protrusion 200P1-1, and the gate region P5 crosses the boundary protrusions 200P2-2 and 200P3-2.

[0162] Gate region P4 also crosses active regions 200-1 and 230-1 and can therefore be used in one or more transistors having one or more components in protrusion 200P1-1. Gate region P5 also crosses active regions 210-2 and 240-2 and can therefore be used in one or more transistors having one or more components in one or both of protrusions 200P2-2 or 200P3-2.

[0163] Since each of the adjacent gate regions P4 and P5 is included in both cell 200C-1 and 200C-2 and can be used in one or more transistors, the IC layout diagram 700 includes cell 200C-1 adjacent to cell 200C-2 without a dummy gate region between cells 200C-1 and 200C-2.

[0164] In the IC layout diagram 800, as shown in Fig. 8, cell 300C-1 has boundary recesses 300R1-1 to 300R4-1 and boundary protrusions 300P1-1 to 300P4-1, and cell 300C-1 has boundary recesses 300R1-2 to 300R4-2 and boundary protrusions 300P1-2 to 300P4-2. The respective boundary recesses correspond to the boundary recesses 300R1 to 300R4, and the respective boundary protrusions correspond to the boundary protrusions 300P1 to 300P4, each of which was described above with reference to Fig. 3 was discussed.

[0165] Cell 300C-1 is adjacent to cell 300C-2, whereby boundary projection 300P1-1 is fitted in boundary recess 300R4-2, boundary projection 300P2-1 is therefore fitted in boundary recess 300R3-2, boundary projection 300P3-2 is therefore fitted in boundary recess 300R2-1, and boundary projection 300P4-2 is therefore fitted in boundary recess 300R1-1.

[0166] Each of the gate regions P4 and P5 is aligned along the Y direction at a position corresponding to the respective gate traces TR4 and TR5 and is included in both cells 300C-1 and 300C-2. The gate region P4 crosses the boundary protrusions 300P1-1 and 300P2-1, and the gate region P5 crosses the boundary protrusions 300P3-2 and 300P4-2.

[0167] Gate region P4 also crosses active regions 220-1 and 240-1 and can therefore be used in one or more transistors having one or more components in one or both of protrusions 300P1-1 or 300P2-1. Gate region P5 also crosses active regions 210-2 and 230-2 and can therefore be used in one or more transistors having one or more components in one or both of protrusions 300P3-2 and 300P4-2.

[0168] Since each of the adjacent gate regions P4 and P5 is included in both cell 300C-1 and 300C-2 and can be used in one or more transistors, the IC layout diagram 800 includes cell 300C-1 adjacent to cell 300C-2 without a dummy gate region between cells 300C-1 and 300C-2.

[0169] In IC layout 700, as in Fig. 7, each of the cells 200C-1 and 200C-2 has an equal height (not labeled) in the Y direction. In the IC layout diagram 900, as shown in Fig. As shown in Figure 9, cell 200C-2 has a height (not labeled) that is different from the heights (not labeled) of each of cells 200C-1, 200C-3, 200C-4, and 200C-5, and cell 200C-2 has a greater number of recesses and protrusions than included in each of cells 200C-1, 200C-3, 200C-4, and 200C-5. Cell 200C-2 may thereby be adjacent to multiple cells in one or both of the positive and negative X directions.

[0170] In the Fig. In the embodiment illustrated in Figure 9, cell 200C-2 is adjacent to two cells, cell 200C-1 and cell 200C-4, in the negative X direction and two cells, cell 200C-3 and cell 200C-5, in the positive X direction. In various embodiments, cell 200C-2 is adjacent to fewer or more than two cells in one or both of the negative or positive X directions.

[0171] In IC layout 800, as in Fig. 8, each of the cells 300C-1 and 300C-2 has an equal height (not labeled) in the Y direction. In the IC layout diagram 1000, as shown in Fig. As shown in Figure 10, cell 300C-2 has a height (not labeled) that is different from the heights (not labeled) of each of cells 300C-1, 300C-3, 300C-4, and 300C-5, and cell 300C-2 has a greater number of recesses and protrusions than included in each of cells 300C-1, 300C-3, 300C-4, and 300C-5. Cell 300C-2 may thereby be adjacent to multiple cells in one or both of the positive and negative X directions.

[0172] In the Fig. In the embodiment illustrated in Figure 10, cell 300C-2 is adjacent to two cells, cell 300C-1 and cell 300C-4, in the negative X direction and two cells, cell 300C-3 and cell 300C-5, in the positive X direction. In various embodiments, cell 300C-2 is adjacent to fewer or more than two cells in one or both of the negative or positive X directions.

[0173] At operation 610, in some embodiments, a layout diagram of a first cell and a layout diagram of a second cell are received. In various embodiments, receiving the layout diagrams of the first and second cells includes receiving a layout diagram of a standard cell, a custom cell, an engineering change order (ECO) cell, a logic gate cell, a memory cell, or another type of cell or combination of cells that can be defined in an IC layout diagram. In various embodiments, a logic gate cell comprises a layout diagram of one or more of an AND, OR, NAND, NOR, XOR, INV, AND-OR invert (AOI), OR-AND invert (OAI), MUX, flip-flop, BUFF, latch, delay, or clock device.In various embodiments, a memory cell comprises a layout diagram of one or more of an SRAM (Static Random Access Memory), a DRAM (Dynamic RAM), an RRAM (Resistive RAM), an MRAM (Magnetoresistive RAM), or a ROM (Read Only Memory) cell, or other device capable of having multiple states representing logical values.

[0174] In some embodiments, receiving the layout diagrams of the first and second cells comprises receiving one or more IC layout diagrams by performing some or all of the acts of method 100 described above with reference to Fig. 1. In various embodiments, receiving the layout diagrams of the first and second cells includes receiving one or both of the cells 200C or 300C discussed above with reference to Fig. 2 and Fig. 3, and / or receiving two or more of the cells 200C-1 to 200C-4 discussed above with reference to Fig. 7 and Fig. 9, and / or receiving two or more of the cells 300C-1 to 300C-5 discussed above with reference to Fig. 8 and Fig. 10 were discussed,

[0175] In various embodiments, receiving the layout diagrams of the first and second cells comprises receiving one or more electronic files and / or receiving the layout diagrams of the first and second cells from a cell library. In some embodiments, receiving the layout diagrams of the first and second cells comprises receiving the layout diagrams of the first and second cells over a network. In some embodiments, receiving the layout diagrams of the first and second cells comprises receiving the layout diagrams of the first and second cells over the network 1314 of the EDA system 1300, which is described below with reference to Fig. 13 is discussed.

[0176] In some embodiments, receiving the layout diagrams of the first and second cells comprises receiving one or more layouts 1422 produced by an IC manufacturing system as part of an IC manufacturing flow, e.g., the IC manufacturing system 1400 described below with reference to Fig. 14 is discussed.

[0177] Receiving the layout diagrams of the first and second cells includes receiving the layout diagram of the first cell having at least one boundary protrusion and the layout of the second cell having at least one boundary recess.

[0178] In some embodiments, receiving the layout diagrams of the first and second cells comprises receiving the layout diagrams of the first cell and the second cell having the same gate pitch. In some embodiments, receiving the layout diagrams of the first and second cells comprises receiving the layout diagrams of the first cell and the second cell having different gate pitches.

[0179] In some embodiments, receiving the layout diagrams of the first and second cells comprises receiving the layout diagrams of the first cell and the second cell having gate pitches where one gate pitch is a multiple of the other gate pitch. In some embodiments, receiving the layout diagrams of the first and second cells comprises modifying one or more gate pitches such that the layout diagrams of the first cell and the second cell have the same gate pitch.

[0180] In some embodiments, receiving the layout diagrams of the first and second cells comprises receiving at least one of the layout diagrams of the first or second cells having one or more conductive regions arranged therein. In various embodiments, the one or more conductive regions comprise one or more conductive regions defined by the conductive regions MD1 to MD5, M1, M2, M01 to M07B, the via Vo, or the via V1 described above with reference to Fig. 5B to 5H2.

[0181] At operation 620, the first cell is adjacent to the second cell by fitting a boundary protrusion of the first cell into a boundary recess of the second cell and a first gate region of the IC layout intersecting the boundary protrusion and a first active region of the second cell.

[0182] In some embodiments, fitting the boundary protrusion of the first cell into the boundary recess of the second cell provides that the boundary protrusion of the first cell coincides with the boundary recess of the second cell. In some embodiments, fitting the boundary protrusion of the first cell into the boundary recess of the second cell includes leaving one or more gaps between the boundary protrusion of the first cell and the boundary recess of the second cell.

[0183] In some embodiments, fitting the boundary protrusion of the first cell into the boundary recess of the second cell comprises fitting more than one boundary protrusion of the first cell into more than one boundary recess of the second cell. In some embodiments, fitting the boundary protrusion of the first cell into the boundary recess of the second cell comprises fitting one or more boundary protrusions of the second cell into one or more boundary recesses of the first cell.

[0184] In various embodiments, adjoining the first cell to the second cell comprises adjoining the first cell to one or more cells in addition to the second cell by one or more of fitting one or more boundary protrusions of the first cell into one or more boundary recesses of the second and / or additional cells, or fitting one or more boundary protrusions of the second and / or additional cell into one or more boundary recesses of the first cell.

[0185] In some embodiments, adjoining the first cell in the second cell comprises adjoining one or more of the cells 20C-1 to 200C-5 or 300C-1 to 300C-5 to another or more of the cells 200C-1 to 200C-5 or 300C-1 to 300C-5 described above with reference to Fig. 7 to 10 were discussed.

[0186] In some embodiments, intersecting the first gate region with the boundary protrusion and the first active region comprises forming the first active region by merging a gate region of the first cell with a gate region of the second cell. In various embodiments, intersecting the first gate region with the boundary protrusion and the first active region comprises either intersecting the first gate region of the first cell with the first active region of the second cell or intersecting the first gate region of the second cell with the boundary protrusion of the first cell.

[0187] In various embodiments, crossing the first gate region with the boundary protrusion and the first active region comprises one or both of crossing the first gate region with one or more additional boundary protrusions of the first cell or crossing the first gate region with one or more additional active regions of the second cell.

[0188] In various embodiments, crossing the first gate region with the boundary protrusion and the first active region comprises one or both of crossing the first gate region with one or more boundary protrusions of one or more additional cells or crossing the first gate region with one or more active regions of one or more additional cells.

[0189] In various embodiments, crossing the first gate region with the boundary protrusion comprises crossing one or more of the gate regions P1 to P7 with one or more of the boundary protrusions 200P1-1 to 200P3-1 to 300P4-2 described above with reference to Fig. 7 and Fig. 8. In various embodiments, crossing the first gate region with the first active region comprises crossing one or more of the gate regions P1 to P7 with one or more of the active regions 210-1 to 240-2 discussed above with reference to Fig. 7 and Fig. 8 were discussed.

[0190] In some embodiments, crossing the first gate region with the boundary protrusion and the first active region comprises aligning the first cell and the second cell based on a gate trace. In some embodiments, aligning the first cell and the second cell based on the gate trace comprises aligning the first cell and the second cell based on one or more gate traces T1 to T7 described above with reference to Fig. 2, Fig. 3, Fig. 7 and Fig. 8 were discussed.

[0191] In some embodiments, adjoining the first cell to the second cell comprises revising the IC layout diagram.

[0192] At operation 630, in some embodiments, the first cell and the second cell are arranged within a pr boundary. In some embodiments, arranging the first cell and the second cell within the pr boundary includes arranging the first cell and the second cell within a distance from the pr boundary PR1 or PR2, each of which is described above with reference to Fig. 7 and 8 respectively.

[0193] In some embodiments, arranging the first cell and the second cell within the pr boundary includes forming one or more clearer regions in the pr boundary that correspond to one or more boundary recesses of one or both of the first cell or the second cell.

[0194] In some embodiments, arranging the first cell and the second cell within the pr boundary includes revising the IC layout diagram.

[0195] At operation 640, in some embodiments, one or more electrical connections are routed to the first cell and the second cell. In some embodiments, routing the one or more electrical connections includes routing the one or more electrical connections in accordance with the pr boundary.

[0196] In some embodiments, routing the electrical connections comprises routing the electrical connections as part of an APR method. In some embodiments, routing the electrical connections is performed by an APR system, e.g., a system described below with reference to Fig. 13 discussed EDA system 1300 and is designed to perform the APR procedure.

[0197] Routing the one or more electrical connections includes arranging one or more conductive regions in the IC layout diagram. Arranging a conductive region includes defining, at least in part, a region in a conductive layer, e.g., metal one, metal two, etc., such that a portion of the conductive layer in an IC device fabricated based on the IC layout diagram forms an electrical connection with one or more underlying elements of the IC device. In various embodiments, arranging one or more conductive regions at least in part defines a portion of a conductive layer comprising copper or another metal suitable for forming electrical connections with the IC device.

[0198] In various embodiments, arranging the one or more conductive regions in the IC layout diagram comprises arranging one or more conductive regions defined by the conductive regions MD1 to MD5, M1, M2, Mo1 to Mo7B, the via V0, or the via V1 described above with reference to Fig. 5B to 5H2.

[0199] In some embodiments, routing the electrical connections to the first cell and the second cell includes revising the IC layout diagram.

[0200] At operation 650, in some embodiments, the revised layout diagram is stored in a storage device. In various embodiments, storing the layout diagram in the storage device comprises storing the layout diagram in a non-transitory, computer-readable memory or cell library, e.g., a database, and / or comprises storing the layout diagram over a network. In some embodiments, storing the layout diagram in the storage device comprises storing the layout diagram over a network 1314 of the EDA system 1300, described below with reference to Fig. 13 is discussed.

[0201] At operation 660, in some embodiments, at least one of one or more semiconductor masks, or at least one component in a layer of a semiconductor IC, is fabricated based on the revised layout diagram. Fabricating one or more semiconductor masks or at least one component in a layer of a semiconductor IC is described below with reference to Fig. 14 discussed.

[0202] At operation 670, in some embodiments, one or more manufacturing operations are performed based on the revised layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the layout diagram. Performing one or more manufacturing operations, e.g., one or more lithographic exposures, based on the layout diagram is described below with reference to Fig. 14 discussed.

[0203] By performing some or all of the acts of method 600, an IC layout diagram is generated in which adjacent cells have a gate region that crosses a boundary protrusion of one of the adjacent cells 100C and crosses one or more active regions of the other of the adjacent cells. IC layout diagrams and IC devices fabricated based on the IC layout diagrams can therefore avoid dummy gate regions at cell boundaries, thereby reducing area requirements compared to approaches that do not have a gate region that crosses one or more active regions in a cell and is capable of crossing one or more active regions of a neighboring cell.

[0204] Fig. 11 is a diagram of an IC device 1100 according to some embodiments. The IC device 1100 is formed by performing some or all of the operations of method 100 and / or 600 and is formed according to the IC layout diagrams 200 and 700 described above, respectively, with reference to Fig. 2 and 7 respectively.

[0205] Fig. 12 is a diagram of an IC device 1200 according to some embodiments. The IC device 1200 is formed by performing some or all of the operations of method 100 and / or 600 and is formed according to the IC layout diagrams 300 and 800 described above, respectively, with reference to Fig. 3 and 8 respectively.

[0206] The representations of the IC device 1100 in Fig. 11 and the IC device 1200 in Fig. 12 are simplified for clarity. Fig. 11 and Fig. 12 show top views of the IC devices 1100 and 1200, with various features included or omitted to simplify the discussion below. Each of the Fig. 11 and Fig. 12 also shows the X and Y directions described above with reference to Fig. 2 and Fig. 3 were discussed.

[0207] The IC device 1100 includes active regions 1110, 1120, 1130, and 1140, each extending along the X-direction, and gate structures G1 and G2, each extending along the Y-direction and overlying each of the active regions 1110, 1120, 1130, and 1140.

[0208] The active regions 1110, 1120, 1130 and 1140 are N-type or P-type active regions designed according to respective active regions 210, 220, 230 and 240, and the gate structures G1 and G2 are gate structures designed according to different ones of the gate regions P1 to P6, each of which was described above with reference to Fig. 2 and Fig. 3 was discussed.

[0209] In the Fig. 11, the IC device 1100 includes four active regions and two gate structures. In various embodiments, the IC device 1100 includes fewer or more than four active regions and / or fewer or more than two gate structures, each configured according to respective active and gate regions, as described above with reference to the IC layout diagram 200 in Fig. 2 was discussed.

[0210] According to the IC layout diagram 200, the gate structure G1 overlies edges of the active regions 1120 and 1130, each of the active regions 1110 and 1140 extends through the gate structure G1, the gate structure overlies edges of the active regions 1110 and 1140, and each of the active regions 1120 and 1130 extends through the gate structure G2.

[0211] In various embodiments, one or more of the gate structure G1 and the active region 1110, the gate structure G1 and the active region 1140, the gate structure G2 and the active region 1120, or the gate structure G2 and the active region 1130 is configured as an NMOS or PMOS transistor.

[0212] The IC device 1200 includes active regions 1210, 1220, 1230, and 1240, each extending along the X-direction, and gate structures G3 and G4, each extending along the Y-direction and overlying each of the active regions 1210, 1220, 1230, and 1240.

[0213] The active regions 1210, 1220, 1230 and 1240 are N-type or P-type active regions designed according to respective active regions 210, 220, 230 and 240, and the gate structures G3 and G4 are gate structures designed according to different ones of the gate regions P1 to P6, each of which was described above with reference to Fig. 2 and Fig. 3 was discussed.

[0214] In the Fig. 12, the IC device 1200 includes four active regions and two gate structures. In various embodiments, the IC device 1200 includes fewer or more than four active regions and / or fewer or more than two gate structures, each configured according to respective active and gate regions, as described above with reference to the IC layout diagram 300 in Fig. 3 was discussed.

[0215] According to the IC layout diagram 300, the gate structure G3 overlies edges of the active regions 1220 and 1240, each of the active regions 1210 and 1230 extends through the gate structure G3, the gate structure G4 overlies edges of the active regions 1210 and 1230, and each of the active regions 1220 and 1240 extends through the gate structure G4.

[0216] In various embodiments, one or more of the gate structure G3 and the active region 1210, the gate structure G3 and the active region 1230, the gate structure G4 and the active region 1220, or the gate structure G4 and the active region 1240 is configured as an NMOS or a PMOS transistor.

[0217] In various embodiments, one or both of the IC devices 1100 or 1200 includes additional IC device elements (not shown), e.g., doped and / or epitaxial regions, wells, or isolation structures suitable for creating one or more combinations of active areas and gate structures as one or more NMOS or PMOS transistors.

[0218] In various embodiments, one or both of the IC devices 1100 or 1200 comprise one or more conductive elements (not shown), e.g., contacts, vias, or portions of a metal diffusion, metal zero, metal one, or a higher metal layer, configured according to conductive regions defined by the conductive regions MD1 to MD5, M1, M2, Mo1 to Mo7B, the vias Vo, or the via V1 described above with reference to Fig. 5B through 5H2, whereby one or both of the IC devices 1100 or 1200 have one or more electrical connections to the one or more NMOS or PMOS transistors.

[0219] In various embodiments, one or more of the gate structure G1 is divided into two sections by a cutting section G1CP, the gate structure G2 is divided into two sections by a cutting section G2CP, the gate structure G3 is divided into two sections by a cutting section G3CP, or the gate structure G4 is divided into two sections by a cutting section G4CP according to one or more cutting poly regions defined by the cutting poly region CP described above with reference to Fig. 5G1 to 5E2, whereby each section of a given gate structure is separately controllable with respect to each other section of the given gate structure.

[0220] In various embodiments, the IC device 1100 comprises, in addition to the active areas 1110 to 1140 and the gate structures G1 and G2 designed according to the IC layout diagram 200, one or more further combinations of active areas and gate structures (not shown) designed according to the IC layout diagram 200, such that the IC device 1100 is designed according to one of the IC layout diagrams 700 or 900, each of which was described above with reference to Fig. 7 and 9 respectively.

[0221] In various embodiments, in addition to the active areas 1210 to 1240 and the gate structures G3 and G4 designed according to the IC layout diagram 300, the IC device 1200 comprises one or more further combinations of active areas and gate structures (not shown) designed according to the IC layout diagram 300, such that the IC device 1200 is designed according to one of the IC layout diagrams 800 or 1000, each of which was described above with reference to Fig. 8 and 10 respectively were discussed.

[0222] By being manufactured by performing some or all of the operations of methods 100 and 600 and designed according to the IC layouts 200, 300, or 700 to 1000 described above with reference to Fig. 1 to 10, each of the IC devices 1100 and 1200 enables the realization of the advantages discussed above with reference to the methods 100, 600 and Fig. 1 to 10 were discussed.

[0223] Fig. 13 is a block diagram of an EDA system 1300 according to some embodiments.

[0224] In some embodiments, EDA system 1300 includes an APR system. Methods described herein for designing layout diagrams and representing wiring route arrangements according to one or more embodiments may, for example, be implemented using EDA system 1300 according to some embodiments.

[0225] In some embodiments, EDA system 1300 is a general computing device comprising a hardware processor 1302 and a non-transitory computer-readable storage medium 1304. Storage medium 1304 is encoded with, i.e., stores, among other things, computer program code 1306, i.e., a set of executable instructions. Execution of instructions 1306 by hardware processor 1302 represents (at least in part) an EDA tool that implements some or all of, e.g., the methods described herein according to one or more of the aforementioned processes and / or methods.

[0226] The processor 1302 is electrically coupled to the computer-readable storage medium 1304 via a bus 1308. The processor 1302 is also electrically coupled to an I / O interface 1310 via the bus 1308. A network interface 1312 is also electrically connected to the processor 1302 via the bus 1308. The network interface 1312 is connected to a network 1314 such that the processor 1302 and the computer-readable storage medium 1304 are capable of connecting to external elements via the network 1314. The processor 1302 is configured to execute the computer program code 1306 encoded in the computer-readable storage medium 1304 to cause the EDA system 1300 to be usable for performing some or all of the mentioned processes and / or methods.In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or any suitable processing unit.

[0227] In one or more embodiments, computer-readable storage medium 1304 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, random access memory (RAM), read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments employing optical disks, computer-readable storage medium 1304 includes a CD-ROM (Compact Disc Read-Only Memory), a CD-RW (Compact Disc Read / Write), and / or a DVD (Digital Video Disc).

[0228] In one or more embodiments, storage medium 1304 stores computer program code 1306 configured to cause EDA system 1300 (such execution representing (at least in part) the EDA tool) to be usable for performing some or all of the mentioned processes and / or methods. In one or more embodiments, storage medium 1304 also stores information enabling some or all of the mentioned processes and / or methods to be performed. In one or more embodiments, storage medium 1304 stores a library 1307 of standard cells comprising such standard cells as disclosed herein.

[0229] The EDA system 1300 includes an I / O interface 1310. The I / O interface 1310 is coupled to external circuitry. In one or more embodiments, the I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor direction keys to communicate information and commands to the processor 1302.

[0230] The EDA system 1300 also includes a network interface 1312 coupled to the processor 1302. The network interface 1312 allows the EDA system 1300 to communicate with the network 1314 to which one or more other computing systems are connected. The network interface 1312 includes wireless network interfaces, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or wired network interfaces, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more EDA systems 1300.

[0231] The EDA system 1300 is configured to receive information via an I / O interface 1310. The information received via the I / O interface 1301 includes one or more of the instructions, data design rules, standard cell libraries, and / or other parameters for processing by the processor 1302. This information is transmitted to the processor 1302 via a bus 1308. The EDA system 1300 is configured to receive information related to a UI via an I / O interface 1310. The information is then stored in the computer-readable medium 1304 as a user interface (UI) 1342.

[0232] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a stand-alone software application for execution by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by the EDA system 1300.In some embodiments, a layout diagram having standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or other suitable tool for generating layouts.

[0233] In some embodiments, the processes are implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of a non-transitory computer-readable recording medium include, but are not limited to, an external / removable and / or internal / built-in storage device, e.g., one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM, a RAM, a memory card, and the like.

[0234] Fig. 14 is a block diagram of an integrated circuit (IC) manufacturing system 1400 and an associated IC manufacturing flow according to some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is manufactured using the manufacturing system 1400.

[0235] In Fig. 14, the IC manufacturing system 1400 includes entities, such as a design house 1420, a mask house 1430, and an IC manufacturer / processor (a "microchip fab") 1450, that cooperate with one another in design, development, and manufacturing cycles and / or services associated with the manufacture of an IC device 1460. The entities 1400 are interconnected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network represents a variety of different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communications channels. Each entity interacts with one or more of the other entities and provides and / or receives services to one or more of the other entities.In some embodiments, two or more of the design house 1420, the mask house 1430, and the IC microchip factory 1450 are owned by a single large company. In some embodiments, two or more of the design house 1420, the mask house 1430, and the IC microchip factory 1450 coexist in a common facility and use common resources.

[0236] The design house (or design team) 1420 creates an IC design layout diagram 1422. The IC design layout diagram 1422 includes various geometric structures designed for the IC device 1460. The geometric structures correspond to the structures of a metal, oxide, or semiconductor layers that form the various components of the IC device 1460 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout diagram 1422 includes various IC features, such as an active region, a gate electrode, a source and drain, metal lines or vias of an interlayer interconnect, and openings for bond pads to be formed in a semiconductor substrate (such as a silicon wafer), and various material layers disposed on the semiconductor substrate.The design house 1420 implements a suitable design method to form the IC design layout diagram 1422. The design method includes one or more of a logic design, a physical design, or a placement and connection (place and route) design. The IC design layout diagram 1422 is represented in one or more data files containing information about the geometric structures. The IC design layout diagram 1422 can be represented, for example, in a GDSII file format or a DFII file format.

[0237] The mask house 1430 includes a data preparation 1432 and a mask fabrication 1444. The mask house 1430 uses the IC design layout diagram 1422 to fabricate one or more masks 1445 to be used to fabricate the various layers of the IC device 1460 according to the IC design layout diagram 1422. The mask house 1430 performs a mask data preparation 1432, in which the IC design layout diagram 1422 is translated into an "RDF" (representative data file). The mask data preparation 1432 provides the RDF for the mask fabrication 1444. The mask fabrication 1444 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1445 or a semiconductor wafer 1453. The design layout diagram 1422 is manipulated by the mask data preparation 1432 to conform to certain characteristics of the mask writer and / or requirements of the IC microchip factory 1450. In Fig. 14, mask data preparation 1432 and mask fabrication 1444 are depicted as separate elements. In some embodiments, mask data preparation 1432 and mask fabrication 1444 may be collectively referred to as mask data preparation.

[0238] In some embodiments, mask data preparation 1432 includes optical proximity correction (OPC) that uses lithographic enhancement techniques to compensate for image defects, such as those that may occur due to diffraction, interference, or other process effects, and the like. OPC adjusts IC design layout diagram 1422. In some embodiments, mask data preparation 1432 includes other resolution enhancement techniques (RET), such as off-axis illumination, resolution assist features, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0239] In some embodiments, mask data preparation 1432 includes a mask rule checker (MRC) that checks the IC design layout diagram 1422, which has undergone processes in OPC, against a set of mask generation rules that include certain geometric and / or interconnect constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout diagram 1422 to accommodate constraints during mask fabrication 1444, which may also undo some of the modifications performed by OPC to conform to mask generation rules.

[0240] In some embodiments, mask data preparation 1432 includes a lithographic process verification (LPC) that simulates processing that will be implemented by IC microchip fabrication 1450 to fabricate IC device 1460. LPC simulates this processing based on IC design layout diagram 1422 to generate a simulated fabricated device, such as IC device 1460. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of field ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof.In some embodiments, after a simulated fabricated device is generated by LPC, if the simulated device does not have an approximately correct shape to conform to the design rules, OPC and / or MRC are repeated to further refine the IC design layout diagram 1422.

[0241] It should be understood that the above description of mask data preparation 1432 has been simplified for clarity. In some embodiments, data preparation 1432 includes additional features, such as a logic operation (LOP) to modify IC design layout diagram 1422 according to manufacturing rules. Furthermore, the processes applied to IC design layout diagram 1422 during data preparation 1432 may be performed in a variety of different orders.

[0242] After mask data preparation 1432 and during mask fabrication 1444, a mask 1445 or a group of masks 1445 is fabricated based on the modified IC design layout diagram 1422. In some embodiments, mask fabrication 1444 includes performing one or more lithographic exposures based on the IC design layout diagram 1422. In some embodiments, an electron beam (e-beam) or a multiple e-beam mechanism is used to form a structure on a mask (photomask or reticle) 1445 based on the modified IC design layout diagram 1422. The mask 1445 can be formed using various technologies. In some embodiments, the mask 1445 is formed using a binary technology. In some embodiments, a mask structure includes opaque regions and transparent regions. A radiation beam, such asUltraviolet (UV) radiation used to expose the image-sensitive material layer (e.g., photoresist) deposited on a wafer is blocked by the opaque region and transmitted through the transparent regions. In one example, a binary mask version of mask 1445 includes a transparent substrate (e.g., fused silica) and opaque material (e.g., chromium) deposited in the opaque regions of the binary mask. In another example, mask 1445 is formed using phase-shift technology. In a phase-shift mask (PSM) version of mask 1445, various features of the structure formed on the phase-shift mask are designed to have an appropriate phase difference to improve image quality resolution. In various examples, the phase-shift mask may be an attenuated PSM or alternating PSM.The mask(s) produced by mask fabrication 1444 are used in a variety of processes. For example, a mask(s) is used in an ion implantation process to form various doped regions in the semiconductor wafer 1453, in an etching process to form various etch regions in the semiconductor wafer 1453, and / or in other suitable processes.

[0243] The IC microchip fab 1450 includes the wafer fabrication 1452. The IC microchip fab 1450 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, the IC microchip fab 1450 is a semiconductor foundry. For example, one manufacturing facility may be provided for the front-end manufacturing of multiple IC products (front-end-of-line manufacturing (FEOL)), while a second manufacturing facility may provide the back-end-of-line manufacturing for interconnecting and packaging the IC products (back-end-of-line manufacturing (BEOL)), and a third manufacturing facility may provide other services to the foundry company.

[0244] The IC microchip fabrication shop 1450 uses a mask(s) 1445 fabricated by the mask house 1430 to fabricate the IC device 1460. Therefore, the IC microchip fabrication shop 1450 at least indirectly uses the IC design layout diagram 1422 to fabricate the IC device 1460. In some embodiments, the semiconductor wafer 1453 is fabricated by the IC microchip fabrication shop 1450 using the mask(s) 1445 to form the IC device 1460. In some embodiments, the IC fabrication shop includes performing one or more lithographic exposures based at least indirectly on the IC design layout diagram 1422. The semiconductor wafer 1453 includes a silicon substrate or other suitable substrate having layers of material formed thereon.The semiconductor wafer 1453 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (which are formed in subsequent manufacturing steps).

[0245] Details regarding a manufacturing system of integrated circuits (IC) (e.g. System 1400 of Fig. 14) and an associated IC manufacturing process can be found, for example, in US patent US 9 256 709 B2 granted on February 9, 2016, US laid-open publication US 2015 / 0 278 429 A1 published on October 1, 2015, US laid-open publication US 2014 / 0 040 838 A1 published on February 6, 2014, and US patent US 7 260 442 B2 granted on August 21, 2007.

Claims

[1] A method for generating a layout diagram of an integrated circuit (IC) cell, the IC layout diagram being stored in a non-transitory computer-readable medium, the method comprising: Defining a boundary recess (200R3; 300R4) in a boundary (200B; 300B) of the cell (200C; 300C) by the following: Creating a first portion (B10; B34) of the boundary (200B; 300B) along a first direction (Y); Creating a second portion (B9; B33) of the boundary (200B; 300B) away from the first portion (B10; B34) in a second direction (-X) perpendicular to the first direction (Y), the second portion (B9; B33) being adjacent to the first portion; and Creating a third portion (B11; B35) of the boundary (200B; 300B) away from the first portion (B10; B34) in the second direction (-X), the third portion (B11; B35) being adjacent to the first portion (B10; B34); and Arranging an active region (220) in the cell by creating the active region (220) away from the first section (B10; B34) in a third direction (X) opposite to the second direction (-X). [2] The method of claim 1, wherein: the active region (220) is a first active region of several active regions in the cell, and the method further comprises arranging a second active region (230) of the plurality of active regions by creating the second active region (230) away from the first portion (B10; B34) in the third direction (X). [3] Method according to claim 2, wherein arranging the first active region (210) of the plurality of active regions comprises receiving the first active region (210) of the plurality of active regions in a PMOS device, and arranging the second active region (230) of the plurality of active regions comprises incorporating the second active region (230) of the plurality of active regions in an NMOS device. [4] The method of claim 1, wherein: the active region (220) is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction (X), and the method further comprises arranging a second active region (230) of the plurality of active regions and a third active region of the plurality of active regions, comprising aligning the second active region of the plurality of active regions, the third active region of the plurality of active regions, the second section, and the third section along the first direction (Y). [5] Method according to claim 4, wherein arranging the second active region of the plurality of active regions comprises incorporating the second active region of the plurality of active regions in a PMOS device, and arranging the third active region of the plurality of active regions comprises incorporating the third active region of the plurality of active regions in an NMOS device. [6] A method according to any one of the preceding claims 1 to 3, further comprising: Defining a boundary projection (200P1, 200P2, 200P3; 300P1, 300P2, 300P3; 300P4) in the boundary (200B; 300B) of the cell by: Creating a fourth section (B4; B24) of the boundary (200B; 300B) in the first direction (Y); Creating a fifth section (B3; B23) of the boundary (200B; 300B) away from the fourth section in a second direction (-X), wherein the fifth section (B3; B23) is adjacent to the fourth section (B4; B24); and Creating a sixth section (B5; B25) away from the fourth section (B4; B24) in the second direction (-X), wherein the sixth section (B5; B25) is adjacent to the fourth section (B4; B24), wherein the active region (220) is located between the first section (B10; B34) and the fourth section (B4; B24). [7] Method according to claim 6, wherein the active region is a first active region of a plurality of active regions in the cell, each active region of the plurality of active regions extending in the third direction (X), defining the boundary recess in the boundary (200B; 300B) of the cell further comprises: Creating a seventh portion of the boundary (200B; 300B) in the second direction, the seventh portion not being adjacent to the fourth portion and being parallel to the fifth portion and the sixth portion, the method further comprising: Arranging a second active region of the plurality of active regions comprising aligning the first active region of the plurality of active regions, the second active region of the plurality of active regions, the fifth section, the sixth section, and the seventh section in the first direction. [8] The method of claim 7, wherein one of arranging the first active region of the plurality of active regions or arranging the second active region of the plurality of active regions comprises: Incorporating one of the first active region of the plurality of active regions or the second active region of the plurality of active regions in a PMOS device, and the other of arranging the first active region of the plurality of active regions or arranging the second active region of the plurality of active regions comprises: Incorporating the other of the first active region of the plurality of active regions or the second active region of the plurality of active regions in an NMOS device. [9] Manufacturing process comprising: Generating a layout diagram of an integrated circuit cell according to the method of any one of the preceding claims; and Manufacture, based on the layout diagram, of: one or more semiconductor masks, and / or at least one component in a layer of a semiconductor IC. [10] A method for generating a layout diagram of an integrated circuit (IC), wherein the IC layout diagram is stored in a non-transitory computer-readable medium, the method comprising: Adjacent a first cell (200C-1; 300C-1) to a second cell (200C-2; 300C-2) in the IC layout diagram (700; 800) by the following: Fitting a boundary protrusion (200P1-1; 300P1-1) of the first cell into a boundary recess (200R3-2; 300R4-2) of the second cell, wherein the first cell and the second cell are cells according to a respective layout diagram of an integrated circuit cell generated by the method of any one of the preceding claims 1 to 8; and Intersecting a first gate region (P5) of the IC layout diagram with the boundary projection (200P1-1; 300P1-1) and with a first active region (210-2) of the second cell. [11] The method of claim 10, wherein crossing the first gate region with the boundary protrusion and the first active region comprises aligning the first cell (200C-1; 300C-1) and the second cell (200C-2; 300C-2) based on a gate trace (T5). [12] The method of any one of the preceding claims 10 or 11, wherein crossing the first gate region (P5) of the IC layout diagram with the boundary protrusion (200P1-1; 300P1-1) and with the first active region (210-2) comprises crossing the first gate region (P5) with a second active region (240-2; 230-2) of the second cell (200C-2; 300C-2). [13] Method according to one of the preceding claims 10 to 12, wherein: the boundary projection (300P1-1) of the first cell (300C-1) is a first boundary projection of a plurality of boundary projections (300P1-1, 300P2-1, 300P3-1, 300P4-1) of the first cell, and crossing the first gate region (P5) of the IC layout diagram (800) with the boundary protrusion (300P1-1) and with the first active region (210-2) comprises crossing the first gate region (P5) with a second boundary protrusion (300P2-1) of the plurality of boundary protrusions. [14] The method of any one of the preceding claims 10 to 13, further comprising arranging the first cell (200C-1; 300C-1) and the second cell (200C-2; 300C-2) within a place-and-route boundary (PR-1; PR-2). [15] Manufacturing process comprising: Generating a layout diagram of an integrated circuit according to the method of any one of claims 10 to 14; and Performing one or more lithographic exposures based on the layout diagram (700; 800). [16] An IC device (1100; 1200) manufactured according to an IC layout diagram produced by a method according to any one of claims 10 to 14, the IC device (1100; 1200) comprising: a plurality of active regions (1110, 1120, 1130, 1140; 1210, 1220, 1230, 1240) fabricated according to respective active regions of the IC layout diagram, each active region of the plurality of active regions extending in a first direction (X); and a first gate structure (G1; G3) extending in a second direction (Y) perpendicular to the first direction (X), the first gate structure (G1, G3) overlying each active region of the plurality of active regions, the first gate structure (G1, G3) being fabricated according to a gate region of the IC layout diagram; wherein a first active region (1120; 1220) of the plurality of active regions is located between a second active region (1110; 1210) of the plurality of active regions and a third active region (1140; 1230) of the plurality of active regions, the first gate structure (G1; G3) lies over an edge of the first active region (1120; 1220) of the plurality of active regions, and each of the second active region (1110; 1210) of the plurality of active regions and the third active region (1140; 1230) of the plurality of active regions extends transversely to the first gate structure (G1) and covers the entire width thereof. [17] The IC device (1100; 1200) of claim 16, further comprising: a second gate structure (G2; G4) extending in the second direction (Y), the second gate structure (G2; G4) overlying each active region of the plurality of active regions (1110, 1120, 1130, 1140; 1210, 1220, 1230, 1240), the second gate structure (G2, G4) being fabricated according to a gate region of the IC layout diagram; wherein the second gate structure (G2; G4) lies over an edge of the second active region (1110; 1210) of the plurality of active regions and an edge of the third active region (1140; 1230) of the plurality of active regions, and the first active region (1120; 1220) of the plurality of active regions extends transversely to the second gate structure (G2; G4) and covers its entire width. [18] IC device (1100) according to claim 16 or 17, wherein a fourth active region (1130) of the plurality of active regions is located between the second active region (1110) of the plurality of active regions and the third active region (1140) of the plurality of active regions, and the first gate structure (G1) lies over an edge of the fourth active region (1130) of the plurality of active regions. [19] The IC device (1200) according to any one of the preceding claims 16 to 17, wherein: the third active region (1230) of the plurality of active regions is located between the first active region (1220) of the plurality of active regions and a fourth active region (1240) of the plurality of active regions, and the first gate structure (G3) lies over an edge of the fourth active region (1240) of the plurality of active regions. [20] The IC device (1100; 1200) of any one of the preceding claims 16 to 19, wherein a first portion of the first gate structure (G1; G3) overlies the second active region (1110; 1210) of the plurality of active regions, and a second portion of the first gate structure (G1; G3) overlies the third active region (1140; 1230) of the plurality of active regions.

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