Double-height cell regions, semiconductor device therewith, and method for producing a corresponding layout diagram

Abstract

Semiconductor device (100) comprising: Fins (212(D), 212(P), 212(N)) extending parallel to a first direction (X) and designed to comprise: Dummy fins (212(D)); first active fins (212(N)) having a first conductivity type; and second active fins (212(P)) having a second conductivity type; and at least one gate structure (216(A)) formed over a respective one of the fins (212(D), 212(P), 212(N)) and extending parallel to a second direction (Y) perpendicular to the first direction (X); where: the fins (212(D), 212(P), 212(N)) and the at least one gate structure (216(A)) are arranged in a first cell region (808A); the first cell range (808A) with respect to the second direction (Y) comprises in this order: a first dummy fin (212(D)); a second active region (850A(2)) comprising L >= 1 second active fins (212(P)); a first active region (850A(1)) comprising a sequence of M = 2 * N + 2 consecutive first active fins (212(N)) arranged in a central portion of the first cell region (808A), where N = 1 or 2; a third active region (850A(3)) comprising L second active fins (212(P)); and a second dummy fin (212(D)); and the semiconductor device further comprises a second cell region (804A), the second cell range (804A) comprises, with respect to the second direction (Y), in this order: a third dummy fin (212(D)); a fourth active region (850A(2)') comprising L second active fins (212(P)); a fifth active region (850A(1)') comprising N consecutive first active fins (212(N)); and a fourth dummy fin (212(D)); wherein a plane of symmetry perpendicular to the second direction (Y) divides the first cell region into two mirror-symmetrical halves; and an arrangement of the fins in one of the two mirror-symmetrical halves of the first cell area differs from an arrangement of the fins in the second cell area only in that the fourth dummy fin is replaced by a first active fin.

Description

BACKGROUND

[0001] A semiconductor device, one or more of which are contained within an integrated circuit (IC), comprises a number of electronic components. One way to represent a semiconductor device is through a plan view of a layout diagram. A layout diagram is hierarchically structured and divided into modules that perform higher-level functions as specified by the semiconductor device's design specifications.

[0002] For a specific semi-custom design (SDC) project, a custom cell is designed with a layout specifically tailored to that SCD project to provide (in operation) a higher-level logic function specific to that SCD project. In contrast, a library of standard cells is designed without a specific project in mind and includes standard cells that provide (in operation) common lower-level logic functions. In terms of space requirements within a layout diagram (relative to plan view), custom cells are larger (typically much larger) than standard cells. In addition, for a given library / collection, all standard cells have at least one dimension that is the same size (typically a multiple of a fixed, library-specific dimension) to facilitate the arrangement of the standard cells in a layout diagram.Typically, the direction of the specified dimension is parallel to the vertical direction, or Y-axis, so the specified dimension is referred to as the height of the standard cell. Standard cells, as such, are described as predefined with respect to a specific SCD project. Custom cells may or may not have at least one dimension that is the same size as the corresponding dimension of the standard cells.

[0003] US 2013 / 0292777 A1 describes an SRAM array comprising a plurality of FinFETs. In one embodiment, each memory cell comprises pull-up PMOS transistors PU-1 and PU-2, each with one fin, and pull-down NMOS transistors PD-1 and PD-2, as well as pass-gate NMOS transistors PG-1 and PG-2, each with two fins.

[0004] US 8786019 B2 describes a CMOS FinFET device comprising a substrate having a first region and a second region. The CMOS FinFET includes a fin structure disposed over the substrate and including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate, and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate, and a second portion of the second fin comprising a germanium material deposited over the first portion of the second fin.

[0005] US 2014 / 0239412 A1 describes an integrated circuit having a first and a second standard cell. A dummy gate comprises a first half and a second half in the first and second standard cells, respectively. The first half and the second half are located at the edges of the first and second standard cells, respectively, and are adjacent to each other. A dummy channel is overlaid by the dummy gate.

[0006] DE 102017125395 A1 describes a semiconductor device in which active regions are formed on a substrate and arranged with respect to a grid having first and second conductive lines substantially parallel to respective orthogonal first and second directions. The active regions are organized into instances of a first row having a first conductivity and a second row having a second conductivity. Each instance of the first row and the second row comprises a respective first and second predetermined number of the first conductive lines. The structure has at least two contiguous rows comprising: at least one instance of the first row; and at least one instance of the second row.In the first direction, the specimens of the first row have a first width and the specimens of the second row have a second width which is substantially different from the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] One or more embodiments are illustrated by way of example in the figures of the accompanying drawings, wherein elements having the same numerical reference designations represent similar elements throughout. Unless otherwise disclosed, the drawings are not to scale. Fig. 1 is a block diagram of a semiconductor device in accordance with some embodiments. Fig. 2A - 2D are corresponding assembly diagrams in accordance with some embodiments. Fig. 3A-3B are corresponding cross-sections of a cell region of a semiconductor device in accordance with some embodiments. Fig. 4A-4D are corresponding layout diagrams in accordance with some embodiments. Fig. 5A-5D are corresponding layout diagrams in accordance with some embodiments. Fig. 6 is a combination diagram showing how a first layout diagram relates to a “building block” in the form of a second layout diagram in accordance with some embodiments. Fig. 7A-7D are combination diagrams showing how first layout diagrams relate to corresponding "building blocks" in the form of corresponding second layout diagrams in accordance with some embodiments. Fig. 8A-8D are combination diagrams showing how first layout diagrams relate to corresponding "building blocks" in the form of corresponding second layout diagrams in accordance with some embodiments. Fig. 9A-9D are combination diagrams showing how first layout diagrams relate to corresponding "building blocks" in the form of corresponding second layout diagrams in accordance with some embodiments. Fig. 10A-10C are combination diagrams showing how first layout diagrams relate to corresponding "building blocks" in the form of corresponding second layout diagrams in accordance with some embodiments. Fig. 11A-11D are combination diagrams showing how first layout diagrams relate to corresponding "building blocks" in the form of corresponding second layout diagrams in accordance with some embodiments. Fig. 12A-12C are combination diagrams showing how first layout diagrams relate to corresponding "building blocks" in the form of corresponding second layout diagrams in accordance with some embodiments. Fig. 13A-13L are combination diagrams showing how first layout diagrams relate to corresponding "building blocks" in the form of corresponding second layout diagrams in accordance with some embodiments. Fig. 14A-14B are flow diagrams of methods for generating a layout diagram in accordance with some embodiments. Fig. 15 is a block diagram of an electronic design automation (EDA) system in accordance with some embodiments. Fig. 16 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, in accordance with some embodiments. DETAILED DESCRIPTION

[0008] The following disclosure illustrates many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components, materials, values, steps, operations, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples. Other components, values, operations, materials, arrangements, or the like are contemplated. For example, the formation of a first element over or on top of a second element in the description that follows may include embodiments in which the first and second elements are formed in direct contact, but may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not disposed in direct contact with each other.Furthermore, the present disclosure may repeat reference numbers and / or characters throughout the various examples. This repetition is for convenience and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, terms of spatial relationships, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature shown in the figures. The terms of spatial relationships are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the terms of spatial relationships used herein may also be interpreted accordingly.When used herein in phrases such as "substantially parallel," "substantially the same," "substantially twice as," "substantially collinear," or the like, the term "substantially" is to be understood as an extension of the phrase containing the term "substantially" such that the phrase denotes a range that includes variations resulting from manufacturing process tolerances. For example, the phrase "substantially parallel" encompasses not only parallel per se, but also deviations from parallel that result from manufacturing process tolerances. Likewise, the phrase "substantially different / distinct" is to be understood as describing differences that are at least of a greater magnitude than mere variations resulting from manufacturing process tolerances.In some embodiments, the term "standard cell structure" refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from a library thereof and used as components in a layout diagram representing a circuit.

[0010] In some embodiments, in at least one double-height cell region, a semiconductor device includes fins and at least one overlying gate structure. The fins (dummy and active) are arranged substantially parallel to a first direction. Each of the gate structures is arranged substantially parallel to a second direction (which is substantially perpendicular to the first direction). The first and second active fins have respective first and second conductivity types.Each double cell region relative to the second direction comprises: a first active region having a sequence of three or more consecutive first active fins arranged in a central portion of the double-height cell region; a second active region having one or more second active fins arranged between the first active region and a first edge of the double-height cell region; and a third active region having one or more second active fins arranged between the first active region and a second edge of the double-height cell region. Compared to a stack of two corresponding first and second single-height cell regions, one or more of the first active fins in the sequence of three or more consecutive first active fins in the first active region of the double-height cell region represent additional fins.In contrast, the stack of the first and second single-height cell regions is separated by at least one dummy fin; each of the single-height cell regions has at least one active fin having the first conductivity type; however, neither the first nor the second single-height cell region would have a sequence of three or more consecutive first active fins; and a sum of the active fins in the first and second single-height cell regions would be equal to a difference between a sum of the active fins in the first active region less a partial sum of the at least one additional active fin in the first active region of the double-height cell region.

[0011] Fig. 1 is a block diagram of a semiconductor device 100 in accordance with some embodiments.

[0012] In Fig. 1, the semiconductor device 100 includes, among other things, a circuit macro (hereinafter referred to as a macro) 102. In some embodiments, the macro 102 is an SRAM macro. In some embodiments, the macro 102 is a macro other than an SRAM macro. The macro 102 includes, among other things, one or more double-height cell regions 104. In some embodiments, each of the cell regions 104 is based on one or more of the cells described in Fig. 2A-2D, 6, 7A-7D, 8A-8C, 9A-9D, 10A-10C, 11A-11D, 12A-12C, and 13A-13L and discussed below. In some embodiments, some or all of the instances of the cell range 104 differ such that the different instances of the cell range 104 are based on correspondingly different ones of the cells shown in Fig. 2A - 2D, 6, 7A - 7D, 8A - 8C, 9A - 9D, 10A - 10C, 11A - 11D, 12A - 12C and 13A - 13L and (in turn) discussed below.

[0013] Fig. 2A is a layout diagram 200A consistent with some embodiments.

[0014] The layout diagram 200A includes a cell 208A. In some embodiments, the cell 208A is used as a standard cell in a library consisting of standard cells. An example of a semiconductor device resulting from a layout diagram including the cell 208A, for example, the layout diagram 200A, is the semiconductor device 100 of Fig. 1, wherein the cell region 104 of the semiconductor device 100 results from the cell 208A. The cell 208A is summarized in row 1 of the table below.

[0015] Cell 208A is designed for FinFET technology and has fin structures extending substantially parallel to a first direction. For reference purposes, there is a second direction that is substantially perpendicular to the first direction. Fig. 2A, the first and second directions are the horizontal and vertical directions, respectively. In some embodiments, the first and second directions are other than the respective horizontal and vertical directions. The fin structures include dummy fin structures 212(D), active fin structures 212(N) dedicated to NMOS technology, and active fin structures 212(P) dedicated to PMOS technology.

[0016] In Fig. 2A, cell 208A is rectangular, with a long axis substantially parallel to the horizontal direction and a short axis substantially parallel to the vertical direction. Cell 208A has a first edge 221A(1), a second edge 221A(2), a third edge 221A(3), and a fourth edge 221A(4). Both the first edge 221A(1) and the third edge 221A(3) are substantially parallel to the horizontal direction. Both the second edge 221A(2) and the fourth edge 221A(4) are substantially parallel to the vertical direction.

[0017] Finns (see the corresponding Fig. 3A, which is discussed below), which consists of specimens of the active fin structures 212(N) of Fig. 2A - 2B are designed for NMOS technology. Fins (see the corresponding Fig. 3A, which is discussed below), which consist of specimens of the active fin structures 212(P) of Fig. 2A-2B are designed for PMOS technology. In some embodiments, fins formed from instances of the dummy fin structure 212(D) of Fig. 2 are not included as functional components in semiconductor devices. Consequently, in some embodiments, fins resulting from instances of the dummy fin structure 212(D) are not designed for either NMOS or PMOS technology. In some embodiments, fins resulting from instances of the dummy fin structure 212(D) are not doped for a particular conductivity. In some embodiments, the dummy fin structures 212(D) are included / arranged to provide isolation, for example, between an instance of the active fin structure 212(N) and the active fin structure 212(P). Because the potential "active state" of the dummy fin structure 212(D) has been sacrificed, the dummy fin structure 212(D) is sometimes referred to as a sacrificial fin structure. Additional details regarding the structure and fabrication of CMOS FinFET technology are disclosed in U.S. Patent No. 8,786,019.

[0018] In Fig. 2A, the immediately adjacent fins are evenly spaced with respect to the vertical direction in accordance with a first grid (not shown). A pitch 253 of such fin structures (hereinafter referred to as "fin pitch 253") is determined according to the design rules and the process / technology node with which a semiconductor device is manufactured according to a layout diagram including cell 208A. Each of the fin structures 212(D), 212(N), and 212(P) is rectangular, with a long axis substantially parallel to the horizontal direction and a short axis substantially parallel to the vertical direction.For each of the fin structures 212(D), 212(N), and 212(P), a short axis size (or "width"), the fin width (width_fin), is also determined according to the design rules and the process / technology node with which a semiconductor device is manufactured according to a layout diagram including the cell 208A.

[0019] The cell 208A is divided into a first active region 250A(N), a second active region 250A(P)(1), and a third active region 250A(P)(2). With respect to the vertical direction, the first active region 250A(N) is arranged in a central portion of the cell 208A. With respect to the vertical direction, the second active region 250A(P)(1) is arranged between the first active region 250A(N) and a first edge 221A(1) of the cell 208A. With respect to the vertical direction, the second active region 250A(P)(2) is arranged between the first active region 250A(N) and a third edge 221A(3) of the cell 208A.

[0020] The first active region 250A(N) comprises a sequence of three or more consecutive active fins 212(N). Fig. 2A, the first active region 250A(N) comprises 5 copies of the active fin 212(N). The second active region 250A(P)(1) comprises one or more active fins 212(P). In Fig. 2A, the second active region 250A(P)(1) comprises two copies of the active fin 212(P). The third active region 250A(P)(2) comprises one or more active fins 212(P). In Fig. 2A, the third active region 250A(P)(2) comprises two copies of the active fin 212(P). Other numbers of active fins are used for the first active region 250A(N), the second active region 250A(P)(1), and the third active region 250A(P)(2), for example, in view of the different numbers of active fins used in Fig. 6, 7A-7D, 8A-8D, 9A-9D, 10A-10C, 11A-11D, 12A-12C and 13A-13L and discussed below, and the like.

[0021] With respect to cell 208A, compared to a stack (in the vertical direction) of two corresponding single-height cells, e.g., the stack of single-height cells 442D(1) and 442D(2) in Fig. 4A (discussed below), the sequence of five active fins 212(N) in the first active region 250A(N) of the double-height cell 208A includes an additional fin. In contrast, the stack of single-height cells 442D(1) and 442D(2) is separated with respect to the vertical direction by a dummy fin 412(D); the single-height cells 442D(1) and 442D(2) each have two active fins 212(N) in the respective active regions 444A(N)(1) and 444A(N)(2); however, none of the active regions 444A(N)(1) and 444A(N)(2) has a sequence of three or more consecutive active fins 212(N); and the sum of active fins 412(N) in the active areas 444A(N)(1) and 444A(N)(2) is 4, which corresponds to a difference between a sum (namely five) of active fins 212(N) in the first active area 250A(N) less the number (namely one) of additional active fins 212(N) in the first active area 250A(N).

[0022] In Fig. 2A, cell 208A includes four instances of the dummy fin structure 212(D). With respect to the vertical direction, one instance of the dummy fin structure 212(D) is arranged in a first gap between the first active region 250A(N) and the second active region 250A(P)(1), the first gap having a size of 255. With respect to the vertical direction, one instance of the dummy fin structure 212(D) is arranged in a second gap between the first active region 250A(N) and the second active region 250A(P)(2), the second gap having a size of 256. A first instance of a “boundary” of the dummy fin structure 212(D) is arranged substantially collinearly with a first edge 221A(1) of the cell 208A such that the cell 208A comprises substantially one-half of the first instance of the boundary of the dummy fin structure 212(D).A second instance of a boundary of the dummy fin structure 212(D) is arranged substantially collinear with the third edge 221A(3) of the cell 208A such that the cell 208A comprises substantially one half of the second instance of the boundary of the dummy fin structure 212(D).

[0023] With respect to the vertical direction, the size of the first gap 255 = d1 * distance 253 - fin width, where d1 is a positive integer representing the number of dummy fin structures 212(D) arranged in the first gap. In cell 208A, d1 = 1, so that 255 = distance 253 - fin width. With respect to the vertical direction, the size 256 of the second gap 256 = d2 * distance 253 - fin width, where d2 is a positive integer representing the number of dummy fin structures 212(D) arranged in the second gap. In cell 208A, d2 = 1, so that 256 = distance 253 - fin width.

[0024] With respect to cell 208A with respect to the vertical direction, for a size S3 of the long axis (or “height”) of cell 208A, S3 = (D+P+N)*Distance_253, where D, N, and P are each a non-negative integer, D represents the number of dummy fin structures 212(D) included in cell 208A, N represents the number of active fin structures 212(N) included in cell 208A, P represents the number of active fin structures 212(P) included in cell 208A, and Distance_253 is a variable representing the fin spacing 253. In cell 208A, N = 5, P = 4, and D = 3. Note that D = 3 because there are two full copies and two half copies of the dummy fin structure 212(D) in cell 208A, so D = 3 = 2 + 2 * (1 / 2). Consequently, for cell 208, S3 = 12 * Distance_253.

[0025] In Fig. 2A, cell 208A further comprises gate structures, at least one of which is an active gate structure 216(A) extending substantially parallel to the second direction in accordance with a second grid (not shown). There may also be dummy gate structures (in Fig. 2A not shown, but see e.g. Fig. 4A-4B, which are discussed below). While cell 208A includes instances of the active gate structure 216(A), cell 208A does not include instances of a dummy gate structure. The gate structures, e.g., active gate structures 216(A), are each disposed over one of the fin structures 212(D), 212(N), and 212(P).

[0026] With respect to the horizontal direction, immediately adjacent instances of the gate structures are evenly spaced in accordance with a second grid (not shown). A pitch 257 of such gate structures (hereinafter referred to as "gate pitch 257") is determined according to the design rules and the process / technology node with which a semiconductor device is manufactured according to a layout diagram comprising the cell 208A. For each of the fin structures 212(D), 212(N), and 212(P), a long axis size (or "length"), the fin length (= length_fin), is an integer multiple of the gate pitch 257. In particular, fin length = j*pitch_257, where j is a positive integer and pitch_257 is a variable representing the gate pitch 257. In Fig. 2A j = 3, so fin length = 3* distance_257.

[0027] In Fig. 2A, respective instances of the active gate structure 216(A) intersect the fin structures at Position_1 ≈ 1 / 3* fin length and at Position_2 ≈ 1 / 2* fin length with respect to the horizontal direction. In some embodiments, instances of the active gate structure 216(A) intersect the fin structure at positions other than Position_1 and Position_2.

[0028] With respect to cell 208A, the second edge 221A(2) and the fourth edge 221A(4) of cell 208A extend a distance d259 beyond the respective ends of the fin structures with respect to the horizontal direction. Fig. 2A, the distance d259 has a value of d259 = (distance_257) / 2. In some embodiments, the distance d259 has a value other than d259 = (distance_257) / 2. A size of the cell width (width_cell) of the short axis of the cell 208A is cell width = k+j*distance_257, where j and k are positive integers. In Fig. 2A, j = 3 (as stated above) and k = 1, so cell width = 4*spacing_462. In some embodiments, j is a positive integer other than j = 3. In some embodiments, k is a positive integer other than k = 1.

[0029] Each of the gate structures 216(A) is rectangular, with a long axis substantially parallel to the vertical direction and a short axis substantially parallel to the horizontal direction. For each of the gate structures 216(A), a short axis dimension (or "width"), the gate width (width-gate), is also determined according to the design rules and the process / technology node at which a semiconductor device is fabricated according to a layout diagram including the cell 208A.

[0030] The construction diagram 200A of Fig. 2A further includes power grid segment (PG) structures 218DD and a PG structure 218SS. Each instance of the PG segment 218DD is dedicated to a voltage VDD. Each instance of the PG segment 218SS is dedicated to a voltage VSS. In some embodiments, each instance of the PG segment 218DD and each instance of the PG segment 218SS is dedicated to voltages other than the corresponding voltages VDD and VSS. Each of the PG structures 218SS and 218DD is rectangular, with a long axis substantially parallel to the horizontal direction and a short axis substantially parallel to the vertical direction. For each of the PG structures 218DD and 218SS, a short axis size (or "width"), the PG width (width_PG), is also determined according to the design rules and the process / technology node with which a semiconductor device is manufactured according to a layout diagram including the cell 208A.

[0031] In layout diagram 200A, there is an instance of PG structure 218SS disposed above and substantially collinear with a centerline of first active region 250A(N), with the centerline of first active region 250A(N) disposed substantially parallel to the horizontal direction. Furthermore, in layout diagram 200A, there are instances of PG structure 218DD disposed above and substantially collinear with respect to first edge 221A(1) and third edge 221A(3), respectively.

[0032] Fig. 2B is a layout diagram 200B consistent with some embodiments.

[0033] The layout diagram 200B has a cell 208B. The cell 208B of Fig. 2B is similar to cell 208A of Fig. 2A. In general, the layout diagram 200B of Fig. 2B similar to the assembly diagram 200A of Fig. 2A. For brevity, the discussion of cell 208B focuses on differences of cell 208B relative to cell 208A. In some embodiments, cell 208B is used as a standard cell in a library of standard cells. An example of a semiconductor device resulting from a layout diagram including cell 208B, for example, layout diagram 200B, is semiconductor device 100 of Fig. 1, where cell region 104 of semiconductor device 100 results from cell 208B. Cell 208B is summarized in row 2 of the table below.

[0034] The cell 208B is divided into a first active region 250B(P), a second active region 250B(N)(1), and a third active region 250B(N)(2). The first active region 250B(P) comprises a sequence of three or more consecutive active fins 212(P). With respect to the vertical direction, the first active region 250B(P) is arranged in a central portion of the cell 208B. In particular, the first active region 250B(P) comprises five copies of the active fin 212(P). The second active region 250B(N)(1) comprises one or more active fins 212(N). With respect to the vertical direction, the second active region 250B(N)(1) is arranged between the first active region 250B(P) and a first edge 221B(1) of the cell 208B. In particular, the second active region 250B(N)(1) comprises two copies of the active fin 212(N). The third active region 250B(N)(2) comprises one or more active fins 212(N).With respect to the vertical direction, the second active region 250B(N)(2) is arranged between the first active region 250B(P) and a third edge 221B(3) of the cell 208B. In particular, the third active region 250B(P)(2) comprises two copies of the active fin 212(N).

[0035] In cell 208B, an instance of the dummy fin structure 212(D) is disposed in a first gap between the first active region 250B(P) and the second active region 250B(N)(1) with respect to the vertical direction, the first gap having a size of 255. Furthermore, an instance of the dummy fin structure 212(D) is disposed in a second gap between the first active region 250B(P) and the third active region 250B(N)(2) with respect to the vertical direction, the second gap having a size of 256.

[0036] The assembly diagram 200B of Fig. 2B further includes PG structures 218DD and 218SS. In layout diagram 200B, there is an instance of PG structure 218DD disposed above and substantially collinear with respect to a centerline of first active region 250B(P), with the centerline of first active region 250B(P) disposed substantially parallel to the horizontal direction. Furthermore, in layout diagram 200B, there are instances of PG structure 218SS disposed above and substantially collinear with respect to first edge 221B(1) and third edge 221B(3), respectively.

[0037] Fig. 2C is a layout diagram 200C in accordance with some embodiments.

[0038] The layout diagram 200C has a cell 208C. The cell 208C of Fig. 2C is similar to cell 208A of Fig. 2A. In general, the structure diagram 200C of Fig. 2C similar to the assembly diagram 200A of Fig. 2A. For brevity, the discussion of cell 208C focuses on differences of cell 208C relative to cell 208A. In some embodiments, cell 208C is used as a standard cell in a library of standard cells. An example of a semiconductor device resulting from a layout diagram including cell 208C, for example, layout diagram 200C, is semiconductor device 100 of Fig. 1, where cell region 104 of semiconductor device 100 results from cell 208C. Cell 208C is summarized in row 3 of the table below.

[0039] With respect to the vertical direction, in cell 208C, no instance of the dummy fin structure 212(D) is arranged in a first gap between the first active region 250C(N) and the second active region 250C(P)(1), the first gap having a size of 255'. With respect to the vertical direction, and in contrast to cell 208A of Fig. 2A, the size 255' of the first gap is not an integer multiple of the fin width (again, width_fin), e.g., 255' ≠ d1*distance_253 - fin width, where d1 (as discussed above) is a positive integer representing the number of dummy fin structures 212(D) arranged elsewhere in the first gap. Furthermore, with respect to the vertical direction, no instance of the dummy fin structure 212(D) is arranged in a second gap between the first active region 250C(N) and the third active region 250C(P)(2), the second gap having a size of 256'. With respect to the vertical direction, and in contrast to cell 208A of Fig. 2A, the size 256' of the second gap is not an integer multiple of the fin width, e.g., 256' ≠ d1*distance_253 - fin width, where d2 is a positive integer representing the number of dummy fin structures 212(D) arranged elsewhere in the second gap. In some embodiments, the fin structures 212(D), 212(N), and 212(P) are arranged in accordance with the first grid, as shown in Fig. 2A, and instances of the dummy fin structure 212(D) are also designated for removal during manufacturing of a semiconductor device. In some embodiments, instances of the dummy fin structure 212(D) are designated for removal by being covered / overlaid in the layup diagram 200C by corresponding cut structures (not shown). A cut structure corresponding to a fin structure indicates that any portions of the fin structure disposed beneath the cut structure will be removed during manufacturing.

[0040] With respect to assembly 200C, in some embodiments, the fin structures 212(D), 212(N), and 212(P) are not formed in accordance with a grid, but are instead formed using mandrel techniques, with the advantageous result that no instances of the dummy fin structure 212(D) are formed in either the first gap or the second gap, thereby eliminating the need to later remove instances of the dummy fin structure 212(D). Compared to formation in accordance with a grid, the mandrel techniques also have the advantage of increased flexibility in determining the sizes 255' and 256'. Additional details regarding mandrel techniques are disclosed in U.S. Patent No. 15 / 362,002, granted November 28, 2016, having pre-grant publication number 20170317089.

[0041] Fig. 2D is a layout diagram 200D consistent with some embodiments.

[0042] The layout diagram 200D has a cell 208D. The cell 208D of Fig. 2D is similar to cell 208B of Fig. 2B. In general, the structure diagram 200D of Fig. 2D similar to the assembly diagram 200B of Fig. 2B. In addition, cell 208D of Fig. 2D similar to cell 208C of Fig. 2C. In general, the structure diagram 200D of Fig. 2D similar to the assembly diagram 200C of Fig. 2C. For brevity, the discussion of cell 208D focuses on differences of cell 208D with respect to each of cells 208B and 208C. In some embodiments, cell 208D is used as a standard cell in a library of standard cells. An example of a semiconductor device resulting from a layout diagram including cell 208D, for example, layout diagram 200D, is semiconductor device 100 of Fig. 1, where cell region 104 of semiconductor device 100 results from cell 208D. Cell 208D is summarized in row 4 of the table below.

[0043] In particular, with regard to the active regions and active fin structures, the active regions 250D(P), 250D(N)(1) and 250D(N)(2) and the associated instances of the fin structures 212(P) and 212(N) of the cell 208D of Fig. 2D similar to the respective active regions 250B(P), 250B(N)(1) and 250B(N)(2) as well as associated examples of the fin structures 212(P) and 212(N) of cell 208B of Fig. 2B. Regarding the dummy fin structures, the dummy fin structures 212(D) of cell 208D are similar to the corresponding dummy fin structures 212(D) of cell 208C of Fig. 2C. With respect to the vertical direction, in the cell 208D, no instance of the dummy fin structure 212(D) is arranged in a first gap between the first active region 250D(P) and the second active region 250D(N)(1), the first gap having the size 255' of Fig. 2C. With respect to the vertical direction, moreover, no instance of the dummy fin structure 212(D) is arranged in a second gap between the first active region 250C(N) and the third active region 250C(P)(2), the second gap having the size 256'.

[0044] Fig. 3A is a cross-section of a cell region 308A of a semiconductor device in accordance with some embodiments.

[0045] The cell region 30\8A is an example of a cell region of a semiconductor device designed based on a layout diagram such as the layout diagrams of Fig. 2A and Fig. 2B, and (as discussed below) Fig. 4A-4B, 5A-5B and 9D. As such, the cell region 308A is an example of a cell region 104 of the semiconductor device 100 of Fig. 1. Given the differences between Fig. 2A - 2B, 4A - 4B, 5A - 5B and 9D in relation to (as discussed below) the Fig. 6, 7A-7D, 8A-8D, 9A-9C, 10A-10C, 11A-11D, 12A-12C and 13A-13L, the cell region 308A is similar to the examples of a cell region of a semiconductor device formed based on a layout diagram, such as the layout diagrams of Fig. 6, 7A - 7D, 8A - 8D, 9A - 9C, 10A - 10C, 11A - 11D, 12A - 12C and 13A - 13L.

[0046] Semiconductor device 308A includes layers 331A, 335A, 337A, and 339A. Layer 335A is formed on layer 331A. Layer 337A is formed on layer 335A. Layer 339A is formed on layer 337A. Layer 331A corresponds to layer M(i) of the metallization, layer 335A corresponds to layer M(i+1) of the metallization, and layer 339A corresponds to layer M(i+1) of the metallization, where i is an integer and i ≥ 0. In some embodiments, the i-th layer is the first layer of the metallization, in which case, depending on the numbering convention of the corresponding design rules, i = 0 or i = 1.

[0047] The layer 331A includes: the lines 312D, 312P and 312N corresponding to the fin structures 212(D), 212(P) and 212(N) of Fig. 2A; and an interlayer dielectric (ILD) 352. Instances of line 312(D) in columns 341A(1) and 341A(2) are optional and have been drawn as dashed lines accordingly. If instances of line 312(D) are present in columns 341A(1) and 341A(2), the cell region 308A of Fig. 3A of cell 208A of the layout diagram 200A of Fig. 2A. If there are no instances of line 312(D) in columns 341A(1) and 341A(2), cell range 308A of Fig. 3A of cell 208B of the layout diagram 200B of Fig. 2B.

[0048] The layer 335A includes a line 316(A) corresponding to the gate structure 216(A) of Fig. 2A. In some embodiments, line 316(A) is formed in direct contact with the corresponding lines 312D, 312P, and 312N corresponding to the fin structures 212(D), 212(P), and 212(N). In some embodiments, vias (not shown) are formed between line 316(A) and the corresponding lines 312D, 312P, and 312N, wherein the vias are arranged in an interconnect layer (not shown) inserted between layers 331A and 335A. Layer 337A includes an ILD 338. Layer 339A includes PG segments 318DD and 318SS corresponding to the PG structures 218DD and 218SS of Fig. 2A; and an ILD 340.

[0049] Fig. 3B is a cross-section of a cell region 308B of a semiconductor device in accordance with some embodiments.

[0050] The cell range 308B of Fig. 3B is similar to cell range 308A of Fig. 3A. For brevity, the discussion of cell region 308B focuses on differences of cell region 308B with respect to cell region 308A. Cell region 308B is an example of a cell region of a semiconductor device that may be formed based on a layout diagram, such as the layout diagrams of Fig. 2C and Fig. 2D, and (as discussed below) Fig. 4C-4D and 5C-5D. As such, the cell region 308B is an example of the cell region 104 of the semiconductor device 100 of Fig. 1.

[0051] The layer 331B comprises: the lines 312D, 312P and 312N corresponding to the fin structures 212(D), 212(P) and 212(N) of Fig. 2B; and an interlayer dielectric (ILD) 352. Instances of line 312(D) in columns 341B(1) and 341B(2) are optional and have been drawn as dashed lines accordingly. If instances of line 312(D) are present in columns 341B(1) and 341B(2), the cell range 308B of Fig. 3B of cell 208C of the layout diagram 200C of Fig. 2C. If there are no instances of line 312(D) in columns 341B(1) and 341B(2), cell range 308B of Fig. 3B of cell 208D of the layout diagram 200D of Fig. 2D.

[0052] Fig. 4A is a layout diagram 400A consistent with some embodiments.

[0053] The layout diagram 400A includes double-height cells 408A(1) and 408A(2), and single-height cells 442A(1) and 442A(2). Each of the cells 408A(1) and 408A(2) of Fig. 4A is similar to cell 208A of Fig. 2A. For brevity, the discussion of cells 408A(1) and 408A(2) focuses on differences with respect to cell 208A. An example of a semiconductor device resulting from the layout diagram 400A is the semiconductor device 100 of Fig. 1, wherein instances of the cell region 104 of the semiconductor device 100 each consist of one or more of the cells 408A(1), 408A(2), 442A(1) and / or 442A(2) of Fig. 4A, or the like.

[0054] In the layout diagram 400A, each of the cells 408A(1), 408A(2), 442A(1), and 442A(2) is dedicated to FinFET technology and includes fin structures extending substantially parallel to a first direction. For reference purposes, there is a second direction that is substantially perpendicular to the first direction. Fig. 4A, the first and second directions are the horizontal and vertical directions, respectively. In some embodiments, the first and second directions are other than the respective horizontal and vertical directions. The fin structures include dummy fin structures 412(D), active fin structures 412(N) intended for NMOS technology, and active fin structures 412(P) intended for PMOS technology. In some embodiments (not shown), the active fin structures of the assembly 400A are, with respect to what is shown in Fig. 4A, so that the active fin structures shown in Fig. 4A are intended for NMOS technology, are instead intended for PMOS technology, and vice versa; consequently, such embodiments (which are again not shown) differ from what is described in Fig. 4A, in a manner similar to how cell 208B of Fig. 2B from cell 208A of Fig. 2A differs.

[0055] Regarding the vertical direction, Fig. 4A, both a centerline of cell 408A(1) and a centerline of cell 408A(2) are substantially collinear with a horizontal reference line 405A. A stack of single-height cells 442A(1) and 442A(2) is inserted between the double-height cells 408A(1) and 408A(2) with respect to the vertical direction. A third edge 461A(3) of cell 442A(2) is substantially collinear with the reference line 405A. A first edge 463A(1) of cell 442A(1) is substantially collinear with the reference line 405A. With respect to the reference line 405A, cell 442A(2) is mirror-symmetric with respect to cell 442A(1).

[0056] The single-height cell 442A(1) is divided into a first active region 444A(N)(1) and a second active region 444A(P)(1). The first active region 444A(N)(1) is disposed between a third edge 461A(3) and a reference line 407A(1), wherein the reference line 407A(1) is substantially collinear with a centerline of the cell 442A(1). The second active region 444A(P)(1) is disposed between a first edge 461A(1) and the reference line 407A(1). The single-height cell 442A(2) is divided into a first active region 444A(N)(2) and a second active region 444A(P)(2). The first active region 444A(N)(2) is disposed between a first edge 463A(1) and a reference line 407A(2), wherein the reference line 407A(2) is substantially collinear with a centerline of the cell 442A(2). The second active region 444A(P)(2) is disposed between a third edge 463A(3) and the reference line 407A(2).

[0057] Each of the first active regions 444A(N)(1) and 444A(N)(2) has three or more active fins 412(N). Fig. 4A, each of the first active regions 444A(N)(1) and 444A(N)(2) includes two copies of the active fin 412(N). Each of the second active regions 444A(P)(1) and 444A(P)(2) includes one or more active fins 412(P). Fig. 2A, each of the second active regions 444A(P)(1) and 444A(P)(2) includes two copies of the active fin 212(P). Other numbers and / or positions of active fins are contemplated for each of the active regions 444A(N)(1), 444A(N)(2), 444A(P)(1) and / or 444A(P)(2), for example, given the different numbers and / or different positions of active fins used in Fig. 6, 7A-7D, 8A-8D, 9A-9D, 10A-10C, 11A-11D, 12A-12C and 13A-13L and discussed below, and the like.

[0058] In the single-height cell 442A(1), an instance of the dummy fin structure 412(D) is disposed, with respect to the vertical direction, substantially parallel to the centerline 407(1) in a gap between the first active region 444A(N)(1) and the second active region 444A(P)(1), the gap having a size of 455. Furthermore, an instance of the dummy fin structure 412(D) is disposed, with respect to the vertical direction, substantially parallel to the centerline 407(2) in a gap between the first active region 444A(N)(2) and the second active region 444A(P)(2), the second gap having a size of 456. A first instance of the boundary of the dummy fin structure 212(D) is arranged substantially collinear with the first edge 461A(1) of the cell 442A(1) such that the cell 442A(1) comprises substantially one half of the first instance of the boundary of the dummy fin structure 212(D).A second instance of the boundary of the dummy fin structure 412(D) is arranged substantially collinear with the third edge 463A(3) of the cell 442A(2) such that the cell 442A(2) comprises substantially one half of the second instance of the boundary of the dummy fin structure 412(D).

[0059] In Fig. 4A, each of the double-height cells 408A(1) and 408A(2) and the single-height cells 442A(1) and 442A(2) includes dummy gate structures 416(D) and active gate structures 416(A). With respect to the horizontal direction, corresponding instances of the active gate structure 416(A) each intersect one of the fin structures at Position_1 ≈ 1 / 3*fin length and Position_2 ≈ 1 / 2*fin length. In some embodiments, instances of the active gate structure 416(A) intersect the fin structures at positions other than Position_1 and Position_2. Also, with respect to the horizontal direction, corresponding instances of the dummy gate structure 416(D) each intersect one of the first and second fin structure ends of the respective fin structure.

[0060] In some embodiments, gate electrodes formed from instances of the dummy gate structure 416(D) of Fig. 4A are not included as functional components in semiconductor devices. Consequently, in some embodiments, gate electrodes resulting from instances of the dummy gate structure 416(D) are not designed for a particular conductivity. In some embodiments, a particular instance of the dummy gate structure 416(D) is intended to be a dummy rather than an active structure because the particular instance of the dummy gate structure 416(D) is disposed over one end of a corresponding active fin, such that the active fin does not sufficiently protrude in the horizontal direction beyond both sides of the particular instance of the dummy gate structure 416(D). Because the potential "active state" of the dummy gate structure 416(D) has been sacrificed, the dummy gate structure 416(D) is sometimes referred to as a sacrificial gate structure.

[0061] In design 400A, a gap 446A(1) is disposed with respect to the horizontal direction where the double-height cell 408A(1) borders the stack of single-height cells 442A(1) and 442A(2). In particular, the gap 446A(1) is disposed between the instance of the dummy gate structure 416(D) disposed near the fourth edge 421A(4) of cell 408A(1) and the instance of the dummy gate structure 416(D) disposed near both the second edge 461A(2) of cell 442A(1) and the second edge 463A(2) of cell 442A(2). As such, neither cell 442A(1) nor cell 442A(2) share an instance of dummy gate structure 416(D) with cell 408A(1), with the “unshared” state in Fig. 4A is indicated by the reference numeral 448A(1).

[0062] Likewise, in design 400A, a gap 446A(2) is disposed with respect to the horizontal direction where the double-height cell 408A(2) borders the stack of single-height cells 442A(1) and 442A(2). Specifically, the gap 446A(2) is disposed between the instance of the dummy gate structure 416(D) disposed near the second edge 421A(2) of cell 408A(1) and the instance of the dummy gate structure 416(D) disposed near both the fourth edge 461A(4) of cell 442A(2) and the fourth edge 463A(4) of cell 442A(2). As such, neither cell 442A(1) nor cell 442A(2) share an instance of dummy gate structure 416(D) with cell 408A(2), with the “unshared” state in Fig. 4A is indicated by the reference numeral 448A(2).

[0063] In Fig. 4A, with respect to the horizontal direction, a boundary between cell 408A(1) and cell 442A(1) is defined by a continuous sequence as follows: active gate structure 416(A) in cell 408A(1); dummy gate structure 416(D) in cell 408A(1); dummy gate structure 416(D) in cell 442A(1); and active gate structure 416(A) in cell 442A(1). Likewise, with respect to the horizontal direction, a boundary between cell 408A(1) and cell 442A(2) is defined by a continuous sequence as follows: active gate structure 416(A) in cell 408A(1); dummy gate structure 416(D) in cell 408A(1); dummy gate structure 416(D) in cell 442A(2); and active gate structure 416(A) in cell 442A(2).

[0064] Likewise, in Fig. 4A, with respect to the horizontal direction, a boundary between cell 442A(1) and cell 408A(2) is defined by a continuous sequence as follows: active gate structure 416(A) in cell 442A(1); dummy gate structure 416(D) in cell 442A(1); dummy gate structure 416(D) in cell 408A(2); and active gate structure 416(A) in cell 408A(2). Likewise, with respect to the horizontal direction, a boundary between cell 442A(2) and cell 408A(2) is defined by a continuous sequence as follows: active gate structure 416(A) in cell 442A(2); dummy gate structure 416(D) in cell 442A(2); dummy gate structure 416(D) in cell 408A(2); and active gate structure 416(A) in cell 408A(2).

[0065] Fig. 4B is a layout diagram 400B consistent with some embodiments.

[0066] The assembly diagram 400B of Fig. 4B is similar to the layout diagram 400A of Fig. 4A. For brevity, the discussion of layout diagram 400B focuses on the differences of layout diagram 400B with respect to layout diagram 400A. An example of a semiconductor device resulting from layout diagram 400B is semiconductor device 100 of Fig. 1, wherein instances of the cell region 104 of the semiconductor device 100 each consist of one or more of the cells 408B(1), 408B(2), 442B(1) and / or 442B(2) of Fig. 4B, or the like.

[0067] The assembly diagram 400B of Fig. 4B differs from the 400A structure of Fig. 4A in a manner similar to how cell 208C of Fig. 2C from cell 208A of Fig. 2A. Consequently, no instance of the dummy fin structure 412(D) is substantially collinear with either the reference line 407B(1) or the reference line 407B(2).

[0068] Fig. 4C is a layout diagram 400C consistent with some embodiments.

[0069] The assembly diagram 400C of Fig. 4C is similar to the layout diagram 400A of Fig. 4A. For brevity, the discussion of the layout diagram 400C focuses on the differences of the layout diagram 400C with respect to the layout diagram 400A. An example of a semiconductor device resulting from the layout diagram 400C is the semiconductor device 100 of Fig. 1, wherein instances of the cell region 104 of the semiconductor device 100 each consist of one or more of the cells 408C(1), 408C(2), 442C(1) and / or 442C(2) of Fig. 4C, or the like.

[0070] While layout diagram 4004 includes columns 446A(1) and 446A(2), with respect to layout diagram 400C, no corresponding columns are present in layout 400C, as indicated by the corresponding labels 446C(1) and 446C(2). With respect to the horizontal direction, one advantage of layout diagram 400C is that layout diagram 400C is denser than layout diagram 400A of Fig. 4A.

[0071] In Fig. 4C, with respect to the horizontal direction, the second edge 421A(2) and the fourth edge 421A(4) of the cell 408C(1) intersect in contrast to the cell 408A(1) of Fig. 4A, the fin structures substantially intersect at respective ends of the fin structures. Likewise, the second edge 421A(2) and the fourth edge 421A(4) of cell 408C(2) substantially intersect the fin structures substantially at respective ends of the fin structures. Also, the second edge 461C(2) and the fourth edge 461C(4) of cell 442C(1) substantially intersect the fin structures substantially at respective ends of the fin structures. Likewise, the second edge 461C(2) and the fourth edge 461C(4) of cell 442C(2) substantially intersect the fin structures substantially at respective ends of the fin structures.

[0072] With respect to structure 400C, a first instance of the dummy gate structure 416(D) associated with cell 408C(1) is substantially collinear with the second edge 421C(2) of cell 408C(1), such that cell 408C(1) substantially comprises one-half of the first instance of the dummy gate structure 416(D) associated with cell 408C(1). A second instance of the dummy gate structure 416(D) associated with cell 408C(1) is substantially collinear with the fourth edge 421C(4) of cell 408C(1), such that cell 408C(1) substantially comprises one-half of the second instance of the dummy gate structure 416(D) associated with cell 408C(1).Accordingly, first and second instances of the dummy gate structure 416(D) associated with the cell 408C(2) are substantially collinear with the second edge 421C(2) and the fourth edge 421C(4) of the cell 408C(2), such that the cell 408C(2) substantially comprises one half of the first and second instances of the dummy gate structure 416(D) associated with the cell 408C(2), respectively.

[0073] Also with respect to structure 400C, a first instance of dummy gate structure 416(D) associated with cell 442C(1) is substantially collinear with second edge 461C(2) of cell 442C(1) such that cell 442C(1) substantially comprises one-half of the first instance of dummy gate structure 416(D) associated with cell 442C(1). A second instance of dummy gate structure 416(D) associated with cell 408C(1) is substantially collinear with fourth edge 461C(4) of cell 442C(1) such that cell 442C(1) substantially comprises one-half of the second instance of dummy gate structure 416(D) associated with cell 442C(1).Accordingly, first and second instances of the dummy gate structure 416(D) associated with cell 442C(2) are substantially collinear with the second edge 463C(2) and the fourth edge 463C(4) of cell 442C(2), such that cell 442C(2) substantially comprises one half of the first and second instances of the dummy gate structure 416(D) associated with cell 442C(2), respectively.

[0074] As such, in structure 400C, the fourth edge 421C(4) of cell 408C(1) shares a dummy gate structure 416(D) with both the second edge 461C(2) of cell 442C(1) and the second edge 463C(2) of cell 442C(2), as indicated by label 448C(1). Consequently, with respect to the horizontal direction, where the double-height cell 408C(1) borders the stack of single-height cells 442C(1) and 422C(2), there is again no gap, as indicated by label 446C(1). Additionally, the second edge 421C(2) of cell 408C(2) shares a dummy gate structure 416(D) with both the fourth edge 461C(4) of cell 442C(1) and the fourth edge 463C(4) of cell 442C(2), as indicated by the label 448C(2).Consequently, with respect to the horizontal direction, where the double-height cell 408C(2) adjoins the stack of single-height cells 442C(1) and 422C(2), there is again no gap, as indicated by the label 446C(2).

[0075] In Fig. 4C, a boundary with respect to the horizontal direction between cell 408C(1) and cell 442C(1) is defined by a continuous sequence as follows: active gate structure 416(A) in cell 408C(1); dummy gate structure 416(D) shared by cell 408C(1) and cell 442C(1); and active gate structure 416(A) in cell 442A(1). Likewise, a boundary with respect to the horizontal direction between cell 408C(1) and cell 442C(2) is defined by a continuous sequence as follows: active gate structure 416(A) in cell 408C(1); dummy gate structure 416(D) shared by cell 408C(1) and cell 442C(1); and active gate structure 416(A) in cell 442C(2).

[0076] In Fig. 4C, a boundary with respect to the horizontal direction between cell 442C(1) and cell 408C(2) is defined by a continuous sequence as follows: active gate structure 416(A) in cell 442C(1); dummy gate structure 416(D) shared by cell 442C(1) and cell 408C(2); and active gate structure 416(A) in cell 408C(2). Likewise, a boundary with respect to the horizontal direction between cell 442C(2) and cell 408C(2) is defined by a continuous sequence as follows: active gate structure 416(A) in cell 442C(2); dummy gate structure 416(D) shared by cell 442C(2) and cell 408C(2); and active gate structure 416(A) in cell 408C(2).

[0077] Fig. 4D is a layout diagram 400D consistent with some embodiments.

[0078] The assembly diagram 400D of Fig. 4D is similar to the assembly diagram 400C of Fig. 4C. For brevity, the discussion of the layout diagram 400D focuses on the differences of the layout diagram 400D with respect to the layout diagram 400C. An example of a semiconductor device resulting from the layout diagram 400D is the semiconductor device 100 of Fig. 1, wherein instances of the cell region 104 of the semiconductor device 100 accordingly consist of one or more of the cells 408D(1), 408D(2), 442D(1) and / or 442D(2) of Fig. 4D, or the like.

[0079] The assembly diagram 400D of Fig. 4D differs from the 400C structure of Fig. 4C in a manner similar to how cell 208C of Fig. 2C from cell 208A of Fig. 2A. Consequently, substantially no instance of dummy fin 412(D) is substantially collinear with either datum line 407C(1) or datum line 407C(2).

[0080] Fig. 5A is a layout diagram 500A consistent with some embodiments.

[0081] The layout diagram 500A includes double-height cells 508A(1) and 508A(2), double-height cells 532A and 534A, and single-height cells 536A. Cell 508A(i) of Fig. 5A is similar to cell 208A of Fig. 2A. Cell 508A(2) of Fig. 5A is similar to cell 208B of Fig. 2B. Cell 536A of Fig. 5A is similar to cells 442A(1) and 442A(2) of Fig. 4A. For brevity, the discussion of cells 508A(i) and 508A(2) focuses on differences with respect to the corresponding cells 208B and 208A. Likewise, for brevity, the discussion of cell 536A focuses on differences with respect to the corresponding cells 442A(1) and 442A(2). An example of a semiconductor device resulting from the layout diagram 5004 is the semiconductor device 100 of Fig. 1, wherein instances of the cell region 104 of the semiconductor device 100 accordingly consist of one or more of the cells 508A(1), 508A(2), 536A, 532A and 534A of Fig. 5A, or the like.

[0082] In layout diagram 5004, each of cells 508A(1), 508A(2), 536A, 532A, and 534A is dedicated to FinFET technology and includes fin structures extending substantially parallel to a first direction. For reference purposes, there is a second direction that is substantially perpendicular to the first direction. Fig. 5A, the first and second directions correspond to the horizontal and vertical directions, respectively. In some embodiments, the first and second directions are directions other than the horizontal and vertical directions. The fin structures include dummy fin structures, active fin structures intended for NMOS technology, and active fin structures intended for PMOS technology, wherein in Fig. 5A, none of which are labeled with reference numbers for ease of illustration. The layout diagram 500A further includes power grid segment (PG) structures, some of which are designated for a voltage VDD and some for a voltage VSS. Although they are labeled with the identifier VDD or VSS, in Fig. 5A, for ease of illustration, the corresponding PG structures are not labeled with reference numbers. In some embodiments (not shown), the active fin structures and the PG structures of assembly 500A are identical with respect to what is shown in Fig. 5A, so that active fin structures that are in Fig. 5A are intended for NMOS technology are instead intended for PMOS technology, and PG structures intended for VSS are instead intended for VDD, and vice versa; consequently, such embodiments (again not shown) differ from what is described in Fig. 5A, in a similar manner as the cell 208B of Fig. 2B from cell 208A of Fig. 2A differs.

[0083] In Fig. 5A, a labeling convention is established for ease of illustration. In particular, with respect to a sequence in the vertical direction, a single-height cell 536A is labeled "PN." Here, "PN" indicates that cell 536A comprises a single active region having active fin structures dedicated to PMOS technology and a single active region having active fin structures dedicated to NMOS technology. For ease of illustration in Fig. 5A, none of the active regions in cell 536A are labeled with reference numerals. Also, each instance of cell 534 includes a single active region, which may be labeled "P" or "N" to indicate that the single active region includes active fin structures, each dedicated to PMOS technology or NMOS technology. To simplify the illustration in Fig. 5A, the active area is not labeled with a reference number in any of the instances of cell 534A.

[0084] Regarding the labeling convention of Fig. 5A, the double-height cell 508A(1) is labeled "PNNP" with respect to a sequence in the vertical direction. "PNNP" here indicates that cell 508A(1) corresponds to a stack (in the vertical direction) of two instances of a single-height "PN" cell 536A, but the "NN" portion of cell 508A(1) represents a larger single active area having active fin structures dedicated to NMOS technology, rather than two separate smaller active fin structures dedicated to NMOS technology (see the above discussion of cell 208A of Fig. 2A). To simplify the presentation in Fig. 5A, none of the active areas in cell 508A(1) are labeled with reference numerals. In the same manner, with respect to a sequence in the vertical direction, the double-height cell 508A(2) is labeled "NPPN." "NPPN" here indicates that cell 508A(1) corresponds to a stack (in the vertical direction) of two instances of a single-height "NP" cell (not shown), but the "PP" portion of cell 508A(2) represents a larger single active area comprising active fin structures dedicated to PMOS technology, rather than two separate smaller active fin structures dedicated to PMOS technology (see the above discussion of cell 208B of Fig. 2B). To simplify the presentation in Fig. 5A, none of the active areas in cell 508A(2) are labeled with reference numbers.

[0085] With further reference to the labeling convention of Fig. 5A, the double-height cell 532A is labeled "PPNN" with respect to a sequence in the vertical direction. Here, "PPNN" indicates that the cell 532A corresponds to a version of the single-height cell 536A that has been stretched / scaled to double height from the single-height cell 536A. Thus, the cell 532A comprises a single active area having active fin structures dedicated to PMOS technology and a single active area having active fin structures dedicated to NMOS technology. With respect to the vertical direction, the size S_532A of the single PMOS active area and the single NMOS active area in the cell 532A is larger than a size S_536A of the single PMOS active area and the single NMOS active area in the cell 536A.The size S_532A is larger than the size S_536A because both the single PMOS active region and the single NMOS active region in cell 532A are configured in a similar manner to cell 208A of FIG. Fig. 2A has additional fins, have additional fins. A sum, Σ, of active fins in both each of the individual PMOS active regions and the individual NMOS active region in cell 532A is Σ = 2*m+n, where m and n are positive integers, m is a variable representing the number in both each of the individual PMOS active regions and the individual NMOS active region in cell 536A, and n is a variable representing the number of additional fins in both each of the individual PMOS active regions and the individual NMOS active region in cell 536A.

[0086] In Fig. 5A, with respect to the vertical direction, the centerlines 537A of the cells 508A(1) are offset from the centerlines 538A of the cells 508A(2). With respect to the vertical direction, to the extent that a first existing instance of the cell 508A(1) overlaps a first existing instance of the cell 508A(2), wherein a first edge 521A(1) or a third edge 521(3) of the first existing instance of the cell 508A(1) is substantially collinear with the centerline 538A of the first existing instance of the cell 508A(2). And further to the extent that a second existing instance of cell 508A(2) overlaps a second existing instance of cell 508A(1), wherein a first edge 521A(1) or a third edge 521(3) of the second existing instance of cell 508A(2) is substantially collinear with the centerline 537A of the second existing instance of cell 508A(1).

[0087] Fig. 5B is a layout diagram 500B consistent with some embodiments.

[0088] The assembly diagram 500B of Fig. 5B is similar to the assembly diagram 500A of Fig. 5A. For brevity, the discussion of the layout diagram 500B focuses on the differences of the layout diagram 500B with respect to the layout diagram 500A. An example of a semiconductor device resulting from the layout diagram 500B is the semiconductor device 100 of Fig. 1, wherein instances of the cell region 104 of the semiconductor device 100 accordingly consist of one or more of the cells 508B(1), 508B(2), 536B, 532B and 534B of Fig. 5B, or the like.

[0089] The assembly diagram 500B of Fig. 5B differs from the 500A structure of Fig. 5A in a manner similar to how cell 208C of Fig. 2C from cell 208A of Fig. 2A. Consequently, no instances of the dummy fin structures are substantially collinear with any of the reference lines 507B(1) - 507B(5).

[0090] Fig. 5C is a layout diagram 500C in accordance with some embodiments.

[0091] The assembly diagram 500C of Fig. 5C is similar to the layout diagram 500A of Fig. 5A. For brevity, the discussion of the layout diagram 500C focuses on the differences of the layout diagram 500C with respect to the layout diagram 500A. An example of a semiconductor device resulting from the layout diagram 500C is the semiconductor device 100 of Fig. 1, wherein instances of the cell region 104 of the semiconductor device 100 accordingly consist of one or more of the cells 508C(1), 508C(2), 536C, 532C and 534C of Fig. 5C, or the like.

[0092] While layout diagram 500A includes columns 546A(1) and 546A(2), layout diagram 500C lacks corresponding columns, as indicated by the corresponding labels 546C(1) and 546C(2). With respect to the horizontal direction, one advantage of layout diagram 500C is that layout diagram 500C is denser than layout diagram 500A of Fig. 5A.

[0093] In Fig. 5C is a boundary, with respect to the horizontal direction, between an instance of a first cell, e.g., cell 508C(1), and a second cell, e.g., an instance of cell 508C(2), defined by a continuous sequence as follows: an instance of the active gate structure in cell 508C(1); an instance of the dummy gate structure shared by cell 508C(1) and cell 508C(2); and an instance of the active gate structure in cell 508C(2).

[0094] Fig. 5D is a layout diagram 500D consistent with some embodiments.

[0095] The assembly diagram 500D of Fig. 5D is similar to the assembly diagram 500C of Fig. 5C. For brevity, the discussion of the layout diagram 500D focuses on the differences of the layout diagram 500D with respect to the layout diagram 500C. An example of a semiconductor device resulting from the layout diagram 500D is the semiconductor device 100 of Fig. 1, wherein instances of the cell region 104 of the semiconductor device 100 accordingly consist of one or more of the cells 508D(1), 508D(2), 536D, 532D and 534D of Fig. 5D, or the like.

[0096] The assembly diagram 500D of Fig. 5D differs from the 500C structure of Fig. 5C in a manner similar to that in which cell 208C of Fig. 2C from cell 208A of Fig. 2A. Consequently, no instances of the dummy fin structures are substantially collinear with any of the reference lines 507D(1) - 507D(5).

[0097] Fig. 6 is a combination diagram showing how a layout diagram 600 relates to a "building block" in the form of a second layout diagram 600' in accordance with some embodiments.

[0098] The layout diagram 600 has a double height cell 608. The cell 608 is, for example, similar to the cell 208A of Fig. 2A and cell 208B of Fig. 2B. The layout diagram 600' includes a cell 604. The cell 604 is, for example, similar to cells 442A(1) and 442A(2) of Fig. 4A. For brevity, the discussion of cell 600 focuses on the differences of cell 600 with respect to cell 208A and cell 208B, and the discussion of cell 604 focuses on the differences of cell 604 with respect to 442A(1) and 442A(2). In some embodiments, cell 600 is used as a standard cell in a library of standard cells. An example of a semiconductor device resulting from a layout diagram including cell 600 is semiconductor device 100 of Fig. 1, where cell region 104 of semiconductor device 100 results from cell 600. Cell 608 is summarized in row 5 of the table below.

[0099] Each of the cells 600 and 600' is designed for FinFET technology and has fin structures extending substantially parallel to a first direction. For reference purposes, there is a second direction that is substantially perpendicular to the first direction. Fig. 6, the first and second directions correspond to the horizontal and vertical directions, respectively. In some embodiments, the first and second directions are directions other than the horizontal and vertical directions. The fin structures include dummy fin structures 612(D) and active fin structures 612(X). In some embodiments, a first set of active fin structures 612(X) is dedicated to NMOS technology, and a second set of active fin structures 612(X) is dedicated to PMOS technology, in a manner similar to that, for example, in cell 208A of Fig. 2A. In some embodiments, the first and second sets of active fin structures 612(X) are reversed, such that the first set of active fin structures 612(X) is instead dedicated to PMOS technology, and the second set of active fin structures 612(X) is instead dedicated to NMOS technology, in a manner similar to, for example, cell 208B of Fig. 2B.

[0100] The cell 600 is divided into a first active region 650(1), a second active region 650(2), and a third active region 650(3). The first active region 650(1) comprises a sequence of three or more consecutive active fins 612(X) designed for NMOS / PMOS. The second active region 650(2) comprises one or more active fins 612(X) designed for PMOS / NMOS. The third active region 650(3) comprises one or more active fins 612(X) designed for PMOS / NMOS. As shown in Fig. 6, the first active region 650(1) comprises a sequence of three consecutive active fins 612(X) designed for NMOS / PMOS, the second active region 650(2) comprises one active fin 612(X) designed for PMOS / NMOS, and the third active region 650(3) comprises one active fin 612(X) designed for PMOS / NMOS. The cell 604 is divided into a first active region 650(1)' and a second active region 650(2)'. The first active region 650(1)' comprises one or more active fins 612(X) designed for PMOS / NMOS. The second active region 650(2)' comprises one or more active fins 612(X) designed for PMOS / NMOS. As shown in Fig. 6, the first active region 650(1)' includes an active fin 612(X) designed for NMOS / PMOS, and the second active region 650(2)' includes an active fin 612(X) designed for PMOS / NMOS. Other numbers of active fins and / or positions of active fins are contemplated for the first active region 650(1), the second active region 650(2), and the third active region 650(3), and accordingly also for the first active region 650(1)' and the second active region 650(2)', for example, in view of the different numbers of active fins discussed below. Fig. 7A - 7D, 8A - 8D, 9A - 9D, 10A - 10C, 11A - 11D, 12A - 12C and 13A - 13L, and the like.

[0101] In Fig. 6, cell 604 has a first edge 661(1), a second edge 661(2), a third edge 661(3), and a fourth edge 661(4). The third edge 661(3) of cell 604 is substantially collinear with a reference line 605'. Cell 608 is based, with respect to the vertical direction, on a stack of first and second copies (not shown) of cell 604. Cell 608 has a first edge 621(1), a second edge 621(2), a third edge 621(3), and a fourth edge 621(4). Indeed, using the reference line 605' as a rotation axis, the first copy of the cell 604 is rotated 180 degrees about the reference line 605' and arranged such that the third edge 661(3) of the first copy of the cell 604 is collinear with a reference line 605.Likewise, in fact, the second copy of cell 604 is aligned the same as cell 604 and is stacked on top of the first copy of cell 604 such that the third edge 661(3) of the second copy of cell 604 is collinear with a reference line 605. Thus, the second active area 650(2) in cell 608 corresponds to the second active area 650(2)' in the second copy of cell 604, the third active area 650(3) in cell 608 corresponds to the second active area 650(2)' in the first copy of cell 604, a first portion of the first active area 650(1) in cell 608 corresponds in part to the first active area 650(1)' in the second copy of cell 604; and a second portion of the first active area 650(1) in cell 608 corresponds in part to the first active area 650(1)' in the first copy of cell 604.

[0102] In cell 608, the first active region 650(1) further includes a third portion between the first and second portions with respect to the vertical direction. The third portion of the first active region 650(1) includes one or more additional fins. As shown in Fig. 6, the third portion of the first active region 650(1) includes an additional NMOS / PMOS-designed active fin 612(X). Other numbers of additional active fins are contemplated for the first active region 650(1), for example, in light of the various numbers of additional active fins described in the following Fig. 7A - 7D, 8A - 8D, 9A - 9D, 10A - 10C, 11A - 11D, 12A - 12C and 13A - 13L, and the like.

[0103] The reference line 605 represents a center line of the cell 608 with respect to the vertical direction. With respect to the reference line 605, the cell 608 is mirror-symmetrical.

[0104] Fig. 7A-7D are combination diagrams showing how layout diagrams 700A-700D relate to corresponding "building blocks" in the form of corresponding layout diagrams 700A'-700D' in accordance with some embodiments.

[0105] For example, each of the layout diagrams 700A - 700D is similar to the layout diagram 600 of Fig. 6. Each of the layout diagrams 700A' - 700D' is, for example, similar to the layout diagram 600' of Fig. 6.

[0106] The layout diagrams 700A - 700D include corresponding double-height cells 708A - 708D and 704A - 704D. The semiconductor device 100 of Fig. 1 is an example of a semiconductor device resulting from layout diagrams comprising cells 708A-708D, respectively, wherein the cell region 104 of the semiconductor device 100 results from the corresponding cells 708A-708D. The cells 708A-708D are summarized in the respective rows 6-9 of the table below.

[0107] For example, cells 708A - 708D are similar to cells 608 of Fig. 6, however, cells 708A-708D also differ from 608 with respect to different numbers of active fins in first active regions 750A(1)-750D(1), second active regions 750A(2)-750D(2), and third active regions 750A(3)-750D(3) and / or different positions (with respect to the vertical direction) of the first active regions 750A(i)-750D(1), the second active regions 750A(2)-750D(2), and the third active regions 750A(3)-750D(3). Cells 704A-704D are, for example, similar to cell 604 of Fig. 6, however, cells 704A-704D also differ from 604 with respect to different numbers of active fins in first active regions 750A(1)'-750D(1)' and second active regions 750A(2)'-750D(2)' and / or different positions (with respect to the vertical direction) of first active regions 750A(1)'-750D(1)' and second active regions 750A(2)'-750D(2)'.

[0108] Fig. 8A-8D are combination diagrams showing how layout diagrams 800A-800D relate to corresponding "building blocks" in the form of corresponding layout diagrams 800A'-800D' in accordance with some embodiments.

[0109] For example, each of the layout diagrams 800A - 800D is similar to the layout diagram 600 of Fig. 6. Each of the layout diagrams 800A' - 800D' is, for example, similar to the layout diagram 600' of Fig. 6.

[0110] The layout diagrams 800A - 800D include corresponding double-height cells 808A - 808D and 804A - 804D. The semiconductor device 100 of Fig. 1 is an example of a semiconductor device resulting from layout diagrams comprising cells 808A-808D, respectively, wherein the cell region 104 of the semiconductor device 100 results from the corresponding cells 808A-808D. The cells 808A-808D are summarized in the respective rows 10-13 of the table below.

[0111] For example, cells 808A - 808D are similar to cell 608 of Fig. 6, however, cells 808A-808D also differ from 608 with respect to different numbers of active fins in first active regions 850A(1)-850D(1), second active regions 850A(2)-850D(2), and third active regions 850A(3)-850D(3) and / or different positions (with respect to the vertical direction) of the first active regions 850A(1)-850D(1), the second active regions 850A(2)-850D(2), and the third active regions 850A(3)-850D(3). Cells 804A-804D are, for example, similar to cell 604 of Fig. 6, however, cells 804A-804D also differ from 604 with respect to different numbers of active fins in first active regions 850A(1)'-850D(1)' and second active regions 850A(2)'-850D(2)' and / or different positions (with respect to the vertical direction) of the first active regions 850A(1)'-850D(1)' and second active regions 850A(2)'-850D(2)'.

[0112] Fig. 9A-9D are combination diagrams showing how layout diagrams 900A-900D relate to corresponding "building blocks" in the form of corresponding layout diagrams 900A'-900D' in accordance with some embodiments.

[0113] For example, each of the layout diagrams 900A - 900D is similar to the layout diagram 600 of Fig. 6. Each of the layout diagrams 900A' - 900D' is, for example, similar to the layout diagram 600' of Fig. 6. In addition, Fig. 9D in some aspects Fig. 2A.

[0114] The layout diagrams 900A - 900D include corresponding double-height cells 908A - 908D and 904A - 904D. The semiconductor device 100 of Fig. 1 is an example of a semiconductor device resulting from layout diagrams comprising cells 908A-908D, respectively, wherein the cell region 104 of the semiconductor device 100 results from the corresponding cells 908A-908D. The cells 908A-908D are summarized in the respective rows 14-17 of the table below.

[0115] For example, cells 908A - 908D are similar to cell 608 of Fig. 6, however, cells 908A-908D also differ from 608 with respect to different numbers of active fins in first active regions 950A(1)-950D(1), second active regions 950A(2)-950D(2), and third active regions 950A(3)-950D(3) and / or different positions (with respect to the vertical direction) of the first active regions 950A(1)-950D(1), the second active regions 950A(2)-950D(2), and the third active regions 950A(3)-950D(3). It should be noted that cell 908D of cell 208A of Fig. 2A and cell 208B of Fig. 2B. For example, cells 904A - 904D are similar to cell 604 of Fig. 6, however, cells 904A-904D also differ from 604 with respect to different numbers of active fins in first active regions 95A(1)'-950D(1)' and second active regions 950A(2)'-950D(2)' and / or different positions (with respect to the vertical direction) of the first active regions 950A(1)'-950D(1)' and second active regions 950A(2)'-950D(2)'.

[0116] The Fig. 10A-10C are combination diagrams showing how layout diagrams 1000A-1000C relate to corresponding "building blocks" in the form of corresponding layout diagrams 1000A'-1000C' in accordance with some embodiments.

[0117] For example, each of the layout diagrams 1000A - 1000C is similar to the layout diagram 600 of Fig. 6. Each of the layout diagrams 1000A' - 1000C' is, for example, similar to the layout diagram 600' of Fig. 6. The assembly diagrams 1000A' - 1000C' are, for example, similar to corresponding assembly diagrams 800A' - 800C' of the respective Fig. 8A - 8C.

[0118] The layout diagrams 1000A - 1000C include corresponding double-height cells 1008A - 1008C and 1004A - 1004C. The semiconductor device 100 of Fig. 1 is an example of a semiconductor device resulting from layout diagrams comprising cells 1008A-1008C, respectively, wherein the cell region 104 of the semiconductor device 100 results from the corresponding cells 1008A-1008C. The cells 1008A-1008C are summarized in the respective rows 18-20 of the table below.

[0119] For example, cells 1008A - 1008C are similar to cell 608 of Fig. 6, however, cells 1008A-1008C also differ from 608 with respect to different numbers of active fins in first active regions 1050A(1)-1050C(1), second active regions 1050A(2)-1050C(2), and third active regions 1050A(3)-1050C(3) and / or different positions (with respect to the vertical direction) of the first active regions 1050A(1)-1050C(1), the second active regions 1050A(2)-1050C(2), and the third active regions 1050A(3)-1050C(3). Cells 1004A-1004C are, for example, similar to cell 604 of Fig. 6, however, cells 1004A-1004C also differ from 604 with respect to different numbers of active fins in first active regions 1050A(1)'-1050C(1)' and second active regions 1050A(2)'-1050C(2)' and / or different positions (with respect to the vertical direction) of first active regions 1050A(1)'-1050C(1)' and second active regions 1050A(2)'-1050C(2)'.

[0120] The Fig. 11A-11D are combination diagrams showing how layout diagrams 1100A-1100D relate to corresponding "building blocks" in the form of corresponding layout diagrams 1100A'-1100D' in accordance with some embodiments.

[0121] For example, each of the layout diagrams 1100A - 1100D is similar to the layout diagram 600 of Fig. 6. Each of the layout diagrams 1100A' - 1100D' is, for example, similar to the layout diagram 600' of Fig. 6. The assembly diagrams 1100A' - 1100D' are, for example, similar to corresponding assembly diagrams 900A' - 900D' of the respective Fig. 9A - 9C.

[0122] The layout diagrams 1100A - 110D include corresponding double-height cells 1108A - 1108D and 1104A - 1104D. The semiconductor device 100 of Fig. 1 is an example of a semiconductor device resulting from layout diagrams comprising cells 1108A-1108D, respectively, wherein the cell region 104 of the semiconductor device 100 results from the corresponding cells 1108A-1108D. The cells 1108A-1108D are summarized in the respective rows 21-24 of the table below.

[0123] For example, cells 1108A - 1108D are similar to cell 608 of Fig. 6, however, cells 1108A-1108D also differ from 608 with respect to different numbers of active fins in first active regions 1150A(1)-1150D(1), second active regions 1150A(2)-1150D(2), and third active regions 1150A(3)-1150D(3) and / or different positions (with respect to the vertical direction) of the first active regions 1150A(1)-1150D(1), the second active regions 1150A(2)-1150D(2), and the third active regions 1150A(3)-1150D(3). Cells 1104A-1104D are, for example, similar to cell 604 of Fig. 6, however, cells 1104A-1104D also differ from 604 with respect to different numbers of active fins in first active regions 1150A(1)'-1150D(1)' and second active regions 1150A(2)'-1150D(2)' and / or different positions (with respect to the vertical direction) of first active regions 1150A(1)'-1150D(1)' and second active regions 1150A(2)'-1150D(2)'.

[0124] The Fig. 12A-12C are combination diagrams showing how layout diagrams 1200A-1200C relate to corresponding "building blocks" in the form of corresponding layout diagrams 1200A'-1200C' in accordance with some embodiments.

[0125] The assembly diagrams 1200A - 1200C are, for example, equal to corresponding assembly diagrams 800A - 800C of the respective Fig. 8A - 8C. Each of the layout diagrams 1200A' - 1200C' is, for example, similar to the layout diagram 700A' of Fig. 7A. The assembly diagrams 1200A'' - 1200C'' are, for example, similar to corresponding assembly diagrams 800A' - 800C' of the respective Fig. 8A - 8C.

[0126] The layout diagrams 1200A - 1200C include corresponding double-height cells 1208A - 1208C and 1204A - 1204C. The semiconductor device 100 of Fig. 1 is an example of a semiconductor device resulting from layout diagrams comprising cells 1208A-1208C, respectively, wherein the cell region 104 of the semiconductor device 100 results from the corresponding cells 1208A-1208C. The cells 1208A-1208C are summarized in the respective rows 25-27 of the table below.

[0127] For example, cells 1208A - 1208C are similar to cell 608 of Fig. 6, however, cells 1208A-1208C also differ from 608 with respect to different numbers of active fins in first active regions 1250A(1)-1250C(1), second active regions 1250A(2)-1250C(2), and third active regions 1250A(3)-1250C(3) and / or different positions (with respect to the vertical direction) of the first active regions 1250A(1)-1250C(1), the second active regions 1250A(2)-1250C(2), and the third active regions 1250A(3)-1250C(3). Cells 1204A-1204C are, for example, similar to cell 604 of Fig. 6, however, cells 1204A-1204C also differ from 604 with respect to different numbers of active fins in first active regions 1250A(1)'-1250C(1)' and second active regions 1250A(2)'-1250C(2)' and / or different positions (with respect to the vertical direction) of first active regions 1250A(1)'-1250C(1)' and second active regions 1250A(2)'-1250C(2)'.

[0128] The Fig. 13A-13D are combination diagrams showing how layout diagrams 1300A-1300D relate to corresponding "building blocks" in the form of corresponding layout diagrams 1300A'-1300D' in accordance with some embodiments.

[0129] For example, the layout diagram 1300A is similar to the layout diagram 900A of Fig. 9A. The layout diagram 1300B is, for example, similar to the layout diagram 900C of Fig. 9C. The layout diagram 1300C is, for example, similar to the layout diagrams 900A - 900B of the corresponding Fig. 9A - 9B. The layout diagram 1300D is, for example, similar to the layout diagrams 900C - 900D of the corresponding Fig. 9C - 9D.

[0130] For example, each of the layout diagrams 1300A' - 1300D' is similar to the layout diagram 700B' of Fig. 7B. The layout diagram 1300A'' is, for example, similar to the layout diagram 900A' of Fig. 9A. The layout diagram 1300B'' is, for example, similar to the layout diagram 900B' of Fig. 9B. The layout diagram 1300C'' is, for example, similar to the layout diagram 900C' of Fig. 9C. The layout diagram 1300D'' is, for example, similar to the layout diagram 900D' of Fig. 9D.

[0131] The layout diagrams 1300A - 1300D include corresponding double-height cells 1308A - 1308D and 1304A - 1304D. The semiconductor device 100 of Fig. 1 is an example of a semiconductor device resulting from layout diagrams comprising cells 1308A-1308D, respectively, wherein the cell region 104 of the semiconductor device 100 results from the corresponding cells 1308A-1308D. The cells 1308A-1308D are summarized in the respective rows 28-31 of the table below.

[0132] For example, cells 1308A - 1308D are similar to cell 608 of Fig. 6, however, cells 1308A-1308D also differ from 608 with respect to different numbers of active fins in first active regions 1350A(1)-1350D(1), second active regions 1350A(2)-1350D(2), and third active regions 1350A(3)-1350D(3) and / or different positions (with respect to the vertical direction) of the first active regions 1350A(1)-1350D(1), the second active regions 1350A(2)-1350D(2), and the third active regions 1350A(3)-1350D(3). Cells 1304A-1304D are, for example, similar to cell 604 of Fig. 6, however, cells 1304A-1304D also differ from 604 with respect to different numbers of active fins in first active regions 1350A(1)'-1350D(1)' and second active regions 1350A(2)'-1350D(2)' and / or different positions (with respect to the vertical direction) of first active regions 1350A(1)'-1350D(1)' and second active regions 1350A(2)'-1350D(2)'.

[0133] The Fig. 13E-13H are combination diagrams showing how layout diagrams 1300E-1300H relate to corresponding "building blocks" in the form of corresponding layout diagrams 1300E'-1300H' in accordance with some embodiments.

[0134] For example, the layout diagram 1300E is similar to the layout diagrams 900A - 900B of the corresponding Fig. 9A - 9B. The layout diagram 1300F is, for example, similar to the layout diagrams 900C - 900D of the corresponding Fig. 9C - 9D. The layout diagram 1300G is, for example, similar to the layout diagram 900B of Fig. 9B. The layout diagram 1300H is, for example, similar to the layout diagrams 900B and 900D of the corresponding Fig. 9B and Fig. 9D.

[0135] For example, each of the layout diagrams 1300E' - 1300H' is similar to the layout diagram 700C' of Fig. 7C. The layout diagram 1300E'' is, for example, similar to the layout diagram 900A' of Fig. 9A. The layout diagram 1300F'' is, for example, similar to the layout diagram 900B' of Fig. 9B. The layout diagram 1300G'' is, for example, similar to the layout diagram 900C' of Fig. 9C. The layout diagram 1300H'' is, for example, similar to the layout diagram 900D' of Fig. 9D.

[0136] The layout diagrams 1300E - 1300H include corresponding double-height cells 1308E - 1308H and 1304E - 1304H. The semiconductor device 100 of Fig. 1 is an example of a semiconductor device resulting from layout diagrams comprising cells 1308E-1308H, respectively, wherein the cell region 104 of the semiconductor device 100 results from the corresponding cells 1308E-1308H. The cells 1308E-1308H are summarized in the respective rows 28-31 of the table below.

[0137] For example, cells 1308E - 1308H are similar to cell 608 of Fig. 6, however, cells 1308E-1308H also differ from 608 with respect to different numbers of active fins in first active regions 1350E(1)-1350H(1), second active regions 1350E(2)-1350H(2), and third active regions 1350E(3)-1350H(3) and / or different positions (with respect to the vertical direction) of the first active regions 1350E(1)-1350H(1), the second active regions 1350E(2)-1350H(2), and the third active regions 1350E(3)-1350H(3). Cells 1304E-1304H are, for example, similar to cell 604 of Fig. 6, however, cells 1304E-1304H also differ from 604 with respect to different numbers of active fins in first active regions 1350E(1)'-1350H(1)' and second active regions 1350E(2)'-1350H(2)' and / or different positions (with respect to the vertical direction) of first active regions 1350E(1)'-1350H(1)' and second active regions 1350E(2)'-1350H(2)'.

[0138] The Fig. 13I-13L are combination diagrams showing how layout diagrams 1300I-1300L relate to corresponding "building blocks" in the form of corresponding layout diagrams 1300I'-1300L' in accordance with some embodiments.

[0139] For example, the layout diagram 1300I is similar to the layout diagrams 900A and 900C of the corresponding Fig. 9A and Fig. 9C. The layout diagram 1300J is, for example, similar to the layout diagram 900C of Fig. 9C. The layout diagram 1300K is, for example, similar to the layout diagrams 900B and 900C of the corresponding Fig. 9B and Fig. 9C. The layout diagram 1300L is, for example, similar to the layout diagrams 900C and 900D of the corresponding Fig. 9C and Fig. 9D.

[0140] For example, each of the layout diagrams 1300I' - 1300L' is similar to the layout diagram 700D' of Fig. 7D. Each of the layout diagrams 1300A'', 1300E'' and 1300I'' is, for example, similar to the layout diagram 900A' of Fig. 9A. Each of the layout diagrams 1300B'', 1300F'' and 1300J'' is, for example, similar to the layout diagram 900B' of Fig. 9B. Each of the layout diagrams 1300C'', 1300G'' and 1300K'' is, for example, similar to the layout diagram 900C' of Fig. 9C. Each of the layout diagrams 1300D'', 1300H'' and 1300L'' is, for example, similar to the layout diagram 900D' of Fig. 9D.

[0141] The layout diagrams 1300I - 1300L include corresponding double-height cells 1308I - 1308L and 1304I - 1304L. The semiconductor device 100 of Fig. 1 is an example of a semiconductor device resulting from layout diagrams comprising cells 1308I-1308L, respectively, wherein the cell region 104 of the semiconductor device 100 results from the corresponding cells 1308I-1308L. The cells 1308I-1308L are summarized in the respective rows 28-31 of the table below.

[0142] For example, cells 13081 - 1308L are similar to cell 608 of Fig. 6, however, cells 1308I-1308L also differ from 608 with respect to different numbers of active fins in first active regions 1350I(1)-1350L(1), second active regions 1350I(2)-1350L(2), and third active regions 1350I(3)-1350L(3) and / or different positions (with respect to the vertical direction) of the first active regions 1350I(1)-1350L(1), the second active regions 1350I(2)-1350L(2), and the third active regions 1350I(3)-1350L(3). Cells 1304I-1304L are, for example, similar to cell 604 of Fig. 6, however, cells 1304I-1304L also differ from 604 with respect to different numbers of active fins in first active regions 1350I(1)'-1350L(1)' and second active regions 1350I(2)'-1350L(2)' and / or different positions (with respect to the vertical direction) of first active regions 1350I(1)'-1350L(1)' and second active regions 1350I(2)'-1350L(2)'.

[0143] Some of the attributes of cells 208A - 208D, 608, 708A - 708D, 808A - 808D, 908A - 908D, 1008A - 1008C, 1108A - 1108D, 1208A - 1208C and 1308A - 1308L from corresponding FIGS. of the corresponding Fig. 2A - 2B are summarized in the following table. Likewise, some of the attributes of cells 200A - 200B of the corresponding Fig. 2A - 2D, 6, 7A - 7D, 8A - 8C, 9A - 9D, 104 - 10C, 11A - 11D, 12A - 12C and 13A - 13L (discussed above) are summarized in the following table.

[0144] In particular, lines 1 - 39 of the following table contain information on the Fig. 2A - 2D, 6, 7A - 7D, 8A - 8C, 9A - 9D, 104 - 10C, 11A - 11D, 12A - 12C, and 13A - 13L (discussed above). For a particular cell (indicated by the respective row of the table), columns 3, 4, and 5 of the table indicate the number of active fins located in the second active region x50y(2), the first active region x50y(1), and the third active region x50y(3), respectively. For example, row 7 of the table thus refers to cell 708B of Fig. 7B that: in column 3 with respect to “x50y(2)”, x = 7 and y = B, thus column 3 refers to the second active region 750B(2) having 1 active fin; in column 4 with respect to “x50y(1)”, x = 7 and y = B, thus column 4 refers to the first active region 750B(1) having 3 active fins; in column 5 with respect to “x50y(3)”, x = 7 and y = B, thus column 5 refers to the third active region 750B(3) having 1 active fin; column 6 indicates that the second active region 750A(2) and the third active region 750A(3) are symmetric; column 7 indicates that the total number (Σ) of active and dummy fins in cell 708B is 10; Column 8 indicates that an additional fin is substantially collinear with a centerline (with respect to the vertical direction) of cell 708B; Column 9 indicates that cell 708B includes one additional active fin;and column 10 indicates that first and second dummy fins are substantially collinear with the first (upper) and third (lower) edges of cell 708B, which implies that 1 / 2 of the first dummy fin and 1 / 2 of the second dummy fin are contained in cell 708B. ;

[0145] Fig. 14A is a flow diagram of a method 1400 for generating a layout diagram of a standard cell in accordance with some embodiments.

[0146] For example, the method 1400 is feasible using the EDA system 1500 ( Fig. 15, discussed below) in accordance with some embodiments.

[0147] In Fig. 14A, method 1400 includes blocks 1422-1432. At block 1422, a standard cell is generated. Examples of such standard cells include the standard cells mentioned in the table above.

[0148] From Block 1422 of Fig. 14A, the flow continues at block 1424. At block 1424, the standard cell is added to a library. An example of the library is library 1507 of Fig. 15, which is discussed below. From block 1424, the flow continues to block 1426. At block 1426, the standard cell is selected from the library. From block 1426, the flow continues to block 1428. At block 1428, the standard cell is recorded in a flowchart.

[0149] From block 1428 of Fig. 14A, the process continues at block 1430 and / or block 1432. At block 1430, one or more lithographic exposures are performed based on the setup. See the following discussion of Fig. 10. At block 1432, based on the structure, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated. See the discussion of Fig. 16.

[0150] Fig. 14B is a flowchart illustrating block 1422 of Fig. 14A in more detail in accordance with some embodiments.

[0151] In Fig. 14B, block 1422 includes blocks 1422-1454. At block 1422, fin structures are created. Examples of fin structures include fin structures 212(D), 212(N), and 212(P) in Fig. 2A. From block 1422, the flow continues at block 1424. At block 1424, the fin structures are arranged substantially parallel to a first direction. In the example of Fig. 2A, the fin structures 212(D), 212(N), and 212(P) are arranged parallel to the horizontal direction. From block 1444, the flow continues to block 1446. At block 1446, the structures are determined to include dummy fin structures, first active fin structures, and second active fin structures. In the example of Fig. 2A, there are dummy fin structures 212(D), first active fin structures 212(N), and second active fin structures 212(P). From block 1446, the process continues at block 1448.

[0152] At block 1448, the fin structure is arranged to be included in first, second, and third active regions. In the example of Fig. 2A, there is a first active region 250A(N), a second active region 250A(P)(1), and a third active region 250A(P)(2). From block 1448, the flow continues at block 1450. At block 1450, one or more gate structures are created. In the example of Fig. 2A, there are the gate structures 216(A). From block 1450, the flow continues at block 1452. At block 1452, the one or more gate structures are arranged to be substantially parallel to the second direction. In the example of Fig. 2A, the second direction is vertical. From block 1452, flow continues to block 1454. At block 1454, the one or more gate structures are each disposed over a corresponding one of the fin structures.

[0153] Fig. 15 is a block diagram of an electronic design automation (EDA) system 1500 in accordance with some embodiments.

[0154] In some embodiments, EDA system 1500 includes an APR system. Methods described herein for generating layout diagrams in accordance with one or more embodiments may be implemented, for example, using EDA system 1500 in accordance with some embodiments.

[0155] In some embodiments, EDA system 1500 is a general-purpose computing device comprising a hardware processor 1502 and a non-transitory, computer-readable storage medium 1504. Storage medium 1504 is encoded with, i.e., stores, computer program code 1506, i.e., a set of executable instructions, among other things. Execution of instructions 1506 by hardware processor 1502 constitutes (at least in part) an EDA tool that implements, for example, a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter referred to as the recited processes and / or methods).

[0156] The processor 1502 is electrically connected to the computer-readable storage medium 1504 via a bus 1508. The processor 1502 is also electrically connected to an input / output interface 1510 through the bus 1508. A network interface 1512 is also electrically connected to the processor 1502 via the bus 1508. The network interface 1512 is connected to a network 1514 such that the processor 1502 and the computer-readable storage medium 1504 are capable of connecting to external elements via the network 1514. The processor 1502 is configured to execute computer program code 1506 encoded in the computer-readable storage medium 1504 to cause the system 1500 to be usable to perform some or all of the listed processes and / or methods.In one or more embodiments, processor 1502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or any suitable processing unit.

[0157] In one or more embodiments, computer-readable storage medium 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or corresponding device or apparatus). For example, computer-readable storage medium 1504 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, random access memory (RAM), read-only memory (ROM), a magnetic hard disk, and / or an optical disk. In one or more embodiments employing optical disks, computer-readable storage medium 1504 includes compact disc read-only memory (CD-ROM), compact disc read / write (CD-R / W), and / or a digital video disk (DVD).

[0158] In one or more embodiments, storage medium 1504 stores computer program code 1506 configured to cause system 1500 (in which the execution represents (at least in part) the EDA tool) to be usable to perform a portion or all of the listed processes and / or methods. In one or more embodiments, storage medium 1504 also stores information enabling the performance of a portion or all of the listed processes and / or methods. In one or more embodiments, storage medium 1504 stores library 1507 of standard cells comprising such standard cells as disclosed herein.

[0159] The EDA system 1500 includes the input / output (I / O) interface 1510. The I / O interface 1510 is connected to external circuitry. In one or more embodiments, the I / O interface 1510 includes a keyboard, keypad, mouse, tactile ball, touch screen, and / or cursor direction keys for communicating information and commands to the processor 1502.

[0160] The EDA system 1500 also includes the network interface 1512, which is connected to the processor 1502. The network interface 1512 enables the system 1500 to communicate with the network 1514 to which one or more other computer systems are connected. The network interface 1512 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion of, or all of, the listed processes and / or methods are implemented in two or more systems 1500.

[0161] System 1500 is configured to receive information through I / O interface 1510. The information received through I / O interface 1510 includes one or more items selected from the group consisting of instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by processor 1502. The information is transferred to processor 1502 via bus 1508. EDA system 1500 is configured to receive information associated with a UI (user interface) through I / O interface 1510. The information is stored in computer-readable medium 1504 as user interface (UI) 1542.

[0162] In some embodiments, a portion of, or all of, the listed processes and / or methods is implemented as a stand-alone software application for execution by a processor. In some embodiments, a portion of, or all of, the listed processes and / or methods is implemented as a software application that forms part of an additional software application. In some embodiments, a portion of, or all of the listed processes and / or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the listed processes and / or methods is implemented as a software application that forms part of an EDA tool. In some embodiments, a portion of, or all of the listed processes and / or methods is implemented as a software application used by EDA system 1500.In some embodiments, the layout diagram comprising standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout creation tool.

[0163] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of a non-transitory computer-readable recording medium include, but are not limited to, external / removable and / or internal / built-in storage or memory devices, for example, one or more members from the group comprising an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as ROM, RAM, a memory card, and the like.

[0164] Fig. 16 is a block diagram of an integrated circuit (IC) manufacturing system 1600 and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit are manufactured using the manufacturing system 1600.

[0165] In Fig. 16, an IC manufacturing system 1600 includes entities, such as a design house 1620, a mask house 1630, and an IC manufacturer / fabricator (“fab”) 1650, that cooperate with one another regarding the design, development, and manufacturing cycles and / or services associated with the fabrication of an IC device 1660. The entities in system 1600 are interconnected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a plurality of different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communications channels. Each entity interacts with one or more of the other entities and provides or receives services from one or more of the other entities.In some embodiments, two or more of the design house 1620, mask house 1630, and IC fabricator 1650 units are owned by a single larger company. In some embodiments, two or more of the design house 1620, mask house 1630, and IC fabricator 1650 units are co-located in a common facility and share common resources.

[0166] The design house (or design team) 1620 generates an IC design layout diagram 1622. The IC design layout diagram 1622 includes various geometric structures designed for an IC device 1660. The geometric structures correspond to patterns of metal, oxide, or semiconductor layers that form the various components of the IC device 1660 to be manufactured. The various layers combine to form various IC features. For example, a portion of the IC design layout diagram 1622 includes various IC features, such as an active area, a gate electrode, source and drain, metal lines or vias of an interlayer interconnect, and openings for contact pads to be formed in a semiconductor substrate (such as a silicon wafer), as well as various metal layers disposed on the semiconductor substrate.The design house 1620 executes an appropriate design process to form the IC design flowchart 1622. The design process includes either a logical design and / or a physical design, or location and routing. The IC design layout diagram 1622 is formed in one or more data files that include information about the geometric structures. For example, the IC design layout diagram 1622 may be expressed in a GDSII file format or a DFII file format.

[0167] The mask house 1630 includes data preparation 1632 and mask fabrication 1644. The mask house 1630 uses the IC design layout diagram 1622 to create one or more masks 1645 to be used to fabricate the various layers of the IC device 1660 according to the IC design layout diagram 1622. The mask house 1630 performs mask data preparation 1632, in which the IC design layout diagram 1622 is translated into a representative data file ("RDF"). The mask data preparation 1632 provides the RDF to the mask fabrication 1644. The mask fabrication 1644 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1645 or a semiconductor wafer 1653.The design layout diagram 1622 is processed by the mask data preparation 1632 to conform to the particular characteristics of the mask writer and / or the requirements of the IC manufacturer 1650. In . Fig. 16, mask data preparation 1632 and mask fabrication 1644 are illustrated as separate elements. In some embodiments, mask data preparation 1632 and mask fabrication 1644 may be collectively referred to as mask data preparation.

[0168] In some embodiments, mask data preparation 1632 includes near-field optical correction (OPC), which uses lithography enhancement techniques to compensate for image defects, such as those resulting from diffraction, interference, other process effects, and the like. OPC adjusts IC design layout diagram 1622. In some embodiments, mask data preparation 1632 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, reverse lithography technology (ILT) is also used, which treats OPC as a reverse image enhancement problem.

[0169] In some embodiments, mask data preparation 1632 includes a mask rule checker (MRC) that checks the IC design layout diagram 1622, which has undergone processes at the OPC, against a set of mask creation rules that include certain geometric and / or connection constraints to ensure sufficient margins, account for variations in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 1622 to compensate for constraints during mask fabrication 1644 that could undo some of the modifications performed by the OPC, in order to comply with mask creation rules.

[0170] In some embodiments, mask data preparation 1632 includes a lithography process check (LPC) that simulates the processing that IC fabricator 1650 implements to fabricate IC device 1660. LPC simulates this processing based on IC design layout diagram 1622 to create a simulated fabricated device, such as IC device 1660. The processing parameters of the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of field ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof.In some embodiments, the OPC and / or MRC are repeated after a simulated fabricated device has been created by the LPC if the simulated device does not sufficiently satisfy the design rules in terms of its shape to further refine the IC design layout diagram 1622.

[0171] It should be understood that the above description of mask data preparation 1632 has been simplified for clarity. In some embodiments, data preparation 1632 includes additional features, such as a logic operation (LOP), to modify IC design layout diagram 1622 according to manufacturing rules. Furthermore, the processes performed on IC design layout diagram 1622 during data preparation 1632 can be performed in a variety of different orders.

[0172] After mask data preparation 1632 and during mask fabrication 1644, a mask 1645 or a group of masks 1645 is fabricated based on the modified IC design layout diagram 1622. In some embodiments, mask fabrication 1644 includes performing one or more lithographic exposures based on the IC design layout diagram 1622. In some embodiments, an electron beam (e-beam) or a multiple electron beam mechanism is used to form a pattern on a mask (photomask or reticle) 1645 based on the modified IC design layout diagram 1622. The mask 1645 can be formed using various technologies. In some embodiments, the mask 1645 is formed using a binary technology. In some embodiments, a mask pattern includes opaque and transparent regions.A beam of light, such as an ultraviolet (UV) ray, used to expose the image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque region and penetrates the transparent regions. In one example, a binary mask version of mask 1645 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1645 is formed using phase-shifting technology. In a phase-shifting mask (PSM) version of mask 1645, various features in the structure formed on phase-shifting mask are configured to have an appropriate phase difference to improve resolution and imaging quality.In various examples, the phase-shifting mask may be a damped PSM or an alternating PSM. The mask(s) produced by mask fabrication 1644 are used in a variety of processes. For example, such a mask is used in an ion implantation process for forming various doped regions in the semiconductor wafer 1653, in an etching process for forming various etch regions in the semiconductor wafer 1653, and / or in other suitable processes.

[0173] The IC fabricator 1650 includes the wafer fabrication 1652. The IC fabricator 1650 is an IC manufacturing company that has one or more facilities for manufacturing a variety of different IC products. In some embodiments, the IC fabricator 1650 is a semiconductor manufacturer. For example, there could be one fabrication facility for the front-end manufacturing of a variety of IC products (front-end-of-line (FEOL) manufacturing), while a second fabrication facility provides the back-end manufacturing for interconnecting and packaging the IC products (back-end-of-line (BEOL) manufacturing), and a third fabrication facility provides other services to the manufacturing company.

[0174] The IC fabricator 1650 uses masks 1645 fabricated by the mask house 1630 to fabricate the IC device 1660. Thus, the IC fabricator 1650 at least indirectly uses the IC design layout diagram 1622 to fabricate the IC device 1660. In some embodiments, the semiconductor wafer 1653 is fabricated by the IC fabricator 1650 using the mask(s) 1645 to form the IC device 1660. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design layout diagram 1622. The semiconductor wafer 1653 comprises a silicon substrate or other suitable substrate on which material layers are formed. The semiconductor wafer 1653 further includes one or more different doped regions, dielectric features, multilevel interconnects, and the like (formed in successive manufacturing steps).

[0175] Details relating to an integrated circuit (IC) manufacturing system (e.g. System 1600 from Fig. 16) and an IC manufacturing flow in connection therewith can be found, for example, in US 9 256 709 B2, granted on 9 February 2016, US 2015 / 0 278 429 A1, published on 1 October 2015, US 2014 / 0 040 838 A1, published on 6 February 2014 and US 7 260 442 B2, granted on 21 August 2007.

[0176] The invention is defined by the main claim and the subordinate claims. The subclaims describe further embodiments of the invention.

Claims

[1] A semiconductor device (100) comprising: Fins (212(D), 212(P), 212(N)) extending parallel to a first direction (X) and designed to comprise: Dummy fins (212(D)); first active fins (212(N)) having a first conductivity type; and second active fins (212(P)) having a second conductivity type; and at least one gate structure (216(A)) formed over a respective one of the fins (212(D), 212(P), 212(N)) and extending parallel to a second direction (Y) perpendicular to the first direction (X); where: the fins (212(D), 212(P), 212(N)) and the at least one gate structure (216(A)) are arranged in a first cell region (808A); the first cell range (808A) with respect to the second direction (Y) comprises in this order: a first dummy fin (212(D)); a second active region (850A(2)) comprising L >= 1 second active fins (212(P)); a first active region (850A(1)) comprising a sequence of M = 2 * N + 2 consecutive first active fins (212(N)) arranged in a central portion of the first cell region (808A), where N = 1 or 2; a third active region (850A(3)) comprising L second active fins (212(P)); and a second dummy fin (212(D)); and the semiconductor device further comprises a second cell region (804A), the second cell range (804A) comprises, with respect to the second direction (Y), in this order: a third dummy fin (212(D)); a fourth active region (850A(2)') comprising L second active fins (212(P)); a fifth active region (850A(1)') comprising N consecutive first active fins (212(N)); and a fourth dummy fin (212(D)); wherein a plane of symmetry perpendicular to the second direction (Y) divides the first cell region into two mirror-symmetrical halves; and an arrangement of the fins in one of the two mirror-symmetrical halves of the first cell area differs from an arrangement of the fins in the second cell area only in that the fourth dummy fin is replaced by a first active fin. [2] A semiconductor device (100) according to claim 1, wherein: the semiconductor device (100) further comprises a third cell region (508A(2)); the fins and the at least one gate structure are arranged in the first and third cell regions (508A(1), 508A(2)); and the first cell range (508A(1)) and the third cell range (508A(2)) each comprise: at least three gate structures, at least one of which is a dummy gate structure and at least one of which is an active gate structure; and a boundary with respect to the first direction (X) between the first cell region (508A(1)) and the third cell region (508A(2)) is defined by a continuous sequence of a first active gate structure, a first dummy gate structure, a second dummy gate structure and a second active gate structure. [3] A semiconductor device (100) according to claim 1, wherein: the semiconductor device (100) further comprises a third cell region (50SC(2)); the fins and the at least one gate structure are arranged in the first and third cell regions (508C(1), 508C(2)); and the first cell range (508C(1)) and the third cell range (50SC(2)) each comprise: at least three gate structures, at least one of which is a dummy gate structure and at least one of which is an active gate structure; and a boundary with respect to the first direction (X) between the first cell region (508C(1)) and the third cell region (508C(2)) is defined by a continuous sequence of a first active gate structure, a first dummy gate structure and a second active gate structure. [4] A semiconductor device (100) according to any one of the preceding claims, wherein: a distance between immediately adjacent pairs of fins (212(D), 212(P), 212(N)) is a fin pitch (253), the fin pitch being uniform; Sizes, in the second direction (Y), of the first active region (S50A(1)), the second active region (S50A(2)) and the third active region (S50A(3)) are each based on the fin pitch (253); and Sizes, in the second direction (Y), of a first gap (255) between the first active region (850A(1)) and the second active region (850A(2)) and a second gap (256) between the first active region (850A(1)) and the third active region (850A(3)) are each based on the fin pitch (253). [5] A semiconductor device (100) according to any one of claims 1 to 3, wherein: a distance between immediately adjacent pairs of fins (212(D), 212(P), 212(N)) is a fin pitch (253), the fin pitch being uniform; Sizes, in the second direction (Y), of the first active region (250C(N)), the second active region (250C(P)(1)) and the third active region (250C(P)(2)) are each based on the fin pitch (253); and Sizes, in the second direction (Y), of a first gap (255') between the first active region (250C(N)) and the second active region (250C(P)(1)) and a second gap (256') between the first active region (250C(N)) and the third active region (250C(P)(2)) are each not based on the fin pitch (253). [6] A semiconductor device (100) comprising: Fins (412(D), 412(P), 412(N)) extending parallel to a first direction (X); and Gate structures (416(A), 416(D)) each formed over a corresponding one of the fins (412(D), 412(P), 412(N)) and extending parallel to a second direction (Y) perpendicular to the first direction (X), wherein the gate structures (416(A), 416(D)) are designed to comprise: Dummy gate structures (416(D)); and active gate structures (416(A)); and where: the fins (412(D), 412(P), 412(N)) and the at least one gate structure (416(A), 416(D)) are divided into cell regions (508C(1), 508C(2), 536C, 532C, 534C); and a boundary with respect to the first direction (X) between a first (508C(1)) and a second (508C(2)) of the cell regions is defined by a continuous sequence of a first active gate structure (416(A)), a first dummy gate structure (416(D)), and a second active gate structure (416(A)), wherein the boundary with respect to the first direction (X) between the first cell region (508C(1)) and the second cell region (508C(2)) is collinear with the first dummy gate structure (416(D)); and the fins (412(D), 412(P), 412(N)) are configured to comprise: Dummy fins (412(D)); first active fins (412(N)) having a first conductivity type; and second active fins (412(P)) having a second conductivity type; and where: the fins (412(D), 412(P), 412(N)) and the at least one gate structure (416(A), 416(D)) are arranged in one of the cell regions (508C(1), 508C(2), 536C, 532C, 534C); and the first cell range (508C(1)) and a third cell range (508C(1)) with respect to the second direction (Y) each comprise in this order: a first dummy fin (412(D)); a second active region (850D(2)) comprising L second active fins (412(P)), where L >= 1; a first active region (850D(1)) comprising a sequence of M = 2 * N + 2 consecutive first active fins (412(N)) arranged in a central portion of the cell region, where N = 1 or 2; a third active region (85oD(3)) comprising L second active fins (412(P)); and a second dummy fin (412(D)); and the semiconductor device further comprises a fourth cell region (536C), and the fourth cell region comprises, with respect to the second direction (Y), in this order: a third dummy fin (412(D)); a fourth active region (850D(2)') comprising L second active fins (412(P)); a fifth active region (850D(1)') comprising N consecutive first active fins (412(N)); and a fourth dummy fin (412(D)); wherein a plane of symmetry perpendicular to the second direction (Y) divides the first cell region into two mirror-symmetrical halves; and wherein an arrangement of the fins in one of the two mirror-symmetrical halves of the first cell area differs from an arrangement of the fins in the fourth cell area only in that the fourth dummy fin is replaced by a first active fin. [7] A semiconductor device (100) according to claim 6, wherein: a distance between immediately adjacent pairs of fins (412(D), 412(P), 412(N)) is a fin pitch (253), the fin pitch being uniform; Sizes, in the second direction (Y), of the first active area (850D(1)), the second active area (850D(2)) and the third active area (850D(3)) are each based on the fin pitch (253); and Sizes, in the second direction (Y), of a first gap between the first active region (850D(1)) and the second active region (850D(2)) and a second gap between the first active region (850D(1)) and the third active region (850D(3)) are each based on the fin pitch (253). [8] A semiconductor device (100) according to claim 6, wherein: a distance between immediately adjacent pairs of fins is a fin pitch (253), the fin pitch being uniform; Sizes in the second direction (Y) of the first active area, the second active area and the third active area are each based on the fin pitch (253); and Sizes, in the second direction (Y), of a first gap between the first active region and the second active region and a second gap between the first active region and the third active region are each not based on the fin pitch (253). [9] A method (1400) for generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the method comprising: Selecting (1426) a first standard cell (800A) and a second standard cell (800A') from a library; and Recording (1428) the first standard cell (800A) and the second standard cell (800A') in a layout diagram; and where: the first standard cell (800A) and the second standard cell (800A') each have: Fin structures (212(D), 212(P), 212(N)) arranged parallel to a first direction (X), the fin structures comprising: Dummy fin structures (212(D)); first active fin structures (212(N)) of a first conductivity type; and second active fin structures (212(P)) of a second conductivity type; and at least one gate structure (216(A)) arranged parallel to a second direction (Y) perpendicular to the first direction (X), wherein the at least one gate structure is further arranged above a respective one of the fin structures (212(D), 212(P), 212(N)); the first standard cell (800A) is designed to comprise, with respect to the second direction (Y), in this order: a first dummy fin structure (212(D)); a second active region (850A(2)) comprising L >= 1 second active fin structures (212(P)); a first active region (850A(1)) comprising a sequence of M = 2 * N + 2 consecutive first active fin structures (212(N)) arranged in a central portion of the first standard cell (800A), where N = 1 or 2; a third active region (850A(3)) comprising L second active fin structures (212(P)); and a second dummy fin structure (212(D)); and the second standard cell (800A') with respect to the second direction (Y) comprises in this order: a third dummy fin structure (212(D)); a fourth active region (850A(2)') comprising L second active fin structures (212(P)); a fifth active region (850A(1)') comprising N consecutive first active fin structures (212(N)); and a fourth dummy fin structure (212(D)); wherein a plane of symmetry perpendicular to the second direction (Y) divides the first standard cell into two mirror-symmetric halves; and wherein an arrangement of the fin structures in one of the two mirror-symmetrical halves of the first standard cell differs from an arrangement of the fin structures in the second standard cell only in that the fourth dummy fin structure is replaced by a first active fin structure; and at least one aspect of the method (1400) is performed by a processor of a computer. [10] The method (1400) of claim 9, further comprising: Creating (1422) the first standard cell (800A); and Recording (1424) the first standard cell (800A) into the library; and wherein generating the first standard cell (800A) comprises: Creating (1442) the fin structures (212(D), 212(P), 212(N)); Arranging (1444) the fin structures (212(D), 212(P), 212(N)) parallel to the first direction (X); Determining (1446) that the fin structures (212(D), 212(P), 212(N)) comprise: the dummy fin structures (212(D)); the first active fin structures (212(N)); and the second active fin structures (212(P)); Arranging (1448) the fin structures (212(D), 212(P), 212(N)) so that they are contained in the first, second and third active regions (850A(1), 850A(2), 850A(3)); Creating (1450) the at least one gate structure (216(A)); Arranging (1452) the at least one gate structure (216(A)) such that it is arranged parallel to the second direction (Y); and Arranging (1454) the at least one gate structure (216(A)) over a respective one of the fin structures (212(D), 212(P), 212(N)). [11] A method (1400) comprising the method of claim 9 or 10, further comprising: manufacturing (1432), based on the layout diagram, (A) one or more semiconductor masks and / or (B) at least one component in a layer of a semiconductor integrated circuit. [12] A method (1400) comprising the method of any one of claims 9 to 11, further comprising: performing (1430) one or more lithographic exposures based on the build diagram.

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