Method for forming a semiconductor-on-insulator (SOI) substrate and semiconductor structure

Abstract

Method for forming a semiconductor-on-an-insulator substrate (102), the method comprising: Forming an insulating layer (106) on a support substrate (104), wherein the insulating layer (106) is formed so that it completely covers a surface of the support substrate (104); Forming a device layer (108) on a sacrificial substrate (602), wherein the sacrificial substrate (602) and the device layer (108) comprise the same semiconductor material and wherein the sacrificial substrate (602) and the device layer (108) have the same doping types but different doping concentrations; Bonding the sacrificial substrate (602) to the support substrate (104), such that the device layer (108) and the insulator layer (106) are located between the sacrificial substrate (602) and the support substrate (104); and Removal of the sacrificial substrate (602), wherein the removal comprises performing an etching into the sacrificial substrate (602) until the device layer (108) is reached; Structuring the device layer (108) to remove edge sections (108e) of the device layer (108), wherein the top surface of the insulator layer (106) remains completely covered during structuring, wherein the structuring comprises dry etching into the device layer (108), and wherein the dry etching stops at the insulator layer (106).

Description

TECHNICAL BACKGROUND

[0001] Integrated circuits have traditionally been fabricated on bulk semiconductor substrates. In recent years, semiconductor-on-insulator (SOI) substrates have emerged as an alternative to bulk semiconductor substrates. An SOI substrate comprises a support substrate (or stabilizing substrate or handle substrate), an insulator layer above the support substrate, and a device layer above the insulator layer. Among other benefits, an SOI substrate results in reduced parasitic capacitance, reduced leakage current, reduced latch-up, and improved semiconductor device performance (e.g., lower power consumption and higher switching speed).

[0002] A method for forming a semiconductor-on-an-insulator substrate is known from US 5,494,849 A. Another method is known from US 2010 / 0093,153 A1.

[0003] From publication CN 1 225 499 A, an SOI substrate is known which comprises a support substrate, an insulating layer on the support substrate, and a device layer above the insulating layer. A further insulating layer surrounds the support substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood by referring to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the clarity of the discussion. Fig. Figure 1 illustrates a sectional view of some embodiments of a semiconductor-on-an-insulator (SOI) substrate with a thick device layer. Fig. Figure 2 illustrates a sectional view of some alternative embodiments of the SOI substrate. Fig. 1, in which a trapping-site-rich layer separates a support substrate of the SOI substrate and an insulator layer of the SOI substrate. Fig. Figure 3 illustrates a top view of some embodiments of the SOI substrate. Fig. 1. Fig. Figure 4 illustrates a sectional view of some embodiments of a semiconductor structure in which the SOI substrate of the Fig. 1 application is found. Fig. Figures 5-16 illustrate a series of sectional views of some embodiments of a method for forming and using an SOI substrate with a thick fixture layer. Fig. Figure 17 illustrates a block diagram of some embodiments of the method of Fig. 5-16. DETAILED DESCRIPTION

[0005] The present disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative expressions such as "below," "under," "below," "above," "above," "over," and the like may be used herein to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. These spatially relative expressions are intended to accommodate different orientations of the device in use or an additional operation beyond the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] According to a method for forming a semiconductor-on-an-insulator (SOI) substrate, a device substrate is oxidized to form an oxide layer surrounding it. Hydrogen ions are implanted into the device substrate to form a hydrogen-rich region that is embedded within the substrate. The device substrate is bonded to a support substrate through the oxide layer, and the device substrate is split along the hydrogen-rich region to partially remove a portion of the oxide layer and a portion of the device substrate from the support substrate. A chemical-mechanical polish (CMP) is performed on a portion of the device substrate remaining attached to the support substrate to flatten the remaining section.The remaining portion of the device substrate defines a device layer of the SOI substrate, and a portion of the oxide layer that remains on the support substrate defines an insulator layer of the SOI substrate.

[0008] One challenge of this method is that it is limited to creating small thicknesses for the fixture layer and the insulator layer. For example, the fixture layer and the insulator layer may each be limited to a thickness of less than approximately 270 nm and an insulator layer less than approximately 680 nm, respectively. These small thicknesses can arise, for example, from the use of ion implantation to create the hydrogen-rich region. The fixture layer thickness is defined by the depth at which ions are implanted. Because ion implantation is limited to a shallow depth, the fixture layer is also limited to a small thickness. Furthermore, the ions are implanted through the insulator layer, which dissipates some of the implantation energy.Because of this deduction, the depth at which ions can be implanted decreases as the thickness of the insulating layer increases, thus limiting the insulating layer to a small thickness.

[0009] The small thicknesses limit the use of the SOI substrate. For example, the small thickness of the fixture layer can restrict devices on the fixture layer to small semiconductor contact points (e.g., small PN contacts), thus limiting the use of the SOI substrate to applications that rely on large semiconductor contact points. As another example, the small thickness of the insulator layer can limit electrical insulation between devices on the fixture layer, thus limiting the use of the SOI substrate to applications that rely on low tracking current.Applications where small thicknesses pose a challenge include high-voltage applications (e.g., greater than approximately 100 volts), complementary metal-oxide semiconductors (CMOS), double-diffused metal-oxide semiconductors (DMOS), embedded flash (eFlash), CMOS image sensor (CIS), near-infrared (NIR), and others. One solution for small thicknesses is to perform epitaxial growth to increase the device layer thickness. However, this increases costs and reduces manufacturing throughput.

[0010] Different embodiments of the present application relate to a method for forming a SOI substrate with a thick fixture layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer that completely covers a support substrate and epitaxially forming a fixture layer on a sacrificial substrate. The sacrificial substrate is bonded to a support substrate such that the fixture layer and the insulator layer are sandwiched between the sacrificial and support substrates, and the sacrificial substrate is removed. Removal includes etching into the sacrificial substrate until the fixture layer is reached. In some embodiments, the method further includes etching edge portions of the fixture layer and stopping at the insulator layer, so that the support substrate is completely covered during etching.

[0011] Because the device layer is formed and transferred to the substrate by epitaxy, it can be formed with a large thickness (e.g., greater than approximately 0.3 micrometers). Epitaxy is not subject to the thickness limitations associated with other approaches to device layer formation (e.g., approaches using ion implantation). Furthermore, since epitaxy is not affected by the thickness of the insulator layer, the insulator layer can be formed with a large thickness (e.g., greater than approximately 1 micrometer). Because the sacrificial substrate is removed using etching, the removal can be highly controlled, and the total thickness variation (TTV) of the device layer can be low.The TTV can, for example, be the difference between a minimum thickness value across the device layer and a maximum thickness across the device layer. Since the substrate remains completely covered during edge etching, arc flashover to the substrate can be avoided in embodiments where the substrate has high resistance and dry etching is performed. Furthermore, arc flashover to the substrate can be avoided for subsequent plasma processing (e.g., plasma etching), which is used to form semiconductor devices on the SOI substrate.

[0012] With reference to Fig. Figure 1 provides a sectional view 100 of some embodiments of an SOI substrate 102. The SOI substrate 102 can be used, for example, with high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, and other devices. The high-voltage devices can, for example, be devices that operate at voltages higher than about 100 volts. In some embodiments, the SOI substrate 102 has a circular top surface and / or a diameter of about 200, 300, or 450 millimeters. In other embodiments, the SOI substrate 102 has a different shape and / or different dimensions. Furthermore, in some embodiments, the SOI substrate 102 is a semiconductor wafer. The SOI substrate 102 comprises a support substrate 104, an insulator layer 106 and a fixture layer 108.The support substrate 104 can, for example, be or comprise a monocrystalline silicon, another silicon material, another semiconductor material, or any combination of the aforementioned.

[0013] In some embodiments, the support substrate 104 has a high resistance and / or a low oxygen concentration. The high resistance can be, for example, greater than about 1, 3, 4, or 9 kilohms / centimeter (kΩ / cm) and / or can be, for example, about 1–4 kΩ / cm, about 4–9 kΩ / cm, or about 1–9 kΩ / cm. The low oxygen concentration can be, for example, less than about 1, 2, or 5 parts per million (ppm) and / or can be, for example, between about 0.1–2.5 ppmm, about 2.5–5.0 ppmm, or about 0.1–5.0 ppmm. The low oxygen concentration and the high resistance each reduce substrate and / or radio frequency (RF) losses. In some embodiments, the support substrate 104 has a low resistance. The low resistance reduces the cost of the carrier substrate 104, but can lead to increased substrate and / or RF losses.The low resistance can be, for example, less than approximately 8, 10, or 12 Ω / cm and / or can be, for example, between approximately 8 and 12 Ω / cm, approximately 8 and 10 Ω / cm, or approximately 10 and 12 Ω / cm. In some embodiments, the support substrate 104 is doped with p-type or n-type dopants. The resistance of the support substrate 104 can be controlled, for example, by the dopant concentration of the support substrate 104. For example, increasing the dopant concentration can decrease the resistance, whereas decreasing the dopant concentration can increase the resistance, or vice versa. In some embodiments, a thickness T is specified. hs of the carrier substrate 104 approximately 720-780 micrometers, approximately 720-750 micrometers or approximately 750-780 micrometers.

[0014] The insulating layer 106 lies above the support substrate 104 and can be, for example, silicon dioxide, silicon-rich oxide (SRO), another oxide, another dielectric, or any combination thereof. In some embodiments, the insulating layer 106 completely covers an upper surface 104¹ of the support substrate 104. In at least some embodiments, where the support substrate 104 has high resistance, completely covering the upper surface 104¹ of the support substrate 104 prevents arc flashover during plasma processing (for example, plasma etching) used to form devices (not shown) on the device layer 108. In some embodiments, the insulating layer 106 completely encloses the support substrate 104. The insulating layer 106 has a first insulating thickness T. fiat the top side of the support substrate 104, between the device layer 108 and the support substrate 104. The first insulator thickness T fi is large to provide a high degree of electrical insulation between the support substrate 104 and the device layer 108. The high degree of electrical insulation can, for example, enable reduced leakage current between devices (not shown) on the device layer 108 and / or can, for example, improve the work performance of the devices. In some embodiments, the first insulator thickness T is fi approximately 0.2–25 micrometers, approximately 0.2–1.35 micrometers, or approximately 1.35–2.5 micrometers, and / or is greater than approximately 1 or 2 micrometers. In some embodiments, the insulating layer 106 has a second insulating thickness T. si at the base of the support substrate 104 and / or along side walls of the support substrate 104. In some embodiments, the second insulator thickness T siless than the first insulator thickness T fi In some embodiments, the second insulator thickness T si approximately 20-600 nm, approximately 2-301 nm or approximately 301-600 nm.

[0015] In some embodiments, the insulator layer 106 has stepped profiles at SOI edge sections 102e of the SOI substrate 102, each located on opposite sides of the SOI substrate 102. In some embodiments, the insulator layer has upper surfaces located at the SOI edge sections 102e, which are recessed below a cover surface of the insulator layer 106 by a vertical depression VR. i are recessed. The vertical recession dimension VR i For example, it can be approximately 2-600 nm, approximately 2-301 nm, or approximately 301-600 nm. In some embodiments, the sum of the vertical recess dimension VR is i and the second insulator thickness T si equal to or approximately equal to the first insulator thickness T fiIn some embodiments, the insulator layer 106 has inner walls, which are located at the SOI edge section 102e and which are laterally separated from outer walls of the insulator layer 106 by a lateral insulator recess dimension LR. i are recessed. The lateral insulator recess dimension LR i It could be, for example, approximately 0.8-1.2 millimeters, approximately 0.8-1.0 millimeters, or approximately 1.0-1.2 millimeters.

[0016] The device layer 108 lies above the insulating layer 106 and can be, for example, monocrystalline silicon, another silicon, another semiconductor material, or any combination thereof. In some embodiments, the device layer 108 and the support substrate 104 are the same semiconductor material (for example, monocrystalline silicon). The device layer 108 has a thickness T d, which is large. The large thickness of the device layer 108 can, for example, enable the formation of large semiconductor contact points (e.g., PN contacts) on which certain devices (e.g., NIR image sensors) may depend. In some embodiments, the thickness T d The device layer 108 is large in that it is larger than approximately 0.2, 0.3, 1.0, 5.0, or 8.0 micrometers and / or in that it is approximately 0.2–8.0 micrometers, approximately 0.2–4.0 micrometers, or approximately 4.0–8.0 micrometers. In some embodiments, the device layer 108 has side walls, which are the SOI edge section 102e, and which are laterally separated from side walls of the support substrate 104 by a lateral device recess quantity LR. d are recessed. The lateral device recess quantity LR d For example, it could be approximately 1.4–2.5 millimeters, approximately 1.4–1.9 millimeters, or approximately 1.9–2.5 millimeters. Furthermore, the lateral device recess depth LR can be...d for example, larger than the lateral insulator recess dimension LR i be.

[0017] With reference to Fig. Figure 2 is a sectional view of 200 of some alternative embodiments of the SOI substrate 102 of the Fig. Figure 1 provides a structure in which a trapping-site-rich layer 202 separates the support substrate 104 from the insulating layer 106. The trapping-site-rich layer 202 has a high density of carrier traps relative to the support substrate 104 and / or relative to the device layer 108. The carrier traps can be, for example, dislocations and / or other defects in a crystal lattice of the trapping-site-rich layer 202 or comprise them. The carrier traps trap mobile charge carriers (e.g., mobile electrons) along a surface of the support substrate 104 to reduce the effects of parasitic surface conduction (PSC). The mobile charge carriers can be attracted to the surface of the support substrate 104, for example, by fixed charges in the insulating layer 106.By reducing the effects of PSC, the trapping-point-rich layer 202 promotes low substrate and / or RF losses, passive device with high Q-factors, low cross-talk and high linearity (e.g., low second harmonics).

[0018] In some embodiments, the trap-rich layer 202 is or comprises undoped polycrystalline silicon, amorphous silicon, or another suitable semiconductor material having a high density of carrier traps. In some embodiments where the trap-rich site 202 is or comprises undoped polycrystalline silicon, the carrier traps concentrate at grain boundaries of the undoped polycrystalline silicon, and a reduction in grain size of the undoped polycrystalline silicon increases the density of carrier traps in the undoped polycrystalline silicon. In some embodiments, a thickness T trThe trap-rich layer 202 has a thickness of approximately 1-2 micrometers, approximately 1.0-1.5 micrometers, or approximately 1.5-2.0 micrometers. If the thickness T tr If the thickness T is too small (for example, less than about 1.0 micrometer), the trapping-site-rich layer 202 within it may be ineffective at trapping mobile charge carriers and reducing the effect of PSC. tr If the substrate is too large (for example, larger than approximately 2.0 micrometers), the SOI substrate 102 may be prone to a higher degree of substrate distortion. In some embodiments, the support substrate 104 has a high resistance and / or a low oxygen concentration. The high resistance may, for example, be greater than approximately 1, 3, 4, or 9 kΩ / cm and / or may be, for example, between approximately 1–4 kΩ / cm, approximately 4–9 kΩ / cm, or approximately 1–9 kΩ / cm. The low oxygen concentration may, for example, be less than approximately 1, 2, 5, or 10 ppma and / or may be, for example, between approximately 1–2 ppma, 2–5 ppma, or 5–10 ppma.

[0019] With reference to Fig. Figure 3 shows a top view of 300 of some embodiments of the SOI substrate 102. Fig. 1. The SOI substrate 102 is circular and comprises a plurality of IC dies 302 arranged in a grid over the device layer 108. For ease of illustration, only some of the IC dies 302 are labelled 302. In some embodiments, the diameter D of the SOI substrate 102 is approximately 150, 200, 300, or 450 millimeters. In some embodiments, an inner wall 106isw of the insulator layer 106 is laterally separated from an outer wall 106osw of the insulator layer 106 by a lateral insulator recess dimension LR. i recessed. In some embodiments, a side wall 108sw of the device layer 108 is laterally separated from a side wall 104sw (shown as outline) of the support substrate 104 by a lateral device recess quantity LR. drecessed. The lateral insulator recession quantity LR i For example, it can be approximately 0.8–1.2 millimeters, approximately 0.8–1.0 millimeters, or approximately 1.0–1.2 millimeters. The lateral device recess quantity LR d can, for example, be larger than the lateral insulator depression quantity LR i It may be, for example, approximately 1.4-2.5 millimeters, approximately 1.4-1.9 millimeters, or approximately 1.9-2.5 millimeters.

[0020] With reference to Fig. 4 A sectional view 400 of some embodiments of a semiconductor structure is provided, in which the SOI substrate 102 of the Fig. 1. The semiconductor structure comprises a variety of semiconductor devices 402 spaced laterally above the device layer 108. The semiconductor devices 402 can be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), other metal-oxide-semiconductor (MOS) devices, other insulated-gate field-effect transistors (IGFETs), other semiconductor devices, or any combination thereof. Furthermore, the semiconductor devices 402 can be, for example, high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, other devices, or any combination thereof.

[0021] In some embodiments, the semiconductor devices 402 comprise corresponding source / drain regions 404, corresponding selectively conductive channels 406, corresponding dielectric gate layers 408, corresponding gate electrodes 410, and corresponding spacers 412. For clarity, only some of the source / drain regions 404 are designated with reference 404, only one of the selectively conductive channels 406 is designated with reference 406, only one of the dielectric gate layers 408 is designated with reference 408, only one of the gate electrodes 410 is designated with reference 410, and only one of the spacers 412 is designated with reference 412. The source / drain regions 404 and the selectively conductive channels 406 are located in the device layer 108.The source / drain regions 404 are located at the ends of the selectively conductive channels 406, and each of the selectively conductive channels 406 extends from one of the source / drain regions 404 to another of the source / drain regions 404. The source / drain regions 404 have a first doping type and are directly adjacent to sections of the device layer 108 that have a second doping type in contrast to the first doping type.

[0022] The dielectric gate layers 408 are each located above the selectively conductive channels 406, and the gate electrodes 410 are each located above the dielectric gate layers 408. The dielectric gate layers 408 can be, for example, silicon oxide and / or other dielectric material, and / or the gate electrodes 410 can be, for example, doped polysilicon, metal, other conductive material, or any combination thereof. The spacers 412 are located above the source / drain regions 404 and line the sidewalls of the gate electrodes 410 and the sidewalls of the dielectric gate layers 408. The spacers 412 can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another dielectric, or any combination thereof.

[0023] A back-end-of-line (BEOL) interconnect structure 414 covers the SOI substrate 102 and the semiconductor devices 402. The BEOL interconnect structure 414 comprises a dielectric interconnect layer 416, a plurality of wires 418, and a plurality of vias 420. For ease of illustration, only some of the wires 418 are labeled 418 and only some of the vias 420 are labeled 420. The dielectric interconnect layer 416 may, for example, be or comprise boron phosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicon glass (USG), another low dielectric, silicon oxide, another dielectric, or any combination thereof.As used herein, a dielectric with a low dielectric constant may, for example, be or include a dielectric with a dielectric constant κ of less than about 3.9, 3, 2 or 1.

[0024] The wires 418 and the vias 420 are stacked alternately in the dielectric interlayer 416 and define conductive paths extending to the semiconductor devices 402. These conductive paths can, for example, electrically couple the semiconductor devices 402 to other devices (such as other semiconductor devices), contact pads, or other structures. The wires 418 and the vias 420 can be made of, for example, copper, aluminum-copper, aluminum, tungsten, another metal, or any combination thereof. In some embodiments, the uppermost wires of the wires 418 are thicker than the underlying wires of the wires 418.

[0025] While Fig. 3 and Fig. 4 with regard to embodiments of the SOI substrate 102 in Fig. As described in section 1, it is to be understood that embodiments of the SOI substrate 102 in Fig. 2 alternatively in Fig. 3 and Fig. 4 can be used. While Fig. Figure 3 illustrates a specific number of IC dies 302 and a specific configuration of IC dies 302; however, more or fewer IC dies 302 and / or other configurations of dies 302 are possible in other embodiments. Fig. Figure 4 illustrates a specific design of the BEOL intermediate connection structure 414; other designs of the BEOL intermediate connection structure 41 are possible in other embodiments. Fig. Figure 4 illustrates three semiconductor devices 402 and a specific design for the semiconductor devices 402; more or fewer semiconductor devices and / or other designs for the semiconductor devices 402 are possible.

[0026] With reference to Fig. Figures 5-16 provide a series of sectional views 500-1600 of some embodiments of a method for forming and using an SOI substrate 102. While the method is described as embodiments of the SOI substrate 102 in Fig. As illustrated in Figure 1, the method can alternately produce embodiments of the SOI substrate 102 in Fig. 2 and other embodiments of the SOI substrate 102. Furthermore, while the in Fig. Sectional views 500-1600 shown in Figures 5-16 describe a process; it will be welcomed that the [document / section] in [reference] Fig. The structures shown in 5-16 are not limited to the procedure and can stand alone without the procedure.

[0027] As shown in section view 500 of the Fig. Figure 5 illustrates a support substrate 104. In some embodiments, the support substrate 104 is or comprises monocrystalline silicon, other silicon material, other semiconductor material, or any combination thereof. In some embodiments, the support substrate 104 has a circular top surface and / or a diameter of approximately 200, 300, or 450 millimeters. In other embodiments, the support substrate 104 has a different shape and / or dimensions. Furthermore, in some embodiments, the support substrate 104 is a semiconductor wafer. In some embodiments, the support substrate 104 has high resistivity and / or a low oxygen concentration. The high resistivity and low oxygen concentration each reduce substrate and / or RF losses.The high resistance can be, for example, greater than approximately 1, 3, 4, or 9 kΩ / cm and / or can be, for example, between approximately 1–4 kΩ / cm, approximately 4–9 kΩ / cm, or approximately 1–9 kΩ / cm. The low oxygen concentration can be, for example, less than approximately 1, 2, or 5 ppma and / or can be, for example, between approximately 0.1–2.5 ppma, approximately 2.5–5.0 ppma, or approximately 0.1–5.0 ppma. In some embodiments, the support substrate 104 has a low resistance to reduce substrate costs, since a high-resistance substrate can be more expensive than a low-resistance substrate, for example. The low resistance can be, for example, less than approximately 8, 10, or 12 Ω / cm and / or can be, for example, approximately 8–12 Ω / cm, approximately 8–10 Ω / cm, or approximately 10–12 Ω / cm. In some embodiments, the support substrate 104 is doped with p-type or n-type dopants. The resistance of the support substrate 104 can be controlled, for example, by the doping concentration of the support substrate 104.In some embodiments, a thickness T is specified. hs of the carrier substrate 104 approximately 720-780 micrometers, approximately 720-750 micrometers or approximately 750-780 micrometers.

[0028] As shown in section view 500 of the Fig. As illustrated in Figure 5, a first insulating layer 106a is formed on an upper surface 104µs of the support substrate 104. In some embodiments, the first insulating layer 106a completely covers the upper surface 104µs of the support substrate 104. In at least some embodiments, where the support substrate 104 has high resistance, completely covering the upper surface 104µs can, for example, prevent arc flashover during plasma processing, which is described below. In some embodiments, the first insulating layer 106a completely encloses the support substrate 104. In some embodiments, the first insulating layer 106a is or comprises silicon dioxide and / or another dielectric. In some embodiments, a thickness T is fi' the first insulating layer 106a approximately 0.2-2.0 micrometers, approximately 0.2-1.1 micrometers or approximately 1.1-2.0 micrometers.

[0029] In some embodiments, a process for forming the first insulating layer 106a comprises depositing the first insulating layer 106a by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), another deposition process, or any combination thereof. For example, the first insulating layer 106a can be deposited by a dry oxidation process using oxygen gas (for example, O2) or another gas as an oxidizing agent. As another example, the first insulating layer 106a can be deposited by a wet oxidation process using water vapor as an oxidizing agent. In some embodiments, the first insulating layer 106a is formed at temperatures of about 800–1100 degrees Celsius (°C), about 800–950°C, or about 950–1100°C.For example, where the first insulating layer 106a is formed by heat oxidation (for example, any of the wet and dry oxidation processes), the first insulating layer 106a can be formed at these temperatures.

[0030] As shown in section view 600 of the Fig. As illustrated in Figure 6, a sacrificial substrate 602 is provided. In some embodiments, the sacrificial substrate 602 is or comprises monocrystalline silicon, other silicon material, other semiconductor material, or any combination thereof. In some embodiments, the sacrificial substrate 602 is doped with p-type or n-type dopants and / or has a low resistance. The low resistance may, for example, be less than about 0.01 or 0.02 Ω·cm and / or may be, for example, about 0.01–0.2 Ω·cm. In some embodiments, the sacrificial substrate 602 has a lower resistance than the support substrate 104 (see Figure 6). Fig. 5) In some embodiments, the sacrificial substrate 602 has a circular top surface and / or a diameter of about 200, 300, or 450 millimeters. In other embodiments, the sacrificial substrate 602 has a different shape and / or different dimensions. In some embodiments, the sacrificial substrate 602 is a bulk semiconductor substrate and / or is a semiconductor wafer. In some embodiments, a thickness T ss The thickness of the sacrificial substrate 602 is approximately 720–780 micrometers, approximately 720–750 micrometers, or approximately 750–780 micrometers. In some embodiments, the thickness T ss of the sacrificial substrate 602 the same or approximately the same as the thickness T hs of the carrier substrate 104 (see Fig. 5).

[0031] Also from the section view 600 of the Fig. As illustrated in Figure 6, a device layer 108 is formed on the sacrificial substrate 602. The device layer 108 has a thickness T. d, which is large. In some embodiments, the thickness T dThe device layer 108 is large in that it is approximately 0.7–10.0 micrometers, approximately 0.7–5.0 micrometers, or approximately 5.0–10.0 micrometers, and / or in that it is larger than approximately 0.7, 5.0, or 10.0 micrometers. In some embodiments, the device layer 108 is or comprises monocrystalline silicon, other silicon material, other semiconductor material, or any combination thereof. In some embodiments, the device layer 108 is or comprises the same semiconductor material as the sacrificial substrate 602, has the same doping type as the sacrificial substrate 602, has a lower doping concentration than the sacrificial substrate 602, or any combination thereof. For example, the sacrificial substrate 602 may be or comprise P+ monocrystalline silicon, whereas the device layer 108 may be or comprise P- monocrystalline silicon. In some embodiments, the device layer 108 has a low resistance.The low resistance can, for example, be greater than that of the sacrificial substrate 602. Furthermore, the low resistance can, for example, be less than approximately 8, 10, or 12 Ω·cm and / or can be, for example, approximately 8–12 Ω·cm, approximately 8–10 Ω·cm, or approximately 10–12 Ω·cm. In some embodiments, the device layer 108 has the same doping type, the same doping concentration, the same resistivity, or any combination thereof, as the support substrate 104 (see Figure 1). Fig. 5) In some embodiments, a process for forming the device layer 108 comprises molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), another Epital process or any combination of the foregoing.

[0032] As shown in section view 700 of the Fig. Figure 7 illustrates the structuring of the device layer 108 and the sacrificial substrate 602. The structuring removes edge regions 604 (see Fig. 6), which are defined by the fixture layer 108 and the sacrificial substrate 602. Removing the edge regions 604 prevents defects from forming at the edge regions 604 during subsequent grinding and / or chemical wet setting. Edge defects tend to concentrate at the edge regions 604 and negatively affect the quality of the fixture layer 108. Furthermore, the structuring forms a shoulder 702 at an edge of the sacrificial substrate 602. The shoulder 702 is defined by the sacrificial substrate 602 and has a pair of shoulder segments, each located on opposite sides of the sacrificial substrate 602. In some embodiments, the shoulder 702 has a top surface design that extends along an edge of the sacrificial substrate 602 in an annular path or other closed path.In some embodiments, the recess 702 has a width W of approximately 0.8–1.2 millimeters, approximately 0.8–1.0 millimeters, or approximately 1.0–1.2 millimeters. In some embodiments, the recess 702 is recessed below an upper or top surface of the device layer 108 by a distance D of approximately 30–120 micrometers, approximately 30–75 micrometers, or approximately 75–120 micrometers. In some embodiments, the recess 702 is further recessed below an upper or top surface of the sacrificial substrate 602.

[0033] In some embodiments, the structuring is performed by a photolithography / etching process or another structuring process. In some embodiments, the structuring further comprises forming a mask 704 over the device layer 108, performing an etch into the device layer 108 and the sacrificial substrate 602 with the mask 704 in place, and removing the mask 704. The mask 704 may, for example, be formed such that the device layer 108 and the sacrificial substrate 602 are completely covered, except at the edge regions 604. In some embodiments, the mask 704 is or comprises silicon nitride, silicon oxide, another hard mask material, photoresist, another mask material, or any combination thereof. In some embodiments, the mask 704 is formed using a wafer edge exposure (WEE) process tool.For example, a process for forming the mask 704 may include: depositing a photoresist layer on the device layer 108; selectively irradiating an edge section of the photoresist layer with radiation using the WEE process tool; and developing the photoresist layer to form the mask 704.

[0034] As shown in section view 800 of the Fig. As illustrated in Figure 8, the device layer 108 and the sacrificial substrate 602 are cleaned to remove etch residue and / or unwanted byproducts that may have occurred during the execution of preceding processes (for example, the structuring of the Fig. 7) generated, to remove. In some embodiments, the cleaning process scrubs the device layer 108 and the sacrificial substrate 602 using a physical brush or a water jet. In some embodiments, the cleaning process cleans the device layer 108 and the sacrificial substrate 602 using a chemical solution. The chemical solution may be, for example, hydrofluoric acid or another chemical solution. In some embodiments, the cleaning increases the distance D at which the step 702 is recessed below the top or upper surface of the device layer 108. In other embodiments, the distance D remains substantially unchanged by the structuring. Fig. 7 unchanged.

[0035] As shown in section view 900 of the Fig. As illustrated in Figure 9, a second insulating layer 106b is formed on an upper surface 108us of the device layer 108. In some embodiments, the second insulating layer 106b completely covers the upper surface 108us of the device layer 108. In some embodiments, the second insulating layer 106b completely encloses the sacrificial substrate 602 and the device layer 108. In some embodiments, the second insulating layer 106b is or comprises silicon dioxide and / or another dielectric. In some embodiments, the second insulating layer 106b is the same dielectric material as the first insulating layer 106a. In some embodiments, a thickness T si' the second insulating layer 106b approximately 2-600 nm, approximately 2-301 nm or approximately 301-600 nm.

[0036] In some embodiments, a process for forming the second insulating layer 106b comprises depositing the second insulating layer 106b by thermal oxidation, CVD, PVD, another deposition process, or any combination thereof. For example, the second insulating layer 106b can be deposited by a dry oxidation process using oxygen gas (for example, O2) or another gas as an oxidizing agent. As another example, the second insulating layer 106b can be deposited by a wet oxidation process using steam as an oxidizing agent. In some embodiments, the second insulating layer 106b is formed at temperatures of about 750–1100°C, about 750–925°C, or about 925–1100°C.For example, where the second insulating layer 106b is formed by thermal oxidation (for instance, any of the wet and dry oxidation processes), the second insulating layer 106b can be formed at these temperatures. In some embodiments, the second insulating layer 106b is formed at a temperature lower than that of the first insulating layer 106b.

[0037] As seen through the section view 1000 of the Fig. As illustrated in Figure 10, the sacrificial substrate 602 is bonded to the support substrate 104, such that the device layer 108, the first insulator layer 106a, and the second insulator layer 106b are located between the support substrate 104 and the sacrificial substrate 602. Bonding presses the first and second insulator layers 106a and 106b together, forming a composite 1002 at an interface where the first insulator layer 106a and the second insulator layer 106b are in direct contact. Bonding can be performed, for example, by fusion bonding, vacuum bonding, or another bonding process. Fusion bonding can be performed, for example, at pressures of approximately 1.013 bar (1 standard atmosphere), approximately 0.507–1.013 bar, approximately 1.013–1.520 bar, or approximately 0.507–1.520 bar. Vacuum bonding can be performed, for example, at pressures of approximately 0.5–100 millibar (mbar), approximately 0.5–50 mbar, or approximately 50–100 mbar.

[0038] In some embodiments, bond annealing is performed to strengthen bond 1002. In some embodiments, the bond annealing is performed at a temperature of approximately 300–1150°C, approximately 300–725°C, or approximately 735–1150°C. In some embodiments, the bond annealing is performed for approximately 2–5 hours, approximately 2–3.5 hours, or approximately 3.5–5 hours. In some embodiments, the bond annealing is performed at a pressure of approximately 1.013 bar, approximately 0.507–1.013 bar, approximately 1.013–1.520 bar, or approximately 0.507–1.520 bar. In some embodiments, the bond annealing is performed while nitrogen gas (for example, N2) and / or another gas is applied over the structure of the Fig. 10 flows. The flow rate for the gas can be, for example, about 1-20 standard liters per minute, about 1-10 standard liters per minute, or about 10-20 standard liters per minute.

[0039] As shown in section view 1100 of the Fig. As illustrated in Figure 11, a first dilution process is carried out in the second insulator layer 106b and the sacrificial substrate 602. The first dilution process removes an upper portion of the second insulator layer 106b and further removes an upper portion of the sacrificial substrate 602. In some embodiments, the first dilution process is carried out in the second insulator layer 106b and the sacrificial substrate 602 until the apparatus layer 108 and the sacrificial substrate 602 together have a predetermined thickness T. pd have the predetermined thickness T pd For example, it can be approximately 20-45 micrometers, approximately 20-32.5 micrometers, or approximately 32.5-45 micrometers.

[0040] In some embodiments, the first thinning process is carried out partially or entirely by a mechanical grinding process. In some embodiments, the first thinning process is carried out partially or entirely by a chemical-mechanical polish (CMP). In some embodiments, the first thinning process is carried out by a mechanical grinding process followed by a CMP. As noted previously, removing the edge region 604 of the Fig. 6. Edge defects form at the edge region 604 during grinding. These edge defects tend to form during grinding, concentrate at the edge section 604, and negatively affect the quality of the fixture layer 108.

[0041] As shown in section view 1200 of the Fig. Figure 12 illustrates how an etching process is carried out on the sacrificial substrate 602 (see Fig. 11) The etching stops at the device layer 108 and removes the sacrificial substrate 602. In some embodiments, the etching further removes a section of the second insulator layer 106b on side walls of the sacrificial substrate 602 and side walls of the device layer 108. Furthermore, in some embodiments, the etching laterally etches side walls 108sw of the device layer 108. Due to the lateral etching, the side walls 108sw of the device layer 108 may, for example, be curved and / or concave. After completion of the etching, the thickness T d The thickness of the device layer 108, for example, may be approximately 0.6–9.5 micrometers, approximately 0.6–5.05 micrometers, or approximately 5.05–9.5 micrometers. In some embodiments, etching reduces the thickness T. d the device layer 108 due to, for example, over-etching, minimal.

[0042] In some embodiments, the etching is performed by hydrofluoric / nitric / acetic acid (HNA), another wet etching, a dry etching, or another type of etching. For example, the HNA etching can etch the sacrificial substrate 602 with a chemical solution comprising hydrofluoric acid, nitric acid, and acetic acid. The etching has a first etch rate for material of the sacrificial substrate 602 and further has a second etch rate for material of the device layer 108, which is less than the first etch rate. In some embodiments, the first etch rate is approximately 90–100, 90–95, or 95–100 times greater than the second etch rate. These embodiments of the first and second etch rates can arise, for example, when the first etching is performed by HNA etching, the sacrificial substrate is or comprises 602 P+ monocrystalline silicon, and the device layer is or comprises 108 P- monocrystalline silicon.

[0043] Due to the use of etching (for example, HNA etching) to remove the sacrificial substrate 602, the removal of the sacrificial substrate 602 can be, for example, highly controlled. Therefore, the thickness T can be d The device layer 108, for example, can be highly uniform across the entire device layer, and the TTV of the device layer 108 can, for example, be low. The TTV can be low, for example, by being less than approximately 50 or 150 nm. In some embodiments, the TTV decreases with the thickness T. d the device layer 108. For example, the TTV can be less than about 50 nm, where the thickness T d The device layer 108 is less than about 300 nm and the TTV can be greater than about 50 nm, but less than about 150 nm, where the thickness T d The device layer 108 is more than approximately 300 nm.

[0044] As shown in section view 1300 of the Fig. As illustrated in Figure 13, the device layer 108 is structured. The structuring removes edge sections 108e (see Figure 13). Fig. 12) of the device layer 108. By removing the edge sections 108e, edge defects that occur at the edge sections 108e during etching of the Fig. 12 form, removed. The edge defects reduce the quality of the device layer 108 and form due to lateral etching into the side walls 108sw of the device layer 108 during the etching of the Fig. 12. The structuring process further deepens the side walls 108sw of the device layer 108 laterally. In some embodiments, after removal of the edge sections 108e, the side walls 108sw of the device layer 108 are each laterally deepened by side walls of the support substrate 104 by a lateral device indentation quantity LR. d recessed. The lateral device recess quantity LR dIt could be, for example, approximately 1.4-2.5 millimeters, approximately 1.4-1.95 millimeters, or approximately 1.95-2.5 millimeters.

[0045] In some embodiments, the structuring is performed by a photolithography / etching process or another structuring process. Furthermore, in some embodiments, the structuring comprises forming a mask 1302 over the device layer 108, performing an etch into the device layer 108 with the mask 1302 in place, and removing the mask 1302. The mask 1302 may be, for example, silicon nitride, silicon oxide, another hard mask material, photoresist, another mask material, or any combination thereof. The mask 1302 may, for example, be formed so that the device layer 108 is completely covered, except at the edge sections 108e, and / or may, for example, be formed using a WEE process tool.In some embodiments, a process for forming the mask 1302 using the WEE process tool comprises: depositing a photoresist layer onto the device layer 108; selectively irradiating an edge section of the photoresist layer with radiation using the WEE process tool; and developing the photoresist layer to form the mask 1302. The etching can be performed, for example, by dry etching or another type of etching and / or can, for example, stop at the first and second insulator layers 106a, 106b. In some embodiments, where the support substrate 104 has a high resistance (for example, a resistance greater than about 1 kΩ / cm) and the etching is performed using dry etching, the first and second insulator layers 106a, 106b prevent arc flashover by completely covering and / or completely enclosing the support substrate 104.Mask 1302 can be removed, for example, by plasma ashing or other means. Plasma ashing can, for example, involve irradiating mask 1302 with O2 plasma and can be performed, for example, if mask 1302 is or contains photoresist.

[0046] In some embodiments, a cleaning step is performed after structuring the Fig. 13 is carried out to remove etch residue and / or other unwanted byproducts generated during structuring. In some embodiments, the cleaning process removes oxide formed on the device layer 108 during structuring. The cleaning process may, for example, involve cleaning using hydrofluoric acid or another chemical solution. Hydrogen fluoride may, for example, constitute approximately 0.1–2.0%, approximately 0.1–1.0%, or approximately 1.0–2.0% of the volume of the hydrofluoric acid. The remainder of the hydrofluoric acid may, for example, be deionized water or another type of water.

[0047] As shown in section view 1400 of the Fig. As illustrated in Figure 14, a second thinning process is carried out in the device layer 108 to increase the thickness T. d to reduce the device layer 108. In some embodiments, the second thinning process reduces the thickness T. dto approximately 0.3–8.0 micrometers, approximately 0.3–4.15 micrometers, or approximately 4.15–8.0 micrometers, and / or to greater than approximately 0.3, 1.0, 2.0, 5.0, or 8.0 micrometers. Together, the device layer 108, the first insulator layer 106a, the second insulator layer 106b, and the support substrate 104 define an SOI substrate 102. In some embodiments, the second dilution process is carried out by a CMP, another dilution process, or any combination thereof.

[0048] Because the device layer 108 is formed by epitaxy and transferred to the support substrate 104, the device layer 108 can be formed with a large thickness (for example, a thickness greater than approximately 0.3 micrometers). Epitaxy is not subject to the thickness limitations associated with other approaches to forming the device layer. Furthermore, because epitaxy is not affected by the thickness of the first and second insulator layers 106a, 106b, the first and second insulator layers 106a can be formed individually and / or together with a large thickness (for example, a thickness greater than approximately 1 micrometer). The large thickness of the device layer 108 can, for example, enable the formation of large semiconductor contact points (for example, PN contacts) upon which certain devices (for example, NIR image sensors) may depend.The large thickness of the first and second insulating layers 106a can, for example, facilitate improved electrical insulation between devices on the device layer 108 and / or reduce leakage current between the devices. Devices that can benefit from the large thicknesses include, for example, high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, other devices, or any combination thereof.

[0049] As of the average 1500 of the Fig. As illustrated in Figure 15, a plurality of semiconductor devices 402 are formed on the device layer 108. In some embodiments, where the support substrate 104 has a high resistance (for example, a resistance greater than about 1 kΩ / cm), the first and second insulating layers 106a, 106b prevent arcing during plasma processing (for example, plasma etching) performed to form the semiconductor devices 402 by completely covering and / or completely enclosing the support substrate 104. The semiconductor devices 402 can be, for example, high-voltage devices, BCD devices, eFlash devices, CMOS image sensors, NIR image sensors, other devices, or any combination thereof. The high-voltage devices can, for example, be devices operating at more than about 100 volts.

[0050] In some embodiments, the semiconductor devices 402 comprise corresponding source / drain regions 404, corresponding selectively conductive channels 406, corresponding dielectric gate layers 408, corresponding gate electrodes 410, and corresponding spacers 412. For clarity, only some of the source / drain regions 404 are labelled 404, only one of the selectively conductive channels 406 is labelled 406, only one of the dielectric gate layers 408 is labelled 408, only one of the gate electrodes 410 is labelled 410, and only one of the spacers 412 is labelled 412. The source / drain regions 404 and the selectively conductive channels 406 are located in the device layer 108.The source / drain regions 404 are located at the respective ends of the selectively conductive channels 406, and each of the selectively conductive channels 406 extends from one of the source / drain regions 404 to another of the source / drain regions 404. The dielectric gate layers 408 are located over the selectively conductive channels 406, and the gate electrodes 410 are located over the dielectric gate layers 408. The spacers 412 are located over the source / drain regions 404 and line the side walls of the gate electrodes 410.

[0051] In some embodiments, a process for forming the semiconductor devices 402 comprises depositing a dielectric layer covering the device layer 108 and further depositing a conductive layer covering the dielectric layer. The conductive layer and the dielectric layer are structured into the gate electrodes 410 and the dielectric gate layers 408 (for example, by a photolithography / etching process). Dopants are implanted into the device layer 108 in place of the gate electrodes 410 to define lightly doped sections of the source / drain regions 404, and a spacer layer is formed covering the source / drain regions 404 and the gate electrodes 410. The spacer layer is etched back to form the spacers 412 and dopants are implanted into the fixture layer 108 with the spacers 412 in place to extend the source / drain areas 404.

[0052] As shown in the sectional view 1600 of the Fig. As illustrated in Figure 16, a BEOL interconnect structure 414 is formed over the device layer 108 and the semiconductor devices 402. The BEOL interconnect structure 414 comprises an interlayer dielectric (ILD) layer 416ild, a plurality of interwire dielectric (IWD) layers 416iwd, and a passivation layer 416p. The IWD layers 416iwd are located over the ILD layer 416ild, and the passivation layer 416p is located over the IWD layers 416iwd. The ILD layer 416ild, the IWD layers 416iwd, and the passivation layer 416p can be, for example, BPSG, PSG, USG, another dielectric with a low dielectric constant, silicon oxide, another dielectric, or any combination thereof. The BEOL interconnect structure 414 further comprises a variety of wires 418 and a variety of vias 420.For the sake of clarity, only some of the wires 418 are labelled 418 and only some of the vias 420 are labelled 420. The wires 418 and the vias 420 are stacked alternately in a dielectric interconnect layer defined by the ILD layer 416ild, the IWD layers 416iwd, and the passivation layer 416p.

[0053] In some embodiments, a process for forming the BEOL interconnect structure 414 comprises forming a bottom layer of the vias 420 by a single damascus process and subsequently forming a bottom layer of the wires 418 by the same single damascus process. Furthermore, in some embodiments, the process comprises forming remaining layers of the vias 420 and remaining layers of the wires 418 by repeatedly performing a double damascus process. In some embodiments, the single damascus process comprises depositing a dielectric layer, structuring the dielectric layer with openings for a single layer of conductive features (for example, a layer of vias or wires), and filling the openings with conductive material to form the single layer of conductive features.The dielectric layer can, for example, correspond to the ILD layer 416ild or a bottom IWD layer of the IWD layers 416iwd. In some embodiments, the double damascus process includes depositing a dielectric layer, structuring the dielectric layer with openings for two layers of conductive features (for example, a layer of vias and a layer of wires), and filling the openings with conductive material to form the two layers of conductive features. The dielectric layer can, for example, correspond to one of the IWD layers 416iwd above the bottom IWD layer.

[0054] With reference to Fig. 17 is a block diagram 1700 of some embodiments of the method of Fig. 5-16 provided. The process can, for example, form an SOI substrate with a thick fixture layer and a thick insulator layer.

[0055] At 1702, a first insulating layer is formed, which covers (for example, completely covers) a support substrate. See, for example, Fig. 5.

[0056] In 1704, a device layer is formed epitaxially on a sacrificial substrate. See, for example, Fig. 6.

[0057] At 1706, edge areas defined by the fixture layer and the sacrificial substrate are removed. See, for example, Fig. 7.

[0058] At step 1708, the fixture layer and the sacrificial substrate are cleaned. See, for example, Fig. 8.

[0059] At 1710, a second insulating layer is formed, covering the device layer. See, for example, Fig. 9.

[0060] In step 1712, the sacrificial substrate is bonded to the support substrate, so that the first insulator layer, the second insulator layer, and the fixture layer are located between the sacrificial substrate and the support substrate. See, for example, Fig. 10.

[0061] At 1714, the sacrificial substrate is diluted. See, for example, Fig. 11.

[0062] In process 1716, an etching process is performed into the sacrificial substrate to remove it, thereby exposing the device layer. See, for example, Fig. 12.

[0063] In 1718, edge sections of the device layer are removed, where the support substrate remains covered (e.g., completely covered) by the first and second insulator layers during removal. See, for example, Fig. 13. Arc flashover at the substrate can be prevented, for example, by the first and second insulator layers in embodiments in which the substrate has a high resistance (for example, a resistance greater than about 1 kΩ / cm), removal is carried out by dry etching, and the substrate is completely covered by the first and second insulator layers during removal.

[0064] At 1720, the device layer is thinned. See, for example, Fig. 14. The fixture layer of the first and second insulator layers and the support substrate together define an SOI substrate. Because the fixture layer is formed and transferred to the support substrate by epitaxy, it can be formed with a large thickness (for example, greater than approximately 0.3 micrometers). Epitaxy is not subject to the thickness limitations associated with other approaches to forming the fixture layer. Furthermore, because epitaxy is not affected by the thickness of the insulator layer, the insulator layer can be formed with a large thickness (for example, greater than approximately 1 micrometer).

[0065] At 1722, a semiconductor device is formed on the device layer. See, for example, Fig. 15. In some embodiments, the semiconductor devices are formed using plasma processing. For example, plasma etching can be used to structure a dielectric layer and a conductive layer into a dielectric gate layer and a gate electrode, respectively. Arc flashover at the substrate can be prevented, for example, by the first and second insulating layers in embodiments where the substrate has a high resistance (for example, a resistance greater than about 1 kΩ / cm), the semiconductor devices are formed using plasma processing, and the substrate is completely covered by the first and second insulating layers via the plasma processing.

[0066] At 1724, a BEOL interfacial structure is formed, covering the device layer and the semiconductor device. See, for example, Fig. 16.

[0067] While the block diagram 1700 of the Fig. 17. Where a series of actions or events is illustrated and described herein, it is appreciated that the illustrated sequence of such actions or events is not to be interpreted in a restrictive sense. For example, some actions may occur in different sequences and / or concurrently with other actions or events besides those illustrated and / or described herein. Furthermore, not all illustrated actions may be necessary to implement one or more aspects or embodiments of the description herein, and one or more of the actions depicted herein may be implemented in one or more separate actions and / or phases.

[0068] In some embodiments, the present application provides a method for forming an SOI substrate, wherein the method comprises: forming an insulator layer on a support substrate, wherein the insulator layer is formed such that it completely covers a top surface of the support substrate; epitaxial formation of a device layer on a sacrificial substrate; bonding the sacrificial substrate to the support substrate such that the device layer and the insulator layer are between the sacrificial and support substrates; and removing the sacrificial substrate, wherein the removal includes etching into the sacrificial substrate until the device layer is reached; structuring the device layer to remove edge sections of the device layer, wherein the top surface of the insulator layer remains completely covered during structuring, wherein the structuring comprises dry etching into the device layer.and wherein the dry etching stops at the insulator layer. In some embodiments, the sacrificial substrate and the device layer comprise the same semiconductor material, wherein the sacrificial substrate and the device layer have the same dopant types but different doping concentrations. In some embodiments, the sacrificial substrate contains P+ monocrystalline silicon and wherein the device layer contains P- monocrystalline silicon. In some embodiments, the etching employs an HNA etchant. In some embodiments, the removal includes further grinding of the sacrificial substrate prior to etching. In some embodiments, the structuring includes forming a mask on the device layer using a WEE process tool. In some embodiments, the support substrate has a high resistivity, greater than about 1 kΩ / cm. In some embodiments, the insulator layer completely encloses the support substrate.

[0069] In some embodiments, the present application provides an SOI substrate comprising: a support substrate; an insulator layer covering the support substrate, wherein the insulator layer has a pair of edge sections along an upper surface of the insulator layer, the edge sections being located on opposite sides of the insulator layer and each having a stepped profile; a dielectric interleaving layer arranged over the pair of edge sections of the insulator layer and the device layer; and a device layer located over the insulator layer, wherein the insulator layer completely encloses the support substrate, the dielectric interleaving layer having a dielectric constant k of less than about 3.9 and being in direct contact with a side wall of the device layer.In some embodiments, the insulator layer comprises: a pair of first upper surface sections exposed by the device layer, the first upper surface sections being located on opposite sides of the insulator layer; and a pair of second upper surface sections exposed by the device layer, the second upper surface sections being located on opposite sides of the insulator layer, the first upper surface sections being laterally positioned between the second upper surface sections and raised relative to the second upper surface sections. In some embodiments, the insulator layer completely encloses the support substrate. In some embodiments, the thickness of the insulator layer is greater than approximately 0.7 micrometers and the thickness of the device layer is greater than approximately 0.3 micrometers.In some embodiments, the support substrate contains silicon and has a resistance greater than about 1 kΩ / cm.

[0070] In some embodiments, the present application provides a method for forming an SOI substrate, wherein the method comprises: forming a dielectric layer covering a first semiconductor substrate; epitaxially forming a semiconductor layer on a second semiconductor substrate, wherein the semiconductor layer and the second semiconductor substrate have the same doping types and wherein the second semiconductor substrate is highly doped relative to the semiconductor layer; bonding the second semiconductor substrate to the first semiconductor substrate such that the semiconductor layer and the dielectric layer are located between the first semiconductor substrate and the second semiconductor substrate; performing a first etch into the second semiconductor substrate until the semiconductor layer is reached; and performing a second etch into the semiconductor layer to remove edge regions of the semiconductor layer, the second etch stopping at the dielectric layer.In some embodiments, the dielectric layer completely covers the first semiconductor substrate during the second etching, wherein the first semiconductor substrate has a high resistance greater than about 1 kΩ / cm, and wherein the second etching is performed with a dry etchant. In some embodiments, the first etching has a first etch rate for the second semiconductor substrate and a second etch rate for the semiconductor layer, wherein the first etch rate is about 90 or more times greater than the second etch rate. In some embodiments, the semiconductor layer and the second semiconductor substrate are doped with p-type dopants, and the first etching uses an HNA etchant.In some embodiments, the method further includes: structuring the semiconductor layer and the second semiconductor substrate to define a step, wherein the step is recessed below an upper surface of the second semiconductor substrate and wherein the step has a pair of step segments located on opposite sides of the second semiconductor substrate; and after defining the step, forming a second dielectric layer covering the semiconductor layer, wherein the bonding is performed such that the second dielectric layer is between the first semiconductor substrate and the second semiconductor substrate.

Claims

[1] Method for forming a semiconductor-on-an-insulator substrate (102), the method comprising: Forming an insulating layer (106) on a support substrate (104), wherein the insulating layer (106) is formed so that it completely covers a surface of the support substrate (104); Forming a device layer (108) on a sacrificial substrate (602), wherein the sacrificial substrate (602) and the device layer (108) comprise the same semiconductor material and wherein the sacrificial substrate (602) and the device layer (108) have the same doping types but different doping concentrations; Bonding the sacrificial substrate (602) to the support substrate (104), such that the device layer (108) and the insulator layer (106) are located between the sacrificial substrate (602) and the support substrate (104); and Removal of the sacrificial substrate (602), wherein the removal comprises performing an etching into the sacrificial substrate (602) until the device layer (108) is reached; Structuring the device layer (108) to remove edge sections (108e) of the device layer (108), wherein the top surface of the insulator layer (106) remains completely covered during structuring, wherein the structuring comprises dry etching into the device layer (108), and wherein the dry etching stops at the insulator layer (106). [2] Method according to claim 1, wherein the sacrificial substrate (602) comprises P+ monocrystalline silicon and wherein the device layer (108) comprises P- monocrystalline silicon. [3] Method according to claim 1 or 2, wherein the etching uses a hydrofluoric / nitric / acetic acid etchant. [4] Method according to any of the preceding claims, comprising the removal of further grinding of the sacrificial substrate (602) prior to etching. [5] Method according to any of the preceding claims, wherein the sacrificial substrate (602) is a bulk semiconductor substrate and wherein the device layer (108) is formed by epitaxy. [6] Method according to one of the preceding claims, wherein the structuring comprises forming a mask (1302) on the device layer (108) using a wafer edge irradiation process tool. [7] Method according to any of the preceding claims, wherein the insulator layer (106) completely encloses the support substrate (104). [8] Semiconductor structure (400), comprising: a carrier substrate (104); an insulator layer (106) covering the support substrate (104), wherein the insulator layer (106) has a pair of edge sections (102e) along an upper surface of the insulator layer (106), and wherein the edge sections (102e) are each on opposite sides of the insulator layer (106), and each has a stepped profile; a device layer (108) that lies above the insulator layer; and a dielectric interleaving layer (416) arranged above the pair of edge sections (102e) of the insulator layer (106) and the device layer (108), wherein the insulator layer (106) completely encloses the support substrate (104), wherein the dielectric interlayer (416) has a dielectric constant k of less than about 3.9 and is in direct contact with a side wall of the device layer (108). [9] Semiconductor structure (400) according to claim 8, wherein the insulating layer (106) comprises: a pair of first upper surface sections exposed by the device layer (108), wherein the first upper surface sections are each on opposite sides of the insulator layer (106); and a pair of second upper surface sections exposed by the device layer (108), wherein the second upper surface sections are each on opposite sides of the insulator layer (106), wherein the first upper surface sections are laterally between the second upper surface sections and are raised relative to the second upper surface sections. [10] Semiconductor structure (400) according to claim 8 or 9, wherein the thickness of the insulating layer (106) is greater than about 0.7 micrometers, and wherein the thickness of the device layer (108) is greater than about 0.3 micrometers. [11] Method for forming a semiconductor-on-an-insulator substrate (402), the method comprising: Forming a dielectric layer (106a) covering a first semiconductor substrate (104); Forming a semiconductor layer (108) on a second semiconductor substrate (602), wherein the second semiconductor substrate (602) is a bulk semiconductor substrate; Bonding of the second semiconductor substrate (602) to the first semiconductor substrate (104), such that the semiconductor layer (108) and the dielectric layer (106a) are between the first semiconductor substrate (104) and the second semiconductor substrate (602); Performing a first etch into the second semiconductor substrate (602) until the semiconductor layer (108) is reached, the first etching employing a hydrofluoric / nitric / acetic acid etchant; and Performing a second etching into the semiconductor layer (108) to remove edge sections (108e) of the semiconductor layer (108), the second etching stopping at the dielectric layer (106a). [12] Method according to claim 11, wherein the dielectric layer (106a) completely covers the first semiconductor substrate (104) during the second etching, wherein the first semiconductor substrate (104) has a high resistance greater than about 1 kΩ / cm and wherein the second etching is carried out with a dry etching agent. [13] Method according to claim 11 or 12, wherein the first etching has a first etch rate for the second semiconductor substrate (602) and a second etch rate for the semiconductor layer (108), and wherein the first etch rate is about 90 times or more greater than the second etch rate. [14] Method according to claims 11 to 13, wherein the second semiconductor substrate is P+ monocrystalline silicon and wherein the semiconductor layer is P- monocrystalline silicon. [15] Method according to claims 11 to 14, further comprising: Structuring the semiconductor layer (108) and the second semiconductor substrate (602) to define a recess (702), wherein the recess (702) is recessed below an upper surface of the second semiconductor substrate (602), and wherein the recess (702) has a pair of recess segments located on opposite sides of the second semiconductor substrate (602); and After defining the section (702), forming a second dielectric layer (106b) covering the semiconductor layer (108), the bonding being carried out such that the second dielectric layer (106b) is between the first semiconductor substrate (104) and the second semiconductor substrate (602).

Images